SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " revenue " 1,493 found 🔀 AI-powered Shuffle
Inside the Record-Setting Business of the Los Angeles Dodgers with President & CEO Stan Kasten
Stan Kasten, Los Angeles Dodgers President, CEO and Part Owner, joins Sports Business Radio to discuss the record-setting business of the Dodgers. From superstar Shohei Ohtani's impact on attendance, sponsor sales and merchandise sales, to improvements to the fan experience at Dodger Stadium, to the Dodgers surpassing 4 million fans last season and being on track to draw that many fans again this season, we discuss how in many regards, the Dodgers are maximizing revenues better than any other pr
Inside the Record-Setting Business of the Los Angeles Dodgers with President & CEO Stan Kasten
Stan Kasten, Los Angeles Dodgers President, CEO and Part Owner, joins Sports Business Radio to discuss the record-setting business of the Dodgers. From superstar Shohei Ohtani's impact on attendance, sponsor sales and merchandise sales, to improvements to the fan experience at Dodger Stadium, to the Dodgers surpassing 4 million fans last season and being on track to draw that many fans again this season, we discuss how in many regards, the Dodgers are maximizing revenues better than any other pr
What SoundHound AI (SOUN)'s S-4 Business Combination and Platform Expansion Means For Shareholders
In recent days, SoundHound AI, Inc. filed an S-4 registration statement for a planned business combination and confirmed strong year-over-year revenue growth alongside ongoing quarterly losses and a solid cash balance with no debt. At the same time, the company is pushing beyond its automotive roots into a broader enterprise AI platform, using acquisitions and subscription services to expand use cases across restaurants, healthcare, retail, financial services, and telecom. We’ll now examine...
Navigating the Business Tax Account: Summer 2026 Enhancements, Access Protocols, and Strategic Implications for Practitioners
Internal Revenue Service. Summer 2026 Expanded Features for BTA. Fact Sheet FS-2026-11. July 2026. Retrieved from IRS.gov Newsroom. Internal Revenue Service. Business Tax Account. Official Platform Documentation & Eligibility Guide. Last Updated: July 9, 2026. Retrieved from IRS.
NC budget raises sports-betting tax, adds prediction markets
New NC budget raises sports-betting taxes, redirects revenue to public universities, and creates a new tax on prediction markets.
UGA searching for revenue options, not ruling out entertainment district
Georgia athletic director Josh Brooks says never say never, but no definitive plans are in place for UGA to build entertainment district.
I worked 16-hour days building a business inspired by my son
Craig Moody says watching his son play basketball on a screen inspired Shoot 360, a company that generated $20 million in revenue last year.
World Cup feeds Seattle's appetite for international sports
The World Cup broke visitation and hotel revenue records in Seattle. Officials hope the games made the city a destination for future international sporting events.
UnityPoint Health confirms layoffs as part of Revenue Cycle outsourcing
UnityPoint says it will transition "certain Revenue Cycle functions" to Omega Healthcare.
DePaul Athletics and Playfly Sports Enter Multimedia Rights Partnership
CHICAGO, IL / NEW YORK, NY, July 8, 2026 – DePaul University Athletics and Playfly Sports, the sports industry's leading revenue maximization company, today ...
Right Angle Entertainment Names Todd Rossi as First-Ever VP of Marketing and Revenue
Right Angle Entertainment appointed Todd Rossi to a newly created VP of Marketing and Revenue role, the company's first. Rossi brings over 20 years of live entertainment marketing and revenue strategy experience.
Make the Business Case for Your Sustainability Initiative
Sustainability proposals often stall not because they lack merit, but because they are framed in a language that does not match how senior leaders allocate capital. While CSOs tend to emphasize impact, materiality, and disclosure, CFOs and CEOs need to understand cash flow, risk, and return. External reporting frameworks are useful for accountability, but they are poorly suited to internal investment decisions, which require project-level comparisons rather than aggregated enterprise metrics. Sustainability investments should therefore be evaluated like any other investment: by showing how they reduce current costs, avoid future costs, generate new revenue, or protect existing revenue. Strong cases begin with a clear business story that links the proposed action to a specific business impact and cash-flow outcome, then quantify what can credibly be quantified while treating harder-to-measure benefits as either upside or an explicit strategic bet.
UGA Josh Brooks on alternative revenue options: Georgia will be 'very selective'
Georgia athletic director Josh Brooks says never say never, but no definitive plans are in place for UGA to build entertainment district.
Why Buyers Pay More For Businesses With Recurring Revenue
Learn why recurring revenue increases business value, reduces buyer risk, and helps founders build a more predictable and sellable company.
College Merger Sparks Athletics Lawsuit Amid Enrollment Cliff
As some colleges merge to better handle a new higher education landscape with fewer students—and thus diminished tuition, dorm and meal plan revenue—along with less federal money for research, greater restrictions on international student visas and more restrictive federal student loan caps, the athletics implications could prove confounding and litigious. Enter: a new lawsuit brought …
What Is The Biggest Mistake Founders Make When Building A Business?
She built a company with twenty employees and steady revenue. So why did her dream vacation turn into a seven-day phone call?
This rural Colorado hospital is using AI to go after health insurers that ghosted payments. Here’s how.
The promise of modern AI to help Spanish Peaks Regional Health Center recover lost revenues is built on a system that keeps medical data private.
The CEO using AI to double revenue with 1,000 fewer hires: ‘Nobody’s going to replace the last mile’
"I was having a conversation this weekend with Claude and it was a pretty in-depth conversation," W.J. Werzyn told Fortune. And then it hallucinated.
Prediction market betting would be authorized in NC’s new budget. What it means for sports betting
Tucked into the state budget is a proposal that could have massive implications for how prediction markets operate in North Carolina. Some lawmakers say it’ll create a new revenue stream. Others worry it’ll cost the state millions.
Colorado Sports Betting May 2026: Table Tennis Cracks the Top Three, and Tax Rises as Revenue Falls
Colorado took $469.1M in May 2026 sports bets. Revenue fell to $44.7M, but state tax rose to $3.86M as free-bet deductions phase out. Table tennis was 7.2% of handle.
Happy Independence Day Dawg Sports!
It’s July 4th, the day we celebrate one of history’s earliest and most impactful conference realignments. The decision by our founding fathers that the British Empire’s revenue sharing model just wasn’t for them, and became the Notre Dame of the Western Hemisphere, geopolitically speaking. Their fateful decision saved us from a number of indignities, such […]
Nevada’s FY26 preliminary business sales revenue increases by 3.8%, Secretary of State Francisco Aguilar says
State's preliminary business sales revenue is $226.6 million, according to officials.
Trump filing shows he took in about $1.2 billion from crypto businesses last year
Mere startups when he took the oath of office, the new ventures have now eclipsed in revenue much of his vast property portfolio that took him decades to accumulate.
Former Post & Courier executive joins Georges Media as Chief Revenue Officer
Chase Heatherly, a veteran media executive, has joined the parent company of The Times-Picayune and The Advocate as its chief revenue officer.
IRS Launches "Direct Pay for Businesses"
Internal Revenue Service, Pay Business Taxes from Your Bank Account, IRS.gov (last updated June 27, 2026), https://www.irs.gov/payments/pay-business-taxes-from-your-bank-account In a long-awaited update to its electronic payment systems, the Internal Revenue Service (IRS) officially roll
Soaring revenue at Mar-a-Lago shows how Trump’s business interests and politics intersect
As President Donald Trump’s wealth has soared since retaking office, a new financial disclosure shows his two premier Florida resorts have also delivered record-breaking surges in revenue.
Soaring revenue at Mar-a-Lago shows how Trump’s business interests and politics intersect
As President Donald Trump’s wealth has soared since retaking office, a new financial disclosure shows his two premier Florida resorts have also delivered record-breaking surges in revenue.
Experity acquires AI firm to automate urgent care revenue management
The move by the Machesney Park-based Experity is meant to accelerate revenue cycle management automation through artificial intelligence.
Meta Stock Rises on Report It’s Building a Cloud Business. CoreWeave Drops.
Meta rises on a report that it hopes to generate revenue from selling excess computing power to third parties. CoreWeave and Nebius are falling.
Spartan Venture launches with aim to boost revenue for sports and student-athletes
Spartan Ventures launches today as a way for the university to bring in more money for sports and student athletes.
Trump raked in more than $1bn from crypto businesses in 2025, filing shows
President’s crypto ventures have eclipsed in revenue much of his property portfolio that took decades to accumulate
Anthropic launches Claude Science in bid to expand revenue streams ahead of IPO
Anthropic is launching its Claude Science product as it seeks to increase revenue streams ahead of its anticipated initial public offering.
NC budget includes UNC, NC State athletics for sports betting tax distribution
The state’s two major universities were left out of the previous model, which provided tax revenue to college athletic programs.
BT and Verizon Agree to Merge Global Business Ventures
Verizon CEO Dan Schulman says the joint venture will create an “AI-ready and secure” platform with a combined annual revenue of US$4bn
Louisiana Sports Betting May 2026: Parlays Drove 77% of Revenue as the World Cup Looms
Louisiana took $318M in May 2026 sports bets, with parlays driving 77% of revenue. State tax jumped 41% to $9.5M under the new 21.5% rate. A World Cup surge is next.
Experts bet World Cup wagers will bring Mass. big tax revenue
Experts say the tournament is on pace to be the biggest sports betting event in history, bringing new revenue to the state. But some fear it carries public health costs, too.
Experts bet World Cup wagers will bring Mass. big tax revenue
Experts say the tournament is on pace to be the biggest sports betting event in history, bringing new revenue to the state. But some fear it carries public health costs, too.
But-For Causation and the Essential Business Hurdle: Analyzing the Summary Judgment in RAAM Construction
RAAM Construction Inc v. United States of America, Case No. 2:25-cv-04681-SPG-AJR, 2026 WL 18391 (C.D. Cal. June 23, 2026). The Employee Retention Credit (ERC) codified under Internal Revenue Code Section 3134 remains a significant source of controversy, audits, and high-stakes federal litigation.
How one lawyer built a $1.3 million firm on social media
An entrepreneur shifts from a traditional law firm to an AI-based legal service, gaining $650K funding and achieving $372K in revenue post-launch.
Texas Tech's Red Raider Meats Has Steak Down to a Science
The Lubbock university is training the next generation of agriculture scientists using revenue from selling some of the state's best beef
Moncks Corner woman, 35, charged after running business without retail license
A Berkely County woman was charged after South Carolina Department of Revenue officals found that she was with operating a business without a Retail LicenseFrid
CSUF Report Finds Family Businesses Drive Jobs and Revenue in Fullerton
The city of Fullerton is home to a vibrant entrepreneurial community, with family-owned businesses serving as a cornerstone of the local economy. The family business sector in Fullerton is the subject of a new report researched and published by Tim Schultz, the head of Cal State Fullerton’s Center for Family Business. Chethan Srikant, associate professor […]
Business owner in South Carolina arrested, officials say
A business owner in South Carolina was arrested Friday and is accused of operating without a retail license, according to the South Carolina Department of Revenue.
Is AMC Entertainment Holdings (AMC) Undervalued Or Is Its Recent Rally Already Priced In?
AMC Entertainment Holdings (AMC) is under renewed scrutiny as investors weigh its recent share price swings and ongoing losses against reported revenue of $5,031.8 million and a market value of about $1.5 billion. See our latest analysis for AMC Entertainment Holdings. At a share price of $1.89, AMC Entertainment Holdings has seen sharp swings, with a 7 day share price return down 33.22% but a 90 day share price return up 99.33%. The 1 year total shareholder return is down 37.42%, indicating...
Corus Entertainment reports $36.5M Q3 loss, revenue down 26 per cent from year ago
TORONTO — Corus Entertainment Inc. reported a net loss attributable to shareholders of $36.5 million in its latest quarter as the company behind Global Television saw its revenue fall 16 per cent compared with a year ago.
Robot startup FieldAI achieves $100M milestone in revenue, contracts
FieldAI says it has crossed $100 million in revenue and contracts by building software for robots to work in mines, construction sites, and factories.
How Outward Intelligence founders bootstrapped to seven-figure revenue
Three friends with résumés spanning Google, Palantir, and Harris Poll skipped venture capital and bootstrapped their startup instead.
Windcrest welcomes new restaurants, businesses as city works to close revenue gap left by Rackspace
Windcrest leaders say the city is gaining momentum in its effort to attract new businesses and rebuild sales revenue after Rackspace left behind a more than a $1 million gap in the city’s annual budget.
A taxing conversation: Stafford County supervisors explore business-license levy
The board also talked about how to use future revenue expected from data centers.
Micron forecasts quarterly revenue above estimates
Micron Technology forecast quarterly revenue above Wall Street estimates on Wednesday, signaling that insatiable demand for AI-related infrastructure will continue to drive strong demand for its memory chips.
Dorchester County man charged for operating business without retail license
A Dorchester County man was arrested Wednesday and charged with operating a business without a retail license, according to the South Carolina Department of Revenue.
Business owner in South Carolina arrested, officials say
A business owner in South Carolina was arrested Wednesday for not having a retail license, according to the South Carolina Department of Revenue.
CC Biz Buzz: A busy business is not always a healthy one
Columbia College Business faculty member Gina Singleton writes about lessons of cash versus revenue.
Road-funding initiative in Colorado qualifies for November ballot
A measure that would dedicate all transportation-related revenue to Colorado’s roads and bridges has officially qualified for the November ballot after it cleared the state’s signature threshold, according to election officials. Backed by the coalition Restore Our Roads, Initiative No. 175 would require that all transportation-related revenue be used exclusively for building and repairing roads […]
Road-funding initiative clears signature threshold, qualifies for November ballot
A measure that would dedicate all transportation-related revenue to Colorado’s roads and bridges has officially qualified for the November ballot after Initiative No. 175 cleared the state’s signature threshold, according to the Secretary of State’s Office. Backed by the coalition Restore Our Roads, Initiative 175 would require that all transportation-related revenue be used exclusively for […]
Student Turns LEGO Resale Hobby Into $50,000 Business
Cedarville University senior Micah Torres turned a LEGO minifigure hobby into Rusty’s Figs, a business generating $50,000 in revenue. Through mentorship, faith and...
Utica ballpark to host its first music festival
The professional baseball league operator is bringing another entertainment option and revenue stream to the ballpark.
Prediction markets push gambling to new level, causing concern
The state is waging a legal fight to preserve oversight and tax revenue amid competition from the increasingly popular platforms, which are regulated by the federal government.
Global entertainment revenues to reach $4.2 trillion by 2030 as advertising powers industry growth
The global media industry is on course to generate US$4.2 trillion in annual revenues by 2030, according to the latest forecasts. The sector will add around US$600 billion in new revenue over the n…
The top 10 nonprofit health systems by 2025 operating revenue
The 2025 fiscal year saw across-the-board performance improvements for the country’s 10 largest nonprofit health systems, if not necessarily an expansion of their business. | Operating performances may have improved across the board, but not all of the country's largest nonprofit health systems grew their businesses.
Global entertainment and media advertising revenues to hit US$1.4 trillion in 2030 - as global box office continues recovery: PwC
The global entertainment and media (E&M) industry will hit US$4.2 trillion in revenues in 2030, growing at a CAGR of 3.4%, as AI-powered advertising and in-person, live experiences power growth in the industry, according to PwC's Global Entertainment & Media Outlook 2026-30, released today.
PEDESTRIANIZE NOW! Financial District Businesses Want Space for People Not Cars
Financial District businesses want more space for pedestrians to boost their revenues.
Media Buying Briefing: How Sport Beach became a big Cannes Lions destination
Sport Beach has grown into one of Cannes Lions' most popular activations -- and a standalone business unit for holdco Stagwell.
Global entertainment and media advertising revenues to hit US$1.4 trillion in 2030 – as global box office continues recovery: PwC
The global entertainment and media (E&M) industry will hit US$4.2 trillion in revenues in 2030, growing at a CAGR of 3.4%, as AI-powered advertising and in-person, live experiences power growth in the industry, according to PwC’s Global Entertainment & Media Outlook 2026-30, released today.
Dartmouth Health reports $63.5 million deficit for first six months of fiscal year
Dartmouth Health faces a $62.5 million deficit due to weather-related closures and high costs, but sees increased patient volumes and revenues.
Tennessee Sports Betting Handle Holds Near $443M in May 2026 as Its Handle Tax Stays Flat
Tennessee took $443M in May 2026 sports bets at a 9.25% hold. As the only state taxing handle (1.85%) rather than revenue, its tax stays tied to volume. Full breakdown.
Connecticut Sports Betting Handle Hits a May High in 2026, but Revenue Falls to $15.6M
Connecticut took $187.3M in May 2026 sports bets, up 1.8% YoY, but revenue fell 13.6% to $15.6M as hold dropped to 8.31%. State tax was $2.14M at the 13.75% rate.
How To Start A Profitable B2B Business—And 11 Ideas Worth Exploring
From consulting to SaaS, these profitable B2B business ideas can help you build recurring revenue and long-term growth.
San Diego begins installing parking meters in San Ysidro Business District
To develop the plan, city leaders worked with the San Ysidro business community. Revenue collected from the meters is reserved for transportation, parking and safety improvements in San Ysidro.
Report: PlayStation changed first-party single-player PC strategy due to lack of revenue
But CEO Hideaki Nishino has confirmed that live-service titles will continue to come to the platform
Tech Investor Prosus’ Revenue Rises on Growth Across Businesses, Tencent
Core headline earnings are expected to increase between 19% to 28% reflecting strong revenue growth and profitability across its businesses, most notably Tencent.
Tech Investor Prosus’ Revenue Rises on Growth Across Businesses, Tencent
Core headline earnings are expected to increase between 19% to 28% reflecting strong revenue growth and profitability across its businesses, most notably Tencent.
The Tricky Politics of Revenue
Our nation’s fiscal trajectory is unsustainable, in part due to the decline in revenue collection stemming from a series of tax cuts. Often enacted with bipartisan support, these tax cuts have severely damaged the linkage between economic growth and revenue flows to the U.S. Treasury. The result: Ev
SpaceX's diverse business model and future as an AI infrastructure company
Charles Payne and Dave Mazza discuss SpaceX's current revenue breakdown, with Starlink contributing 55%. Mazza highlights SpaceX's future as an AI infrastructure company, mentioning Grok and XAI, and its impact on its valuation.
California wealth tax sparks debate among billionaires, voters
A wealth tax proposal in California is running into left-leaning resistance, with critics arguing it's not a stable revenue source.
Is SEO Dead? Here's What I'm Telling Every Client Who Asks Me in 2026
The version of SEO your competitors are selling is dying. The version that actually drives revenue isn't.
Why Flutter Entertainment (FLUT) Shares Are Trading Lower Today
Shares of global online betting powerhouse Flutter Entertainment (NASDAQ:FLUT) fell 4.3% in the afternoon session after a report from Barclays showed the company's digital sports betting handle and revenue declined in May.
Reid Sigmon Named Senior Deputy Director of Athletics/ Chief Business and Revenue Officer
ANNAPOLIS, Md. – Naval Academy Director of Athletics Michael Kelly has named Reid Sigmon senior deputy director of athletics/chief business and revenue officer, a newly created leadership position designed to accelerate revenue growth, expand business operations and enhance the long-term strategic positioning of Navy Athletics.
Skill game ruling leaves Pennsylvania businesses facing possible taxes, new regulations
A Pennsylvania Supreme Court ruling that classifies skill games as gambling devices is raising concerns among small businesses that rely on the machines for extra revenue.
AI And Your HVAC Guy: HBS Founders Reveal Inside Business Strategies
AI startups succeed by solving real industry problems, prioritizing adoption, trust, workflows, and revenue.
SpaceX Bolsters AI Business With $60 Bil Deal. Musk Targets $1 Tril In Revenue.
SpaceX boosts AI business with $60 billion deal for Cursor. Elon Musk makes this bold revenue target. ARK details its SpaceX forecast.
Taking on tax: Toward progressive revenue-raising business tax reform
Hamilton Project director Aviva Aron-Dine discusses three new Hamilton Project proposals that offer ideas to raise revenue from business tax reform.
Taking on tax: Toward progressive revenue-raising business tax reform
Hamilton Project director Aviva Aron-Dine discusses three new Hamilton Project proposals that offer ideas to raise revenue from business tax reform.
This family-owned Fort Worth business plans to shut down after three decades
The family said it has lost too much revenue to nearby construction and is heartbroken to have to close in a couple of months.
Dave & Buster's Entertainment Inc. (PLAY) Stock Falls on Q1 2026 Earnings
Dave & Buster's Entertainment Inc. (PLAY) reported first-quarter 2026 results with total revenue of $559.2 million, a 1.5% decline year-over-year, and gross profit of $479.4 million, down 1.3% versus the prior year.Total revenue: $559.2 million (-1.5% YoY)Gross profit: $479.4 million (-1.3% YoY)Operating profit: $46.9 million (-25.8% YoY)Net income attributable to common shareholders: $5.7 million (-73.7% YoY)Diluted earnings per share: $0.16 (-7
Thanks For Making Me 12th Highest on Substack’s List Of “Rising” Business- and Economics-Related Newsletters
A big thank you to those of you who upgraded to paid subscriptions to read my two most recent paid memos: https://richardkatz.substack.com/publish/posts/detail/201675746?referrer=%2Fpublish%2Fposts%2Fpublished and https://richardkatz.substack.com/publish/posts/detail/201774434?referrer=%2Fpublish%2Fposts%2Fpublished As a result, total paid subs rose by 5.6% over the past seven days. And that put me at 12th on Substack’s list of “rising” newsletters in business and economics. “Rising” means those with the biggest percentage increase in revenue from subs over a short period of time. Of course, as is often the case with the issues I discuss, this is a good-news/not-so-good-news story. The good news is a rush of new subs. The caveat is that it’s easier to get a big percentage increase when the base is relatively small. I have enough paid subs to be in the initial rank of Substack’s “best seller list,” but a way to go before enough of the 12,000 subs to Japan Economy Watch are paid subs. For most hybrid newsletters—a combination of free and paid posts—2-7% of the total subs are paid. 5% is my initial goal. If you gain insight from reading this blog, please join those who’ve already upgraded; help me reach 5%—and beyond. Subscribe
Fitzgerald tells ‘UpFront’ Packers will be fine as he explores issues with NFL, Sports Broadcasting Act
Fresh off his hearing on Capitol Hill, U.S. Rep. Scott Fitzgerald said the NFL may be violating the Sports Broadcasting Act and quickly dismissed concerns from the Green Bay Packers about any changes to the league's shared revenue model.
South Korea lacks venues to match K-pop’s global reach
South Korea's shortage of large concert venues is pushing K-pop demand abroad and costing cities potential tourism, lodging and retail revenue.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
Renton World Cup watch party zone brings big crowds, business for restaurants
Local businesses in downtown Renton say that the FIFA World Cup watch party zone at Legacy Square has been bringing in big crowds, and much appreciated revenue
Why Accel Entertainment (ACEL) Is Up 9.5% After Beating Revenue Forecasts With 8.5% Growth
Earlier this quarter, Accel Entertainment reported quarterly revenue growth of 8.5% year on year, surpassing analyst expectations even as operating income trends were mixed. This revenue surprise stands out because it reflects resilience in Accel’s local gaming footprint while many consumer discretionary peers also beat sales forecasts. Next, we’ll examine how this stronger-than-expected revenue performance may influence Accel Entertainment’s existing investment narrative and growth...
SBA moves to revise 8(a) rules while preserving tribal, ANC eligibility
Details By Brian Edwards Native Contracting June 13, 2026 The U.S. Small Business Administration has proposed changes to its 8(a) Business Development Program that would eliminate race-based presumptions of social disadvantage for individually owned businesses while leaving eligibility standards unchanged for tribally owned enterprises, Alaska Native corporations and other Native entity-owned participants. In both the title and summary of the proposed rule published in the Federal Register, SBA emphasized that the changes only apply to individually owned firms and “do not impact entity-owned firms,” including tribes, Alaska Native corporation, Native Hawaiian organizations and community development corporations. The proposed rule, announced June 11, would require all individual applicants seeking admission to the 8(a) program to submit evidence demonstrating social disadvantage. Membership in a racial or ethnic group alone would no longer establish eligibility, according to the SBA. For Indian Country, the agency said eligibility standards for businesses owned by federally recognized tribes, Alaska Native corporations, Native Hawaiian organizations and community development corporations would remain unchanged. The proposal comes after the Department of Defense reaffirmed that participation by tribes and Alaska Native corporations in the 8(a) program is based on their political status under federal law rather than diversity, equity and inclusion initiatives. In a May 28 letter to Alaska's Republican Sens. Lisa Murkowski and Dan Sullivan, Under Secretary of Defense for Acquisition and Sustainment Michael P. Duffey wrote that participation by federally recognized tribes and Alaska Native corporations in federal programs is “grounded in their political status as Native Americans, not DEI initiatives.” The SBA proposal follows a 2023 federal court ruling that found unconstitutional the program's rebuttable presumption that members of certain racial and ethnic groups were socially disadvantaged. SBA Administrator Kelly Loeffler said the proposed rule would establish a single standard for individually owned applicants by requiring evidence of social disadvantage. The 8(a) Business Development Program provides participating firms with business development assistance and access to federal set-aside and sole-source contracting opportunities. The program remains a major source of federal contracting revenue for tribal enterprises and Alaska Native corporations. Native-owned firms received $16.1 billion of the program's approximately $26 billion in federal contract awards during fiscal 2024, according to data previously reported by Tribal Business News. The proposal also arrives amid ongoing concerns from Native contractors about SBA administration of the program. In May, the Native American Contractors Association and 53 Native-owned businesses urged SBA to address delays in processing 8(a) applications, saying some reviews had stretched beyond regulatory deadlines and appeared to have stalled since August 2025. The proposed rule is open for public comment through July 13. The Federal Register notice does not reference tribal consultation or indicate whether SBA determined consultation was unnecessary because tribal eligibility standards are unchanged. The SBA has not announced when the proposed rule would take effect. The agency is expected to accept public comments before issuing a final rule.About The AuthorAuthor: Brian EdwardsBrian Edwards is associate publisher and associate editor of Tribal Business News and Native News Online. He is a longtime publisher, editor, business reporter and serial entrepreneur. Subscribe Today!Other Articles by this authorDefense Department reaffirms tribal, ANC eligibility in SBA 8(a) programTribal heritage projects eligible for up to $100K in federal funding through NPS programIHS launches tribal long-term care construction initiative with three projectsIḷisaġvik College acquires site for long-planned Utqiaġvik campus This article is available to paid digital subscribers. Click here to sign in or get access.
Portland’s iconic Sports Bra bar pitches investors on national expansion as it bleeds red ink
Financial statements filed in The Sports Bra's latest fundraising effort show declining revenues amid widening operating losses.
Portland’s iconic Sports Bra bar pitches investors on national expansion as it bleeds red ink
Financial statements filed in The Sports Bra's latest fundraising effort show declining revenues amid widening operating losses.
Sharon O'Keefe
As president of the University of Chicago Medical Center and chief operating officer of the 1,286-bed University of Chicago Medicine health system, Sharon O’Keefe oversees a clinical enterprise with annual operating revenue of $2.21 billion. In the past 18 months, UChicago Medicine opened an expanded adult emergency department—a $39 million investment—and an adult trauma center. Since 2011, the system has generated annual growth of nearly 5 percent in revenue and 4 percent in patient admissions. O’Keefe previously was president of Loyola University Medical Center and executive vice president and chief operating officer at Boston’s Beth Israel Deaconess Medical Center. She serves on the Illinois Hospital Association finance and audit committee and is on the American Heart Association’s Midwest affiliate board.
Does Jeff Bezos benefit from a NH Business Enterprise Tax cut? - THE JOSIAH BARTLETT CENTER FOR PUBLIC POLICY
New Hampshire’s unique state tax structure is hard to understand, especially for people who don’t own a business. More than a third (36%) of the state General Fund and Education Trust Fund revenue comes from business taxes. The vast majority of that comes from the Business Profits Tax (BPT), but the lesser-known Business Enterprise Tax […]
College Sports PE Takes Next Step With $100M+ Utah-Otro Deal
Private equity firm Otro Capital is investing at least $100 million into a new company that encompasses most sports revenue at the University of Utah.
Senate panel sets markup on college sports bill
The Senate Commerce Committee has scheduled the markup of a bipartisan measure that proposes sweeping changes to collegiate athletics and has the backing of President Donald Trump. The panel is expected to take up several amendments at the markup on June 18, including one aimed at protecting non-revenue sports. Some athletics departments in recent years […]
Radial Entertainment Names Brendon Thomas As Chief Revenue Officer
Radial Entertainment, operator of the largest independent catalog of film and television in the industry, today announced the appointment of Brendon Thomas as Chief Revenue Officer. Thomas, who most recently served as Senior Vice President of Distribution and Business Development at Paramount Global, will lead revenue generation across the company's library, recent acquisitions, and expanding global content portfolio.
Radial Entertainment Names Brendon Thomas As Chief Revenue Officer
/PRNewswire/ -- Radial Entertainment, operator of the largest independent catalog of film and television in the industry, today announced the appointment of...