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Pitching, prose, politics: The many sides to Larry Jackson
As a newspaper sports columnist, Larry Jackson had an edge over contemporaries such as Red Smith, Jim Murray and Shirley Povich. He not only wrote about Jackie Robinson, he pitched against him. Thi…
How a Miami-area entrepreneur won a $15,000 grant. What you can learn
Six tips from a Miami entrepreneur about winning pitch competitions
City Council approves small business pitch competition in collaboration with UT
Austin City Council approved a proposal Thursday authorizing Austin Economic Development to partner with TEXAS Entrepreneurship within the McCombs School of Business to develop a small business pitch competition. The competition will give local small businesses in their early stages — especially those in areas like hospitality, creative industries and health and wellness — the...
Think Beyond Brita — These Advanced Water Filter Pitchers From $15 Help Remove Microplastics From Your Glass
More microplastics and forever chemicals are popping up in our drinking water. As a public health expert, I rounded up seven water filter pitchers to help reduce your microplastic exposure in your drinking water. Picks include pitchers from Culligan, Aquagear, LifeStraw, Aarke, and more.
Tigers Close 2026 Season With 4-2 Loss to Pirates
Late-inning solo shots by Kevin McGonigle and Eduardo Valencia sparked a rally, but early pitching struggles stifled Detroit's comeback as the club shifts focus toward a youthful 2027.
Max Scherzer Gets A Win To Finish The Season
Reds 1 Blue Jays 5 If I were Max Scherzer, that’s how I’d want to end my career. He threw seven innings, allowed six hits, one earned run, one walk, and seven strikeouts (which would finish him with 3,557 strikeouts, three fewer than Justin Verlander). Max threw 114 pitches. That’s just amazing, especially on short […]
Anna Kendrick Is “Over the Moon” About Directing ‘The Seven Husbands of Evelyn Hugo’
The 'Babies' actress covered George Clooney, 'Twilight' ("what the f*** am I doing here?") and 'Pitch Perfect's "revisionist history" in a career-spanning conversation at the Zurich Film Festival.
Chicago Cubs news
David Peterson and the pitching staff kept the Cubs in the games Friday, but the lack of offense led to Boston’s DH sweep.
Some health questions answered, others arise for Dodgers with October looming
The Dodgers need a healthy Snell, even if he might not pitch until Game 3 of the NLDS.
THE GUARDIANS ARE YOUR AL CENTRAL CHAMPIONS!!!!!!!!
WHAT A GAME!!! WHAT A SEASON!!! The offense has completely bailed out the pitching staff the last couple weeks, and tonight was no different. We got contributions from just about everyone. Multi HR games from both Patrick Bailey and Brayan Rocchio is just a hilariously beautiful way to finish the regular season. We also saw […]
St. Louis Cardinals vs Milwaukee Brewers Game Discussion Saturday
The St. Louis Cardinals will invade American Family Field again Saturday night for game 2 against the Milwaukee Brewers. Quinn Mathews will put on the pearls for his final start of the season Saturday night for St. Louis while it will be former Cardinals starter Dustin May taking the mound for the Brewers. First pitch […]
Padres Place All-Star Pitcher on IL Days Before Postseason
The Padres placed Casey Mize on the 15-day injured list with an ankle injury one day after the struggling starter acknowledged his physical limitations.
Phillies make stunning pitching announcement with season on the line
A veteran starting pitcher will take the ball on two days' rest in a surprise last-minute move.
Justin Verlander’s final start for Tigers ends with major surprise
Justin Verlander pitched into the sixth inning in his final start for the Tigers
Game 161: Rangers at Twins
First Pitch: 3:10 pm CDTTV: Twins.TVRadio: TIBN / WCCO 830 / The Wolf 102.9 FM / Audacy Last night, you got Joe Ryan and Jacob deGrom. This afternoon, you get Bailey Ober and Nathan Eovaldi. After another full season of Saturday previews, all I can tell you is that after last night’s veteran matchup resulted […]
Justin Verlander Empties the Tank in Final MLB Start
Justin Verlander pitched 5.1 innings with six strikeouts before his daughter, Genevieve, joined him on the mound to end his legendary career.
Saturday Jays Notes
Second-to-last day of the regular season. There isn’t much news. Max Scherzer says he’ll wait until after the season to decide whether he wants to pitch next year, but he’s set to start tomorrow, in front of his kids (just in case). He hasn’t put up numbers that would make me want to re-sign him. […]
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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The state’s Democratic and Republican Senate candidates have not squared off yet.
Sporting Spotlight: Moisés Mosquera
Get to know Sporting KC Defender Moisés Mosquera. His journey to soccer and the man off the pitch.
Rumor: Mario + Rabbids dev pitched Zelda spin-off to Nintendo featuring Ganondorf
According to a report from Insider Gaming, the team behind the Mario + Rabbids games once made a pitch to Nintendo for a Zelda spin-off featuring Ganondorf. Nintendo and Ubisoft Milan were apparently discussing their next collaboration in 2022. Previously, this team made Mario + Rabbids Kingdom Battle and Mario + Rabbids Sparks of Hope. The initial pitch was an...
EA Sports FC 27 review: Evolution over revolution
EA Sports FC 27 makes meaningful changes to Career Mode and gameplay, but The Grounds and some of its new systems still need to spend some time on the training pitch.
Fleets urged to build AI strategy around data, business value
Fleets looking to deploy AI should focus on clean, accessible data and defined business problems, not the latest technology pitch, panelists said at The AI Summit.
Find out what Mineirão’s new pitch will be like
Mineirão will replace its current 100% natural grass pitch with a hybrid model to host the 2027 Women’s World Cup, meeting a contractual requirement from FIFA.Because of this, ge published a report...
MLB's CC Sabathia Shares Health Message, Talks Hall of Fame
MLB star CC Sabathia joins TODAY to share a message about the importance of understanding your cholesterol numbers and shares his own health scare. “I was pitching in the big leagues and had no idea I had this blockage and just got lucky enough to be able to catch it,” he says. He also opens up about being inducted into the Monument Park Hall of Fame at Yankee Stadium. “It means more than going into the Hall of Fame…To be able to come to the Bronx, put on the pinstripes and succeed here…feels great.”
EU science policy wonks debate prospect of stronger ties with Canada
Europe’s research and innovation sector has started asking questions on how European Commission President Ursula von der Leyen’s offer to make Canada “the first associate member of the EU” would actually work in practice, and who will get to shape priorities in a transatlantic relationship that is getting stronger. The Commission says it wants “a new model of association” under which the EU and Canada will aim to develop “a shared space” to face ongoing challenges. “Working in close coordination with our member states and the European Parliament, we will aim to create a new form of partnership that has not existed until now, building the closest imaginable form of association with a partner outside Europe,” a spokesperson told Science|Business.Locked in an escalating trade war with US President Donald Trump, who has repeatedly talked of annexing Canada, Prime Minister Mark Carney has been looking east, but full EU membership was never in play. Taking the floor a day after von der Leyen’s proposal, he agreed to strengthen ties under “an alliance of the future” but reined in enthusiasm on the new label. He also suggested expanding Canada’s involvement in the Erasmus+ student mobility scheme, to which it currently has limited access, and the next iteration of Horizon Europe. Canada joined the present Horizon Europe in 2024, but only contributes to collaborative projects.Neither side has detailed the next practical steps in developing this new relationship. “I think nobody at the moment truly knows how this will work,” said Michael Browne, chief executive and founder of Crowdhelix, a global collaborative network that connects players in research and innovation. “It’s more of a statement of intent for closer collaboration, which requires legislative frameworks and approval processes, which have not started.”Kurt Deketelaere, secretary general of the League of European Research Universities, said von der Leyen’s pitch to Canada is “politically significant, but the legal content still has to be negotiated and constructed.”Mattias Björnmalm, secretary general of the Cesaer university group, agreed that she had only opened “a political door” to Canada, as “associate membership does not come with a predefined set of rights in the EU institutions.”Not only does this status not currently exist as a legal category in the two treaties that set up how the EU functions, but the Commission president cannot unilaterally create a new category of EU membership.According to Deketelaere, Article 217 of the Treaty on the Functioning of the EU, which allows the bloc to make association deals with non-EU countries involving reciprocal rights and duties, is “the most obvious existing legal basis for building a much deeper EU-Canada relationship.”Getting universities involvedNo matter how this new cooperation takes shape, Liviu Matei, who heads the School of Education, Communication and Society at King’s College London, hopes to see universities involved in discussions from an early stage.“Its primary motivations, entirely justifiably, are political and geopolitical,” he said. “In the area of higher education, however, restricting the initiative to political and geopolitical considerations would limit the scope of cooperation and lead to distorted frameworks and counterproductive implementation.”It is all the more important since academic interests on the two sides of the Atlantic are “neither identical nor fully aligned,” Matei added. “This is not insurmountable; it simply requires work to articulate the details of this privileged cooperation, including its governance and funding frameworks, as well as its substantive content in education and research.”Related articlesCanada looks to deepen research and education links with the EUZaharieva hopes for a Horizon Europe deal in 2026Canada might participate in European Research Council schemes, for example, which was not on offer in the present Horizon Europe association agreement. But “there would have to be something in it for the EU,” Browne said. “They don’t want to be funding projects outside of the EU where intellectual property is going to sit outside of the EU. There has to be some kind of transfer of knowledge.”But access to funding will not by itself resolve all the practical difficulties of working together, said Björnmalm. “For researchers and students, these include visas and residence arrangements, recognition of qualifications and study periods, and the conditions for pursuing a research career across borders,” he said. “For universities, there is scope for more predictable access to shared laboratories, computing and research data, and stronger support for joint doctoral training and long-term institutional partnerships.”Linda Doyle, provost and president of Trinity College Dublin, said Europe should strive for the “closest possible expression” of this new political alliance. “If Europe is serious about recovering its voice and its place in the world, it needs to be strongly allied with countries who share its values and its vision for a stable, rules-based, peaceful world.”
Cubs’ Kevin Gausman Departs With Potential Injury: Latest Updates
The magic number for the Chicago Cubs to punch their ticket to the MLB postseason is one, but they’re certainly hoping right now that they’re not dealing with an injury to one of their most important players. During Wednesday evening’s contest at Wrigley Field against the Miami Marlins, starting pitcher Kevin Gausman dove to make […] The post Cubs’ Kevin Gausman Departs With Potential Injury: Latest Updates appeared first on HEAVY.
Health dept. lists Shelby Co.’s top air polluters in pitch to raise fines for emission violations
They also specifically noted where Elon Musk’s tech company, SpaceXAI, ranked during the morning discussion on hospitals and health at the Shelby County Commission.
Aaron Boone Gives Surprising Yankees Wild Card Rotation Update
The New York Yankees have a huge Wild Card series coming up against the Boston Red Sox for a chance to compete for the World Series. Aaron Boone has lucked out with a tremendous MLB pitching staff of superstars giving NY a viable chance in every series. However, a new quote from Boone claims that […] The post Aaron Boone Gives Surprising Yankees Wild Card Rotation Update appeared first on HEAVY.
This Yankees’ Prospect Could Be X Factor in October Bullpen
Yankees right-handed pitching prospect and their third-best prospect, Carlos Lagrange, is being considered for possible addition to the postseason roster, reported Yankees beat writer Bryan Hoch of MLB.com in a tweet, per Aaron Boone.Lagrange has been recovering from a right shoulder capsular sprain that has kept him out since July. Lagrange returned to Triple-A Scranton […] The post This Yankees’ Prospect Could Be X Factor in October Bullpen appeared first on HEAVY.
How the Cubs Playoff Rotation is Shaping Up
With the MLB postseason race shaping up, the Chicago Cubs' playoff rotation is becoming clearer. They have occasionally had a rough time with their pitching staff this season, and it has been hard to know who they can trust. However, they are heading for a best-of-three series in the Wild Card round. This means that …
Guardians’ Parker Messick in Impressive Franchise Territory
Parker Messick is among the Cleveland Guardians franchise leaders in innings pitched by a rookie.
Blakeman pitches himself as Republican Democrats can back
Blakeman received an endorsement from former Council Member Bob Holden.
St. Louis Cardinals vs Pittsburgh Pirates Game Discussion Wednesday
The St. Louis Cardinals will do battle with the Bucs again at PNC Park Wednesday night. Matthew Liberatore is the scheduled starter for the Cardinals Wednesday night while the Pirates have announced RHP Lake Bachar as their starter. First pitch is scheduled for 5:40pm central time and the game broadcast will be available via Cardinals.tv.
11-12 IN SPAIN | OPEN THREAD
Welcome to The Daily Merengue! THESE ARE YOUR MODS: Ezek XI, Valyrian Steel, KungFuZizou, NeRObutBlanco, Felipejack, and Juninho ENOUGH OF “MR NICE GUY” Over the past 2+ years, we’ve lost to much on the pitch that now, when i see our players looking as nonchalant as possible. It irritates me more than their inability to […]
Don Cooper, former White Sox pitching coach, dies at 70
Don Cooper, the pitching coach who led the White Sox to their 2005 World Series title, has died at age 70.
Justin Verlander Reveals How Long He Will Pitch on Saturday
A.J. Pierzynski says Justin Verlander plans to push for 100 pitches and pitch “until my arm falls off” in his final MLB start.
Talent firm 24 Seven consolidates the new business efforts of its three concentric agencies
SktechDeck, Markacy and Futureman are now being pitched by 24 Seven’s new business team as any combination of the three shops that a client might want to tap
Former Yankees Pitcher, World Series Champion, Dies At 70
The New York Yankees received news that a former New York native, draft pick and team pitcher has died after a long and successful career in baseball.
“The Amazing Race” host Phil Keoghan pitches 5 reasons to watch season 39
It includes one of the most personal and emotional days ever on set for the host.
How do you feel about Everton's start to the season?
As we enter the season's first international break, we want to hear your thoughts on the opening five games of the Premier League. After an underwhelming summer transfer window, perhaps some fans will still be restless with the club's hierarchy. On the pitch though, David Moyes has made the most of his squad as the Toffees have made a strong start to the season.
Justin Verlander Reveals Reason Behind Retirement Decision
In case you missed it, Detroit Tigers pitcher Justin Verlander will make the last start of his illustrious career on Saturday afternoon against the Pittsburgh Pirates. Recently, Verlander explained what went into the retirement decision and why he’s ultimately deciding to hang up the cleats at 43 years old. Saturday starter 🫡 pic.twitter.com/ZZW3f4CHAz — Detroit […] The post Justin Verlander Reveals Reason Behind Retirement Decision appeared first on HEAVY.
Two Observations From Giants' 3-2 Loss vs. Twins
An observation on the hitting and pitching side of things following the San Francisco Giants' latest loss.
Klopp hints at Musiala start for Germany against Netherlands
Germany coach Jürgen Klopp has said “there’s no reason” to talk to Jamal Musiala about the two collapses the 23-year-old Bayern Munich star experienced on the pitch during pre-season.After expl...
Pat Murphy calls Jacob Misiorowski’s Brewers development a “Beautiful Story”
Jacob Misiorowski has become a major part of the Milwaukee Brewers’ push toward the postseason after putting together a historic season. With the 2026 MLB Playoffs approaching, Brewers manager Pat Murphy reflected on how the young pitcher’s performance this year compares with what he showed during the 2025 season. During an appearance on The Pat [...]
POLITICS OF AI: Why Emerging Tech Is Shaping the Midterms
Artificial intelligence is fast becoming a core campaign issue ahead of the midterms. As members of Congress pitch voters at home, state leaders, including Governor Ron DeSantis are pressing for tougher state-level regulations. Political analyst Dr. Larry Walker joins us to discuss why AI is top of mind for voters.
Chess-Presidential candidate Buettner pitches outsider shake-up, promises to leave politics out of FIDE
FIDE presidential candidate Jan Henric Buettner says his lack of traditional chess credentials is not a weakness but an asset, with the German entrepreneur betting that his business experience can modernise the world governing body.
Yankees news: Judge expected to miss first round
The captain unlikely to return for Wild Card Series; Rays clinch East, Yankees to host Red Sox in Wild Card round; pitchers’ steady devaluation
PRINT ONLY Autumn brings a full season of events
The cooler weather brings more than fall colors — festival season is about to reach a fever pitch. Start planning your weekend excursions now. See a full list of fall
Buffalo Sabres’ Trade Pitch Could Land $25 Million Veteran Center
The Buffalo Sabres have hope and potential, but is it enough to push them into the Stanley Cup race during their 2026-27 campaign?Some NHL insiders are putting the possibility on the table, but one key player could turn that far-fetched possibility into reality.Buffalo Sabres Named Top Landing Spot for Edmonton Oilers CaptainAdam Gretz of Bleacher […] The post Buffalo Sabres’ Trade Pitch Could Land $25 Million Veteran Center appeared first on HEAVY.
Dodgers notes: Blake Snell, Dalton Rushing, Will Klein
LOS ANGELES — It’s the final week of the regular season and the Dodgers are sorting things out as they prepare for the postseason, which they hope will start on October 3 in the National League Division Series rather than September 29 in the wild card round. Before Tuesday’s game, Blake Snell pitched a bullpen […]
St. Louis Cardinals vs Pittsburgh Pirates Game Discussion Tuesday
Just 6 games to go for the St. Louis Cardinals this season. Tuesday night, it’s the beginning of a 3-game series against the Pittsburgh Pirates. Andre Pallante will get the start for the Cardinals while the Pirates will give the ball RHP Jared Jones. First pitch at PNC Park in Pittsburgh is scheduled for 5:40pm […]
Dodgers activate Andy Pages, Roki Sasaki from injured list
LOS ANGELES — The Dodgers on Tuesday got a few regulars back as reinforcements heading into the final week of the regular season and into October, activating center fielder Andy Pages and pitcher Roki Sasaki off the injured list. Pages missed 27 games after getting hit by a fastball on his left hand on August […]
Celtic should accelerate Liverpool approach after source's reveal
Andoni Iraola on pitch with Michael Nicholson in stands left inset
New York Yankees Announce Ryan McMahon Decision Before Rays Series
The New York Yankees are set to begin a series with the American League-leading Tampa Bay Rays on Tuesday with a doubleheader scheduled.The first game is set to feature left-handed pitcher Carlos Rodón for New York and righty Nick Martinez for the Rays, with first pitch scheduled for 1:05 p.m. ET.Ahead of the matchup, Yankees […] The post New York Yankees Announce Ryan McMahon Decision Before Rays Series appeared first on HEAVY.
With new Macs, Apple aims to take on Microsoft, Nvidia in a rush to lower AI costs
When Apple's new desktop computers start shipping Tuesday, the company's executives will make an unusual pitch to corporate buyers: They are cheaper than renting data centers.
With new Macs, Apple aims to take on Microsoft, Nvidia in a rush to lower AI costs
SAN FRANCISCO, Sept 22 (Reuters) - When Apple's new desktop computers start shipping Tuesday, the company's executives will make an unusual pitch to corporate buyers: They are cheaper than renting data centers. Apple's upgraded Mac Minis and Mac Studios which can cost nearly $20,000 and handle AI tasks locally will go head-to-head against new desktop machines that Nvidia and PC makers are rolling out, expected to be the focus of a Microsoft Windows event in San Francisco next month.
Pens Points: Preseason Positives
Back on PPG Paints Arena ice for the first time since April, the Pittsburgh Penguins opened their preseason slate with a 4-1 victory over the Buffalo Sabres. Sergei Murashov got the nod in goal and pitched a shutout, stopping 13 shots, in his 30 minutes of action before Joel Blomqvist took over. Connor Dewar, Bryan […]
Yet Another Jays Depressing Loss
Blue Jays 3 Orioles 4 Sometimes you make the right moves and yet they don’t work out. Bottom of the eighth Mason Fluharty pitching. He gave up a leadoff walk. Then got a pop out and a fly out. With Pete Alonso up, John brought in Tyler Rogers. I liked the call. But….Alonso hit his […]
Being run over by pitch roller was 'terrifying'
Townsend says he was lucky to only escape from under the roller with a few "bumps and bruises".
Pirates Pitcher on Streak Not Seen in Over 100 Years
Mason Montgomery's current streak solidifies his spot in the Pittsburgh Pirates' bullpen for years to come.
Florida governor candidates pitch different approaches to homeowners insurance costs
Homeowners insurance is becoming a major issue in Florida’s race for governor, with Democratic nominee David Jolly and Republican nominee Byron Donalds proposing different approaches to lowering costs.
Paul Skenes points to World Baseball Classic as the 'root' of his pitching woes this season
Video: These Singing Lemurs Belt Like Opera Stars, Scientists Say
Scientists have found singing lemurs, known as indris, and opera singers use similar mouth shapes to create loud, high-pitched calls.
Monday Morning Minnesota: The “Time To Say Goodbye” Edition
We come to the last week of the season, and the Twins have officially been eliminated from playoff contention and will not be able to finish the season with a winning record. On the bright side, Walker Jenkins figured out major league pitching! The Twins wrap up the season with a series in San Francisco […]
New York Yankees Announce Starting Pitchers for Pivotal Rays Series
The New York Yankees officially announced their starting pitchers for their upcoming series against the Tampa Bay Rays. The post New York Yankees Announce Starting Pitchers for Pivotal Rays Series appeared first on HEAVY.
Pirates' Paul Skenes Gets Honest About Big Mistake He Made
Pittsburgh Pirates star pitcher Paul Skenes spoke out honestly about a big mistake he made before this season.
Marquette Business to host Baum Spirit of Entrepreneurship Summit Presented by Marcus Corporation, Nov. 18
This complimentary event will feature MIT entrepreneurship leader Bill Aulet, an expert panel and the Marquette Invitational Pitch Competition.
Yankees Face New Pitching Concern After Diamondbacks Loss
The New York Yankees lost 8-4 to the Arizona Diamondbacks on Sunday at Chase Field. The game featured a blown 4-1 lead, a grand slam from Nolan Arenado, and another difficult afternoon for a bullpen that has been stretched thin down the stretch.But a quieter moment during the game raised a different kind of concern. […] The post Yankees Face New Pitching Concern After Diamondbacks Loss appeared first on HEAVY.
Angels Issue Injury Updates On Three Players
The Los Angeles Angels are shutting down two players, but one pitcher won't need surgery.
This One Yankees’ Brent Headrick Concern
It’s no secret that Yankees left-handed relief pitcher Brent Headrick has been one of, if not their most dominant relief pitcher this season in 2026. However, concerns are growing about Brent Headrick as we approach the final week of the regular season before the postseason.Yankees beat writer Brendan Kuty of The Athletic posted earlier this […] The post This One Yankees’ Brent Headrick Concern appeared first on HEAVY.
Why Brewers Pulled Jacob Misiorowski After Pitching 3 Innings
Jacob Misiorowski must’ve wanted to watch the Sunday Night Football matchup between the Kansas City Chiefs and Indianapolis Colts. Because after pitching three innings on Sunday Night Baseball for the Milwaukee Brewers, he was pulled from the game. For those not paying more attention, it certainly could cause alarm. The Brewers are just a week […] The post Why Brewers Pulled Jacob Misiorowski After Pitching 3 Innings appeared first on HEAVY.
The Weeknd Debuts New Song Sampling Neon Genesis Evangelion Theme
He performed it in Tokyo with Yoko Takahashi, who sings the anime’s opening theme “A Cruel Angel’s Thesis”
Did Brewers Make Mistake by Not Bringing Back Peralta?
Former Milwaukee Brewers ace Freddy Peralta is dominating with the Tampa Bay Rays following a tactical pitch-mix overhaul.
Analysis: Late goal eases pressure on Carrick
It is too early in the season for Michael Carrick's position to be under serious threat. With a three-week international break to come, there will be no escaping a certain amount of criticism and it is a long time to wait before Manchester United can attempt to start putting things right on the pitch. Overall, United were good value for a point and might even argue snatching all three would not have been unwarranted given their strong finish.
La Lew wins $15K in RIT business pitch competition
La Lew Public Relations won the $15,000 grand prize in RIT's ROC the Pitch competition, while Allergy Advocates NY received $10,000.
Detmers Joins Ohtani, Finley in Angels' 200-Strikeout Club
Reid Detmers became the first Angels pitcher since Shohei Ohtani and the first left-hander since Chuck Finley to reach 200 strikeouts in a season.
Ed Sheeran Clarifies Gaza Stance, Again Blames Venues for Kicking Macklemore Off Tour
Sheeran called what’s happening in Gaza “catastrophic, unjustifiable, and disproportionate” but did not take responsibility for the rapper being removed from the show
Dodgers Finally Secure First Series Victory of 2026 vs. Giants
The Los Angeles Dodgers ignited a 15-hit offensive explosion to dismantle the San Francisco Giants' pitching staff.
EU associate membership: The name is irrelevant, the politics aren’t
Each week, Euronews’ chief Europe editor Maria Tadeo debriefs the ins and outs of continental politics. This week, reporting from Strasbourg, she examines the EU’s pitch for associate membership for Canada.
Townsend run over by pitch roller in Thailand
Former England winger Andros Townsend jokes that playing Stoke away "wasn't so bad after all" following a bizarre incident before a game in Thailand.