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Trump’s strait blockade risks another serious blow to the global economy
The failure of US-Iran peace talks leaves President Donald Trump with a set of unattractive options that are unlikely to hand him a decisive or swift victory.
Boomer Esiason rips ‘very attractive’ Olympic star: ‘She’s insufferable’
Olympic champion Eileen Gu is once again drawing criticism in the U.S. — this time from WFAN host Boomer Esiason.
Has Arbeloa 'underestimated' the Premier League?
"If you are a Fulham fan, you are worried right now," former Premier League striker Chris Sutton has said after seeing the Cottagers pick up zero points from their first three league games of the season. "I thought Fulham were quite an attractive team under Marco Silva," Sutton said on BBC Radio 5 Live's Monday Night Club.
CineD tested the Sony A7rVI: Highest DR ever tested (with a caveat) and promising prospects for the A7sIV :)
CineD tested the Sony A7rVI and wrote this: Sony managed to create a very attractive package with the a7R VI – rolling shutter values with or without the dual gain mode are very manageable, and the dynamic range results show the power of dual gain “ON” – we get up to 14 stops at SNR
United Bank hires Phil Poliquin to lead government contracting business
Phil PoliquinUnited Bank, a subsidiary of United Bankshares, Inc. (NASDAQ: UBSI), has announced that Phil Poliquin has joined the Bank as senior vice president and managing director of Government Contracting (GovCon), leading the next phase of growth for United’s GovCon business across the Bank’s footprint.United has a longstanding history of serving government contractors and meeting the dynamic banking needs of companies supporting federal, state and commercial markets. Building on that foundation, the Bank is establishing a dedicated GovCon team led by Poliquin. The new team will bring together bankers from across United's footprint under a focused strategy designed to deepen industry expertise, strengthen client relationships and expand the Bank's presence in this important market.“Government contractors operate in a complex and highly specialized environment, and Phil understands that environment from multiple perspectives,” said United Bank Chief Commercial Lending Officer Mike Proctor in a press release. “His extensive commercial banking experience, combined with more than two decades of military and government service, brings tremendous depth and expertise to our team. We’re excited to have his leadership and insight as we continue strengthening how United serves our GovCon clients across the nation’s capital and beyond.”In his new role, Poliquin will lead United’s GovCon lending strategy and a team of specialists, with a focus on deepening client relationships and expanding the Bank’s presence in the government contracting and defense sectors. He will also serve as a subject matter expert across the organization, partnering with bankers across United’s footprint to support GovCon clients and opportunities.“Government contracting has long been an important part of the economy across the Washington region, and we believe it remains an attractive sector for growth,” said United Chief Executive Officer Richard M. Adams, Jr. in a press release “As the needs of these companies continue to evolve, investing in specialized leadership strengthens our ability to build on our established presence, expand how we serve this market, and pursue new opportunities.”Poliquin has a decade of experience in commercial banking, most recently serving as executive director of Aerospace, Defense, and Government Services (ADG) commercial banking at JPMorgan Chase. In this role, he led a team responsible for providing specialized financing and treasury advice to federal government contractor companies across the nation. Previously, he also held senior leadership positions at Bank of America.Prior to his banking career, Poliquin served 24 years in the U.S. Navy, retiring at the rank of Captain in 2013. A Naval aviator, he flew more than 100 combat missions in operations around the world and served in senior leadership positions, including as commanding officer of an F/A-18 Super Hornet squadron, leading more than 250 personnel during two combat deployments. He later joined the Intelligence Community as a program manager at the National Reconnaissance Office and contributed to the development of the Navy’s unmanned aircraft system strategy.“United has a strong foundation in government contracting, and I’m excited about the opportunity to build on that foundation by expanding our industry presence, deepening relationships, and developing a team with specialized expertise focused on serving government contractors,” said Poliquin in the release. “The goal is to be a trusted resource for growth-oriented companies that need a banking partner who understands what they do, where they’re headed and can help them navigate the opportunities and complexities of this market.”Poliquin holds a bachelor’s degree in mathematics from the University of Oklahoma, a master’s degree in national security strategy from the U.S. Naval War College, and an MBA from the University of North Carolina at Chapel Hill’s Kenan-Flagler Business School.
People who lost the most weight on Ozempic saw huge health benefits
People who lost significant weight while taking Ozempic, Wegovy, Mounjaro, or Saxenda had sharply lower risks of major obesity-related health problems, including sleep apnea and kidney disease. Those who gained weight instead faced higher risks — especially for heart failure — even though many patients discontinued the medications within a year.
Xiaomi 18 Fold hands-on: An attractive 'mid-size' foldable with powerful specs
Xiaomi's impressive-sounding new foldable arrives on the eve of Apple's big foldable iPhone event.
The Fierce Battle For Kids’ Eyeballs...Plus Two “Devils” Face Off
(Welcome to my weekly streaming ratings report, the single best guide to what’s popular in streaming TV and what isn’t. I’m the Entertainment Strategy Guy, a former streaming executive who now analyzes business strategy in the entertainment industry. If you were forwarded this email, please subscribe to get these insights each week.) During the week of this report, Spider-Man: Brand New Day hit theaters and went on to become one of the biggest films of all time. So, you know what that means! It’s time for a poll! Recently, Project Hail Mary came to Prime Video and became a top five film for them, but didn’t smash streaming records, a feat I cautiously thought it could accomplish. Can Spider-Man 4 do better? To set the stakes, some of the biggest films of all time do just okay on streaming. Wicked, Top Gun: Maverick, and Barbie come to mind... But unlike those films, Spider-Man: Brand New Day is a Sony film which means it’s headed to Netflix, the world’s largest streamer. Now, per friend of the newsletter and my go-to Netflix expert, Kasey Moore of What’s on Netflix, Sony films usually appear on Netflix 120 days after they premiere, which means Spidey 4 would land on Netflix on, checks notes, 28-November, one of the two biggest streaming weekends of the year! But Sony occasionally delays its biggest hits for a bit longer, to give them more time to make money on PVOD, so Spider-Man: Brand New Day might not swing onto Netflix until late December or even February 2027. Loading... Okay, on to this week’s issue. Since The Super Mario Galaxy Movie made its way to Peacock, I’m looking at the true workhorse of streaming viewership: kids films. And the surprising film that bested most Netflix animated movies. All that, plus Hulu has a new show that might be a hit (for them…?), two “Devils” square off on streaming, Zendaya tries to find some streaming magic, Netflix’s I Will Find You continues to do well, House of the Dragon tries to break into the season three top ten, some big NBC sports and summer programs, what friendly neighborhood Spider-Man character actually generates the most viewership on streaming, all the flops, bombs and misses, and a whole lot more. Let’s dive right in! (Reminder: The streaming ratings report focuses on the U.S. market and compiles data from Nielsen’s weekly top ten viewership ranks, Luminate’s Top Ten Data, JustWatch and Reelgood interest data, Samba TV household viewership, company datecdotes, Netflix hours viewed data, Google Trends, and IMDb to determine the most popular content. While most data points are current, Nielsen’s data covers the weeks of July 27th to August 2nd, 2026. You can find a link to my terminology here.) Subscribe Film - As The Super Mario Galaxy Movie Hits Peacock, How Have Kids Films Fared in 2026? Like Mario hopping on a Koopa, The Super Mario Galaxy Movie landed on Peacock on 30-July. (Yeah, I kinda forced that Mario reference.) How did it do? Great, just like the first film. It got 13.0 million hours on its opening, and that’s good enough to take second place among Peacock films on the Nielsen charts all time: As I mention all the time, Peacock just isn’t the world’s biggest streamer—in fact, nowhere close—so its films struggle to put up numbers like Netflix (or even Prime Video and Disney+). So this is a solid debut for that streamer. And as we saw last time, The Super Mario Bros. Movie had a HUGE second life on Netflix when it moved streamers. This chart doesn’t even show how long the first Mario lasted on Netflix: a whopping, KPop-esque 31 weeks. For NBCUniversal, though, the big win was the second Mario movie grossing $429 million in America and over $1 billion globally. But yeah, to add a very strong streaming performance only makes its success even greater. Illumination pretty clearly has another hit franchise on their hands. This is a good time, though, to check in on kids films so far in 2026. We’ve had a few big, big titles, a rare Netflix success, and some disappointments. Let’s start with the top animated films since November of 2025, over their first four weeks on the charts, along with a few of the “best all time” animated films: (As a reminder, if a film doesn’t make the Nielsen top ten lists, I don’t have data for it, so it gets a “zero” in terms of viewership. Now, it had some viewership, but I don’t know what it is, so it gets a zero.) I added a few titles to get an idea of what the best of the best looks like in terms of animation. And you can see, through four weeks, Zootopia 2 can now claim “one of the biggest streaming films of all time” titles. GOAT too did surprisingly well, besting Netflix’s biggest films (Swapped and In Your Dreams) through four weeks. When I’ve talked about how films can have varying performances on streaming compared to their box office, this is what I mean. Goat just managed to gross even $103 million at the box office—so it’s popular, but just barely—but did very well on streaming. Of course, what set Encanto and KPop Demon Hunters apart from the rest was their absolutely insane longevity. Here are the kids film charts through eight weeks to show that: And really KPop Demon Hunters just kept going, and no 2025 or 2026 kids films have had that sort of longevity. I can’t wait to see the sequel in theaters. Film - Two Devils and a Drama As I wrote last week, in the past, theatrical-first film flops weren’t eligible for “Miss of the Week” or “Miss of the Year” honors/dishonors, but since so many more films go to theaters first these days, I’ve made them eligible now! But it’s complicated. You see, this is a Streaming Ratings Report, emphasis on streaming, which makes analyzing this week’s two biggest streaming misses—The Drama on HBO Max (A24’s dramedy starring Zendaya and Robert Pattinson) and Prime Video’s The Devil Mouth (a killer shark movie starring young attractive people)—somewhat tricky. The Drama isn’t eligible for Luminate, but The Devil’s Mouth only had 1.5 million hours in its first week: The Devil’s Mouth notched 5.2 million hours according to Nielsen. Meanwhile, The Drama missed the charts entirely. Not great! But Prime Video is a much bigger streamer than HBO Max. That said, HBO Max titles are on Prime Video, but I think Prime Video prioritizes their original/exclusive titles, which helps boost their viewership. Complicating this further, The Drama made $48 million in the US—while A24 sells foreign distribution; the $57 million of overseas grosses helps A24 sell overseas rights for money in the future—off of a $28 million budget (which seems low for Zendaya and Pattinson, so they might have backend). The Devil’s Mouth, though, had zero dollars at the box office. The other stats for The Devil’s Mouth are bleak, and by “bleak”, I mean horrendous: a 4.7 on 15K reviews on IMDb (yikes) and a 46 on Metacritic (double yikes). The Drama, though buzzy online, only has a solid (but far from elite) 7.1 IMDb score on 121K reviews and a 59 on Metacritic (which is far, far lower than I’d have guessed). So which film is the “Miss of the Week”? I’m giving it to The Devil’s Mouth for one simple reason: it’s a horror film. And almost all horror films, even poorly reviewed horror films, should get a shot in theaters to at least try to recoup some of their budgets. The Drama made money at the box office and The Devil’s Mouth didn’t. It’s just like the situation last issue with Obsession and Masters of the Universe. Sure, Obsession didn’t pop on the streaming charts, but at least it already made it money at the box office. And as we’ve been seeing for years now and we’ll see all fall, theatrical films just do better on streaming. After all, the big “devil” winner this week was actually The Devil Wears Prada 2 with 14.8 million hours according to Nielsen. That’s right, The Devil Wears Prada 2—one of the box office success stories of May—came to streaming and parlayed its $220 million box office into 14.8 million Nielsen hours. Disney also put out a datecdote that it had 15.2 million “views” globally in five days, but again we don’t have a lot of great context for what that means. Here’s how it stacks up to other Hulu films, since I’m categorizing this mainly as a Hulu title (though it was also on Disney+): Share Quick Notes on Film We’re just getting started with this issue, but the rest is for paid subscribers of the Entertainment Strategy Guy, so if you’d like to find out… Whether Hulu has a new hit show on its hands... The top first and third seasons of all time and which shows are climbing those charts… What version of Spidey is the most popular... What sport and TV show are performing better on NBC than the NBA... All the flops, bombs and misses... ...please subscribe! We can only keep doing this great work with your support. Coming Soon! Next week, wow, things stay so busy. One of streaming’s biggest shows of all time, Ted Lasso, returns along with new YA-ish shows from Hulu (The Shards, from Ryan Murphy) and Prime Video (Sterling Point). The Challenge moves to Paramount+, plus My Life with the Walter Boys returns to Netflix and Futurama returns to Hulu. And Netflix has a new horror film, The Last House. Lots to talk about! All month, things stay busy. We’re talking Reacher on Prime Video! Outer Banks and Tires on Netflix! Lanterns on HBO Max! UFC 330 on Paramount+ and the MLB Field of Dreams game on Netflix. And a ton of smaller films come to streaming. Long term, the VMAs are back on 27-Sep! I feel like I haven’t heard much about this show in past years, but I’m seeing more news coverage and buzz for this show than in past years. I’m curious to see how it does.
Is Tenet Healthcare Corporation (THC) A Solid Play on Expanding Ambulatory Business?
Tenet Healthcare Corporation (NYSE:THC) is increasingly relying on its ambulatory business as an important driver of growth, combining favorable long-term outpatient trends with attractive margins. According to BMO Capital Markets, Tenet’s ambulatory operations give the company exposure to an end market with favorable long-term growth characteristics. The firm expects continued investment in Tenet’s hospital operations […]
Is It Time To Reassess Six Flags Entertainment (FUN) After Its Recent Share Price Rebound?
If you are wondering whether Six Flags Entertainment is attractively priced today or a potential value trap in disguise, this article breaks down what the current share price is really offering you. The stock last closed at US$19.69, with returns of 9.3% over the past week, 10.1% over the past month, 27.1% year to date, and a 45.5% decline over the past year as well as 52.2% and 54.1% declines over the last 3 and 5 years. Recent headlines around Six Flags Entertainment have focused on its...
Is Live Nation Entertainment (LYV) Still Attractively Priced After Strong Multi‑Year Share Gains?
If you are wondering whether Live Nation Entertainment is priced for perfection or still has room to run, the recent share performance gives you a useful starting point. The stock last closed at US$167.82, with returns of 9.6% over the past week, 4.8% over the past month, 15.5% year to date, 25.1% over 1 year, 113.6% over 3 years and 115.4% over 5 years. Recent headlines have focused on Live Nation Entertainment's position in global live events and ticketing, including regulatory attention...
Why Site Preparation Makes Sense as Public Investment
Funding for site preparation can support improvements that make Michigan's best business locations more attractive and draw investment and jobs to our state.
What Makes Men Attractive? Science Reveals the Ideal Body
Do muscles make the man? New research reveals that body fat and BMI play a bigger role in male attractiveness than most people think.
Comcast is spinning out its media business. Deutsche Bank says it's time to buy the stock
Comcast is planning to spin off NBCUniversal, which makes the stock more attractive to own, according to Deutsche Bank.
Endocrinology — Uniting the Legacy and Future of Basic Endocrine Science
Read the inaugural editorial from Endocrinology’s new Editor-in-Chief, Manuel Tena-Sempere, MD, PhD, outlining the vision for the journal to continue its high-quality standards spanning foundational, translational, and preclinical research investigating endocrine and metabolic function in health and disease while becoming more influential and attractive for a wider array of scientists worldwide.
‘Business is booming:’ Broward welcomed many employers, expansions, Greater Fort Lauderdale Alliance says
Broward County welcomed a wealth of new companies in 2026 as the tri-county region remained an attractive landing spot for those seeking a better business climate.
Viewpoint: FP10 should remain open, excellent and secure
Europe is right to worry about research security. Foreign interference is real. So is the misuse of sensitive knowledge. Universities working in sensitive areas such as AI, quantum, semiconductors and advanced materials cannot afford to ignore the geopolitical environment around them.But Europe is in danger of drawing the wrong conclusion, one that would increase, not reduce, its strategic vulnerabilities.If the EU applies an “EU preference” logic to the next Framework Programme for research and innovation (FP10), it will weaken one of its greatest strategic assets: a research system built on openness, excellence and international collaboration. In the name of security, Europe could end up advancing science more slowly, innovating less effectively and making itself less attractive to global talent and partners in advanced science and technology.That would be a serious mistake.The EU preference included in Article 10 of the proposed European Competitiveness Fund may make sense in some industrial or deployment contexts, but is far harder to justify when applied to collaborative research in advanced science and technology, where excellence and global connectivity are crucial. Research is not procurement. It does not thrive when isolated. It advances through access to the best ideas, the best people, the best facilities and the best data, wherever they are found. This is why FP10 should not simply absorb industrial policy logic by default. Doing so would risk importing instruments that are ill-suited to research and that ultimately increase vulnerability rather than resilience.For universities of science and technology, the issue is especially acute. These institutions sit at the frontier of knowledge and technology creation in the very fields Europe sees as critical for its future competitiveness and resilience. They know better than most that security risks are real. But they also know that openness and security are not opposites. In practice, they have to be made to work together. Research security is not about closing doors. It is about building resilience through collective responsibility, trust, proportionate safeguards and better governance. That is a fundamentally different approach from default restriction.The risks of non-collaborationThe real danger in the current debate is that Europe talks too much about the risks of collaboration and not enough about the risks of non-collaboration. Those risks are strategic too. Cut researchers off from international networks and Europe loses access to knowledge, data, infrastructures and talent. Slow down global collaboration in critical technologies and Europe slows down its own progress on cutting-edge science. Make participation rules unpredictable and Europe weakens its attractiveness to researchers and investors alike.In other words, over-restricting collaboration will create strategic vulnerabilities, particularly in advanced science and technologies.This point is often underestimated in policy discussions that frame openness mainly as a value to be defended. Europe’s scientific strength, technological development and long-term competitiveness depend on remaining connected to the best research ecosystems in the world. For a continent that wants to accelerate deep tech, strengthen industrial capacity and reduce strategic dependencies, weakening the excellence base would be self-defeating. That does not mean ignoring risk. Quite the opposite. Universities are already strengthening due diligence, internal governance, awareness-raising, screening procedures and compliance support. Across Europe, institutions are working to manage risks linked to foreign interference, sanctions, export controls and the misuse of research. The right response is not complacency. It is better risk management. But that means targeted, evidence-based and proportionate measures, not blunt top-down restrictions with wide spillover effects. In the daily reality of universities, openness and restriction often coexist. The real challenge is how to apply safeguards without sliding into securitisation that damages academic freedom, open science and international cooperation. Restrict partners, not nationsMore restrictive treatment of collaborators from European Economic Area members Iceland, Liechtenstein and Norway, or from Switzerland and the UK, is strategically very difficult to justify. These are deeply embedded partners in Europe’s research and innovation ecosystem. Beyond that, Europe should still resist default exclusion and instead rely on case-by-case assessment. The relevant question is not nationality in the abstract. It is the actual risk profile of a collaboration: the institution, the affiliations, the field, the knowledge involved, the intended use and the safeguards available. Screening should focus on institutions and affiliations rather than nationality alone. Related articlesParliament ‘misreads’ link between Horizon Europe and ECF, Commission official saysFrustration grows at governance gap in next Horizon EuropeIf EU preference logic is imported into research without careful calibration, the likely result is a chilling effect. Researchers may step back from legitimate and beneficial collaboration, even where risks are manageable. International partners may see Europe as less predictable. And Europe may end up undermining the very excellence base it needs to compete, scale up and lead in strategic technologies, thereby increasing its dependence on others.FP10 should do the opposite. It should remain open by default, with restrictions used only exceptionally, and then on the basis of clear evidence. It should integrate research security into open science and research integrity frameworks, not set them against each other. And it should recognise that academic freedom, scientific excellence and responsible international collaboration are not obstacles to Europe’s security, they are part of it. Europe needs stronger tools to protect itself. But it also needs the discipline to avoid measures that would weaken it and increase its strategic vulnerabilities in the process. In FP10, that means staying open, excellent and secure.Louise Drogoul is senior advisor for innovation and sustainability at the Cesaer university association.
'China shock': Germany struggles as key market turns business rival
China was long a lucrative market for Germany Inc, but the Asian giant's rise in high-tech fields has put the heat on Europe's industrial powerhouse and its companies, big and small."In all key industrial sectors, China has changed from a very attractive market into a very capable competitor," said its CEO Joerg Jetter at company headquarters in Alsdorf, western Germany.
You're probably using too many skin care products. Here are the 3 essentials
We asked half a dozen skin care experts: Which products do you really need to keep your skin healthy and attractive? Here's what they said.
Science and the public are learning the wrong lessons from Covid
“Post-pandemic polarization threatens to lock our memories into attractive, untrue conclusions that will leave us unprotected next time,” write Marc Lipsitch and Sara Cody.
How to keep ticks out of your yard
Skip the essential oils and try expert-recommended tick prevention methods to make your yard less attractive to ticks.
MAGA's attack on science is even worse than it looks
In my post on America’s 250-year anniversary, I argued that respect for the individual was the “secret sauce” in the U.S.’ long-lasting preeminence among nations. But it was certainly not the only factor. There were plenty of institutional innovations that helped the U.S. stay on top — economically, militarily, and in terms of the attractiveness of its society. One of these was American science. Today we take things like the modern research university, government grants for science, public-to-private research spinoffs, etc. for granted, but a lot of that infrastructure wasn’t there before World War 2. It was either invented or scaled up massively by the U.S. government in the postwar period, led by far-sighted scientist-bureaucrats like Vannevar Bush (pictured above). If you want to read about this history, a good place to start would be Jonathan Gruber and Simon Johnson’s excellent book Jump-Starting America. Those scientific institutions didn’t exist in a vacuum, however. They were backed by the U.S. government’s abiding faith in the power of science — and, even more fundamentally, by deep popular trust in the scientific enterprise. Science gave us radar and the atom bomb in wartime, and in peacetime it gave us plastics, vaccines, cheap food, and a thousand other things that made our lives easier. Science was also the driver behind American industry — chemicals, aerospace, telecommunications, computers, electronics, and so on. We owed science our jobs, our livelihoods, our comfortable living standards, and our greatness and power as a nation. It’s little wonder that both political parties, even as they fought viciously over other issues, were steadfast in their support of science. For a long time, the only people who distrusted science were a hippie fringe on the left who disliked modernity (or thought they did, anyway), who also disliked American industry and American power, and who subscribed to an early version of degrowth environmentalism. America’s scientific enterprise is still strong, especially compared to the systems in Europe, Japan, Korea, and other developed countries. It has lost a lot of ground to China in a relative sense, but a lot of that is because of China’s incredible growth; as China has poured untold amounts of money and talent into its research labs, spending and output have overtaken the U.S. by some measures. There are a few ways in which China’s rise creates problems for American science — for example, top scientists can choose to work in China instead of in the U.S. — and of course there’s the concern that China’s technological strength will help its military to reign supreme. But overall, China’s rise in science should be good for American science, since American scientists can use Chinese discoveries for free and build on them. The much bigger problem is that the scientific enterprise America built during and after World War 2 is now being threatened with absolute decline. The biggest problem, of course, is that much of the country — the Republican half — has basically lost faith in the scientific enterprise. To what degree this loss of faith is justified is an open question, and deserves to be discussed openly. But the larger point — that the system that powered American dominance is under threat — is true either way. Most Americans still trust science, but MAGA Republicans don’t There’s a myth, popular in right-wing circles, that scientists have lost the trust of regular Americans — either due to the increasingly left-wing composition of academic departments, or to misbehavior during Covid, or to DEI-related research taking over science, etc. This also fits with a wider narrative that Americans are losing trust in all of our institutions. But it just isn’t true. Poll after poll shows that on the whole, Americans still trust scientists and want to spend more on science. For example, here’s a Pew poll from late 2025 showing that although about a fifth of Republicans did lose confidence in science in 2020, two thirds still have at least “a fair amount” of confidence: That same poll found that scientists are among America’s most trusted groups — even better trusted than the military! In fact, Americans trust scientists more than people in most other countries do. Other polls show that although Republican trust in science has dropped somewhat, Republican support for spending more on science remains very strong: A Pew poll in 2023 found the exact same thing: So when MAGA types tell you about scientists losing their credibility, or a drop in trust in science, they’re only talking about themselves. Whatever left-wing politicization of science happened during the Biden administration — and there was definitely some of that — it was not enough to make most Republicans lose faith in the scientific enterprise, or favor research cuts in order to purge unwanted ideology from the system. That doesn’t mean I think progressives should continue down the path of politicizing scientific research. They should not, and Biden made real missteps in this area. Objectivity clearly matters for public trust of science in the long term. But as of right now, there’s no crisis of trust in science, except among the smallish minority of people who are running around screaming that there’s a crisis of trust in science. But despite science’s overwhelming popularity and public trust, Trump and his administration are launching an unprecedented and devastating attack on American science — cutting funding, and forcing science projects to undergo ideological review by government commissars. Trump’s comprehensive attack on science
Starz Entertainment: Even After The Sharp Rally, Upside Remains
Starz Entertainment remains a compelling Buy with strong tailwinds and an attractive valuation despite doubling YTD. Read more on STRZ stock here.
Deutsche Bank Says Just Half of Business Earned Cost of Capital
Most of Deutsche Bank AG’s business activities still failed to earn their cost of capital last year, demonstrating the long struggle the German lender is facing in generating attractive shareholder returns.
International science cooperation must go on, say research leaders
Science leaders in Europe and Canada say international cooperation must go on amid geopolitical turmoil. At the same time, Europe and like-minded countries should continue to enhance and diversify international partnerships, a Science|Business conference hears. Hugh Brady, president of Imperial College London, told delegates that Europe’s response to the current geopolitical climate should be to “diversify in terms of research partnerships and build resilience and scale into our own system.”A first priority should be for the EU to sort out the scope of the upcoming European Competitiveness Fund and ensure that, together with the next iteration of Horizon Europe, it can drive the development and scale up of new technologies. The EU and the countries associated to the Horizon Europe programme represent “the world's most successful research innovation ecosystem,” Brady said. In order to mitigate the negative effects of shifting geopolitics, the EU together with the UK, Switzerland, Canada, South Korea and others should talk about “building resilience” and address their own “regional needs,” he added. Responding to TrumpUnder Donald Trump’s leadership, the US government has slashed science budgets and shut down international research programmes. Nearly 8,000 grants at the National Institutes of Health and the National Science Foundation have been frozen or terminated. Courts have overturned most of these cancellations, but the disruption caused remains significant. While Europe may persuade a few thousand disgruntled scientists to move across the ocean to work on topics that have been de-funded in the US, it’s unclear what should happen next with transatlantic scientific cooperation more broadly.“Now is the time for us to show [US researchers] our support as much as we can,” Brady said.The European Research Council (ERC), the EU’s basic science funder, has seen a surge in applicants from the US. According its latest data, US-based researchers submitted 347 proposals to the last three big funding rounds, up from 158 in the previous set of calls. The European Commission has also launched a €22.5 million pilot call in 2025 for the Marie Skłodowska Curie Actions, the EU’s researcher training scheme. It plans to extend this support with a €51.25 million call in 2027 as part of the Choose Europe initiative, which is intended to make the continent a more attractive place to pursue a career in research. Related articlesData corner: US researchers are choosing EuropeEU-India deal highlights growing alignment on technology policyMeanwhile, in the private non-profit sector, the Volkswagen Foundation is experimenting with a new type of grant that would allow US researchers to split their time between the US and Germany. While these schemes are useful, Europe should not bet on an exodus of scientists from the US. “The idea that we might all see them flocking over to Europe is naïve and counterproductive,” said Maria Leptin, president of the ERC, also speaking at the Science|Business conference on February 5. “We need research in the US to be as healthy as possible. I really admire those who are staying there with a will to fight and an optimism that the world will turn into a better place again,” Leptin said. Preserving dataDespite political disruption, academics have found ways to continue cooperating and sharing research data. Leslie Weir, president of the International Federation of Library Associations and Institutions and Canada’s national librarian, said the US cuts have raised concerns about research data security, after ideologically sensitive databases were limited or deleted by the Trump administration. But international organisations teamed up to ensure that the data is not lost. “It's interesting to see that researchers and libraries across North America are collaborating to make sure that data at risk is duplicated elsewhere outside [the US],” Weir said.
Lenovo goes MacBook Neo: Hands-on review with Lenovo's best-looking $699 laptop
Consumer laptops do not have to look boring - with the Lenovo IdeaPad vibe, Lenovo goes for a design with a few colorful twists, at an attractive price-point with many useful features. We had a chance to check it out at IFA 2026.
Port of Grandview works to attract new businesses with active marketing and land development
The BriefThe Port of Grandview is actively marketing the community to attract new business development, with efforts including attendance at trade shows and conventions like Food Northwest in Portland.The Port reports strong demand for business property, with several prospective clients currently seeking space to build in Grandview.The Port recently acquired 45 acres for its new Woodworth Road Business Park, with planning underway to support the community's continued growth.GRANDVIEW — The Port of Grandview is capitalizing on strong interest in the community by actively marketing Grandview to businesses seeking locations for expansion and growth. The Port's efforts are paying off, with increased development activity and growing demand for available business property.Grandview's appeal stems from multiple factors. The community's available land and central location between the Tri-Cities and Yakima make it an attractive option for businesses looking to establish or expand operations. The Port has recognized these advantages and is taking a proactive approach to market the community directly to potential clients.Port Executive Director Randy Tucker says the Port has been actively attending trade shows and conventions to promote Grandview as a business destination. These events, including Food Northwest in Portland, provide opportunities to connect with companies actively seeking new locations."Say, hey, locate your business here and bring your customers here. And it's worked out pretty good for us," Tucker said.The Port's marketing strategy is generating results. The Port reports strong demand for business property, with several prospective clients currently looking for space to build in Grandview. This interest reflects the effectiveness of the Port's outreach efforts and the community's appeal to businesses in various industries.To support this growth, the Port recently acquired 45 acres for its new Woodworth Road Business Park. Planning is underway to determine how the property can best support Grandview's continued development and attract additional businesses to the area.The combination of available land, strategic location, and active marketing positions Grandview as an increasingly attractive option for businesses seeking to relocate or expand. As the Port continues its efforts to promote the community, Grandview appears poised for continued economic growth and development. News Three Queens Fire approaching 10,000 acres, now 11% contained Robert Desaulniers, Josh Culbreth News Two injured after rear-end crash leads to rollover near Grandview Robert Desaulniers News Grandview High School temporarily enters secure and teach for possible altercation between students Robert Desaulniers News Port of Grandview pursues economic growth with new business park development William Albert, Apple Valley News Now News Driver dies in fiery crash in Columbia Park Friday Erin Wencl COPYRIGHT 2026 BY APPLE VALLEY NEWS NOW. ALL RIGHTS RESERVED. THIS MATERIAL MAY NOT BE PUBLISHED, BROADCAST, REWRITTEN OR REDISTRIBUTED.
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Polish scientists and students have been flooding social media with calls on the government to raise research and development spending as part of 3% for Science, 100% for Poland, a campaign born earlier this month out of frustration with chronic underfunding in the academic sector. On May 27, thousands took the slogan on to the streets.The EU has been trying to convince member states to raise their R&D expenditures to 3% of GDP for more than two decades, but the idea has never gained traction in capitals. Finance ministers were too busy plugging budget holes created in the aftermath of the 2008 crisis, then the Covid pandemic, the war in Ukraine, and now the war in Iran.Critics say that countries missed or ignored the target because it is voluntary, but also because research communities have rarely raised their voice to put pressure on national governments. The European Commission hopes to make the target legally binding in the upcoming European Research Area Act, an EU-wide regulation that should be announced by the end of the year. Academia in Poland has been faced with a funding crisis for years, often leaving its members with no other choice but to work abroad in order to access better resources, or leave the sector altogether in the hope of earning a decent living. The risk, in the long-term, is that brain drain stifles local innovation capacity and technological competitiveness.In just a few weeks, the movement rallied nationwide support, including from major academic bodies and trade unions such as the Conference of Rectors of Academic Schools in Poland and the Presidium of the Polish Academy of Sciences. Its public petition collected more than 23,000 signatures. On May 27, it formed the first large protest for science in Poland, gathering thousands of people in front of the parliament building in Warsaw.Ilona Uryga-Bugajska, representative of the Marie Curie Alumni Association Poland Chapter, was there. “The protest was peaceful, with no incidents reported, and the entire event took place in a respectful and calm atmosphere,” she said. Banners she saw in the crowd carried slogans such as “A little longer and I’ll be teaching in a supermarket,” “National culture, starvation salary,” “Stop the destruction of science,” “Passion will not pay the rent,” “Without action, don’t expect a better future,” and “Pull science out of the hole.” She also observed a strong presence of young researchers, who are on the frontline of Poland’s academic crisis.“Academics are usually people who prefer discussion, analysis, dialogue and compromise. We are not a group that protests easily,” said Katarzyna Marzec, professor at the Faculty of Pharmacy of the Jagiellonian University Medical College and AGH University of Krakow, who also took part. “But many of us feel that we have been pushed against the wall.”Aleksandra Rutkowska, translational neuroscientist and research group leader at the Medical University of Gdańsk, agreed. “Frustration in the scientific community is very high,” she said. “Science is often used politically as a symbol of innovation and modernity, but the everyday reality inside many institutions is much more difficult. There is a large gap between the public narrative and the actual condition of the sector.”Maria Wiktoria Górna, head of the structural biology group at the University of Warsaw and one of the organisers of the movement, told Science|Business that the campaign would continue without proven results. This might involve another strike in the autumn, she said. “Empty promises are not enough by now.”Campaign demandsAccording to Uryga-Bugajska, the organisers officially presented their demands and concerns to representatives of the government present at the event. These included Marek Gzik, deputy minister of science and higher education, and Karolina Zioło-Pużuk, secretary of state of that same ministry.The headline demand, for the government to increase national spending on R&D to 3% of GDP by 2030, should be within Poland’s economic capacity, Rutkowska said. “The real question is whether there is genuine long-term political commitment to treating science as a strategic priority rather than a slogan.”In 2024, R&D expenditure in Poland stood at 1.41% of GDP, which is slightly above the average for central and eastern Europe, with countries such as Czechia recording 1.82%, Hungary 1.31% and Romania 0.46%. However, it falls noticeably short of the EU average of 2.24%, which just a handful of countries exceed, including Germany, Belgium and Sweden.Campaigners are also asking for fair wages for scientific staff, including PhD stipends and junior academic salaries, which are widely considered uncompetitive. Starting doctoral scholarships amount to some €843 gross per month, when the statutory minimum wage stands at €1,135. By pushing early-career researchers out of Poland, growing precarity has caused a generational gap in the academic workforce, with just 25% of lecturers aged under 40. In this context, the movement fears that scientific careers could soon be accessible to a privileged minority only.Grzegorz Spólnik is a case in point. After 15 years working in mass spectrometry at the Polish Academy of Sciences, he decided to leave partly “to earn enough money to live a normal life,” he said. “At that time, my earnings were similar to those of people working in grocery shops, and the work-life balance is something that does not exist in science, or is very hard to achieve.”Now a senior field service engineer for Polish laboratory equipment supplier Bioanalytic, he would consider going back to research, “but never in the public sector, maybe some start-up or a big private company with ambitious R&D.”The campaigners want to see more support for basic research and have called for €236 million to be added to the budget of the National Science Centre (NCN) in 2027 so that the average grant application success rate does not fall below 25%.“At the protest, there was a banner I particularly liked: ‘NCN is not a lottery.’ Unfortunately, for many researchers, it increasingly feels exactly like one,” Marzec said. “Personally, I am one of the lucky ones. I work at two of the strongest institutions in the country, where the research standards are very high. I know that in many other institutions, the situation is much worse and obtaining funding for research at an early-career stage is becoming nearly impossible.”Rutkowska also considers herself fortunate. After studying abroad and holding a postdoctoral position, she returned to Poland, where her pay was supported through an NCN-funded project linked to the Marie Skłodowska-Curie Actions. “This also made me very aware that good research conditions in Poland often depend on external competitive funding rather than on stable support from the system itself,” she said.Long-term strategyBeyond the lack of funds for both salaries and grants, scientists believe that the issue is structural. “The biggest problem at the moment is the complete lack of a clear long-term strategy for the development of science and research from the current government,” Marzec said. “Everything ends with declarations and promises that are never truly followed by concrete actions or structural reforms.”Rutkowska agreed, citing a lack of infrastructure, continuity and long-term institutional support.“Running a research group in Poland often means functioning as an entire institution at once,” she said. “I am a principal investigator, a mentor, a recruiter, a project administrator and, when needed, still someone who returns to the lab bench to help with experiments,” she went on. “This creates a large hidden workload that takes time and energy away from actual science. At times, it feels as though scientists are no longer expecting extra help; we simply hope the system will stop creating additional obstacles that make research unnecessarily difficult.”Related articlesStrategic thinking: Germany funds joint research with Poland and FrancePoland to transfer €30M of regional funds to boost Horizon Europe participationPoland is funding fewer basic research grants as high inflation hitsIn short, “academics are expected to teach, publish papers, apply for grants and conduct high-quality research, while funding and salaries remain very limited,” said Uryga-Bugajska, who returned to her home country after 13 years in the UK.According to Marzec, another issue is the way that research institutions are evaluated. Previously, this took place every four years, with a clear differentiation between stronger and weaker institutions. “The current government, perhaps to avoid political backlash, effectively concluded that everyone is doing well, so in practice no meaningful evaluation took place,” she said.But in her view, “some form of serious assessment is necessary” to ensure the excellence and international competitiveness of Polish institutions, and to determine how to best use public resources and where institutional structures need reform. “Some institutions may need to rethink hiring practices in order to attract ambitious young researchers who are capable of obtaining competitive grants and building internationally visible research groups.” Rutkowska has already had to adapt. “When hiring PhD students, I often have to combine different funding sources creatively to make positions attractive enough for talented people to stay in science,” she said. “Many young researchers do not see a stable future in academia in Poland, and that is deeply worrying.”
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Chartbook 464 The"China squeeze" - the politics of development counterfactuals.
There are three types of China shock discourse. Each has a distinct temporal register. China shock 1.0 was a phrase coined by US academics in the 2010s to retrospectively summarize the impact on particular US labour markets, which they identified through painstaking empirical investigation. China shock 2.0 on everyone’s lips in Europe in the mid 2020s is an alarm raised by trans-Atlantic policy thinkers warning of a coming disaster which they project onto Europe’s ailing car industry. The third type of China shock discourse - commonly known as the “China squeeze” launched most recently by Indian economists Shoumitro Chatterjee and Arvind Subramanian in the pages of Foreign Affairs - mobilizes a different, more speculative temporal register: the counterfactual realm of alternate history. The China squeeze argument asks not what has happened, or what is going to happen, but what might have been. Specifically, what options for economic development might have been open to Global South economies like India or the economies of sub-Saharan Africa, had it not been for China’s spectacular industrialization since the late 1990s and the persistent competitiveness of China’s manufacture in low-skilled segments. Chatterjee and Subramanian’s argument is that whilst China has built a powerful position in electrical machinery and other high-skill manufacturing, which is now delivering China Shock 2.0, it also continues to run a trade surplus in low-skill, labour-intensive manufacturing. This surplus is large and has remained largely unchanged in fifteen years. Indeed, in the 2010s, in trade with low-income countries, China’s surplus rapidly increased. On their reading, this squeezes low-income producers in low-skill sectors in which they “should” be able to compete. Source: “China’s Mercantilist Squeeze on Developing Countries” Shoumitro Chatterjee and Arvind Subramanian. Peterson Institute for International Economics 26-7 May 2026 Chatterjee and Subramanian’s wording is telling: (emphasis mine) The canonical trajectory of economic development in the post-World War II period is for countries to transition from agriculture to manufacturing, first in low-skilled manufacturing and then later on to high-skill manufacturing (Herrendorf, Rogerson, and Valentinyi 2013). At the global level, this implies that high-income countries (HICs) that once specialized in low-skilled activities cede manufacturing export space to poorer countries that come along to occupy that space. In 1965, advanced economies accounted for about 60 percent of global value-added exports in four key low-skilled manufacturing sectors, i.e., apparel, leather, textiles, and footwear. Over time this share declined and began to be occupied first by the East Asian tigers and, beginning in the late 1990s, by China. Today China accounts for about 50 percent of the global market. The question is whether China, with its rising prosperity, is continuing to behave like its richer counterparts and ceding export space to poorer followers or to behave unlike them and continuing to occupy space. In terms of the conceptual maneuvers it performs, of the three China shock discourses, the “China squeeze” argument is by far the most ambitious. After all, it bases its critique of China on a counterfactual imagining of the world. Like any counterfactual argument, to construct this alternative reality it must rely on a heuristic model. To make their argument Chatterjee and Subramanian mobilize two key claims. The first reference point is the actual history of rich-country industrialization, what they refer to as the “canonical path”. The idea is that countries transition from agriculture to light industry and low-skilled manufacturing and from there up the value chain. To make this useful as a standard of comparison and a means to construct a normative standard, they adjust sectoral export shares for two factors: 1. the underlying level of economic development of the exporting country, as measured by national income and 2. the degree to which the sector in question is internationalized. The idea being that for a high income country to have a high export share in low-skill sectors is anomalous and even more so if that particular product is highly internationalized and thus suitable for being “conceded” to lower-income competitors. Where should this process end? Here Chatterjee and Subramanian introduce their second benchmark. Their normative idea of a global development path is one in which, in due course, low-skill manufacturing exports are distributed in proportion to a country’s share in the global labour force. They imagine, in other words, a world of proportional, polycentric global development without much national specialization in low-skill manufacturing. A useful benchmark is that, in labor-intensive manufacturing sectors, a country’s share of world exports should be broadly commensurate with its share of the world’s low-skilled labor endowment. … In the Heckscher-Ohlin model, this would be true if value added per worker and export propensities, i.e., fraction of output that is exported, are the same across countries. It is this pleasant liberal vista of orderly global development, progressing towards a general distribution of low-skilled manufacturing against which they judge reality and conclude that the low-income countries are suffering a “China squeeze”. China is not exiting low-skill sectors fast enough Allowing for its gdp level and the degree of globalization, China’s share of low-skill manufacturing exports is far higher than it “should” be. Relative to population, its low-skill share of exports is far too high. That in turn yields the conclusion that huge numbers of jobs - the authors suggest tens of millions - are being hoarded by China. For the four sectors captured in figure 4, this excess in value-added exports is $110 billion in 2022. For all low-skilled sectors overall captured in appendix figure D.1, excess value-added exports amount to $365 billion. The crowding out of LMIC exports by China is therefore substantial. Both these claims have in common that they are strong structuralisms. The first is that development paths ought to resemble each other. The second is that broadly speaking as far as low-skilled manufacturing is concerned, all countries are alike. If the world currently diverges from the distribution of trade implied by these assumptions, if China is not following the advanced economy path and has huge exports, this must be the result of “policy”, which the authors then put in question as illegitimate or unfair. Thus the naturalistic construction of a canonical path leading to a “level” distribution of low-skilled manufacturing reveals itself to be a polemical tool. From the point of view of China shock polemics, this discourse is no doubt welcome. But as an account of economic history, it must surely be regarded as nothing short of bamboozling. Development paths do not follow a regular, natural sequence. As David Fishman put it aptly, “development is not a queue”. They are always and everywhere, through and through political. Development is not so much a process, as a project. Each such project is more or less well adjusted to its context. As Gerschenkron taught uneven and combined development implies differentiation rather than simple imitation on a single parth. It may be true that Europe and the US exited relatively early from low-skill work. But clearly technology has changed. As C&S themselves point out, China no longer enjoys a low wage environment. Do they really believe that such huge differences can be accounted for either by industrial policy, which as they admit does not operate powerfully in low-skill sectors, or by exchange rate manipulation? What is overwhelmingly dominant in explaining the persistence of “low-skill” manufacturing in China are surely the network effects of complex supply chains. Indeed the label of “low-skill” may miss the point. The degree of globalization which Chatterjee and Subramanian decide to conjure away in their model of the development path - to allow for the fact that Europe and American textiles exporters did not enjoy just-in-time logistics in the 1950s - obscures the point that the networks through which Chinese factories supply the world are themselves key parts of the low-skill industrialization project. China isn’t knocking out 1970s style “cheap”. It has redefined the entire product cycle. C&S’s casual reference to “T-shirts” is telling. In today’s “fast fashion”, there is weight on both terms. Fashion and fast. China’s success in delivering on both at unprecedentedly high speed and at unprecedentedly low cost, isn’t a low-skill operation at all. If we see development trajectories not as the serial repetition of the same, but as distinctive, crafted projects that cumulate in complex agglomerations of skill, technology and labor, then this explains why the assumption that low-skilled manufacturing should follow the distribution of population flies in the face of all experience. As countless cases attest, low-wage, low-income developed economies are not by themselves the makings of a competitive production base. As Leon Liao puts it quite fairly: “International trade has never been allocated according to population. A country’s population gives it no natural claim to an equivalent share of global exports." And the remarkable fact is that Subramanian alone and with co-authors has long been making this point, not to pillory China, as is the case of the tendentious _Foreign Affair_s and Peterson pieces, but to highlight the great counterpart to China’s industrial success, namely India’s relative failure. The much-quoted Foreign Affairs piece showed low-skill export shares only for China, not for India. If you put both countries in the picture as Chaterjee and Subramanian have done on other occasions, the picture looks like this. China is far above the line, but India, almost as large in terms of population, is no less anomalous, just in the opposite direction. As far as global populations are concerned, and the imagining of tens of millions of “squeezed” jobs, it is this Sino-Indian pair that account for a huge share of the action. What this graph reveals is not China’s cheating, but India’s “greatest development failure”, at least this is the argument made Arvind Subramanian, this time in co-authorship with Devesh Kapur, in their major book, A Sixth of Humanity. Independent India’s Development Odyssey which appeared with Oxford University Press earlier this year. In this highly critical work on India’s development, China is repeatedly evoked, not to criticize but as a benchmark against which to illuminate what India’s political economy has not delivered i.e. large-scale formal employment for hundreds of millions of citizens. Kapur and Subramanian leave no doubt, if you want to understand why China, not India was the main driver of manufacturing globalization from the 1980s, don’t look to slots opening up in the division of labour thanks to the liberal mindedness of advanced economies, look to the contrasting political economy of the Maoist PRC and India’s post-independence political economy. As Kapur and Subramian note: The great divergence between China and India did not begin in 1978 with the Deng reforms—it was well underway by then. In one of the great ironies of modern history, the conditions created by Maoism turned out to be a great launching pad for industrial globalization. As the comparison of India and China in 1980 makes clear, to imagine manufacturing would be equally distributed when populations are so differently endowed in terms of educational and nutritional is fanciful. Here is the data from Kapur and Subramanian, data which I explored back at the very beginning of Chartbook. As Kapur and Subramanian insist, the striking fact is that even as India’s growth accelerated from the 1980s, structural change has not. Formal employment in India lags woefully behind. Why? As Kapur and Subramanian note, the path-dependent impact of India’s poor early start was devastating. The list of factors they mention is long and weighty: We argue for a new five-fold explanation applicable at different stages of Indian history: in the initial stages, the legacy of two key pre-1980s policies, the neglect of agriculture and the strangling of the domestic private sector, were critical. The failure of broad-based agricultural growth militated against rural industrialization, which would have been devoted to satisfying local needs that would have necessarily been labour intensive. Then, when the boom came after 1980, the thicket of regulation and broader labour protections that were legislated prematurely in a nascent democracy, underpinned by a deep ideological aversion to private capital in general and big capital specifically, became a barrier to attaining the size that would be necessary to compete globally. Similarly, the reforms after 1991, while wide-ranging, did not quite encompass non-tradeable inputs critical to manufacturing, namely, land, logistics infrastructure and power. A combination of low investment (logistics infrastructure), regulation (land) and the continued monopoly supply by state governments (power), combined with residual socialism, kept costs at 75–100 per cent above efficient supply. These factors were compounded on the supply side by the government, which dominated the formal labour market and established exorbitantly high wages at the lower end of the skill spectrum. This made their employment in the labour-intensive sector by the private sector less attractive. Finally, when the services sector and its exports boomed, wages soared even further via a Dutch Disease effect: one successful tradeable sector killed and cannibalized another less-skilled tradable sector, namely, manufacturing. Thus, scarcity-inducing policies of the planning era, precocious democracy and a Gandhian aversion to size; inefficient, monopolistic supply of critical non-tradable inputs; the behemoth of government; and super-successful skill-intensive services successively undermined India’s unskilled labour employment opportunities. The employment failure seems to have been over-determined. … Less quantifiable but no less important are some of the sociological factors that have undermined manufacturing and factory jobs. Take the impact of the success of the IT sector—located in urban areas with better working conditions, such as air-conditioned offices, good schools for children and attractive entertainment options. It became a more attractive place for engineering and management graduates to flock to. … Consider manufacturing and female employment. Indian society makes it difficult for women to work, reflected in India’s unusually low female labour force participation (elaborated in Chapter XIII). Indian society, in particular the routine harassment of women in public spaces, makes it even more difficult for them to travel long distances to take up work.37 Combined with onerous regulations on creating hostels and dormitories for women—which, in turn, prevents multiple shifts of operation—factories need to be located in areas with a large female labour pool. While firms can take apparel plants to female labour or bring them to the plants by building large-scale dormitories, this raises costs. If there was a case for subsidies to encourage labour-intensive manufacturing, housing subsidies to build dormitories for women workers would be a good place to start. All of this meant, that when opportunities did open up, in part thanks to adjustments in China, India was in no position to take advantage. Here is the account of the 2020s from Kapur and Subramanian. It stands in dizzying contrast to the one-sided, “China squeeze” argument delivered in the Peterson and Foreign Affairs pieces: In 2022, for example, India’s share of global exports in clothing (the canonical labour-intensive sector) was 3.1 per cent compared to 32 per cent for China. This is extremely disappointing because China started vacating export space in this sector after the Global Financial Crisis as its wages started rising; it then vacated further space in the aftermath of geopolitical developments that led investors to seek alternative investment locations. Between its peak and today, China lost about 7.5 percentage points of global export share (worth about $43 billion in 2022); over this period, India’s export share remained stagnant at 3 per cent, while that of Vietnam and Bangladesh rose by 3.5 to 4 percentage points. China’s loss did not translate into any gain for India in terms of low-skill exports and employment. Put differently, when the conditions for dynamism and prosperity were established after 1991, and even more tantalizingly when the global export opportunities opened up, it was as if India was a high-wage economy and only skilled labour could benefit from the dynamism. It had converted its physically abundant unskilled workforce into an economically expensive resource, penalizing its use. It is not my mission here to argue for or against Kapur and Subramanian’s interpretation of India’s development trajectory. The point in this context is simply that the “China squeeze” such as it is can only be understood, in relation to the heavy burden of domestic constraints that Kapur and Subramanian so unsparingly enumerate. I am concentrating here on India because it is the great counterpart to China and the unspoken reference point of the “China squeeze” discourse. But the point is more general. Can anyone with a straight face suggest that the main problems afflicting the development of South Africa or Nigeria, the great centers of mass underemployment in sub-saharan Africa, are cheap competition from China driven by Beijing’s industrial policy and an undervalued RMB? Likewise, is the main problem of the American working-class the threat of Chinese competition or the manifest crisis of social reproduction in the United States itself? The point here, as in the discourse around China shock 2.0 in Europe, is to insist that we should not normalize the world and pathologize China, without actually investigating what is going on in America’s industrial wastelands, the German car industry, or India’s lopsided labour market. One-sided pathologization should be understood for what it is, a polemical gesture. Concepts like China shock and China squeeze are, what Reinhart Koselleck, following Carl Schmitt, would have described as “asymmetrische Kampfbegriffe”, or “asymmetrical counter-concepts” or “asymmetrical combat concepts”. If the function of arguments like the “China squeeze” is to alert elites in the rest of the world of the need to rejuvenate and energize their development projects, so be it. But let us see the resulting discourses as the mobilizing interventions that they are. Interestingly, a significant slice of China’s public sphere - the so-called industrial party - have been obsessed for the last twenty years with precisely these questions of counterfactual economic history. Since the mid 2000s, a massive online discourse developed around an alternative history in which Chinese techno-patriots were asked to imagine how they would proceed if they had the possibility of traveling back in time to transport modern technology into the Ming dynasty (1368-1644) thus averting the “great divergence” of the 18th and 19th centuries. It is a fantasy of course, but also a goad. The point was not directed at Westerners. The alternate history is dramatically nationalist, but few n the West had even heard of it until recently. The adherents of the industrial party are not liberal moralists. They don’t project natural ladders of international development and ask why others don’t cede space. They take the Realpolitik of global economic development for granted. Their pointe was directed against fellow Chinese. The rallying cry of the alternative narrative was this: Now that we are beginning to gain steam and push forward on our national development path, now that we are breaking out of the inferior position assigned to us even in the early years following WTO accession, do not lose yourself in humanistic imaginings about better futures. In the spirit of Deng, they called on China to embrace the hard truth of development. Perhaps one might of the Industrial Party as a cultural trend born out of desire for symbolic revenge against those who had inflicted the century of humiliation. In terms of the various temporalities of the “China shock” - retrospective, prospective and counterfactual - one might think of the Industrial Policy discourse as truly speculative, conjuring up the China shock that never was. Or perhaps one might better think of it as imagining a world in which a powerful China was no shock at all, but simply a defining fact of modern history. I love putting out Chartbook. I am particularly pleased that it goes out for free to thousands of subscribers around the world. But, writing this newsletter takes a lot of work. If you are enjoying it and would like to support the project, sign up for one of the subscription options here. It is the equivalent of a fancy cup of coffee per month! Subscribe
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Is Flutter Entertainment (NYSE:FLUT) Attractive After A 43% One Year Share Price Decline
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Is PENN Entertainment (PENN) Attractively Priced After Recent 20% Weekly Share Price Jump?
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Polish scientists and students rally in campaign for 3% funding target
Polish scientists and students have been flooding social media with calls on the government to raise research and development spending as part of 3% for Science, 100% for Poland, a campaign born earlier this month out of frustration with chronic underfunding in the academic sector. On May 27, thousands took the slogan on to the streets.The EU has been trying to convince member states to raise their R&D expenditures to 3% of GDP for more than two decades, but the idea has never gained traction in capitals. Finance ministers were too busy plugging budget holes created in the aftermath of the 2008 crisis, then the Covid pandemic, the war in Ukraine, and now the war in Iran.Critics say that countries missed or ignored the target because it is voluntary, but also because research communities have rarely raised their voice to put pressure on national governments. The European Commission hopes to make the target legally binding in the upcoming European Research Area Act, an EU-wide regulation that should be announced by the end of the year. Academia in Poland has been faced with a funding crisis for years, often leaving its members with no other choice but to work abroad in order to access better resources, or leave the sector altogether in the hope of earning a decent living. The risk, in the long-term, is that brain drain stifles local innovation capacity and technological competitiveness.In just a few weeks, the movement rallied nationwide support, including from major academic bodies and trade unions such as the Conference of Rectors of Academic Schools in Poland and the Presidium of the Polish Academy of Sciences. Its public petition collected more than 23,000 signatures. On May 27, it formed the first large protest for science in Poland, gathering thousands of people in front of the parliament building in Warsaw.Ilona Uryga-Bugajska, representative of the Marie Curie Alumni Association Poland Chapter, was there. “The protest was peaceful, with no incidents reported, and the entire event took place in a respectful and calm atmosphere,” she said. Banners she saw in the crowd carried slogans such as “A little longer and I’ll be teaching in a supermarket,” “National culture, starvation salary,” “Stop the destruction of science,” “Passion will not pay the rent,” “Without action, don’t expect a better future,” and “Pull science out of the hole.” She also observed a strong presence of young researchers, who are on the frontline of Poland’s academic crisis.“Academics are usually people who prefer discussion, analysis, dialogue and compromise. We are not a group that protests easily,” said Katarzyna Marzec, professor at the Faculty of Pharmacy of the Jagiellonian University Medical College and AGH University of Krakow, who also took part. “But many of us feel that we have been pushed against the wall.”Aleksandra Rutkowska, translational neuroscientist and research group leader at the Medical University of Gdańsk, agreed. “Frustration in the scientific community is very high,” she said. “Science is often used politically as a symbol of innovation and modernity, but the everyday reality inside many institutions is much more difficult. There is a large gap between the public narrative and the actual condition of the sector.”Maria Wiktoria Górna, head of the structural biology group at the University of Warsaw and one of the organisers of the movement, told Science|Business that the campaign would continue without proven results. This might involve another strike in the autumn, she said. “Empty promises are not enough by now.”Campaign demandsAccording to Uryga-Bugajska, the organisers officially presented their demands and concerns to representatives of the government present at the event. These included Marek Gzik, deputy minister of science and higher education, and Karolina Zioło-Pużuk, secretary of state of that same ministry.The headline demand, for the government to increase national spending on R&D to 3% of GDP by 2030, should be within Poland’s economic capacity, Rutkowska said. “The real question is whether there is genuine long-term political commitment to treating science as a strategic priority rather than a slogan.”In 2024, R&D expenditure in Poland stood at 1.41% of GDP, which is slightly above the average for central and eastern Europe, with countries such as Czechia recording 1.82%, Hungary 1.31% and Romania 0.46%. However, it falls noticeably short of the EU average of 2.24%, which just a handful of countries exceed, including Germany, Belgium and Sweden.Campaigners are also asking for fair wages for scientific staff, including PhD stipends and junior academic salaries, which are widely considered uncompetitive. Starting doctoral scholarships amount to some €843 gross per month, when the statutory minimum wage stands at €1,135. By pushing early-career researchers out of Poland, growing precarity has caused a generational gap in the academic workforce, with just 25% of lecturers aged under 40. In this context, the movement fears that scientific careers could soon be accessible to a privileged minority only.Grzegorz Spólnik is a case in point. After 15 years working in mass spectrometry at the Polish Academy of Sciences, he decided to leave partly “to earn enough money to live a normal life,” he said. “At that time, my earnings were similar to those of people working in grocery shops, and the work-life balance is something that does not exist in science, or is very hard to achieve.”Now a senior field service engineer for Polish laboratory equipment supplier Bioanalytic, he would consider going back to research, “but never in the public sector, maybe some start-up or a big private company with ambitious R&D.”The campaigners want to see more support for basic research and have called for €236 million to be added to the budget of the National Science Centre (NCN) in 2027 so that the average grant application success rate does not fall below 25%.“At the protest, there was a banner I particularly liked: ‘NCN is not a lottery.’ Unfortunately, for many researchers, it increasingly feels exactly like one,” Marzec said. “Personally, I am one of the lucky ones. I work at two of the strongest institutions in the country, where the research standards are very high. I know that in many other institutions, the situation is much worse and obtaining funding for research at an early-career stage is becoming nearly impossible.”Rutkowska also considers herself fortunate. After studying abroad and holding a postdoctoral position, she returned to Poland, where her pay was supported through an NCN-funded project linked to the Marie Skłodowska-Curie Actions. “This also made me very aware that good research conditions in Poland often depend on external competitive funding rather than on stable support from the system itself,” she said.Long-term strategyBeyond the lack of funds for both salaries and grants, scientists believe that the issue is structural. “The biggest problem at the moment is the complete lack of a clear long-term strategy for the development of science and research from the current government,” Marzec said. “Everything ends with declarations and promises that are never truly followed by concrete actions or structural reforms.”Rutkowska agreed, citing a lack of infrastructure, continuity and long-term institutional support.“Running a research group in Poland often means functioning as an entire institution at once,” she said. “I am a principal investigator, a mentor, a recruiter, a project administrator and, when needed, still someone who returns to the lab bench to help with experiments,” she went on. “This creates a large hidden workload that takes time and energy away from actual science. At times, it feels as though scientists are no longer expecting extra help; we simply hope the system will stop creating additional obstacles that make research unnecessarily difficult.”Related articlesStrategic thinking: Germany funds joint research with Poland and FrancePoland to transfer €30M of regional funds to boost Horizon Europe participationPoland is funding fewer basic research grants as high inflation hitsIn short, “academics are expected to teach, publish papers, apply for grants and conduct high-quality research, while funding and salaries remain very limited,” said Uryga-Bugajska, who returned to her home country after 13 years in the UK.According to Marzec, another issue is the way that research institutions are evaluated. Previously, this took place every four years, with a clear differentiation between stronger and weaker institutions. “The current government, perhaps to avoid political backlash, effectively concluded that everyone is doing well, so in practice no meaningful evaluation took place,” she said.But in her view, “some form of serious assessment is necessary” to ensure the excellence and international competitiveness of Polish institutions, and to determine how to best use public resources and where institutional structures need reform. “Some institutions may need to rethink hiring practices in order to attract ambitious young researchers who are capable of obtaining competitive grants and building internationally visible research groups.” Rutkowska has already had to adapt. “When hiring PhD students, I often have to combine different funding sources creatively to make positions attractive enough for talented people to stay in science,” she said. “Many young researchers do not see a stable future in academia in Poland, and that is deeply worrying.”
Scientists found a cannabis compound that relieves pain without the high
Compounds responsible for the aroma of cannabis and many other plants may offer a surprising new way to relieve chronic pain. Researchers found that several cannabis-derived terpenes significantly reduced pain in mouse models of fibromyalgia and post-surgical pain, with one terpene, geraniol, showing especially strong effects. Unlike THC, these compounds are not associated with psychoactive effects, making them a potentially attractive alternative for pain treatment.
Are sports & entertainment becoming the 'anti-AI trade'?
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Charlie Day recalls in horror taking all his clothes off in front of Jennifer Aniston: 'Never felt less attractive'
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Purdue's College of Veterinary Medicine and One Health Innovation District expansion aims to strengthen workforce pipeline
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Family investors turn to old-economy businesses like dealerships and fisheries to avoid AI disruption
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Is PENN Entertainment (PENN) Now Attractively Priced After Recent Share Price Rebound?
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Trump compares White House UFC cage to Eiffel Tower, says 'maybe we’ll never ever take it down'
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Truth and Politics in the Age of Post-Truth
Get E-International Relations delivered to your inbox, free of charge. As you sign up, consider becoming a paid subscriber, or make a donation, to support our work. Subscribe This is an excerpt from Global Politics in a Post-Truth Era. You can download the book free of charge from E-International Relations. The term post-truth is by now so ubiquitous in describing the state of politics in the Western world and even beyond that the most pressing issue of the day appears to be about making democracy work in the era of post-truth rather than questioning the normalisation of the term itself in the first place. The critical turning point appeared to have occurred in 2016 when the term was chosen by the Oxford English Dictionary as ‘The Word of the Year.’ On its website, the Dictionary notes the transformation of post-truth from ‘being a peripheral term to being a mainstay in political commentary and connects ‘the spike in frequency’ directly with the Brexit referendum in the United Kingdom and the election of Donald J. Trump in the United States – both occurring in 2016. Paired with the noun ‘politics,’ post-truth is defined as an adjective ‘relating to or denoting circumstances in which objective facts are less influential in shaping public opinion than appeals to emotion and personal belief.’ The Oxford English Dictionary traces the first use of the term to a 1992 essay in The Nation by the playwright Steve Tesich as he reflected on the 1980s Iran-Contra scandal and the 1990–91 Gulf War: We are rapidly becoming prototypes of a people that totalitarian monsters could only drool about in their dreams. All the dictators up to now have had to work hard at suppressing the truth. We, by our actions, are saying that this is no longer necessary, that we have acquired a spiritual mechanism that can denude truth of any significance. In a very fundamental way we, as a free people, have freely decided that we want to live in some post-truth world (Tesich 1992, 13; emphasis added). He then continued, The Gulf War is over but the war at home goes on. The gulf between rich and destitute widens – between those of us who live in a modern post-industrial nation and those of us who live in the Third World countries of our inner cities. The present administration’s response to this internal crisis has shifted from benign to malignant neglect. The current levels of misery and decomposition of our cities and the economic gulags of our ghettos are acceptable. Since there is only so much hope to go around, there is a freeze on hope. The have-nots have now been reclassified as never-will-haves (Tesich 1992, 13). In the context of Tesich’s essay, truth includes both facts, as in what happens, and ‘moral absolutes,’ as in the ‘self-evident truths mentioned in our Constitution’ (Tesich 1992, 14). Together, these two notions of truth entail the obligation to both act and react. The two passages cited above show that even in the early post-Cold War years, Tesich was already deeply concerned that the American people are neither prepared to act on truth nor react to truth that is disconcerting, or what he calls ‘bad news’ (Tesich 1992, 12). Accordingly, Tesich’s insight as captured by the term post-truth is not that truth is irrelevant to what we know, but rather it is irrelevant to how we act. In contrast, ‘post-truth politics,’ as defined by Oxford as a term that pitches ‘objective facts’ against ‘emotion and personal belief’ such that the latter appears to have overtaken the former in shaping ‘public opinion’ and thereby, democratic politics. When Tesich’s post-truth politics and its current usage are juxtaposed, the two are in fact not identical in terms of what truth is and how it relates to politics. Against such consideration, this chapter provides a critical survey of selected historical events and theoretical considerations for the purpose of gaining a more nuanced understanding of the relation between truth and politics. Truth and Language One notable impact of post-truth politics is that language is being overtly deployed as a political weapon not only by politicians and those in power, but among the general population. It seems that once facts are irrelevant to the validity of what is being said, language becomes the platform for an all-out political contest in which what is said is no more than an act of will expressed as an assertion of power and/or an exercise in defiance. As early as in the writings of Thucydides (460–400 BCE), the vulnerability of logos – which is the human capacity for rational discourse in tumultuous times – was already noted. Thucydides belonged to a school of Greek thought which maintained that language is conventional and that the association between name and things is a result of ‘human use and habit’ rather than ‘nature or divine dispensation’ (Connor 1984, 99). The conventional nature of language means that it is incapable of providing its users with any independent criteria for judgement. In Thucydides’ study of the Peloponnesian War (431–405 BCE), the subversion of logos as seen in the manipulation of language was introduced through his account of the civil war in Corcyra (Thucydides 1972, 236-245). The war first broke out in 427 BCE between the pro-Athenian democratic faction and the pro-Spartan oligarchic faction before it spread to the rest of the Greek world. There was a general breakdown of law and order, resulting in extreme violence and death. Language underwent changes that were reflective of the events of the time. The English philosopher Thomas Hobbes (1588–1679) translated Thucydides’ description of the situation as follows: The received value of names imposed for signification of things, was changed into arbitrary. For inconsiderate boldness, was counted true-hearted manliness: provident deliberation, a handsome fear: modesty, the cloak of cowardice: to be wise in everything, to be lazy in everything... he that had been so provident as not to need to do the one or the other, was said to be a dissolver of society, and one that stood in fear of his adversary. In brief, he that could outstrip another in the doing of an evil act, or that could persuade another thereto that never meant it, was commended (Hobbes 1839–1845, 8: 348; Thucydides 1972, 242-243). What concerned Thucydides most was that the meanings of words are no more than linguistic conventions that require logos to support them. The Corcyrean civil war was a reminder that such capacity cannot be assumed. This is why history understood as an authentic account of what happens matters. Guided by logos, the historian’s task is ‘the search after truth’, which is established through ‘the absence of the fabulous,’ including ‘the rejection of myth and unverifiable stories’ (de Jonge 2017, 2). Thus, history plays an important role in facilitating the stability of language – without which distinctions and judgements cannot be rendered communicable. Just like Thucydides, Hobbes was a nominalist who subscribed to the view that there is no inherent meaning to words. Hobbes’ state of nature, where there is no common authority, is precisely one in which distinctions cannot be made. As Hobbes put it, there is ‘no Mine and Thine distinct’ nor is there distinction between ‘the notions of Right and Wrong, Justice and Injustice’ (1968, 188; emphasis in original). This is clearly an unsustainable condition for everyone. Behind Hobbes’ famous words that life in the state of nature is ‘solitary, poor, nasty, brutish, and short’ is his uncompromising argument for the ‘Leviathan’, which is described by the late American political theorist, Sheldon Wolin (1922–2015), as the ‘sovereign definer’ (Hobbes 1968, 186; Wolin 2004, 238–243). Accordingly, the social contract is importantly a ‘linguistic contract’ that binds all parties to ‘general names agreed upon’ (Peters 1979, 125; Hobbes 1968, 111). Through Thucydides and Hobbes, we can identify a line of thinking that sees politics as a contestation over the use of language, which is based on shared conventions and norms. Thus understood, politics is not a collective quest for the true nature of our being or an epistemological exercise in pursuit of true knowledge. Rather, politics is about humans living with one another by finding a shared language to communicate with one another on matters that affect them all. Truth is in that sense contingent on what is being said as opposed to setting the standard for it. In other words, truth is the embodiment of shareability among us. While truth as such ensures the viability of a political entity, truth by no means represents a normative standard to adjudicate among contesting actors in what they say, let alone in what they do. During Thucydides’ times, ancient China was also experiencing a tumultuous time as the ruling Zhou dynasty deteriorated into the period of the Warring States (481–221 BCE). This was when the rulers of Zhou no longer presided over the territories brought under its control through conquest. Instead of professing allegiance to the Zhou royalty, the lords of these territories became kings themselves to rule over their own land. The period was one marked by endless military campaigns as each of the seven major states aimed to conquer the rest (Lewis 1999). Yet, the period was also known for its intellectual vibrancy as different thinkers challenged the restoring of order among these warring states – including offering ideas and advice to rulers on good governance. Among these thinkers was Confucius (551–479 BCE). His thought, which came to be known as Confucianism, went on to become the state ideology of China from the Han dynasty (206 BCE–222 CE) until the end of the Qing dynasty in 1911 when China became a republic. The founding text of Confucianism was the Analects, which is a collection of dialogues between Confucius and his students as recorded by them. One key concept Confucius advanced is the ‘rectification of names’. Though the term only appears in one exchange in the Analects, it is considered a major aspect of Confucius’ thought. Generations of Confucian scholars from past and present, including Western academics, have debated over its interpretation (Makeham 2003). The passage in question reads as follows: Zi Lu said: ‘The monarch of the state of Wei wants you to govern the country, what is the first thing you plan on doing?’ Confucius said: ‘First it is necessary to rectify the names.’Zi Lu said: ‘Is that really what has to be done? You are being too pedantic, aren’t you now? How will you rectify these names?’Confucius said: ‘Zhong You, you are too unrefined. A gentleman, faced with a matter that he does not understand, takes a skeptical attitude. If names are not correct, one cannot speak smoothly and reasonably, and if one cannot speak smoothly and reasonably, affairs cannot be managed successfully. If affairs cannot be managed successfully, rites and music will not be conducted. If rites and music are not conducted, punishments will not be suitable. And if punishments are not suitable, the common people will not know what to do. So, when the gentleman uses names, it is necessary to be able to speak so that people understand. If one can say it, one can definitely do it. A gentleman should not be careless with words’ (Analects 13:3 in Cao 2016, 148). This translation is offered by the contemporary philosopher Cao Feng. As Cao notes, the passage is what started the whole debate over ‘exactly what kind of names did Confucius... wish to rectify’ (Cao 2016, 148). Of the three major groups of interpretation examined by Cao, beginning with classical Confucian scholarship, one is arguably the most influential and certainly most pertinent to the issue of language and politics. This is the interpretation that was first associated with the Neo-Confucian master, Zhu Xi (1130–1200), who argued that the ‘rectification of names is simply the rectification of politics’ (Cao 2016, 149). Within this interpretive framework, rectification has the dual functions of correction and prescription by ensuring that predetermined hierarchical roles are strictly adhered to through following ‘the system of rites and propriety’ (Cao 2016, 151). In addition, the rectification of names entails ‘using names to rectify actuality’ (Cao 2016, 151). Yet Cao rejects this whole body of interpretive works by arguing that these were ideas developed later. Instead, Cao suggests the following: The original meaning of Confucius’ rectification of names may, then, be quite simple. Confucius did not mean to establish a concrete, normative system of “names”; rather, Confucius was simply the first person in history to realize or remark upon the importance of language in politics. As a politician, he noticed and foresaw the impact that the indeterminacy, ambiguity, and arbitrariness of names would have on politics. Confucius recognized the political consequences of language’s not accurately expressing meaning or not being accurately received by people. He realized the great role that names, as a means of distinguishing right and wrong and establishing norms, could play in society and politics (Cao 2016, 168). Scholarly debates aside, Cao’s view has the advantage of identifying an interpretation of this controversial exchange in the Analects that enables its readers to extrapolate from it the observation that the meaning of words depends as much on their users as on their interpreters; neither of which can be predetermined. Accordingly, a good ruler is someone who can speak without ambiguity to his subjects and make good his words through actions. Stated differently, Cao’s view on what concerned Confucius then, who was living through times of protracted political upheaval, is that language is an indispensable political tool for those in power and can be deployed by both good and bad rulers alike. To sum up, this historical survey shows that politics as a war of words is by no means a distinctive marker of contemporary politics nor the Western world. Be it ancient or current, east or west, language is subject to manipulation to serve political purposes and when there is an outright war of words that defies existing norms, it is indicative of a political situation in which people no longer share a language and truth becomes irrelevant. Accordingly, political order entails stability in language use. Truth and Politics As previously noted, current use of the term post-truth as an adjective to the term ‘politics’ suggests that once there was a time when politics aligned with truth. Indeed, if we start with Plato’s Republic as the key founding text of Western political thought, we see that the ideal polis (city-state of ancient Greece) is where truth and politics converge, and justice is achieved. Written around 380 BCE when Athens was still coping with its defeat by the Spartans in the Peloponnesian War, the Republic is a defence of the rule of the ‘philosopher king’, defined as someone who is ‘guided by the truth’ and is ‘always and in every way’ in pursuit of the truth (Plato 1974, 490a). For Plato, truth converges with virtues and hence, letting the philosopher take charge of politics is to let the wisest and the most virtuous lead the less wise and the less virtuous even if it requires compulsion (Plato 1974, 499b). In Plato’s words, ‘…until the philosophers attain power in a city there will be no respite from evil for either city or citizens…’ (Plato 1974, 501e). The uncompromising rule of philosopher-kings is made palatable by the claim that we are all ‘earth- born brothers’ with random mixtures of gold, silver, bronze and iron, but only the gold can rule (Plato 1974, 414–415). Understandably, academic debates over the interpretation of Plato’s Republic revolve around the question of whether truth as attained in philosophy can be realised in politics as action and whether such a connection is even desirable. Without getting into the details of these scholarly exchanges, I suggest that they all share the concern that truth acquired through the rigorous process of philosophical reasoning is not without problem when applied to the real world of living humans. This is because not all humans are philosophers – and indeed, in Plato’s view, not everyone is capable of becoming a philosopher given the protracted and arduous training that one needs to endure to become one. Hannah Arendt (1906–1975), a highly influential political philosopher of the twentieth century, notes that ‘Plato was the first to introduce the division between those who know and do not act and those who act and do not know’ and that such a separation has remained ‘at the root of all theories of domination’ (Arendt 1958, 223, 225). What Arendt points out in this remark is not the gap between theory and practice, but rather that Plato provides the normative ground for those who know the truth to tell those who do not know what to do. Arendt herself took on the challenge of understanding the relationship between truth and politics through her analysis of Nazism and Stalinism. Arendt’s insight, which was controversial when The Origins of Totalitarianism was published in 1951, was to identify Nazism and Stalinism as representative of a new form of political rule – totalitarianism – making it distinct from ‘other forms of political oppression... such as despotism, tyranny and dictatorship’ (Arendt 1973, 460). Arendt defines totalitarianism as a self- contained system of ideas driven by their ‘logic’ and marked by a mode of reasoning called ‘ideological thinking.’ Ideological thinking as such is a distinctive form of political reasoning defined by three characteristics. First, ideological thinking claims to provide a ‘total explanation’ of all historical happenings, encompassing the past, the present, and the future. Second, while ideological thinking is an attempt to account for ‘factual reality’ in its totality, this mode of thinking is paradoxically divorced from reality and experience. This is because experience, being rooted in specificity, is clearly limited in its claim to totality. It follows that as its third characteristic, ideological thinking aims to emancipate thought from the limitation imposed by experience through a ‘specific method of demonstration.’ The method involves arranging facts into an ‘absolutely logical procedure’ that starts from an ‘axiomatically accepted premise’. It is, in short, a ‘process of deduction from a premise’ – which is the only possible movement in the realm of logic that leads to one definitive conclusion. This is how the ‘logicality of ideological thinking’ provides the basis for total explanation and the ‘principle of action’ for totalitarian movement (Arendt 1973, 468–474). Stated differently, totalitarianism is a form of uncompromising idealism that exists in one’s head irrespective of shared reality as experienced. It is the perverse form of what Arendt later refers to as ‘rational truth’, which is the product of the ‘speculative mind’ that belongs to philosophy, mathematics and the sciences. The ‘speculative mind’ is the mind working on its way to generate axioms and theories by relying on the cognitive capacity of the human brain (Arendt 1977, 231). The presence of others has no bearing whatsoever on rational truth. In contrast, ‘factual truth’ is what happens when humans are ‘living and acting together’ (Arendt 1977, 231). Factual truth is therefore particular and temporal by definition. But more importantly, factual truth is ‘political by nature’ because it can only be validated in the context of the human community (Arendt 1977, 238). In other words, factual truth is about humans in their plurality rather than in their singularity. For factual truth to be sustainable, we need what Arendt calls ‘common sense’ – understood as ‘community sense’ (Arendt 1982, 72). There is also another distinction about truth that Arendt makes which is pertinent to understanding how totalitarianism works. The issue is whether the so-called totalitarian ideology is simply an unnecessarily cumbersome way of saying that it is an all-round and polished lie. Here, Arendt calls totalitarian ideology the ‘modern lie’ – in contrast to the ‘traditional lie’. The latter is restricted by two conditions: that it is a lie about the ‘particulars’ and that it deceives only the ‘enemy’ – which means that the liar is not engaged in self- deception. The modern lie, however, involves a ‘complete rearrangement of the whole factual texture’. It also intends to deceive everyone alike, to the extent that those who initiate the lie eventually ‘fall victims to their own falsehood’ (Arendt 1977, 249–254). This distinction between the traditional and modern lie is important. It indicates that not only is totalitarianism a lie, but the lie is in fact too big to fit into the standard meaning of the word. To tell a lie from truth, we need a common standard. In the case of a traditional lie, the common standard is precisely ‘the fabric of factuality’. As such, a lie always appears as a ‘tear’ to that fabric. Yet, modern lies require making a surrogate reality with a completely different context for facts to fit ‘without seam, crack, or fissure, exactly as the facts fitted into their original context’. Arendt notes that as long as those who concoct the surrogate reality are prepared to engage in self- deception to ‘create a semblance of truthfulness’, there is nothing to prevent ‘these new stories, images, and non-facts from becoming an adequate substitute for reality and factuality’ (Arendt 1977, 253–254). Totalitarianism therefore requires a person to stand outside of the system itself in order to make sense of it. Arendt points out that it is futile for us to argue with (for example) a Nazi or a Stalinist on race or class. To confront totalitarianism requires more than just a confrontation with specific facts. It is a more fundamental confrontation between reality as experienced and its total rejection. This means that Nazism and Stalinism are more than radical ways of conducting racial conflict or class struggle. Rather: Totalitarian politics – far from being simply antisemitic or racist or imperialist or communist – use and abuse their own ideological and political elements until the basis of factual reality, from which the ideologies originally derived their propaganda value– the value of struggle, for instance, or the interest conflicts between Jews and their neighbours – have all but disappeared (Arendt 1973, xv). Accordingly: The ideal subject of totalitarian rule is not the convinced Nazi or the convinced Communist, but people for whom the distinction between fact and fiction (that is, the reality of experience) and the distinction between true and false (that is, the standards of thought) no longer exist (Arendt 1973, 474). Who then is the ‘ideal subject’ of totalitarianism? Although there is a revival of interest in Arendt’s observation on truth and politics since the onset of post- truth politics, not enough has been said about her reply to the question (Hyvönen 2018; Klinkler 2018; Lee 2019; Zerilli 2020). Yet if we take a look at Arendt’s portrait of this ideal subject, her view is even more pertinent to our current challenge. As a self-contained system of ideas that is detached from experience, totalitarian thinking offers consistency in ways that reality cannot. Arendt notes that this kind of consistency is especially appealing to those who have lost a sense of bearing in the world (Arendt 1973, 353). They constitute what she calls the ‘masses’. The ‘mass man’ is thus a highly isolated and atomised individual, who is ‘obsessed by a desire to escape from reality’ (Arendt 1973, 318, 352). In his ‘essential homelessness’ the mass man can ‘no longer bear its accidental, incomprehensible aspects’ (Arendt 1973, 352). This longing for escape from reality is a ‘verdict against the world’ in which one is ‘forced to live’ but ‘cannot exist’ (Arendt 1973, 352). Such a situation is ripe for the ‘revolt of the masses’ against ‘common sense,’ which is ‘the result of their atomisation, of their loss of social status’ and with it, the ‘whole sector of communal relationships in whose framework common sense makes sense’ (Arendt 1973, 352). In short, the masses are people who are considered to be ‘superfluous or can be spared … [who] cannot be integrated into any organisation based on common interest’ (Arendt 1973, 311). Whether one agrees with Arendt’s analysis of the social conditions in the interwar years that led to the formation of the ‘masses’, her portrait of the ‘mass man’ is a powerful account of what can happen to an individual who has become disposable to the society that they used to belong to. Hand in hand with this phenomenon is indeed the collapse of ‘common sense’ that leaves the dislodged individual scrambling for reconnection. By offering the masses a substitute reality validated by the ‘logic of an idea’ rather than by experience, totalitarianism makes it possible for them to live in a world where there is no condition of plurality. Between ‘facing the anarchic growth and total arbitrariness of decay’ and ‘bowing down before the most rigid, fantastically fictitious consistency of an ideology’, the masses will likely ‘choose the latter’ (Arendt 1973, 352). A world created by ideology, then, is more attractive to the masses not because ‘they are stupid and wicked, but because in the general disaster this escape grants them a minimum of self- respect’ by conjuring up ‘a lying world of consistency which is more adequate to the needs of the human mind than reality itself’ (Arendt 1973, 353). Moreover, it is precisely this ability to guarantee consistency that makes it possible for the leaders of totalitarian movements to demand ‘total, unrestricted, unconditional and unalterable loyalty of the individual member’ (Arendt 1973, 323). While this chapter is not a study of the social factors that led to specific contemporary developments such as the result of the Brexit referendum or the election of Donald Trump in 2016, Arendt’s ‘mass man’ seem to have found their counterparts among the supporters of Brexit and Trumpism. Studies of voters’ profiles in both events point to a disproportionate share of supporters from white male lower income backgrounds without university educations. These are individuals who have either already lost their jobs to globalisation or who are at high risk of losing their job with very little capacity to be retrained for the twenty-first century market economy of advanced industrialised states (BBC 2016; Pew Research Center 2018). In short, these displaced workers are part of the tapestry forming the modern equivalent of Arendt’s ‘mass man’ – ready to be the recruits of totalitarianism. Conclusion If we step back to take a more comprehensive approach to the relationship between truth and politics, both historically and theoretically, it is not so obvious that 2016 is a defining moment. From ancient China and ancient Greece to our so-called post-truth age, the indeterminacy of language appears to be a persistent political challenge. Language is always open to manipulation by its users to serve power. Nonetheless, the tendency these days is to single out the ubiquity of social media and the proliferation of Internet platforms as the incubator for the countless cyberwars of words that in turn fuel the real world of politics. In this context, language is no longer the conveyor of objective facts and accurate information, but rather the medium for expressing subjective opinions and feelings, as captured by the Oxford Dictionary’s definition of the term ‘post-truth politics’. In contrast, the historical approach used in this chapter shows that it is in fact too easy to point the figure at the Internet and digital communication for the political challenge that we face today. What is being suggested here is that with or without the Internet, language, be it used to convey facts or emotions, is simply a tool for communication that humans have invented. While language per se cannot adjudicate what is true or not true, what is right or wrong, it embodies such capacity when language is a shared norm. That shared norm cannot be sustained without some semblance of cohesion in any given community. Any war of words, irrespective of its platform, is indicative of the breakdown of such cohesiveness. Returning to the original context in which the term post-truth politics was first used by Steve Tesich helps to identify the important distinction between truth as the standard for knowledge and truth as the standard for action. The two do not necessarily coincide. Placed in the context of the history of political thought, this distinction is in fact at the heart of Plato’s Republic. Yet when the philosopher as the quintessential bearer of truth becomes king, the polis that he rules over is far from the ideal of a just state that it purports to be. Instead, it is one that is held together by lies and coercion. What Arendt reveals through her study of Nazism and Stalinism is that it is dangerous for the kind of truth that philosophy generates – ‘rational truth’ – to become the guide to politics. Politics guided by rational truth can only be uncompromising and follows a logic of its own that cannot afford the ambiguity and indeterminacy of reality as lived experiences of humans. A world of post-truth politics can be an opportunity for a new kind of politics if it is indeed about dismantling the idea that truth is the ideal that politics should strive for. But as it stands, the post-truth politics of today is more about invoking a past that never exists to judge the presence as a crisis in naming when the real crisis is about rebuilding a shared space that has room for all – be they of the left, right or centre; cosmopolitan or parochial; civic-minded or self-centred; liberal-minded or bigoted. Politics is and always will be about striving for that space, without which no human can thrive. References Arendt, Hannah. 1958. The Human Condition. Chicago: The University of Chicago Press. Arendt, Hannah. 1973. The Origins of Totalitarianism. Rev. ed. New York: Harcourt Brace Jovanovich. Arendt, Hannah. 1977. “Truth and Politics.” In Between Past and Future, 227–264. New York: Penguin Books. Arendt, Hannah. 1982. Lectures on Kant’s Political Philosophy, edited by Ronald Beiner. Chicago: University of Chicago Press. British Broadcasting Corporation. 2016. “Brexit vote: The breakdown.” BBC News, December 7, 2016. https://www.bbc.com/news/uk-politics-38227674 Cao, Feng. 2016. “A New Examination of Confucius’ Rectification of Names.” Journal of Chinese Humanities 2: 147–171. https://doi-org.subzero.lib. uoguelph.ca/ doi/ 10.1163/23521341-12340032. Connor, W. Robert. 1984. Thucydides. Princeton: Princeton University Press. de Jonge, Casper C. 2017. “Dionysius of Halicarnassus on Thucydides.” in The Oxford Handbook of Thucydides, edited by Sara Forsdyke, Edith Foster, and Ryan Balot. Oxford University Press. DOI: 10.1093/ oxfordhb/9780199340385.013.17 https://www-oxfordhandbooks-com.subzero. lib.uoguelph.ca/view/10.1093/oxfordhb/9780199340385.001.0001/oxfordhb-9780199340385 Hyvönen, Ari-Elmeri. 2018. “Careless Speech: Conceptualizing Post-Truth Politics.” New Perspectives 26 (3): 31–55. https://www.proquest.com/ scholarly-journals/careless-speech-conceptualizing-post-truth/ docview/2204515132/se-2?accountid=11233. Hobbes, Thomas. 1839–1845. The English Works of Thomas Hobbes, edited by Sir William Molesworth. London: John Bohn. Vol. 8. Klinkner, Melanie. 2018. “Reasonable Truth.” International Journal of Media & Cultural Politics 14 (3): 393–99. doi:10.1386/macp.14.3.393_7. Lee, Haiyan. 2019. “When Nothing Is True, Everything Is Possible: On Truth and Power by Way of Socialist Realism.” PMLA/Publications of the Modern Language Association of America 134 (5). Cambridge University Press: 1157–64. https://doi.org/10.1632/pmla.2019.134.5.1157 Lewis, Mark E. 1999. “Warring States Political History.” In The Cambridge History of Ancient China: From the Origins of Civilization to 221 BC, edited by Michael Loewe and Edward Shaughnessy, 587–650. Cambridge: Cambridge University Press. Makeham, John. 2003. “Zheng ming (Rectification of names).” In RoutledgeCurzon Encyclopedia of Confucianism, edited by Xinzhong Yao. Vol. 2: 813-814. New York: Routledge. Oxford Languages, n. d. “Word of the Year 2016.” Accessed 19 August 2017. https://languages.oup.com/word-of-the-year/2016/ Peters, Richard. 1979. Hobbes. Westport: Greenwood Press. Pew Research Center. 2018. “An examination of the 2016 electorate, based on validated voters.” Report, August 9, 2018. https://www.pewresearch.org/ politics/2018/08/09/an-examination-of-the-2016-electorate-based-on- validated-voters/ Plato. 1974. Republic. Translated by G. M. A. Grube. Indianapolis: Hackett. Tesich, Steve. 1992. “Watergate Syndrome: A Government of Lies.” The Nation: 12-14. January 6/13, 1992. Thucydides. 1972. The Peloponnesian War. Translated by Rex Warner. Harmondsworth, England: Penguin Books. Wolin, Sheldon. 2004. Politics and Vision: Continuity and Innovation in Westen Political Thought. Expanded Edition. Princeton: Princeton University Press. Zerilli, Linda M. G. 2020. ‘Fact-Checking and Truth-Telling in an Age of Alternative Facts.’ Le foucaldien 6, no. 1: 2, 1–22. Theresa Man Ling Lee is an Associate Professor of Political Science at the University of Guelph (Canada). Lee is a political theorist who specializes in contemporary political thought. Her research and teaching areas include continental philosophy, Marxism and critical theory, feminism, postmodernism, philosophy of social science, psychoanalysis, multiculturalism, human rights, disability studies, modern Chinese political thought and comparative political theory. Lee has published on a wide range of subjects in these areas, including intercultural pedagogy and the challenges of teaching as a person with multiple minority designations in a Canadian university classroom.
With navigating nematodes, scientists map out how brains implement behaviors
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Why America's super rich have embraced the appeal of British soccer teams
American investors now control more than half the Premier League. CNBC examines why U.K. soccer clubs have become attractive long-term assets.
Is Germany benefitting yet from the crisis in US research?
Science|Business - Table.Media partnershipScience|Business has partnered with Table.Media, a leading source of news about higher education and research in Germany. Each week, we are publishing one of each other’s stories to give readers an even broader range of insight into R&D policy across Europe.Drawing over 500 participants, the German Academic International Network conference in San Francisco brings together researchers, universities, scientific organisations and policymakers in the US as part of an attempt to recruit international talent for Germany. It also serves as an annual barometer for the uncertainty triggered by the Trump administration’s science policies. As was the case last year, Germany’s political presence was unusually strong: federal lawmakers, nine state ministers of science and research, and federal research state secretary Marcus Pleyer all attended. Joybrato Mukherjee, president of the German Academic Exchange Service (DAAD), has observed a marked shift at US universities a year after the Trump administration began sweeping interventions: the initial state of "shock and paralysis" has given way to a strategic approach to the situation. Universities are seeking new funding sources, mounting legal challenges against interventions and opening themselves up more to international collaborations, including with Germany, he said. Early-career international researchers with expiring visas are considered particularly vulnerable. Germany is benefiting from increased demand among this pool of young talent; the country’s 1,000 Minds Plus programme, designed in part to lure German academics back home, has already filled up around one-third of its capacity. Meanwhile, Markus Blume, Bavaria’s science minister and current chair of the federal Conference of Science Ministers, sees an "enormous outflow of talent from the US." An increasing number of international researchers want to leave. Applications to Canada have risen by 42% January, and those to Europe by 32%. Meanwhile, the number of people drawn to the US is plummeting. "In this context, Germany must position itself as a prime destination offering reliable conditions, institutional stability and academic freedom, including through smart collaborations," Blume told Table.Briefings.“Darkest hour”At the get-together in San Francisco, the former president of the US National Academy of Sciences, Marcia McNutt, highlighted the gravity of the situation on the ground in a keynote address. She described the present moment as the "darkest hour for the US scientific system." At the same time, she said that cooperation should be maintained, especially during a crisis. Established researchers in the US are less likely to leave. Ulrike Malmendier, a former member of the German Council of Economic Experts and an economist at Berkeley, explained why established researchers are not packing their bags and leaving the US in droves: working conditions and the concentration of talent at places like Berkeley and Stanford remain unparalleled. According to Peter-André Alt, managing director of the Wübben Foundation, which helps Germany attract international academics, political restrictions are not the only grievance voiced by US-based researchers. "There are evidently still many areas where, fortunately, unfettered research is possible," Alt told Table.Briefings. Instead, the primary complaint concerns the cost of living, which has "skyrocketed” to absurd levels. "Runaway inflation, like that currently seen in the US, is certainly no draw for young scientific talent,” he said. Return homeA growing number of early-career researchers from Germany appear to be considering a return home. Jörn Benzinger, who is responsible for recruiting early-career researchers from abroad at Ruhr University Bochum, reports numerous conversations with researchers who are taking a closer look at the German academic landscape."Germany has definitely moved more into the spotlight,” he said. States, university alliances and research organisations joined forces to recruit talent. Bavaria, Baden-Württemberg and North Rhine-Westphalia were prominently represented, as were alliances such as the Berlin University Alliance and the University Alliance Ruhr. Benzinger sums up Germany’s approach with a new formula: "collaboration is the new competition." He notes that it is becoming increasingly difficult for individual universities to gain international visibility, while regional research ecosystems and collaborations are growing in importance. Afraid to leaveThe crisis in the US academic sector is also straining transatlantic research relations. Benzinger reports that some US-based researchers had to decline brief invitations to Germany because they could not be certain of being allowed to re-enter the US afterward.He considers the simple poaching of researchers to be the wrong approach; what is needed, he says, are "reliable offers and long-term partnerships."However, Green Party politician Ayşe Asar, who also attended the conference, sees a significant need for improvement, particularly regarding career paths in Germany.While lifetime professorships and academic freedom certainly make Germany attractive, young researchers also require predictable career paths, tenure-track positions and flatter hierarchies.
Intel Core Ultra 5 250K Plus Review - Disrupting AMD's Entry-Level
Intel is breathing new life into its Arrow Lake lineup with the Core Ultra 5 250K Plus. Priced at an attractive $200, this little powerhouse outperforms most AMD CPUs in applications and delivers competitive gaming performance, too. It's a strong contender for budget-friendly builds, and overclocking potential is good, too.
Towns along Mississippi now offer shops, recreation, entertainment
As traditional industries along the river fade, towns along the Mississippi have found new ways to remain attractive and lively.
How The Investment Story Is Shifting For Phibro Animal Health (PAHC) After Fresh Analyst Targets
Analysts have lifted their price target on Phibro Animal Health by $4, while the model fair value remains at $48.50. That gap reflects a refreshed research view, with some seeing a more attractive balance between risk and reward and others still highlighting execution and valuation sensitivity as key watchpoints. As you read on, you will see how this evolving narrative might shape your own thinking on the stock over time. Stay updated as the Fair Value for Phibro Animal Health shifts by...
Scientists discover natural hormone that reverses obesity
A hormone called FGF21 can reverse obesity in mice by activating a newly identified brain circuit tied to metabolism. Surprisingly, it works in the hindbrain—the same region targeted by GLP-1 drugs like Ozempic and Wegovy—but through a completely different mechanism. Instead of suppressing appetite, FGF21 ramps up the body’s energy burning. This insight could pave the way for more targeted weight-loss and liver disease treatments.
H.264 streaming license fees were raised to as much as $4.5 million, open standards now look even more attractive
Via LA raises H.264 streaming fees for new licensees, existing deals stay unchanged Via Licensing Alliance has updated its H.264, also known as AVC,
Is Live Nation Entertainment (LYV) Pricing Fair After Strong Multi‑Year Share Gains?
If you are wondering whether Live Nation Entertainment is priced attractively today, it helps to step back from the headlines and look closely at what the numbers are saying about the stock. The shares recently closed at US$146.97, with returns of 1.8% over the past week, 0.8% over the last month, 1.1% year to date, 4.4% over 1 year, 82.9% over 3 years and 121.2% over 5 years. These figures may shape how the market currently views its potential and risks. Recent news coverage around Live...
Geena Davis said she was told she wasn’t attractive enough to star in ‘Fletch’
Geena Davis recalls being told she ‘wasn’t attractive enough’ to star in 1985’s ‘Fletch.’
9 software stocks that are attractive to buy now: Morgan Stanley
After Anthropic's latest AI tools sparked panic in tech stocks last week, investors are grasping for answers on where the sector goes from here.
🚨 Tigres v Chivas line-ups confirmed
Tigres hosts Chivas this afternoon at El Volcán in one of the most attractive matches of the weekend. Guido Pizarro’s side will look to take all three points from the league leaders, which would he...
San Diego Padres’ Booming Business Made Them an Attractive Buy
The Southern California-based franchise is the 10th-best revenue generating club in MLB, and that number is poised to keep growing.