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SM Entertainment founder's A2O Entertainment to debut A2O Soul and A2O Lite
A2O Entertainment will debut boy band A2O Soul and girl group A2O Lite together, with former SM producer Yoo Young-jin overseeing their music and performances.
Lee Soo-man’s A2O Entertainment debuts A2O Soul and A2O Lite
A2O Entertainment will debut boy band A2O Soul and girl group A2O Lite together, with former SM producer Yoo Young-jin overseeing their music and performances.
Netflix Executive Says AI Has Touched 300 Titles as Director Claims Budget Savings of Up to 40%
Netflix says it has used AI on about 300 titles, while director Kang Yoon-sung told a Busan festival panel that AI workflows can cut film…
The Harvard Crimson (@theharvardcrimson)
24 likes, 0 comments - theharvardcrimson on October 5, 2026: "Caroline B. Kennedy ’80 introduced the Institute of Politics’ 60th anniversary forum Thursday, marking her first known public appearance at the Institute since she resigned from its Senior Advisory Committee more than six years ago. Kennedy — the daughter of President John F. Kennedy ’40, to whom the IOP is dedicated – stepped down as the committee’s honorary chair in 2020 amid concerns over the IOP’s diminished independence, declining programming, and tensions with Harvard Kennedy School leadership. Full story linked in bio. 🖋: Jen L. Phan and Mirei S. Saneyoshi 📷: Grace E. Yoon".
State Senate Democratic Committee: Robyn Vining earns Recombobulation Area endorsement, highlighting her effective legislative record
MADISON, WI – State Representative Robyn Vining’s campaign for State Senate has earned the endorsement of The Recombobulaiton Area and Dan Shafer. During their conversation on The Recombobulaiton Area podcast, Robyn and Dan highlighted her path to political life, her...
The Best Workout for Lowering Blood Pressure Over 45, According to New Research
A new study suggests that a circuit training routine involving cardio and strength exercises could be most effective for reducing blood pressure.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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If Not AOC, Then Who?
What do we do if Alexandria Ocasio-Cortez decides not to run for president in 2028? It makes sense that many leftists are currently focused on calling on her to take the plunge. But the absence of a Plan B, or even much discussion about one, is worrisome. The US Left can’t afford to sit out the 2028 Democratic primary. Doing so in 2024 was a disaster: our abstention self-marginalized anti-billionaire politics from the national conversation and thereby gave space for Harris to pivot to the “center” (i.e. the policy preferences of corporate donors, establishment hacks, and AIPAC). Abstaining again in 2028 would be especially counterproductive since democratic socialists now have so much wind in our sails after our big electoral wins in NYC and across the country. It’s time to deepen our momentum, organization, and profile — not to retreat to the margins during America’s single most important political battle. Even more urgently, keeping Trump’s heir out of the White House may depend on whether leftists and the party’s unprecedentedly disenchanted base can force the Democrats in 2028 to take meaningful steps towards a very angry electorate and away from the corporate-consultant blob that has helped get us into this mess. If AOC (or Abdul El-Sayed) decides to run, we should enthusiastically go all in — DSA, fighting unions, progressive organizations, anybody who wants to see a better country and world. But, as far as I can tell from the outside, there’s a real chance that she doesn’t run. And we can’t just wait and see where she lands before discussing alternatives, since AOC’s decision might not come for quite a while, giving us little time to scramble at the last minute for an alternative. So we should start working now on getting a Plan B into motion, and recruiting a good candidate for the role. Here’s one idea. A Worker Candidate — Healthcare Not Warfare 2028 Run a union worker Leftists don’t need to always run experienced, well-known socialist politicians for high-profile contests. Lula, the current president of Brazil, began his political career as a metalworker militant who ran for governor of São Paulo in 1982. Especially in an era of institutional distrust, it’s possible to lean hard into making a virtue out of a working-class comrade’s distance from traditional politics. Experience abroad shows this clearly. Rachel Kéké — an immigrant hotel housekeeper — ran as the candidate of the leftist La France Insoumise for the National Assembly in 2022, defeating a former minister in the Macron government. The Belgian Workers’ Party in 2024 won its first Flemish seat in the European Parliament by running Rudi Kennes, a three-decade veteran of the Opel Antwerp auto factory. And the South Korean left in 2024 elected auto factory militant Yoon Jong-oh to the National Assembly. If a tiny French Trotskyist organization could make such a big splash in 2002 and 2007 by running a well-spoken postal worker cadre for office — the LCR’s Olivier Besancenot received about 1.5 million first-round votes — it’s not far-fetched to expect that a much larger organization like DSA, together with a broader coalition of the willing, could run this playbook to much greater effect. This is especially the case now that almost everything DSA does immediately becomes a national news story. We don’t need someone famous. We just need a charismatic, well-vetted comrade who works in a relatable working-class occupation — e.g. a nurse, or a worker in auto or construction, or at Amazon. Ideally, they have a compelling personal story or have been part of a significant strike or organizing campaign, but even those criteria don’t necessarily have to be deal-breakers. The main lesson of the Graham Platner fiasco isn’t that we should never run outsiders for office (the momentum he generated proves the exact opposite), but that they need proper vetting and roots in democratic membership organizations like DSA or a union. In any case, there are plenty of ways to signal working-class authenticity without resorting to Platner’s or Fetterman’s performative macho white dude affect. Better to have someone of any gender or race who is actually working class, with firm socialist politics, who can speak from experience about the day-to-day realities of trying to make it in America. There are surely at least a dozen such worker leaders in our movement nationwide; we just need to sit down and convince one that their personal sacrifice for the greater good (i.e. running for president) will be worth it. If we don’t have a frontrunner with a clear path to victory like AOC (or El-Sayed, were he to win Michigan), it’s better to embrace someone whose decision to run in itself tells an important story about US politics: workers have been iced out of our political system and are now fighting hard to break back in. The novelty factor, in itself, would generate press. And it would help democratic socialists signal to the American public that our movement’s defining characteristic is that we represent workers vs. bosses, not that we’re “the furthest left” force in American politics — a framework that suggests we’re extremists and that helps our opponents isolate us from non-college-educated voters by highlighting extremely minoritarian (and misguided) stances included in DSA’s platform like prison abolition. We don’t get many opportunities to speak to tens of millions of Americans; we need to use these opportunities to broaden our appeal beyond those already in our orbit. Run to polarize the 2028 primary and general election around “Medicare for All” and “End All Aid to Israel” Why should democratic socialists use our scarce time and volunteer energy to run in a race we’re unlikely to win? Running in the 2028 primary will not only recruit us scores of members (imagine having a DSA member intervening in eleven nationally televised primary debates!), but — more importantly — it has the potential to be a decisive leap forward towards an America that finally starts meeting the needs of working people instead of HMO and AIPAC billionaire donors. Polarizing litmus tests are good, actually — as long as they’re fought for around popular demands in a thoughtful and strategic way. Democratic socialists have an opportunity and responsibility to make the 2028 primary about two of the most widely and deeply felt issues of our moment: domestically, America’s unaffordable, family-breaking private healthcare system; internationally, America’s bankrolling of the genocidal Israeli government. A candidacy relentlessly demanding Medicare for All and No Aid to Israel would pose a sharp question to the American public, the Democratic Party, and other 2028 contenders: Why can’t working-class Americans afford their healthcare bills at the same time that our government is spending at least $3.8 billion yearly to fund an Israeli regime eager to keep dragging us and the world into more forever wars? Our candidate can agitate around a clear message: I’m running to give voice to all those working-class Americans who are struggling to get by. No matter what state you live in, who you voted for in 2024, or your background, it’s just plain common sense that we should make healthcare more affordable instead of spending billions to enable the Israeli government’s crimes against humanity. Every American who agrees with me when I say ‘Medicare for All — Not a Dime for Israel’ should make their voice heard through our campaign. Racking up a high number of votes for this agenda is a crucial way to show the Democratic Party and the country as a whole that we can’t keep supporting a life-destroying status quo in our healthcare system and in the Middle East. If we want to defeat Trump’s handpicked crony this coming November, we need to speak to ordinary people’s frustrations with the status quo — we can’t keep running the same tired establishment playbook and expecting a different result. For those highly engaged voters (or skeptical media pundits) who raise concerns about wasting votes, the candidate can take the time to explain why this isn’t the case: It's true I'm a long shot. But Zohran showed anything can happen — and voting for me is a pragmatic decision, not a wasted vote. In a heavily divided primary with a large number of candidates and a very discredited establishment, my campaign and the democratic socialist movement I’m part of are positioned to be the balance of power if we can get a large enough number of voters to loudly demand Healthcare Not Warfare. Since there’s a high chance no candidate will get to 50% in the 2028 primaries, the Democrats could very well be heading towards a brokered convention, where a disciplined, principled current committed to breaking from corporate donors can play an outsized role in making sure whoever ends up with the nomination raises the banner of single-payer healthcare and cutting aid to Israel. How exactly could running this sort of primary campaign be translated into actual leverage? The candidate replies: I’m aiming to win the nomination, but if I don’t achieve that goal, my delegates and I will pledge our support in the primary only for a candidate who agrees in the general election to call for ending US aid to Israel and establishing Medicare for All at home. These are both winning planks for November against the Republicans, and the only reason I can see that other candidates haven’t yet raised these is that they’re still more scared of the donor class than they are of the people. That needs to change. If Democratic leaders want young people, workers, and those sick of the status quo to show up in big numbers this November, they need to meet us halfway. In this way, whether or not we win the nomination, democratic socialists could still play a decisive role in 2028. The approach outlined here is similar to what radical left parties periodically do in parliamentary democracies like Denmark or Sweden when they find themselves as a junior partner electorally: they dictate to center-left allies what their terms would be for enabling, from the outside, the formation of a new government. Running a Healthcare Not Warfare candidate will make it significantly more likely that the 2028 Democratic candidate stands with ordinary people instead of donors on these two pivotal planks — a shift that will, in turn, make it easier to achieve the existentially important task of defeating MAGA’s heir in November. Look at how much popular traction the Uncommitted movement got with a similar strategy in 2024 with so little on-the-ground organization — surely we can go much further with a working-class candidate, a much bigger DSA, and a Democratic Party base that has turned against Israel, billionaires, and the hacks in the party who prop them up. Objections and Responses There are quite a few objections to this proposal, many of which are very reasonable. Let me briefly address each here. Socialists shouldn’t waste their scarce time and resources on a candidate unlikely to win. This is a good rule in general, but there are important exceptions, and presidential elections are the main one. There’s no other political contest that gets anything like this level of attention and engagement in the US, so if you want to be a serious force in nationwide politics, you basically can’t afford not to have a candidate. Far from being an overall drain on our resources, running a dynamic 2028 campaign would likely result in a major net increase in members and capacity. In that spirit, the very pragmatic Milwaukee sewer socialists — who mostly ran to win at home in Wisconsin — supported Eugene Debs’s propagandistic presidential campaigns, which they correctly saw as a crucial means of recruiting to the Socialist Party. And now that the (post-1972) Democratic Party gives more weight to voters than party operatives in determining its presidential nomination, it’s become feasible to run as a socialist in primaries without risking a split in the vote against the Republicans in November. We should just support Ro Khanna, who also supports M4A and ending aid to Israel. I like Ro Khanna and would enthusiastically vote and canvass for him for president were he to get the nomination. But there’s a real chance that Khanna’s bid for office doesn’t catch on; he lacks the grassroots organizational apparatus of DSA, and, because he’s not really of the Left or labor (despite his current very good positions), he’s unlikely to generate the type of buy-in and enthusiasm that a DSA candidate would. Moreover, Khanna would be running as an individual, not as someone emerging from and building an organized movement — his campaign would not likely focus on building sustained power from below, nor would it likely polarize the 2028 primary around M4A and Israel aid. Also, and not inconsequentially, the poor electoral results for Tom Steyer and Saikat Chakrabarti this spring suggest that there’s perhaps not much of a popular appetite in the Democrats’ base to support multi-millionaire class traitors. Much better, then, to run a democratic socialist worker. If by Super Tuesday it’s clear that our campaign has captured the main left lane in the primary, Khanna should drop out and endorse us; conversely, if he’s managed to capture this lane, DSA could at that point transform its Healthcare Not Warfare campaign into an independent campaign to elect Ro Khanna focused on winning (and holding him accountable to) those two critical planks. An openness to consolidating an anti-corporate candidate by Super Tuesday is a necessary component of the strategy I’m proposing, because otherwise we risk splitting the primary votes (per DNC rules, you need at least 15% to get any delegates to convention). We should convince Shawn Fain or Sara Nelson to run for president instead. I agree it’d be great if either ran for president, but my impression is that there’s basically no chance that will happen in 2028, because both are firmly focused on their union leadership duties (and, in the case of Fain, beating back a federal witch-hunt). This plan could have DSA end up endorsing a non-socialist, non-DSAer for president. That’s against our principles. It’s a myth, and bad politics, that socialists can’t ever support candidates who aren’t members of their organization and/or who don’t call themselves socialists. Bernie, after all, was not a DSAer. And socialists abroad regularly make tactical decisions about if and when supporting a non-socialist candidate makes sense from the standpoint of promoting working-class interests, defending democracy, and building a socialist current in the process. If your “principles” prevent you and DSA from helping achieve the momentous stride forward of having a Democratic candidate in 2028 run on Medicare for All and ending aid to Israel, those “principles” are not very good. In fact, they actively undermine the causes they’re aiming to support. We shouldn’t confuse principles (working-class independence) with tactics (the best way to advance this in a given context). In my recent article in Catalyst on Milwaukee sewer socialism (I’ve uploaded the full text here), I have a section showing how similarly rigid rules about endorsements had to be eventually discarded in the old Socialist Party nationwide after WWI because they tended to lead socialists towards a sectarian abstention from broader anti-corporate electoral insurgencies beyond their party’s control. For what it’s worth, Lenin’s current under Tsarism frequently backed bourgeois candidates in the second round of elections and Lenin himself advocated that British Communists support Labour Party candidates; for his part, Kautsky in 1912 defended the German Social Democracy’s electoral pact with the Progressives in the runoffs. If our predecessors could be that tactically flexible in an era before the limits of their underlying strategic assumptions about intransigent class politics in capitalist democracies were made clear, then there’s no need to insist on being more tactically rigid today, after a century’s worth of accumulated experience. As long as you maintain your own political profile and organization while engaging in broader coalitional efforts, there’s zero inherent contradiction with the principle of political independence. More specifically: DSA and allied organizations should enthusiastically back Michigan’s Abdul El-Sayed if AOC declines to run and he throws his hat in the presidential ring. (I have no idea whether he’s even considering this path, but there’ll surely be chatter about it if he wins his Senate race this November.) Though he doesn’t call himself a socialist, El-Sayed is a principled Berniecrat, a consistent fighter for Palestine, and would have a clear path to victory. Using the “s” word is far less important than whether a campaign fights for the interests of working people at home and abroad — and whether actively participating in it can grow the organized working class and the Left. And the same holds true if a less anti-corporate candidate were, under pressure, to adopt our two Healthcare Not Warfare planks. Why focus only on M4A and ending US aid to Israel? There are so many other important issues to fight for! Obviously there are many pivotal issues beyond healthcare and Israel, and our candidate — and especially our organizations involved in the campaign — should be prepared to speak on all of these. But one of the crucial lessons of the Zohran campaign is that you have to relentlessly stay on message if you want to cut through the noise. CNN and Fox News will want to talk about DSA’s views on Venezuela and abolishing the police; we need to polarize the debate on the widely and deeply felt issues that are most favorable for growing the Left, isolating our opponents, and winning urgently needed changes. One recent poll found 63% of Americans support M4A, even after respondents were told it would raise taxes and eliminate most private insurance. Another found that 74% of Democrats opposed “providing additional economic and military support to Israel.” And focusing on two demands sets the campaign up to be able to leverage its mandate to make clear demands upon other candidates (which we can’t do if we run with a laundry list of demands). Talking about a Plan B is a distraction from the more urgent work of building a groundswell of calls on AOC to run. It’s good for DSAers, fightback unionists, and progressive organizations to try to convince AOC to run. This proposal is meant as an addendum to pushes to get AOC to run and to line DSA up for that eventuality, not as a substitute for those efforts. But I’m worried that, like in 2024, we might eventually find ourselves with no time to find a viable alternative unless we start now. DSA, with its abundant deliberative processes, moves slowly. The approach you’re suggesting seems risky. If a DSA candidate runs but doesn’t receive a lot of votes, it’ll undercut our current national momentum. This is a reasonable worry. All big initiatives always carry risks, and the path I’m advocating is certainly not free of these. That said, if a Healthcare Not Warfare campaign doesn’t catch on like we envisioned, it’s a pretty simple pivot in March 2028 to explain that in the future we really need our standard-bearers like AOC, or our growing bench of national electeds, to step up in presidential primaries. Moreover, it’s worth noting that the risk of my Plan B proposal is on the whole significantly less than the risk entailed by an AOC run. We should all back her if she runs, since she’d fire up the base, provide huge openings for organizing, have a real shot at defeating a Republican (especially given MAGA’s unpopularity), be a great standard-bearer for our issues, particularly M4A and ending aid to Israel, and be less willing than mainstream candidates to capitulate to any anti-democratic machinations from Trump and co. But it’s also true that AOC could lose, which would be a devastating setback to the country and the Left. Or she could win and find herself unable to pass much, if any, of her (and our) program, a demoralizing prospect. So if we’re willing to take these risks with AOC (and we should), it follows that we should be able to take lower-level risks if she doesn’t throw her hat in the ring. What’s Your Plan B? The US Left is facing its biggest opening for growth and influence since the 1930s. Initiatives that would have been impossible a few months ago are now potentially feasible. A President AOC is now easier to imagine, but if she ultimately assesses that the risks aren’t worth the potential reward in 2028, we can’t be left flat-footed. So even if you’re not convinced by the specifics of my Plan B, I hope you can at least agree that it’d be a disaster for us not to have one — and not to start getting a Plan B into motion. Hopefully other organizers and political currents will put forward their responses and alternative ideas ASAP. The stakes are too high to just wait and see. More As always, please share this article widely. This newsletter depends on all you lovely people to get the word out. Thank you! I uploaded the full text of my Catalyst article on Milwaukee sewer socialism here (it’s updated and 3x as long as the version published earlier on this substack). If you haven’t yet, please make sure to subscribe to Catalyst here; I read every issue front to back, highly recommend. 🌹🎵 Ivan Lins (arranged by Arthur Verocai) — “General da Banda” 🌹🎵
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