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Q+A: Faraday Future Moves Beyond EVs
Faraday Future Intelligent Electric Inc. is sizing up for a key pivot. Initially a luxury electric vehicle company, the El Segundo-based manufacturer is
SKF eyes role in humanoid robotics business
SKF is looking to work its way into the expanding Chinese robotics market with a recently announced agreement with Leaderdrive (LD), a global manufacturer specializing in precision robotic components. The companies are working together on a venture in China focused on high-precision transmission components for robot joints. SKF officials said the investment is a step […]
Kene Nwangwu to miss opener
Jets RB Kene Nwangwu downgraded from doubtful to out for Week 1
China calls for APEC cooperation as commerce minister skips opening over ‘urgent official business’
China's international trade representative Li Chenggang said he was chairing Friday's meeting as Commerce Minister Wang Wentao had urgent matters to attend to.
Breakthrough Helps Expand Genetic Alphabet - UC San Diego Health Science
Breakthrough Helps Expand Genetic Alphabet - UC San Diego Health Science / Dmitry Lyumkis, Dong Wang, genetic alphabet, Grigore Pintilie, Hui Pen Tan,
Opinion: Let's take closer look at sports gambling addictions in CT
'We should take an honest data-driven look at how sports and online betting affects Connecticut residents, particularly young people,' Sen. Tony Hwang writes.
Samsung Announces World-First Breakthrough in Fainting Prediction With Galaxy Watch
Joint study with Chung-Ang University Gwangmyeong Hospital demonstrates potential for early fainting detection using Galaxy Watch, paving the way for real-time warning systems
Disgraced stem cell researcher stripped of South Korea's top science award
SEOUL - South Korea's highest science and technology award presented in 2004 to former Seoul National University professor Hwang Woo-suk whose stem cell research was later found to have been fabricated was revoked this week, 22 years after it was conferred, the interior ministry said Wednesday.
Ash Center for Democratic Governance and Innovation announces Sports, Democracy, and Civic Health Initiative
The Reimagining Democracy Program at Harvard Kennedy School’s Ash Center for Democratic Governance and Innovation has announced an expanded initiative examining how professional sports and fandom can strengthen civic health and democratic life in the United States. Led by Tova Wang, Director of Research Projects in Democratic Practice at the Ash Center, the Sports, Democracy and Civic Health program brings together scholars, election officials, democracy advocates, professional sports organizations, leagues, athletes, and civic organizations. The initiative will explore how the shared identity and sense of belonging fostered by sports can build trust, reduce polarization, encourage civic participation, and strengthen connections across differences.
Meta's Watermelon AI model has caught up to GPT-5.5, Alexandr Wang says
Meta's superintelligence chief says its upcoming Watermelon model now matches GPT-5.5 on key AI benchmarks.
Computer Science Professor Wei Wang Receives ACM Innovation Award
Wei Wang, a professor and chair of the Computer Science Department at the UCLA Samueli School of Engineering, has received the Innovation Award from the Association for Computing Machinery, the world’s largest professional computing society
Home sports competitions kick off at The Nest
Albany High hosted its first home sports competition of the 2026-27 season at The Nest on Tuesday evening as our boys' soccer team faced off against Schalmont! Our Falcons delivered a thrilling win, defeating the Sabres 4-0. Ahadi Wangya, Adam Rouse, Garnett Ngome Ekiti and Rajanie Morgan each scored a goal, with Ngome Ekiti also delivering an assist. Evan Bermejo recorded five saves for Albany to record the shutout. Come to Albany High tonight, Sept. 2, to pack the stands with Falcon fans! Our girls' tennis team will face off against Guilderland at 4:15 p.m. and our girls' soccer team takes on Berne-Knox-Westerlo at 4:30 p.m. Let's go Falcons!
The U.S. and China running the world together? China says no thanks
For China, President Donald Trump’s use of the term “G2” is an acknowledgment of its growing power. But for U.S. allies, it raises fears they could be cut out of decision-making.
The National Academy of Sciences Elects Two Berkeley Lab Researchers
Two Lawrence Berkeley National Laboratory (Berkeley Lab) scientists have been elected to the National Academy of Sciences (NAS) in recognition of their distinguished and continuing achievements in original research. They are part of a cohort of 120 new members and 25 international members. The National Academy of Sciences is a private, nonprofit institution that was established under a congressional charter signed by President Abraham Lincoln in 1863. It recognizes achievement in science by election to membership, and — alongside the National Academy of Engineering and the National Academy of Medicine — provides science, engineering, and health policy advice to the federal government and other organizations. The 2026 electees bring the total number of active members to 2,705 with 557 international members. Gary Karpen is a biologist senior faculty scientist in Berkeley Lab’s Biological Systems and Engineering Division and a Professor of Cell and Developmental Physiology in the Department of Molecular and Cell Biology at UC Berkeley. Karpen studies how the structure, organization, and maintenance of genetic material impact inheritance and cell function. His lab focuses on chromatin — a packaged form of DNA strands wrapped around proteins that comprises our chromosomes — with a particular emphasis on centromeres, rarely expressed sequences called heterochromatin, DNA repair, and regulatory RNAs. His research reveals insights into fundamental aspects of nuclear organization and genome regulation that are shared across the tree of life, broadening our understanding of cancer and other diseases, birth defects, and aging. Kam-Biu Luk is a Professor Emeritus of physics at UC Berkeley and a retired senior faculty scientist in Berkeley Lab’s Physics Division. He is an experimental particle physicist whose research has focused on neutrinos: nearly massless, electrically neutral elementary particles that can pass through matter virtually undetected. Neutrinos are created during radioactive decay processes, including the fusion process occurring in stars and the fission process that powers nuclear reactors. Luk initiated and co-led the Daya Bay Reactor Neutrino Experiment, a project based in China with more than 200 international collaborators. In 2012, the Daya Bay experiment discovered a new form of a phenomenon called “neutrino oscillation” in which neutrinos change from one type to another. For this discovery, Luk and his collaborator Yifan Wang received the 2014 American Physical Society Division of Particles and Fields W.K.H. Panofsky Prize for outstanding work in experimental particle physics, and he was also the co-recipient of the 2016 Breakthrough Prize. Luk is currently participating in the Deep Underground Neutrino Experiment (DUNE) hosted by Fermi National Accelerator Laboratory, which will investigate any potential difference in behavior between neutrinos and antineutrinos that may shed light on the evolution of the universe, especially why antimatter is absent in the present universe. ### Lawrence Berkeley National Laboratory (Berkeley Lab) is committed to groundbreaking research focused on discovery science and solutions for abundant and reliable energy supplies. The lab’s expertise spans materials, chemistry, physics, biology, earth and environmental science, mathematics, and computing. Researchers from around the world rely on the lab’s world-class scientific facilities for their own pioneering research. Founded in 1931 on the belief that the biggest problems are best addressed by teams, Berkeley Lab and its scientists have been recognized with 17 Nobel Prizes. Berkeley Lab is a multiprogram national laboratory managed by the University of California for the U.S. Department of Energy’s Office of Science. DOE’s Office of Science is the single largest supporter of basic research in the physical sciences in the United States, and is working to address some of the most pressing challenges of our time. For more information, please visit energy.gov/science.
Curiosity Guides 2026 Keller Award Winners
Doctoral graduates Anna Yaschenko and Junjian Wang knew early on that genetics would be part of their future. In NC State labs, their innovative research earned them recognition as the 2026 recipients of the Kenneth R. Keller Research Award.
Another year, another Va. retail cannabis market veto leaves businesses, the public with few options
By Yiqing Wang and Toby Cox/WHRO Throughout her bid for governor, Gov. Abigail Spanberger said she would support a bill to set up a legal, adult-use cannabis market — which is why her veto on May 19 c...
Update coming: Large police and DPS presence outside Carrollton Korean market
Police have blocked off part of a parking lot near a Korean market as they investigate. Officials say to avoid the area until it reopens.
Steam meme game made in days almost turns teen into a millionaire
Even after refunds, a surprising number of people kept the expensive game on Valve's platform
FSU geologists discover North, South American mammals mingled before continental connection
Florida State University researchers are part of an international team whose work reveals that North and South American mammals interacted before the
South Coast Business & Technology Awards Raises More Than $200,000 for Scholarship Foundation
William Wang, Mission Wealth, and UCSB Dept. of Technology Management among the honorees
May 7 Vacaville/Vallejo Arts-Entertainment Source: Faces and Places
U.S. Rep. Mike Thompson announced that Victoria Wang from Sonoma County was chosen as the overall winner for California’s Fourth District 2026 Congressional Art Competition. Lilly Bertlin was named as the Solano County finalist.
Beltrán, Jones, Kent reflect on journey to Cooperstown
The National Baseball Hall of Fame induction ceremony will take place on Sunday at the Clark Sports Center.
The politics and possibilities of ‘AI could kill us all’
I found myself fielding a lot of questions from folks who don’t usually talk much about AI this week. They were mostly along the lines of “do you think AI is going to kill us all?” or “how worried should I be about this human extinction stuff?” Motivating this wave of existential anxiety was the highly dramatic resignation of now-former Anthropic employee Jacob Coxon, who quit his job while publicly sharing his concerns about safety practices at the leading AI companies. More specifically, he declared that almost everyone at OpenAI and Anthropic, the leading AI labs, believes that there’s a decent chance the AI systems they’re producing could “kill us all” by the end of the decade, and the companies aren’t “acting responsibly.” Other AI safety researchers, including those still employed at Anthropic and OpenAI, all confirmed that yes, Coxon is correct, they’re all worried that their company’s products might prove fatal for the entire human race as well. Two more AI employees quit and joined the chorus. Now, the warning shot has been covered everywhere from the Wall Street Journal to Fox News to WIRED to the Guardian. I understand why all this sounds scary, but my response to those who have asked, has generally been: No, you don’t need to worry that AI will kill go rogue and kill us all. But that does not mean we shouldn’t worry, period. Far from it. The companies building AI products are now among the wealthiest and most powerful entities in the world. And they very much are building enormous engines of mass surveillance, extraction, and automation. They can and have allowed their AI systems to carry out felony hacks of other companies, provided the government with autonomously generated kill lists, and sold enterprise technology to firms around the world that is explicitly intended to replace jobs. But “AI” has done these things not because they have all-powerful minds of their own but, ultimately, because people have programmed, calibrated, and directed them to. In other words, it’s not AI we need to worry the most about. It’s the people and corporations working to profit from and gain power by deploying it. The technology is sophisticated, sure, and, especially in cybersecurity contexts, potentially disruptive to plenty of existing systems. But if we want to stop this predatory, profiteering, and extractive form of AI—and it’s worth noting that at this point, most people do—we absolutely can. A quick note/plea: I can only do all of this with the support of readers like you, so if you find value in independent, critical tech journalism and analysis, please consider becoming a paid subscriber. I want to keep as much of this un-paywalled as absolutely possible, and I need your support to do so. Many thanks to all who continue to chip in, it’s very much appreciated. Onward. Subscribe First, some context: AI industry folks like Coxon have been discussing the prospect that AI will destroy humanity for years. Even before the beginning of the AI boom, many working in the industry, from the executive staff to the rank and file researchers, have obsessed over ‘x-risk’, or the possibility that AI will become sentient or semi-sentient and move one way or another to exterminate humanity. This is ostensibly why Elon Musk bankrolled OpenAI in the first place, and is the grounds for his lawsuit alleging OpenAI betrayed its charter by abandoning its nonprofit status to become a commercial enterprise. Many AI engineers and startup founders have calculated their own personal p(doom), or the probability that the tech product they are working on will initiate an actual humanity-extinguishing apocalypse. 10-25% p(doom)s are pretty common. (I wrote about a long weekend I spent among these folks at one of their top conferences here, to give you an idea of their ideas and belief systems.) Sam Altman himself drove the narrative of the imminent rise of a super-powerful AI, or artificial general intelligence, to prominence by declaring that the technology he was building posed an existential risk to humanity. This idea is in other words baked into the DNA of modern AI companies and into the products they engineer. It’s also why the industry is routinely accused, by myself and others, of “doom marketing,” ie, using such proclamations and framings to impart the sheer power of the technology behind your product onto investors, partners, consumers, and the state. Some ambient understanding of this tendency may have helped prevent the press from repeating the claim every time one of the x-risk folks made it over the years, including when they quit their jobs at AI companies while doing so. Yet Coxon’s AI x-risk alarm has broken containment, as they say, and has exposed the idea to the mainstream media once again. This has happened, I think, for a number of reasons. First, when AI CEOs were going around saying AI might kill everyone in 2023, their companies were well-capitalized, but not nearly to the extent they are today. They were more easily dismissed as eccentric geeks of the sort that Silicon Valley is supposed to produce. Now, not only do their products have much greater market saturation, but people are more aware of a) the often unethical ways the executives and companies comport themselves b) the other adverse impacts of AI that have already arrived, and c) the physical cost of building these systems, particularly when it comes to data centers. Finally, toss in the constant stream of headlines in 2026 about AI models going rogue or potentially upending the world’s infrastructure. [ ](https://www.bloodinthemachine.com/p/with-the-backlash-to-data-centers) [ With the backlash to data centers, Flock and AI glasses, a mass opposition to big tech is underway. Silicon Valley is in denial. ](https://www.bloodinthemachine.com/p/with-the-backlash-to-data-centers) Brian Merchant · Aug 27 [ Read full story ](https://www.bloodinthemachine.com/p/with-the-backlash-to-data-centers) As a result, general sentiment was already overwhelmingly skeptical of AI and its overlords, so the table was pretty well set for someone to come along and say ‘just a reminder, the companies that are building the product that promises to take your job and leave a data center in your neighborhood also think that it might exterminate the human race’ and get a strong reaction from the media and the public. The question is: Should we understand this stuff as hype, strategically fanned to feed already swelling valuations? Is it doom marketing? Genuine cause for alarm that the infrastructure that undergirds modern life is facing a novel threat vector? Or reason to be sincerely worried that AI companies are amassing too much power, and that their products are genuinely dangerous? The answer, I’m afraid, is “yes.” Let me try to untangle all of this a bit, because arguments over how to navigate this moment are extremely heated right now, as they are essentially arguments over how to approach the politics of AI at a moment where there may be a unique opening for action. Those sympathetic to AI alignment concerns and x risk arguments—which increasingly includes a faction on the left who want to shut down AI over safety concerns—argue that people who dismiss AI as all hype have their heads in the sand. Meanwhile, critics of the x-risk narrative—which I might note includes a cadre of investors and tech folks on the right, too—argue that it is hype and can be used to further inflate valuations or for pursuing regulatory capture. The challenge is that many feel that dismissing AI as just hype or purely marketing also diminishes the urgency of taking on the AI industry as the novel and threat to labor, civil society, and the public sphere it is; others that by accepting the industry’s own terms, we imbue it with undue power and enable it. But let’s be clear: Declarations that AI is so powerful it might end the world are a kind of marketing, and anyone who says otherwise is just as off base as those who say that’s all that it is. If you don’t think that these sub-trillion dollar companies have higher-ups who noticed that when their founders talked about super-powerful dangerous AI they got spikes in media interest and phone calls from investors, or that those founders didn’t notice that themselves, and lean into certain narratives to advantage their products, then I don’t know what to tell you. Not all marketing is a Pepsi ad campaign with a celebrity spokesperson. Yet confronting the AI industry should certainly be considered an urgent project. Do I share the x-riskers’ fear that out-of-control, super-intelligent AI agents might end the world? I do not. I’ve read a good deal of AI extinction literature over the last couple of years and I have not come across a credible, step-by-step documentation of how exactly AI might move from self-recursively improving AI to killing every single human on the planet. Most of what I’ve read seems predicated on a sort of reverse Ian Malcolmian logic: Eventually, it becomes smart enough and AI, uh, finds a way (to exterminate humanity). Are the AI companies also overstating and dramatizing what their products can do? Yes, pretty much all the time. They’re in a knife fight for market share and are trying to win customers and government contracts before their investors come knocking. And yet. They have concentrated enormous amounts of compute, have extensive data collection and surveillance capacities, have inserted themselves into the state in numerous capacities, including military kill chains, and they are being run by egomaniacal billionaires who are rushing to monopolize an entire new market. The way I think about their most recent frightening-seeming exploits is not as a “swarm of rogue AI agents building a new civilization” or whatever, but as corporations with a hitherto-unimaginable amount of compute at their disposal recklessly experimenting with automation programs, completely unafraid of any repercussions because we have been unwilling or unable to impose any on them. So I think we should welcome any newfound imperative to hold them accountable. I also think that ultimately, the AI critics, Pause AI folks, leftists, doomers, effective altruists, and, honestly, most of the public, want a lot of the same things: legitimate checks and limits on AI companies’ power, actual transparency into what the companies are doing, and for more of AI to be under public control. (Ultimately, a lot of what animates the x-risk fears are rooted in just that: a fear of losing control.) How we move towards all this, exactly, is the question of the day, and while there’s much to be argued over in terms of building a viable political platform to challenge the AI industry’s power, I do want to cast a vote against one particular approach. Not to pick on Chris here, as there are a lot of folks out there proposing stuff like this, and the policy ideas actually stem from AI safety groups. But not only would this be challenging to land politically (I can already hear the ‘China will beat us to AGI’ calls) and all but unworkable in practice, this approach is a) far too limiting, b) fails to address the current harms caused by AI and c) would likely only wind up serving Anthropic and OpenAI; it’s what regulatory capture looks like in action. Full model transparency is the floor for what should be on offer here. If these companies believe their products will kill us, the very least we deserve is to know how. It’s in the public interest. I would also argue we might get a lot of the way to stopping any currently envisioned robot apocalypse simply by forcing AI companies to assume liability, and to submit to the full brunt of the law. If Sam Altman were liable to be charged with a felony for approving the hack on Hugging Face1, if Google was forced to pay defamation fines each time it published a false and injurious AI Overviews, these companies might suddenly find cause to restrain their models’ output, and we might hear less about rogue AI. We would need to introduce new frameworks and available tools for tracking automated lawbreaking, to be sure, but I’d wager that little would frighten the AI companies more than actually being held accountable for what their products enable. To that end, Illinois has passed an AI liability law, which the industry fought tooth and nail, and Florida is considering one. The next steps would be towards moving AI under public control; again, it’s only reasonable, since everyone, not just AI insiders, should get a say over how a technology whose developers say might kill us is developed and deployed. Dismantling the whole industrial project as currently structured should be on the table, too, pending democratic input. But that’s for another post. For now, suffice to say that while I won’t be losing any sleep about an AI-enabled extinction event, Mr. Coxon and co. have given us an opportunity to underscore the urgency of the clear and present damage AI companies are doing, the extreme power they wield and the extent to which they hold themselves unaccountable, and the abundance of political capital there is out there for taking them on. Subscribe 1 Purely speculative! I do not know if he did or not.
Ngarlawangga Aboriginal Corporation and Rio Tinto sign Interim Modernised Agreement
KARRATHA, Australia--(BUSINESS WIRE)--Sep 7, 2026--
Sam Wang Runs to Protect Democracy, Science, and Neighbors
PRINCETON - If I couldn't find my keys on the way to my car, it was a good thing I was with Dr. Sam Wong, who literally wrote a book
Crossing the line: Emotional abuse in college sports
Researchers have found that athletes experience emotional abuse more than any other form of harm. Some athletes maintain that this kind of abuse by coaches can cause lasting, even irreparable damage.
Qunova Appoints CFO and Two Business Development Executives
Qunova Computing appoints Jake Hwang as CFO and adds Evan Kang and Woomin Kyoung to expand quantum software commercialization.
Meta's superintelligence labs taps leader for hardware role
Meta Superintelligence Labs, led by Alexandr Wang, is hiring a new leader to spearhead its AI hardware division, hinting at new AI devices.
Bringing the data to every sideline
MIT PhD student Henry Wang studies how data and technology can improve the way sports are played, analyzed, and refereed. Working in the MIT Sports Lab in collaboration with FIFA, he develops systems with the goals of helping referees make faster, more accurate decisions and expanding access to performance analytics across the globe.
Cardiovascular health spending has tripled, but death rates are rising in major Hampton Roads cities
By Yiqing Wang/WHRO Cardiovascular care has become more advanced over the past two decades, giving doctors new ways to prevent deaths from heart attacks, strokes and other conditions. But a new national study found those advances have come with rapidly rising costs while improvements in cardiovascular death rates have largely stalled. The analysis, published in the Journal […]
Trump admin opens investigations into race in admissions at 3 medical schools
President Donald Trump has been ramping up scrutiny of universities he decries as overrun by liberal influence.
Guest opinion: Rural Wisconsin workers lose health insurance twice as fast as before the pandemic
Wisconsin should expand Medicaid, invest in renewal pathways that don’t assume broadband internet access and revamp the renewal system so eligible people do not lose coverage, Jiyue Wang writes.
[VIDEO] Lucy Wang Featured in Business Interview TV Series
Watch a new Business Insurance interview with Lucy Wang, discussing how California's historic insurance regulatory reform has impacted the state's insurance market and rates in response to increasing wildfire exposure.
NVIDIA Reportedly Ending the RTX 5090, Reserves GB202 Silicon for Workstation GPUs
NVIDIA has reportedly stopped allocating GB202 silicon to the GeForce RTX 5090, according to leaker MEGAsizeGPU (@Zed__Wang) on X. "No more GB202 for 5090, confirmed," the leaker posted, adding in a follow-up that "all future GB202 supplies are RTX Pro exclusive." GB202 is the largest "Blackwell"...
Sam Wang, Politician-in-Training
The neuroscientist went from analyzing elections to running for Congress. But can this rookie win over New Jersey locals—and Trump voters?
US police report raises questions over Chinese researcher Wang Danhao’s death
Key details about semiconductor scientist’s visit from US federal agents the day before he took his own life mysteriously wiped from report.
From Watts to L.A. wildfires: The rise of California's troubled FAIR Plan
As leading insurers have retreated from California, one carrier has stepped in to fill the gap.
Paul Rudd details his 'perfect run-in' with Neil Diamond while DJ'ing a party
Diamond had a priceless response to Rudd asking if he was "Wanging Chung tonight."
Mark Zuckerberg talks about the massive risk Meta took on AI
The Meta CEO said that the company was prepared such a risky bet on AI, that the CFO was concerned and pulled Alexandr Wang aside.
'New queen' Silva beats Wang to UFC flyweight title
Natalia Silva is crowned the new women's flyweight champion with a unanimous decision victory over China's Wang Cong at UFC 332.
Sonam Wangchuk: Indian activist urged to end hunger strike as he loses 9.1kg in 19 days
The environmental activist has been on a hunger strike for 19 days and has visibly weakened.
What public health can learn from the MAHA movement
“What MAHA has built, in a relatively short time, is social capital,” writes Monica L. Wang.
Atmospheric sciences professor recognized for contributions in Asia-Oceania | University of Hawaiʻi System News
UH Mānoa professor Yuqing Wang has been named a Fellow of the Asia Oceania Geosciences Society for groundbreaking research
China is boycotting a major Asian art festival over the naming of a Taiwanese exhibition
Chinese artists are boycotting the Gwangju Biennale in South Korea over plans to designate an exhibition space as the “Taiwan Pavilion.”.
Teen Discovers Coconut Fungi Can Filter Plastic and Sunscreen From Sea—Wins Science Fair
A Hawaii high school student’s discovery of a coconut husk fungi that cleans up plastics and sunscreen in the ocean—and won the Science Fair.
RWJBARNABAS HEALTH NAMES DR. ERWIN WANG, MD, MHA, SFHM, SENIOR VICE PRESIDENT OF PHYSICIAN PERFORMANCE IMPROVEMENT
RWJBarnabas Health has appointed Erwin Wang, MD, MHA, SFHM, as Senior Vice President of Physician Performance Improvement. In this newly created role, Dr. Wang will lead physician-driven initiatives to enhance clinical quality, patient safety, and value-based care across the health system.
UC researcher secures $3.3M grant to study microplastics’ impact on heart
The National Institute of Environmental Health Sciences awarded a $3.3M grant to University of Cincinnati researcher Hong‑Sheng Wang, PhD, to study how microplastics and nanoplastics affect cardiovascular health.
LIVE UFC 332: Silva vs. Wang Results & Highlights
On Saturday the action heads to Utah as the leading MMA promotion presents UFC 332. The card will take place […]
Ash Center for Democratic Governance and Innovation announces Sports, Democracy, and Civic Health Initiative
The Reimagining Democracy Program at Harvard Kennedy School’s Ash Center for Democratic Governance and Innovation has announced an expanded initiative examining how professional sports and fandom can strengthen civic health and democratic life in the United States. Led by Tova Wang, Director of Research Projects in Democratic Practice at the Ash Center, the Sports, Democracy and Civic Health program brings together scholars, election officials, democracy advocates, professional sports organizations, leagues, athletes, and civic organizations. The initiative will explore how the shared identity and sense of belonging fostered by sports can build trust, reduce polarization, encourage civic participation, and strengthen connections across differences.
CECAS recognizes inaugural Global Scholars and Dean’s Scholar Fellows
Those recognized were: Shane Abercrombie, Sumter Archer, Tiffany-Marie Baako, Colleen Clarke, Kylie Folkes, Bryson Hedrick, Sara Henry, Joshua Hoggatt, Taylor Hopkins, Azrin Jamison, Mengdi “Hansen” Li, Robert Lowery, Quincey Miller, Ben Simon, Madison Smith, Arabella Stockdale, Steven Szachara, Tianke “Kirk” Wang and Aidan Wolynn.
A Taiwan School of Music? Rethinking Identity, Politics, and Aesthetics
Written by Min-Erh Wang. This article examines the conceptualisation of a “Taiwan School of Music” within contemporary musicology. Exploring the intersection of music, postcolonial agen…
Mamdani reaches out to CEOs to boost city economy; what it means
Some of the biggest names include Chobani CEO Hamdi Ulukaya, New York Liberty CEO Keia Clarke, Etsy CEO Kruti Patel Goyal and Pat Wang, CEO of Healthfirst.
Why China Insists on the “Existing International Order”: The Politics of UN Centrality and Reform
In May 2026, China held the rotating presidency of the UN Security Council, and Foreign Minister Wang Yi flew […]
This Harvard dropout took a company public before 30. Now he’s raising $205M to fix the business side of medicine
Tim Hwang, who's also a former Obama campaign staffer, now has his sights set on a $10 billion valuation, and the numbers suggest he might not be bluffing.
They're Building Half A Bridge to Save Science...
Today’s post is about science: what you can do now to protect it from unprecedented threats, and how your action is the first half of a long-term program that Congress must take up next. Let me start with describing the embryonic state of science advocacy. There are many well-meaning organizations: the American Association for the Advancement of Science, Research!America, and subject-specific organizations such as the Society for Neuroscience and the American Physical Society. Their general approach is to emphasize the common good: the remarkable value that science and innovation have provided to all Americans. However, these organizations are offering an incomplete solution. Before I start, a preliminary: If you already know about the threat, go ahead and weigh in with OMB at this link. Ideas about what to say come from Research!America and the American Physical Society. You have until Monday, July 13 at 11:59pm Eastern. Then come back here and read the rest of this post. Finally, get in touch with whoever is likely to be your next member of Congress in 2027. The threat: An end to merit-based science… The onslaught of attacks on science is accelerating. It’s not just cuts to grants, which was the last battle. That battle is not done yet, but there is a new and worse threat. Now comes a proposed public rule from the Office of Management and Budget. The rule would take decision-making power over grants away from experts and put it into the hands of political appointees. Former NIH official Elizabeth Ginexi wrote an excellent summary of what OMB is trying to do, which is codify the executive branch’s ability to award or terminate grants, for arbitrary cause or no stated cause. Since World War II, a necessary step in scientific grant-making has been consideration of scientific merit. This approach has made America into a dominant scientific superpower, the envy of the world. Of course, political considerations do come into the mix. The proposed rule tilts the balance dramatically away from merit. …but why? Many people have difficulty comprehending why Russell Vought and OMB would want to damage science in this way. If you’re a working scientist, you are likely to be particularly uncomprehending. Who would hurt an activity so self-evidently good? The answer is: this is part of the program to replace the rule of law with a personalist regime. OMB Director Russell Vought, a Christian nationalist, would like to implement what legal scholars call a “unitary executive,” and what I would call a dictatorship. Or if you like, a personalist authoritarian regime. I am a working scientist. This rule will debilitate my research. It may chill the speech of scientists for speaking freely in the public sphere. It is a form of personalizing power and decision-making within the executive branch. In short, it sacrifices science in the service of tyranny. To Russell Vought, a decrease in the quality of science might be an acceptable cost. He might even consider it an added benefit to weaken a pillar of soft U.S. power based on knowledge and skepticism. The professional societies are building half a bridge The nonprofits are asking you to make public comment. Public comment is like building the first half of a bridge. Before implementation, OMB is compelled by law to have a period of public comment. Rules have to be consistent with the law and the Constitution. They express the federal government’s stance toward how those laws will be implemented. When a presidential administration works in good faith, these public comments are used to inform their eventual action, and sometimes mitigate it. The comment period reflects our First Amendment right to petition our government. The executive branch is then supposed to take those comments into account - completing the bridge between us, the people, and our government. Project 2025 seeks to take away the second half of the bridge. We have to replace it. The first half of the bridge Organizations like AAAS, Research!America, and SfN are partly right. You should certainly comment. Their core model is earnest: if enough of us make noise, then we will achieve change. This idealistic point of view is offered in good faith. That point of view is also currently bullshit. The fundamental reason is that the federal rulemaking process has two parts: There has to be a period of public comment. OMB makes the final rule…but is free to disregard public comment. Oops. That’s a loophole. However, not all is lost. Congress can complete the bridge Congress has enormous power. That power suggests a roadmap for how to proceed. This lawless administration is still going to issue that rule. Nonetheless, your comments still play an essential role. Here are two steps you can take. Step 1: Send your comment to your Representative and Senator. Whether they are Democrats or Republicans, many of them support science. Whatever you wrote as public comment in the Federal Register, also send it to your member of Congress. You can include information about jobs in your district or state by looking at Joshua Weitz’s ScienceMatters interactive map. Call the U.S. Capitol switchboard at (202) 224-3121 and give your town, zip code, or state, then deliver your message. Step 2: Politicize the hell out of science. You heard me, politicize it as an issue. We hear a lot from the old scientific establishment about science being nonpartisan. This is obsolete, sentimental thinking. Under normal conditions, it was true. But we can no longer make that assumption. We can keep on pretending, but we’re putting science at risk. There is a way forward. Rules are subordinate to the law…and Congress makes laws. Therefore Congress can step in. In this fall’s election, it is likely that Democrats will retake the House of Representatives. That puts at least one chamber of Congress in the hands of Democrats. They are far more inclined than the current Congress to investigate and legislate. This opens a path to undoing the damage. It also creates a permission structure for pro-science Republicans to find a way back from the brink. We have to encourage them. In the House, every district is up every two years. In your district, contact both of the major party candidates. If your state has a Senate race, contact those candidates too. Specifically mention the proposed OMB rule. Ask for two things: For this year’s appropriations process in August and September, ask that amendments be added to stop the implementation of the new rule. Those amendments should support peer-reviewed science and stop political interference. Looking ahead to next year, ask the Congressman/Congresswoman/Senator to work to hold hearings in 2027 on the importance and benefits of peer-reviewed science for health and prosperity. What hearings and amendments will accomplish Congress can use its investigatory power to summon heads of agencies and the director of the OMB. That will allow fact-finding regarding the consequences of this rule. Congress can override the rule through the appropriations process. They can write into statute a requirement to follow peer review and best scientific practices. In this way, Congress can stop the attacks on science. Postscript: Moving forward Now I have a request for you, to help me. As many of you know, I ran for Congress in order to save democracy and science. Although I did not win, that battle continues by other means. I met and heard from thousands of supporters both here in New Jersey and nationally. I learned that pro-science, pro-democracy activists have the potential to become a much greater force. In the weeks and months ahead, I will be building ways to harness that energy. I will be announcing those plans soon. In the meantime, an important step is to wind down the Congressional campaign, which has a few remaining bills to pay. Please help me retire that last debt.
Acknowledgments
This is a Pew Research Center report from the Pew-Knight Initiative, a research program funded jointly by The Pew Charitable Trusts and the John S. and James L. Knight Foundation. Find related reports online at https://www.pewresearch.org/pew-knight/. Primary Researchers Elisa Shearer, Senior ResearcherLuxuan Wang, Research AssociateKaterina Eva Matsa, Director, News and Information Research Michael Lipka, Associate Director, News […]
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Science|Business summer reads of 2026
As most people in the European research and innovation policy bubble are going on a well-deserved summer break, we have come up with a list of our favourite books, podcasts and essays from the past year that ask deeper questions about science, technology and politics.BooksPasteur’s Quadrant: Basic Science and Technological Innovation, by Donald StokesIf you haven’t read Pasteur’s Quadrant yet, now is the time. In the EU and elsewhere, we’re living through a period of dwindling faith that curiosity-driven research automatically leads to economic growth and technological progress. Pasteur’s Quadrant, published in 1997 by the Princeton academic Donald Stokes, is the most influential critique of the standard “linear model” of R&D: the idea that new discoveries made in ivory-tower labs get neatly passed on for commercialisation by start-ups. In reality, Stokes argues, practical applications often inspire more theorical lines of inquiry. Of course, we have long known that things are more complex than the linear model, but even today, it’s still often assumed in Brussels discourse. The book is a useful corrective, and is being used now to argue for new types of scientific institutions. David MatthewsThe Weaponization of Expertise: How Elites Fuel Populism, by Jacob Hale Russel and Dennis PattersonAre society’s problems solvable by technical expertise alone? “If only the benighted would listen,” say Jacob Hale Russel and Dennis Patterson, two professors at Rutgers Law School who got frustrated with how scientists and politicians handled public health communication during the Covid-19 pandemic. In the book, they argue that clichéd mantras about scientific evidence and expertise perpetrated by academics, journalists and politicians have harmed public trust in the very institutions they were trying to defend. Paradoxically, slogans such as “we believe in science,” “follow the science” and “defer to the experts” can fuel mistrust in science, experts and democratic institutions. The authors criticise “condescension” and “technocratic paternalism” in the public discourse and make the case for a more nuanced approach to scientific and expert policy advice that rests on humility, doubt, scepticism and open dialogue. “Most complex social questions in fact revolve around values, not the recitation of unambiguous facts,” they say. Florin ZubascuBreakneck: China's Quest to Engineer the Future, by Dan WangIn this book, Dan Wang compares the structural differences between the US and Chinese industrial policies, but raises a very timely question for innovation policy wonks: how can advanced manufacturing know-how contribute to technology-intensive economic growth? Wang says technology has three components: the tools, the blueprints and patents, and the process knowledge. The third component represents the “proficiency gained from practical experience, which isn’t easily communicated and requires years of implementation.” According to Wang, rather than seeing tools and blueprints as the ultimate ends of technological progress, policymakers should see them as milestones in the training of better scientists and manufacturers. Over the past decades, China has amassed “process knowledge” because capital flowed to complex fabrication facilities, while investors in the West have parked their money in capital-light businesses such as digital platforms or chip companies that focus on design. As it turns out, thanks to its oversized focus on manufacturing, China has gained remarkable advantages in the global technology race. Florin ZubascuBaltic: The Future of Europe, by Oliver MoodyWhat can Europe learn from the nine countries surrounding the Baltic Sea? Alongside the familiar stories about Estonia's digital transformation, the book examines how the region has used technology, resilience, education, governance and long-term thinking to respond to geopolitical, economic and security challenges. Innovation policy wonks might find fresh perspectives on how innovation can strengthen defence, societal resilience and Europe's capacity to adapt in an uncertain world. Whether or not you agree with all of Oliver Moody's conclusions, the book is a useful guide to a region that is increasingly shaping European debates on security, competitiveness and technology. Goda NaujokaityteThe Invention of Nature, by Andrea Wulf This book chronicles the wild and adventurous life of natural science pioneer Alexander von Humboldt who at some point in the 19th century seems to have been just about the most famous person in the world. Through scientific expeditions to the Andes Mountains and to the depths of Siberia, von Humboldt contributed a host of discoveries and concepts. During his life he met and formed relationships with historical figures as different as Johann Wolfgang von Goethe, Simon Bolivar, Thomas Jefferson, Napoleon Bonaparte and Charles Darwin. He is also claimed to be the person in the world with most things named after him, a list that includes an ocean current, a penguin and a region of the Moon. Still venerated in Germany, with numerous scientific institutions named after him, von Humboldt has slipped out of public consciousness in most of the rest of the world. For anyone not familiar with him, this book does a good job of describing his fascinating life. Ole EllekrogCareless People, by Sarah Wynn-WilliamsYou may have heard this referred to as the book Meta doesn’t want you to read. The 2025 memoir from Sarah Wynn-Williams, former director of global public policy at Meta, then just called Facebook, includes explosive claims about everything from a toxic workplace culture to how the company worked with advertisers to target vulnerable teens, and the lengths it was prepared to go to in order to break into China. It’s a fascinating insight into how and why the tech company gradually shifted its approach to policy, whether in the US, Europe or Asia. Meta has denied the allegations in the book, and last year won an emergency ruling to prevent Wynn-Williams from promoting it. In response, the author is now suing her former employer. If that doesn’t make you want to read it. Martin GreenacrePodcastsThe Europeans: Europe’s anti-ElonThis podcast is a great choice for a light-hearted dose of European policy and culture news. Most of it has little to do with research, innovation and technology, but this particular podcast features an interview with Mastadon’s founder Eugen Rochko. He talks about his experience running an open-source, federated, European-made social media platform, and leaving it all behind. The conversation, which starts 14 minutes in, gently encourages us to reflect on what kind of technology we, as Europeans, want to make. Goda NaujokaityteSolarpunk and how we escape dystopiaNew technologies are very often taken from science fiction. Alberto Santos-Dumont, inventor the airship, was inspired as a child by the adventure stories of Jules Verne. OpenAI’s attempt to build a personal assistant with the voice of Scarlett Johansson was lifted from the 2013 film Her, completely ignoring the movie’s cautionary message. So if we want better tech, we need to imagine it first. Unfortunately, the state of current sci-fi is relentlessly dystopian, giving inventors precious few ideas or hope. However, a new genre, Solarpunk, which envisages a technologically advanced but ecologically harmonious future, is now taking off. The actual tech the genre imagines, such as permaculture, renewable energy or community repair workshops, while nice, isn’t all that inspiring or ambitious. But it’s a first step towards rescuing sci-fi from its pessimistic Blade Runner rut. David MatthewsEveryday AbundanceLaunched in June, Everyday Abundance is a podcast that tells the stories of the inventions we now take so for granted that we barely given them a second thought. For example, the washing machine, which liberated women from a lifetime “bent over washtubs and washboards.” Or modern dentistry, which ended the reality that “tooth pain was simply part of human life.” Historians of technology, Virginia Postrel and Charles C Mann are very much on the optimistic end of the spectrum when it comes to the capacity of invention to improve human life. Here, they set out their case: if it wasn’t for progress, you might be hunched over a washtub with toothache rather than reading these words. David Matthews‘We will not know what we lost’: Conservation fallout a year after USAID shutdownSince his return to the White House, Donald Trump has been on a mission to undermine science. He slashed jobs at federal agencies, terminated grants in some research areas, took unprecedented control over university affairs and, within hours of his inauguration, suspended the US Agency for International Development. While its initial focus was to administer health and food aid around the world, it had since expanded to conservation projects. The result? Some of these projects were stopped abruptly. In this Mongabay podcast, environmental reporter Michelle Nijhuis tells the story of the EcoGuard conservation programme in Liberia, whose local patrols had helped protect rainforests, monitor endangered wildlife and track illegal threats. From one day to the next, these were left without salaries. Luckily, she notes, the initiative was able to get emergency funding from international NGOs, but its future remains “incredibly uncertain.” Juliette PortalaEssaysThe Mars Delusion, by Henry WismayerWhy is humankind so fixated on establishing a colony on Mars? asks London-based writer Henry Wismayer. From space evangelists promoting Martian settlement as an insurance policy, to billionaire Jeff Bezos, who said humans should settle on Mars “because it’s cool,” the mission is not running short of advocates. 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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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