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Samsung Developing 'Wide Fold' With iPhone Fold-Like Design Ahead of Apple's 2026 Launch
Samsung is working on a new foldable smartphone that's wider and shorter than the models that it's released before, according to Korean news site ETNews. The "Wide Fold" will compete with Apple's iPhone Fold that's set to launch in September 2026. Samsung's existing Galaxy Z Fold7 display is 6.5 inches when closed, and 8 inches when open, with a 21:9 aspect ratio when folded and a 20:18 aspect ratio when open. Samsung has used a similar size for its prior Z Fold devices.
Why a shorter eating window may not mean better metabolic health
In a nationally representative cross-sectional study of 16,973 Korean adults, researchers identified three distinct eating patterns based on the timing and distribution of daily energy intake. Eating later within a shorter daily window was associated with higher odds of metabolic syndrome, elevated blood pressure, triglycerides, and fasting glucose, while frequent grazing showed a mixed metabolic profile.
Men are losing a key chromosome with age and it may be deadly
Aging men often lose the Y chromosome in a growing number of their cells—and it may be far more dangerous than once believed. This loss has been linked to heart disease, cancer, Alzheimer’s, and shorter lifespans. Researchers suspect Y-less cells may grow faster and disrupt normal body functions. What seemed like a minor genetic quirk could actually be a major driver of age-related disease.
Lee Health convenient care centers offer shorter wait times for minor injuries
Lee Health's convenient care centers provide walk-in service and same-day treatment for minor injuries, offering an alternative to hospital visits.
Paramount and Warner Bros. to become one Hollywood giant: Skydance. Here's how we got here
Skydance-owned Paramount is expected to close its $81 billion takeover of Warner Bros. Discovery on Tuesday. The new Hollywood giant will have a shorter nametag: “Skydance.” But it marks one of...
Patients could see smaller incisions, shorter recoveries thanks to U.Va. Health robotic heart surgery program
U.Va. Health has launched Virginia’s first dedicated robotic heart surgery program as a less invasive alternative to traditional open-heart surgery.
League Classic to go offline in January 2027
The return to old-school League of Legends will be shorter than some fans hoped, as Riot Games prepares to end the current version of League Classic while leaving the door open for a comeback.
Goldschmidt Plans To Play In 2027 Despite Yankees’ Crowded Roster
Paul Goldschmidt wants to keep playing in 2027. With a new MLB playoff twist and a shorter season proposed, the veteran first baseman has a clear path.
Long Reads for the Long Weekend
(Welcome to the Entertainment Strategy Guy, a newsletter on the entertainment industry and business strategy. I write a weekly Streaming Ratings Report and a bi-weekly strategy column, along with occasional deep dives into other topics, like today’s article. Please subscribe.) Happy Fourth of July weekend! As has been a tradition of mine going back to the beginning of the EntStrategyGuy website, I’m sharing my favorite long reads of the last year, like I did in 2019, 2020, 2021, 2024, and 2025. Let’s dive right in! Subscribe “Different Prices for the Same Ride: How Uber and Lyft Use AI to Get More Money Out of You“ by Derek Kravitz in Consumer Reports I don’t think surveillance pricing, like the kind described in this brilliant Consumer Reports article, is long for the world—it’s toxically unpopular—but we’ll see if either party takes on this issue. If I ran a political party focused on affordability, I would focus on a few pro-consumer and pro-market policies: Banning non-compete agreements. Ending surveillance pricing Eliminating junk fees (read more here...) Ensuring “right to repair” for consumer (and military!) products Capping excessive app store fees Stopping digital/algorithmic price-fixing tools. Preventing automatic subscription price increases. And more. If you want to fight inflation, there are a lot of great ways to do it quickly. Speaking of higher prices... “Secret Documents Show Pepsi and Walmart Colluded to Raise Food Prices Across the Economy“ by Matt Stoller in BIG Again, I think a political party should focus on lowering prices for consumers. And deals like this—Walmart making a deal/forcing Pepsi to offer the lowest prices at its stores and nowhere else—hypothetically lower prices at Walmart...but raise them everywhere else. “15 DUIs, still driving: California’s failure to take repeat drunk drivers off the road“ by Robert Lewis and Lauren Hepler in CalMatters CalMatters does terrific reporting in California, something the Golden State desperately needs more of, and this article is a great example of that. “PugLips: The next insanely popular thing you’ve never heard of…” by Simon Carless in Game Discover Co I thought that this parody article (and yes, it’s a parody, but I was definitely unsure at first) was hilarious and totally nailed how much tech/business journalism feels these days. Actually, three of my favorite articles this year were on hype in the video game industry, including Georg Zoller’s “The Video Game Industries Very Dark Night”—which I linked to recently and wrote a follow-up here—and Owen Mahoney’s “Derek Zoolander, Videogame Exec”. In particular, I like Mahoney’s focus on user experience as a guide to what trends will actually grab hold of customers. “The Matrix Lies“ by Evan Shapiro in Media War & Peace Evan Shapiro’s first person account of his experience with AI was hilarious. I think LLMs capabilities have significantly grown from last summer, and yet...my editor/researcher just had an abysmal experience using an LLM to do a quite basic task (which our LLM normally does each week) and the LLM made a mistake on every single data entry...along with seven different mistakes affecting twelve of the twenty or so entries, including mistakes that are explicitly spelled out in the prompt. That’s a brutal failure rate. Again, if you use AI/LLM for data collection, you need to take a lot of extra steps to verify and check the data. “Ghosts in the Balcony: A Cross-Country Trip to 58 Theaters Fighting to Survive“ by Matthew Frank in The Ankler I thought Matthew Frank’s pitch to head across America to visit theaters sounded insane aggressive at the time—at least it felt that way to someone a decade older than him; man, to be in your twenties again, am I right?—but I knew the result would be great. And it was, a terrific feature by a great young writer. Also, I loved Matthew’s recent article on who’s getting the precious few entry level jobs in Hollywood. (Hint: nepotism.) “Disney erased FiveThirtyEight“ and “Did Las Vegas get too greedy?” by Nate Silver in Silver Bulletin I love media history and analysis, and there’s no one better to get the history of FiveThirtyEight than from Nate Silver, who wrote about his personal experience in one of my favorite pieces from this year. I also loved Nate’s breakdown of what’s causing Vegas’ woes, but I’ll offer one criticism, summarized as “Might I suggest antitrust?” Many centrists/center-right/libertarian thinkers (Nate is self-described as the latter) often don’t consider consolidation or antitrust as factors in policy issues like housing, America’s military readiness, or, in this case, Las Vegas. Even if libertarians want to debunk antitrust/consolidation concerns, I’d love to read that debunking. In this case, Vegas is incredibly consolidated (though it also has been for a long time) and I’d have loved to read Nate at least contending with this factor, since he addresses almost every other potential factor for Vegas’ decline. “Why Microsoft’s Carbon Removal Pullback Is Such a Big Deal“ by Robinson Meyer in Heatmap News I’m a big supporter of carbon removal efforts, but this nascent industry faces a lot of headwinds, including this big move most recently. I think it’s clear that solar panels and batteries should be able to get the world to its carbon footprint goals, but effective carbon renewal remains necessary to prevent the worst impacts of global warming. “AI is killing the cheap smartphone“ by David Oks LLMs and AI will impact the world in ways we’re not ready for, and already, third world countries are seeing the prices of cheap cellphones skyrocket due to the cost of chips skyrocketing. This article by David Oks is a terrific breakdown. “100 Days of Madness: Netflix, Paramount, Warner and the Future of Hollywood“ by Wade Major at Hollywood Heretic Wade Major dove deep into Hollywood/streaming’s financials in this must read piece. Not that I agree with everything in this article (read my take on Warner Bros./Paramount here) but the analysis is top notch. I think many people discount how quality thinking, regardless of the argument/conclusion, will make you a better thinker. “Erased by the UFC: Frank Shamrock, The MMA GOAT of the 20th Century“ by Nate Wilcox in The MMA Draw Newsletter Growing up playing the UFC fighting game on the Dreamcast, Frank Shamrock was my favorite MMA fighter, and this history/tribute to him was great. Other Fun Reads “The Hardest Part Of History To Tell Is How It Felt“ by Craig Fehrman at Defector “Unmasking the Sea Star Killer“ by Craig Welch at bioGraphic “What Could Save the Industry? Fin-Syn“ by Richard Rushfield in The Ankler Alex Rollins Berg in Underexposed on movie bumpers, pillow shots, Disney trash cinema, cult films, and Casablanca. David H. Montgomery in YouGov’s The Surveyor on punctuation marks, condiments, dinosaurs, and comic strips and kids media. “How Medium finally pivoted its way to profitability“ and “Why the best journalists on YouTube are all former Vox employees“ by Simon Owens in Simon Owens’s Media Newsletter “It’s Not Just You, Netflix Shows Have Gotten Slightly Shorter: Here’s What the Data Says“ by Kasey Moore at What’s on Netflix “Numlock Awards: How Diane Warren became the biggest loser in Oscar history“ by Nathaniel Rakich and “Numlock Awards: The Oscar Bait era is over. The Oscar Chum era is here.” by Walt Hickey & Michael Domanico at Numlock Awards
Why Samsung Gave Its Next Folding Phone a New Shape
People spend hours watching videos on their smartphones. The wider, shorter, and lighter Galaxy Z Fold8 caters to exactly that.
The business blueprint for the Atlanta we know today
In the 1960s, most decisions in Atlanta could be traced to a dozen or so business leaders who called the shots. All were men. Today, many executives are transplants to Atlanta; CEOs tend to have shorter tenures, and they exert less influence. But that also means business has become more diverse, both in staffing and scope.
Jonathan Kuminga’s Agent Defends Reason For Taking Shorter and Cheaper Deal With Timberwolves
On Wednesday, ESPN’s Shams Charania reported that Jonathan Kuminga had agreed to join the Minnesota Timberwolves on a two-year, $12. 4 million deal.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Side-by-side size comparison of Samsung's upcoming foldable lineup leaked
A new leak reveals alleged screen protectors for Samsung’s Galaxy Z Flip 8, Z Fold 8 and Z Fold 8 Ultra, suggesting a wider, shorter Fold 8 design and clearer differentiation across the foldable lineup. While expectations are high that the Fold models will bring some significant changes, the same cannot be said for the Flip.
Are western New Yorkers spending more on digital entertainment as winter sets in?
As winter settles across Genesee County, colder evenings and shorter days are reshaping how households in Batavia and nearby communities spend their discretionary dollars. With outdoor options limited and heating
UFC Freedom 250 Fails to Knock Out The Ratings
(Welcome to my weekly streaming ratings report, the single best guide to what’s popular in streaming TV and what isn’t. I’m the Entertainment Strategy Guy, a former streaming executive who now analyzes business strategy in the entertainment industry. If you were forwarded this email, please subscribe to get these insights each week.) If UFC fans wanted one image to say, “Hey, Paramount+ is crushing it with their UFC rights deal,” I could provide that image. Here it is: (Reminder: this is my creation of the Nielsen Top 30, since Nielsen doesn’t combine the lists or include sports. I take all three lists and combine them. Some streaming TV shows probably have higher ratings than many of the films on this list.) Look at that! UFC Freedom 250 is number one! It topped the Nielsen “Top 30” list for shows and films that made the top ten the week of 15-June. So if you’re a UFC fan or supporter of Paramount+, that’s the good news for you this week. This program topped the ratings charts for one week. Everything else is bad news, or at least a huge caveat to that story, which I’ll explain today in the first part of this week’s Streaming Ratings Report—for the weeks of 8-June and 15-June—which is a double issue since I’ve been writing on a bunch of topics recently. UFC Freedom 250 is one of the biggest streaming events of the year, and super relevant to Paramount+’s strategy, so it merited its own article. Let’s dive in! (Reminder: The streaming ratings report focuses on the U.S. market and compiles data from Nielsen’s weekly top ten viewership ranks, Luminate’s Top Ten Data, JustWatch and Reelgood interest data, Samba TV household viewership, company datecdotes, Netflix hours viewed data, Google Trends, and IMDb to determine the most popular content. While most data points are current, Nielsen’s data covers the weeks of June 8th to June 21st 2026. You can find a link to my terminology here.) Subscribe Check Out My Interview on UFC 250 at MMA Draw After you read this article, if you want even more thoughts on UFC and Paramount-Skydance/Paramount+, I did a written interview with MMA Draw. They asked me to answer some questions about UFC Freedom 250, and I was happy to chat with them. Find it here: [ The MMA Draw Newsletter Did Paramount really overpay for the UFC? What the data tells us so far If you know the history of American television, you also know that combat sports is often a leading indicator of the future… Read more a day ago · 10 likes · 1 comment · Nate Wilcox and Zach Arnold ](https://www.themmadraw.com/p/did-paramount-really-overpay-for?utm_source=substack&utm_campaign=post_embed&utm_medium=web) I never thought I’d need a combat sports newsletter in my life, but the good folks at MMA Draw publish an excellent one on UFC, MMA, pro wrestling, boxing and more, analyzing both the sports themselves and the politics, economics and antitrust issues that impact them. Check the article and their newsletter out! Paramount+ Has Its Best Sporting Event of All Time…But Was It Worth It? Before we look at the UFC Freedom 250 data in particular, let’s talk about what we can’t say. Namely, let’s start with the lack of comparisons. First off, I’d love to put a chart out comparing this fight to past UFC fights on Paramount+…but we don’t have the data. This is the first time we’ve gotten Nielsen data about a Paramount+ UFC fight. As far as I can tell, Paramount provided data for the first fight, but it was a proprietary datecdote (saying it had “an average minute audience” of 5 million “views”) and then, for two fights, we got the linear viewership numbers when they aired on CBS, but no streaming data. Everything else was crickets. We also can’t compare this fight to other fights/combat sports on streaming, in particular the MMA and boxing, because Netflix also didn’t use Nielsen to track those events, opting for TVision and VideoAmp, respectively. (This isn’t Paramount’s fault, but does still suck.) We also can’t compare to UFC’s fights that used to be on ESPN+, since we don’t have any data for that, plus Disney+ didn’t have marquee fights. The comparisons would not be apples-to-apples. Can we compare to past Pay-Per-View fights? Absolutely not. The comparisons would absolutely NOT be apples-to-apples. That didn’t stop Paramount+, though, who bragged that their UFC events have reached drastically more people than past PPV fights. Duh. Sorry, but I gotta make this point again. A basic tenet of economics is that the cheaper something becomes, the more people consume or buy it. That’s Econ 101. (Sometimes pundits call things “Econ 101” that are actually like Econ 210 or even PhD-level economics, but no, this is really like first or second class basic economics.) Yet I still see one analytics firm consistently say that more people watch films on streaming than PVOD proves streaming which means that the streaming window is more valuable than the PVOD window. No, it’s not! Same thing here. Pay-Per-View events back in the day could be really, really, really expensive! So whole groups of people pitched in to buy them. That increased the perceived value of, say, the Mike Tyson fight. Or a UFC numbered event. So yes, the fact that Paramount+ makes numbered UFC fights essentially “free” if you’re already a Paramount+ member means consumption will go up. Obviously. Same for Netflix and their boxing matches. They’re talking about fights that used to cost consumers, in some cases, $50 in 1996…which is over $100 in today’s dollars. Over 1.6 million people paid that to watch the Tyson-Holyfield fight! Again, streaming is essentially “free”. Or $10 to $20, depending on what streamer we’re talking about and what tier you’re on. No wonder more people are “watching”. (Plus, Nielsen’s out-of-home viewing also helps these numbers.) UFC Freedom 250 Did Well…But I Have A Lot of Worries So what can we compare the fights to? Well, the good news is Nielsen put out that the fight averaged 7.0 million viewers for UFC Freedom 250, which is a solid number for a fight. We also know the length, at roughly 4 and a half hours. (I saw different run times, but this seems to be the consensus considering it started at 8 pm, had a delay and then finished after midnight on the East Coast. If you assume a shorter run time, then yes, the total hours viewed would go down.) That means I have the two numbers needed to add this to my Nielsen database. And then…I can compare this viewership to the NFL: And, uh, not great. But also within striking distance, mainly because the runtime for this event was so long. I’d also add that this event had viewership equal to a regular season NFL game on streaming, but if anything, it was more comparable to an NFL playoff or Super Bowl-esque event. And you can compare viewership to the top football games on broadcast, cable and streaming, and it’s not impressive at all: We can also compare it to other sports that week, including the NBA Finals and start of the World Cup: Again, not great. The NBA generated roughly four times as many average viewers each game for its NBA Finals. The World Cup has similarly big numbers. Also, that’s just a tiny fraction of the 25 most watched sporting events each week. The NBA, NHL and FIFA World Cup had many, many more games racking up hours. We could also compare this to other streaming programs to get an idea of “is this a good investment?” and here is how it ranks compared to other top Paramount+ programs: The worry here? Well, unlike scripted programming, which has rewatchability, older fights/sporting events have very little library value. Very, very few people are rewatching these fights, especially years from now. Paramount has also released datecdotes bragging about their subscriber numbers. Earlier this year, they claimed that the first UFC fight on Paramount+ brought in 1 million subscribers. Then, in their quarterly earnings report, they only ended up with 700K subs. Not great! They claimed they dropped lower-value international subscribers, but that’s why I tend to discount subscriber additions when they’re leaked to the press.1 I expect we may see a bump again for UFC Freedom 250, but I’d caution using subscriber growth so soon after these events to judge the success, since new subs with high churn (see Peacock) aren’t great either. Also, analysts often want to attribute all subscriber growth to their favorite/pet show, and that just doesn’t make sense. The biggest caveat for UFC Freedom 250 and Paramount’s very first UFC marquee event is that these could be high watermarks for the sport. UFC Freedom 250 had an incredible amount of earned media coverage compared to most UFC fights. I mean, it had wall-to-wall national news coverage in the lead up to the event. (The first fight also had a lot of promotion from Paramount since it was first.) Other fights could reach this bar—say the Conor McGregor return to the Octagon—but they’ll be fewer and far between. Was This Deal Worth It? All to ask: is this Paramount deal worth it? In this case, I think the UFC Freedom 250 numbers are more distracting than helpful. This fight did well and compares well to other top sporting events. But we know that the first marquee event was at least a third smaller, if Paramount’s own data is to be believed. And it’s likely the other fights are much, much, much smaller. And then you get to the paycheck that Paramount-Skydance paid. FIFA’s World Cup cost about the same for Fox, but clearly generated multiples more total viewership. (Though it’s only every four years.) The NBA is much more expensive, but until the playoffs, they likely didn’t pay for itself. Even still, Disney, NBCUniversal and Amazon Prime Video likely overpaid. So, in that context, the NBA may be an overpay that makes the UFC look not so bad. But two overpays don’t make an underpay, to paraphrase the old cliché about wrongs and rights. And looking at UFC Freedom 250 as the likely ceiling of MMA on Paramount+, Paramount-Skydance likely paid too much. Share 1 I would love regular reports on subscriber additions by programs, but as is, it’s mostly leaked or rumored in haphazard ways.
A Look At Live Nation Entertainment (LYV) Valuation After Recent Share Price Moves
Live Nation Entertainment (LYV) has drawn investor attention after recent share price moves, with the stock up 1.9% over the past week and 4% over the past month, while the past 3 months show a 2.6% decline. See our latest analysis for Live Nation Entertainment. Looking beyond the recent moves, Live Nation Entertainment’s 1-year total shareholder return of 13.97% and 3-year total shareholder return of 99.37% suggest longer term holders have seen stronger gains than the shorter term share...
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
Nashville's statement, Houston's surge & more from Matchday 20
By Charles BoehmThe days are growing shorter, and the kids are going back to school. The FIFA World Cup is in the rearview mirror, and so is Phase One of Leagues Cup.You might not have heard a starter...
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Apple reveals why watchOS 27 will be limited to Apple Watch Ultra 2 and newer models
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Smithsonian Brings Sandy Beach Scientists to Texas A&M Galveston
Scientists from the U.S. and South America are workshopping at Texas A&M University at Galveston (TAMUG) this week to expand sandy beach research and broaden collegiate learning opportunities.The Tides of Opportunity Project, co-led by the Smithsonian’s Marine Global Earth Observatory (MarineGEO) Program, TAMUG, the Smithsonian Marine Station, the Smithsonian National Zoo and Conservation Biology Institute, and the University of Miami, is a collaborative monitoring project with marine science professors and their students.Tuesday, Aug. 18, through Friday, Aug. 21, 15 professors and marine science professionals from the United States, Brazil, Peru, and Urugay will co-design a sandy beaches monitoring protocol and associated course modules and test the protocol in the field.The goal is to incorporate sandy beach monitoring protocols into marine science courses, which college faculty and students can use to achieve learning goals while providing essential data can help researchers diagnose the health of an understudied critical coastal habitat.Dr. Guilherme Corte, an assistant professor of marine biology in the College of Marine Sciences and Maritime Studies at TAMUG, is a principal investigator for MarineGEO. Texas A&M University at Galveston students and faculty package samples collected on the beach to take to campus for study in the Benthic Ecology Lab. Credit: TAMUG Division of Marketing and Communications“One third of the world’s ice-free coastlines are made of sandy beaches, and they go from pole to pole,” Corte said.However, despite their abundance and place as one of the most accessible coastal ecosystems for college-level education and research, they remain critically understudied.The Tides of Opportunity Project recognized that accessibility makes sandy beaches uniquely suited for engaging professors and students, including those with limited resources.“Any students can do sandy beach research,” Corte said, encouraging instructors to help students take a break from typing questions into artificial intelligence tools and embrace opportunities to do real science. “Providing this hands-on experience is something unique.”Tides of Opportunity Project goals include:Training a cohort of professors from across the Americas in standardized sandy beach monitoring methods; Equipping participating faculty with classroom modules, field tools, and multilingual teaching materials; Expanding MarineGEO with new monitoring sites focused on the implementation of long-term sandy beach monitoring; Strengthening hands-on, college-level learning experiences; And cultivating interest, learning, and efficacy in science among college-level students.By the end of this week, workshop participants plan to have a final version of the protocol and associated course modules that we can share with professors shortly after the workshop ends to then test with their students in courses that take place between September 2026 and February 2027.The scheduleDay 1: Tuesday, Aug. 18Location: Aggie Special Events Center (ASEC), Rooms 102 B and C, Texas A&M University at Galveston 8:30 – 9 a.m. Breakfast9 – 9:30 am Welcome and brief group introductions9:30 – 10 a.m. Introduction to Tides of Opportunity Project, Design Workshop, MarineGEO, and the Connecting Coastlines to Campuses Program (presentation)10 a.m. – 1 p.m. Introduction to workshop participants and project coordination team (presentations by each participant)• Brief lunch break from 12-12:30 p.m.1 – 3 p.m. Discussion about why collaborative science matters (presentation and interactive group discussion)3 – 4:15 p.m. Introduction to sandy beaches (presentation and group discussion)Day 2: Wednesday, Aug.19Location:• Morning sessions: ASEC Rooms 102 B and C, Texas A&M University at Galveston • Afternoon sessions: Corte’s field site (location available upon request)8:30 – 9 a.m. Breakfast9 a.m. – noon Prep for fieldwork (presentation and interactive group discussion)• Finish conversation about importance of studying sandy beaches• Go through sandy beaches monitoring protocol and field sheetsNoon – 12:45 p.m. Lunch12:45 – 1:30 p.m Prep for field (including driving to the field site)1:30 – 5:30 p.m. Fieldwork & bring samples back to TAMUGDay 3: Thursday, Aug. 20Location:• Breakfast: ASEC Rooms 102 B and C, Texas A&M University at Galveston • Fieldwork: Guilherme’s field site (location available upon request)• Lab/afternoon sessions: TAMUG lab (location available upon request) and ASEC Rooms 102 B and C8:30 – 9 a.m . Breakfast9 – 11 a.m. Return to field• Shorter field trip – recovering samples left out overnight11 a.m. – noon Lab work12 – 12:45 p.m. Lunch12:45 – 2:45 p.m. Continue lab work3 – 5 p.m. Discuss with professors the feasibility of implementing protocol in their courses and where might need to make changes (discussion)Day 4: Friday, Aug. 21Location: ASEC Rooms 102 B and C, Texas A&M University at Galveston 8:30 – 9 a.m. Breakfast9 a.m. – noon Group Discussion• How to evaluate student learning and engagement• Course modules• Next steps
Why the days feel shorter as you get older, according to science
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Islanders Training Camp News: Barzal health watch
The Islanders open training camp — which are now shorter than past camps per the new CBA — with news that Mathew Barzal will not skate for all of it “due to aggravation of a prior injury that has caused some inflammation.” So we are starting the season with Barzal out, and on Health Watch. […]
Why the days feel shorter as you get older, according to science
Scientists have several theories for why our perception of time changes with age
Hawaiʻi weighs shorter probation, lighter punishment for drugs
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Samsung to Get Jump on Apple’s First Foldable With New Phones in July
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SPECIAL REPORT: Tough Business
A string of vacant restaurant buildings shows that many restaurants in the region are struggling — and several are closing By Stefan Yablonski [caption id=attachment_11132 align=alignright width=401] Smokey Bones Bar & Fire Grill on Route 31 in Clay closed its doors in April. It had been in operation since at least 2008.[/caption] By their nature, most restaurants have a limited life. An astonishing 60% go out of business within three years of opening, largely due to fundamental flaws in the planning of the operation. But even restaurants that experience years of success almost always face eventual closure. The restaurant business is very hard and because of both personal factors and external factors beyond anyone’s control, restaurants don’t last forever. For many restaurants, age is a big factor, according to Kenneth Walsleben, professor of practice, entrepreneurship and emerging enterprises at Syracuse University. “The owners have been at it for 20 or 25 years, if not longer, they want some time to themselves,” he said. Such was the case for Jocko’s Famous Ritz Diner in Oswego. Jocko Reitz bought the building in the late 1970s from Robert Shapiro. However, when he stepped away from the business, it eventually closed. [caption id=attachment_11142 align=alignright width=402] For nearly 80 years, Vona’s Restaurant passed through three generations of family in Oswego. It closed its doors on Dec. 31, 2025.[/caption] For nearly 80 years, Vona’s passed through three generations of family in Oswego. Vona’s Restaurant officially closed its doors on Dec. 31, 2025, when no family member wanted to take over. It is on the market. The Ruby Tuesday in Oswego operated for about two decades before permanently closing in April 2026. The restaurant faced multiple temporary health department closures in 2024 and 2025 due to persistent fruit fly and foundation pest issues. Management posted a final closure notice on the doors in mid-April 2026 and the building was put up for sale. The same pattern has been happening in Onondaga County. The big building once used by Smokey Bones Bar & Fire Grill on Route 31 in Clay remains empty, more than six months after the restaurant closed its doors in April. It had been in operation since at least 2008. [caption id=attachment_11130 align=alignright width=401] Ruby Tuesday in Oswego operated for about two decades before permanently closing in April 2026.[/caption] Just down the road from Smokey Bones, the popular Outback Steakhouse closed in August 2024. Another restaurant took its place, La Cocina Mexican Restaurant, but it closed shortly after. The building sits empty. Other very popular restaurants in the northern suburbs of Syracuse have recently closed. Among them, Fireside by the River in Baldwinsville and Primo Nestico’s Bistro Bar in North Syracuse. “I haven’t really paid attention to the Syracuse area. There has always been some turnover, but there probably has never been a tougher time to be a restauranter than now. It’s just brutal,” Walsleben said. In the first year, roughly 20% to 25% of restaurants close or change hands, according to the National Restaurant Association. [caption id=attachment_11122 align=alignright width=401] Outback Steakhouse closed in August 2024. Another restaurant took its place, La Cocina Mexican Restaurant, but it closed shortly after. The building sits empty.[/caption] “Depending on what statistics you look at, you’ll find that any business has a high mortality rate in the first year. That is just the nature of entrepreneurship,” Walsleben said. “There are certain ones that are getting hit hard while others are more fruitful. “And when you look at the restaurant industry you have to factor in labor which is a large part — typically a third of your expenses — and those costs are going up. And there is always turnover which means investing money to train people. Then you’ve got food costs, which is also a third of the typical restaurant budget. Since the pandemic labor has gone up 41%, food costs have gone up 35%. That’s a big tight squeeze righty there. That’s two-thirds of your budget that has gone up 35% to 40% in the last few years. And then the only way you can make that work is to raise the prices.” The National Restaurant Association reports menu prices are up 36% since February of 2020. In a survey released by the association, more than eight in 10 restaurant owners reported that their food, beverage and labor costs are now higher than before the pandemic. You have to deal with the reality of are the customers willing to pay for that? Walsleben added. Restaurants historically have very thin margins; their profit margin is about 5%. “You have a third that goes into food, a third that goes into labor and about 28%, 29% that goes into everything else — overhead, insurance etc. So that brings you down to your 5% leftover,” he said. “Everything is going up. Customer expectations are going up and people aren’t going to spend that much more. So, you have a tight squeeze here,” Walsleben continued. “Restaurants who use delivery apps, they pay a fee to those guys. Those guys don’t work for free. So, you can kind of see where the squeeze comes from.” Stuck in the middle There are pockets of opportunity; the two extremes of the market can make a profit. But the middle gets squeezed out. “If you are a low-end fast-food kind of place, there is room for that. People have changed their budgets. They are still going out, but they are not spending more,” according to Walsleben. “The high end remains positive. If you have a restaurant that brings a specific experience … a great food product or you are catering to high end customers who aren’t so budget conscious, those patrons are going to expect a high-end experience. They expect excellent food every time. They are expecting excellent service. If you can meet those expectations there is room for you at the top. It’s just the guys in the middle are getting the squeeze from both ends. Tough competition, customer expectations, costs are up. Menu items, you can’t raise the prices as much as you need to. That is why you are seeing a lot of restaurants baling out.” The ones that can adapt quickly are the ones who are doing OK. “Success is heavily dependent on the strength of a restaurant’s concept development and the planning of its execution. Eventually things aren’t always new. Things change. So, if you are in the restaurant business you have got to change your menu — keep things new, fresh and update your meals. It is very fickle industry. One year carbs are out, the next year berries are out. Everybody’s diet changes — constantly chasing the latest phase. You have got to adjust your menu and move with those modifications. If you have a static menu that you have used the last couple years that hasn’t changed except for the pricing, you’ve got a problem,” he said. A lot of times these buildings are singular purpose, he added. “You have a commercially viable kitchen and you got a seating area. There is not a lot of other businesses that cater to that type of a layout. So, it’s pretty common to see another restaurant slide in,” he said. One of the things a banker learns early on is you don’t lend money to restaurants … because they fail so quickly. It is very hard to predict who the winners will be. So, if you are a restaurant in addition to all the other challenges, it is very difficult to get loans, according to Walsleben. “You might work really well in the kitchen. But that doesn’t mean you are a great businessperson,” he said. “Restaurants can fail because the owner didn’t know how to manage things properly. There are a lot of challenges. “There is opportunity at the high end and the low end. But in the middle, that’s the death valley. There are just so many things working against you. You really need to have something that will pull people in and continue to pull people in because you to constantly have to change. Think about a theme and a product that is unique to the area people don’t travel that far these days you have to be able to deliver it in an innovative fashion and keep updating to keep people coming in the door.” Out of Business? How Fast? Do nine out of 10 restaurants fail in their first year, as commonly claimed? No. Survival analysis of 1.9 million longitudinal microdata for 81,000 full-service restaurants in a 20-year U.S. Bureau of Labor Statistics non public census of business establishments in the western US shows that only 17% of independently owned full-service restaurant startups failed in their first year, compared with 19% for all other service-providing startups, according to ResearchGate. The median lifespan of restaurants is about 4.5 years, slightly longer than that of other service businesses (4.25 years). However, the median lifespan of a restaurant startup with 5 or fewer employees is 3.75 years, slightly shorter than that of other service businesses of the same startup size (4.0 years). What Makes a Restaurant Successful? Opening and maintaining a successful restaurant is not as easy as creating a great menu and serving excellent food. It takes more than that, according to local restaurant owners who have been in business for decades in the region. They all agree that there are some guidelines to running a successful restaurant. • Quality food: Successful restaurants know exactly what they serve and who they serve it to. Delivering the same great taste every single time builds loyal customers. • Smooth operations: Friendly greetings and attentive staff make guests feel welcome from the moment they walk in. Hiring staff for personality and training for skill ensures reliable, caring service. • Smart marketing: Exceptional food and experiences naturally get people talking and sharing online. Word of mouth can help entice customers. Consistent social media and targeted advertising brings in new and repeat guests also. The menu is what keeps patrons coming back to Mimi’s Diner in Fulton, located at 201 N. Second St. “We locally source our produce and our meats. Our chicken and biscuits is a popular, popular special,” said Richard Tagliareni, the third-generation owner and general manager. “It’s all homemade. We have consistently served quality food.” His grandfather started the business more than 55 years ago. Mimi’s is engrained in the community. They cater to the community and are very involved in everything from the schools to local events. The first Mimi’s Drive-In opened in Mexico. Then a second in Oswego and then Fulton. Fulton’s Mimi’s is the only one left. “The last couple of weeks have been kind of slower than normal. October is usually a busier month for us People will start coming back around again. Also, the price of gas is affecting some things,” Tagliareni added. “We try to keep our prices in line. You go out to eat, you’re going to spend about a hundred bucks or so for two people for dinner. You come here to Mimi’s you are probably for two people for dinner it’s between $50 and $60. We are trying to keep our prices in line. We did have to increase our prices a little bit but things are looking OK.” For the Press Box, 29 E. First St., Oswego, it’s also about great food and a family atmosphere. “Our sports bar and restaurant was established in 1984,” said Alison Canale Scanlon, manager. “I think putting the time into everything makes a big difference and treating people like family when they walk into your restaurant. That’s how we have always operated since 1984.” “It’s the family oriented aspect,” she added. “Consistency, quality and presentation of our food — that’s the secret to a successful restaurant. We try to be very consistent with it. We treat people like family when they come in; because we know how we want to be treated when we go to a restaurant. We treat people the same or better.”
iPhone 17's 8GB Limit Costs It These Two Siri AI Features in iOS 27
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Opinion: When voting rights are weakened, health suffers
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How proposed cuts to this major national health survey could disadvantage Americans with disabilities
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A Shorter Apple Pencil Was Supposed to Launch Alongside iPhone Duo
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This popular brain supplement was linked to shorter lifespans in men
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Time lost to political haggling means lost momentum for research
While it’s not up to universities to set deadlines for EU institutions, “lost time” in the run-up to the launch of the next Horizon Europe would translate into “lost momentum” for universities, according to Dag Rune Olsen, president of the Young European Research Universities Network.“I think it's important to have [the EU budget] in place in order to be able to work on the research funding mechanisms, because we cannot afford to lose more momentum than we already have,” Olsen told Science|Business in an interview in September, just after EU research lobbies gathered in Brussels to push for a €200 billion budget for the next Horizon Europe programme.A funding gap would mean ramping down research activities, said Olsen. “You can do that quite swiftly, that’s not a problem, but ramping up again is much more difficult.”The last-minute push for an ambitious budget, and for a timely adoption of the research programme, comes at a time when the richest EU states have teamed up to call for significant cuts to European Commission’s proposal for the next multiannual budget, which allocates €175 billion for Horizon Europe. At the same gathering of research associations in September, the European Parliament’s budget rapporteur warned that the EU will need to raise its own taxes, otherwise political pressure and tighter national budgets will translate into a limited EU budget with a less ambitious envelope for research. The research sector hopes EU institutions will reach timely agreement on the budget and on Horizon Europe, but progress has been slow. Legislative progress has been delayed, partly because the European Parliament’s budget committee is still haggling over how to apply new EU-wide spending rules, known as the Performance Framework Regulation, and partly because EU governments have yet to agree on the size of the next EU budget. EU research Commissioner Ekaterina Zaharieva told Science|Business in July that she was hoping for an agreement on Horizon Europe by the end of 2026, but the timelines have been pushed back significantly, with the Parliament now aiming to announce its official position on Horizon Europe only in November. Avoid the funding gapAccording to Olsen, delayed EU funds could prompt universities and researchers to move on and do something else, potentially jeopardising years of work building consortia and collaborations. “If funding is interrupted, the networks fall apart in just a few months,” he said. Olsen also noted that an interruption would affect junior researchers first. PhD students and postdocs are on shorter term contracts and universities risk losing them if funding for EU projects is interrupted. Related articlesEU own resources ‘essential’ for future research budget, says leading MEPParliament haggle over EU-wide spending rules delays vote on Horizon EuropeZaharieva hopes for a Horizon Europe deal in 2026Universities usually have more employees, permanent and short-term staff, than they can cover with national funding, and external funding is essential to keep them all on the payroll. In case of an EU funding gap, “there will be a huge number of people that might end up without any contracts,” he said. Apart from the money issue, Olsen said EU projects forces universities to collaborate more which, in turn, increases the quality of teaching and research. In case of a funding dip, people will look around for opportunities elsewhere, in the private sector or abroad. “And then then you have to recruit again, and it's a tedious business,” said Olsen. “A gap is not a good idea, it's actually a waste of money.”According to Olsen, the difficult political context should encourage universities to make a stronger case for the EU increasing research funding, as universities can deliver on competitiveness, technological sovereignty, security and defence. “The reason why we ask for substantial investments in research is exactly what the Commission, what Europe, the Parliament have been discussing,” he said. “You really need to invest in order to thrive in the longer run.”Focus on the member statesBut EU and national R&D expenditure hasn't kept up with the times. EU governments have failed to reach a spending target set almost 25 years ago. Only six EU countries spend 3% or more of their GDP on R&D. Asked whether universities should put more effort into convincing the governments to ramp up their own spending, but also to support a strong budget for Horizon Europe in the ongoing budget negotiations, Olsen said “the answer is yes.”“We are very actively encouraging our members to talk to their ministries in order to enlighten them about the joint effort,” he said. The network is made up of 25 universities from across Europe, all established in the past 60 years or so.Who will call the shots?Budget and timing issues aside, the Parliament’s research committee has been locked in behind-the-scenes negotiations over the future structure of Horizon Europe, with MEPs disagreeing on the degree to which its collaborative research should be governed by councils of experts.The European Parliament’s lead rapporteur on Horizon Europe wants councils of independent experts to decide on the funding agenda, but the Commission, the Council, and parts of the Parliament disagree. For Olsen, it is normal for politicians to point at the big challenges, but when they start detailing how those challenges should be solved, the endeavour “fails utterly.” He does not necessarily think that “bureaucrats who don’t know the field” would be “much better at it” either. “There has to be a combination” of broad political directions and bottom-up implementation, Olsen said.
Georgia lawmakers give businesses a boost in court battles
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Tennis Australia chief suggests Grand Slams cut back on best-of-5 matches
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Scientists Bred “Super-Athlete” Mice for 30 Years
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Scientists Finally Figured Out Why Big Dogs Age Faster Than Small Dogs
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WHO updated recommendations on HIV clinical management: recommendations for a public health approach
This document provides an overview of the updated World Health Organization recommendations for HIV clinical management, which focus on optimizing antiretroviral therapy, preventing vertical transmission, and enhancing tuberculosis prevention among individuals with HIV. These updates are intended to support global initiatives aimed at ending AIDS as a public health threat by 2030. Key changes include the introduction of new antiretroviral drugs and regimens, revised postnatal prophylaxis and breastfeeding guidelines for managing infants at risk of vertical transmission, and the endorsement of shorter tuberculosis preventive treatments to improve efficacy and adherence. The recommendations are designed to simplify and advance HIV care, promote equity, and contribute to improved health outcomes and quality of life for individuals living with HIV. The updated guidance will be incorporated into the forthcoming revision of the antiretroviral therapy chapter within the Consolidated Guidelines on HIV Prevention, Testing, Treatment, Service Delivery, and Monitoring: Recommendations for a Public Health Approach.
Scientists reveal why walking gets so much harder with age
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10 Healthy Brain Habits To Keep Your Career Sharp This Fall
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Mending Hearts: Danny Romary Turns Struggle Into Service
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The best new science fiction books of December 2025
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31 hours with the spit-shined Mina the Hollower (and 34 with the four games that came before it)
To truly appreciate Mina The Hollower, an extraordinary new throwback of a game, I sent myself to Yacht Club University. That’s not a real institution of higher learning, but it’s the best way I can explain much of the past several weeks as I prepared to play Mina by playing the four biggest game previously made by studio Yacht Club Games. I had expected Mina the Hollower, in development for six years for PC and consoles, to potentially be something special. A demo I tried in March had felt great. Mina the Hollower had an old-school premise: a singular move for its hero that felt so good to control and so rich with possibilities that, in the hands of skilled designers, it could be riffed on in various ways for the length of a full game. Mina’s core maneuver, her hollowing, made her sort of an upside down Super Mario. Nintendo’s hero jumps through the air, discovering power-ups at the apex of his jump by bonking overhead blocks, then defeating enemies by landing on them. Mina essentially jumps into the ground, digging (“hollowing”) into the earth to fetch buried treasure, then burrows for a short distance to emerge on the other side of a wall that hides treasure or an enemy that needs some battering. I wanted to understand how good Yacht Club was at making games. I wanted to see how far they’d come. If Mina was terrific—as I predicted it might be—I wanted to feel how they got there, one button press at a time. On May 6, 21 days before the writing of this review, I checked with Yacht Club Games co-founder and programmer David D’Angelo, to ask which of the studio’s games I should play to truly appreciate the new one’s design. “Hmmm all of them?” he wrote back. “Starting with Shovel Knight definitely is helpful,” he continued, referring to Yacht Club’s first game. He gave me a link to a spreadsheet of over 400 cheat codes that could help me out, if I found the game too tough.1 “Most folks say Specter of Torment is the least difficult and quickest to finish in terms of playtime, and [it] refines much of Shovel Knight,” he told me. “King of Cards is a big celebration of everything we did in [the Shovel Knight compilation] Treasure Trove— might work for you better if you’re a fan of shorter, Mario-style courses. And it’s probably the closest to Mina in terms of polish.” So that was that. Four games, none of which were required. Mina is a whole new game in a whole new world, best I can tell. I’d barely played that first Shovel Knight before and never the other three. I just thought it’d help. It did. It turns out that playing a game studios major works before their latest is very illuminating.
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Olympic ice surface being built to specs smaller than NHL rinks, per source, sparking new concerns
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Large dog breeds die younger. Biologists think they finally know why.
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The new shorter and wider, book-style foldable is likely to steal the show.
How hurricanes triggered lizards' rapid evolution
Hurricane season is upon us and it turns out that these powerful storms can quickly affect the biology of animals. After hurricanes Irma and Maria hit the islands that make up Turks and Caicos about a decade ago, the silver key anole adapted. They now have a shorter fourth toe on their hind legs! That could help them cling to objects better. But how do you know unless you put lizards in front of a fan and record how long they can hold on?This study is out now in the journal Current Biology.Interested in more science in the news? Email us your question at shortwave@npr.org.Support public media with NPR+ and enjoy perks for over 25 podcasts like this one. This show’s perks include sponsor-free listening. Learn more at plus.npr.org.
Oscar Health (OSCR) Stock Looks Cheap Relative To Its Earnings Path
Oscar Health has been on a powerful run in recent years, yet the real question for you today is whether the current share price lines up with what its earnings story can reasonably support. The stock has also seen shorter term pullbacks, which makes the earnings backdrop even more important for anyone trying to judge what they are actually paying for. Over the past 3 years the stock has delivered a very large gain of about 4.3x, which puts a lot of weight on whether the underlying earnings...
India’s entertainment sector eyes Netflix-Warner deal, fears impact
Films in Indian cinemas could be screened for a shorter period before they move to Netflix’s streaming platform, an association warns.
Tired of Being Tired? 7 Science-Backed Ways to Sleep Better
Daylight saving time starts in a few weeks, ushering in the longer nights and shorter days associated with winter. But for many people, the extra hours of darkness aren’t necessarily more restful. Experts say sleep deprivation is on the rise in the U.S. And the combination of stress, shift work and the false bravado of […]
ASUS launches GeForce RTX 5060 DUAL Evo series, slimmer design and shorter PCIe interface
ASUS quietly lists Dual GeForce RTX 5060 EVO and RTX 5060 Ti EVO models ASUS has added new Dual GeForce RTX 5060 EVO and Dual GeForce RTX 5060 Ti EVO
iPhone Duo could be very hard to get at launch, per report
iPhone Duo pre-orders open next month, and a new analyst report indicates the device could be in even shorter supply at launch than expected.
A university professor spent 100 days living in a 100-square-foot habitat 22 feet beneath a Key Largo lagoon — and when he finally surfaced, he measured half an inch shorter after spending the entire mission under elevated pressure
Joseph Dituri went into the water at 73 inches tall. He came out, 100 days later, at just over 72. The final measurement came on a Key Largo dock in June
A Chemical Spill Poisoned an Entire Town. Dogs Are Showing Scientists the Fallout.
Scientists are still trying to understand the extent of the damage, and the shorter lifespan of canines can expedite our understanding of these chemicals’ health impacts.
Dale Jr. Compares Keselowski Split to Kyle Busch’s JGR Exit
Dale Earnhardt Jr. says Brad Keselowski's split from RFK Racing reminds him of Kyle Busch leaving Joe Gibbs Racing. He believes Keselowski should have accepted a shorter deal.
NCAA changes college basketball transfer process with later portal dates, shorter window
The college basketball transfer portal won't officially open until after the NCAA Tournament
Is CVS Health (CVS) Still Attractive After A 27% One Year Share Price Gain
Some investors may be asking whether CVS Health offers good value at around its recent price, or whether much of the potential upside in the stock has already been realized. Over the past year, CVS Health has recorded a 26.8% return, with shorter term moves of 5.7% over 7 days and 6.8% over 30 days. These changes may have influenced how investors view its risk and reward profile. Recent coverage around CVS Health has focused on the company as a large, integrated healthcare player, with...
March Madness bubble watch: Indiana becomes NCAA Tournament contender
The NCAA men's tournament bubble will only get shorter as February rolls around, and Indiana has inserted itself into the March Madness conversation.
Xbox’s ‘Fable’ Is Reportedly As Long As ‘Avowed’
Fable's length has been revealed ahead of its Xbox release, and it's shorter compared to most modern RPGs outside of shorter ones like "Avowed."
Fall Events Preview: A look at what's happening in northeast Indiana
With Labor Day weekend comes the transition from summer to the fall events season. But just because the days are shorter doesn’t mean there isn’t a lot of fun to
Routine Reset: How to Prioritize Your Mental Health This Fall
School is back in session and life is getting back to normal, so psychotherapist Niro Feliciano stops by TODAY to share tips for resetting your routine. See her advice for dealing with shorter daylight hours and packed schedules, which includes “progress over perfection,” limiting phone use, going for walks, and more.
Is the universe ending sooner than we thought? New physics suggests a much shorter lifespan | - The Times of India
Science News: A groundbreaking study from Radboud University suggests the universe may end in approximately 10^78 years, significantly earlier than the previously assumed 10^1100 years. By revisiting Hawking radiation, researchers argue that all compact massive objects will evaporate, altering our understanding of cosmic lifespans.