SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " SPD " 49 found 🔀 AI-powered Shuffle
Most Fort Smith Board members avoid questions about Flock cameras
It’s unknown if Fort Smith will join a growing number of Arkansas cities taking action to end or curtail the use of automatic license plate reader (ALPR) cameras. City Director...
HOMETOWN HEALTH: Pediatricians warn raw milk can increase risk of life threatening infections
The AAP says the risk is even greater for young children and pregnant women.
Countries race to provide oral health care for all in 100-Day Sprint across Asia
Twenty Asian countries and areas across the WHO Western Pacific and South-East Asia regions vowed to strengthen essential oral health benefits as part of a “100-Day Sprint” initiative, during the 16th Asian Chief Dental Officers Meeting held from 27 to 29 September in Kota Kinabalu, Malaysia. The meeting marked the midpoint of the 100-day sprint bolstering support for countries to develop essential oral health benefit packages that can be integrated into national universal health coverage plans. Convened by the two WHO regional offices and the Malaysian Ministry of Health as the Secretariat, the meeting brought together national oral health leaders from 20 Asian countries, staff from all levels of WHO, WHO collaborating centres and other development partners. Participating countries and areas included: Bangladesh, Bhutan, Brunei Darussalam, Cambodia, China, Hong Kong (SAR) China, India, Indonesia, Japan, Lao People’s Democratic Republic, Malaysia, Maldives, Mongolia, Nepal, the Philippines, Singapore, Sri Lanka, Thailand, Timor-Leste and Viet Nam. Participants reviewed progress and refined proposals using the WHO Service Package Delivery and Implementation (SPDI) Platform. Countries conducted bottleneck analyses across four key areas: service delivery, workforce, access to essential medicines and health products, and health financing. They identified practical actions to address implementation challenges and refined proposed revisions to their national oral health benefit packages. “There is no health without oral health. Through the 100-Day Sprint, countries are advancing the implementation of the Western Pacific regional implementation plan on oral health and strengthening progress towards universal health coverage,” noted WHO Regional Director for the Western Pacific Dr Saia Ma'u Piukala. Participants identified bottlenecks and proposed workable solutions to strengthen access to essential oral health care through primary health care, sharing experiences and discussing how best to translate policy commitments into feasible and sustainable action at the country level. Malaysian Minister of Health Datuk Seri Dr Dzulkefly Ahmad highlighted the importance of prevention and primary health-care approaches to improve oral health: “Oral diseases can have lifelong consequences, yet many are preventable. By integrating essential oral health care into primary health care and promoting prevention in schools and communities, we can improve oral health across the life course.”The WHO team led by Dr Huong Tran, Director of the Division of Health Promotion, Disease Prevention and Control of the WHO Western Pacific Region and national oral health leads from over 20 Asian countries visited the SK Pekan Putatan School, Sabah for school oral health programme including flouride mouth rinsing. © WHO / V. ChaudharyDr Huong Tran, Director of the Division of Health Promotion, Disease Prevention and Control for the WHO Western Pacific Region, emphasized key collaborative roles WHO can play. “Oral diseases are the most common noncommunicable diseases, yet many can be prevented and treated through essential oral health services delivered at the primary health-care level,” she said. “By sharing experiences and using WHO tools such as the SPDI Platform, countries are accelerating progress towards universal health coverage for oral health.” “Integrating oral health into broader health services is essential for reducing inequities, expanding access and recognizing oral health as an integral component of overall health and well-being. The 100-Day Sprint provides an important opportunity to translate this commitment into practical action and ensure that quality oral health services reach all people, especially those most in need,” said Dr Suman Rijal, Director of the WHO South-East Asia regional Department of Healthier Populations and Noncommunicable Diseases. As host of the meeting, Malaysia showcased ongoing efforts to strengthen oral health care through primary health care and prevention-focused approaches, while providing a platform for countries across the two WHO regions to exchange experiences and accelerate progress towards universal health coverage for oral health. “WHO is encouraged by Malaysia's leadership in addressing the burden of oral diseases and advancing universal health coverage for oral health through practical, country-led action,” said Dr Rabi Abeyasinghe, WHO Representative to Malaysia, Brunei Darussalam and Singapore. Countries will continue to refine and figure costs for national oral health benefits during the remaining sessions of the 100 days. These efforts support implementation of the WHO Global strategy and action plan on oral health 2023–2030, while also helping to expand access to essential oral health services through stronger and more equitable health systems across the WHO Western Pacific and South-East Asia regions.______________For more information, or to arrange media interviews, contact: WHO Regional Office for the Western Pacific: wprocom@who.int WHO Regional Office for South-East Asia: SEMediaRelations@who.int
Countries race to provide oral health care for all in 100-Day Sprint across Asia
Twenty Asian countries and areas across the WHO Western Pacific and South-East Asia regions vowed to strengthen essential oral health benefits as part of a “100-Day Sprint” initiative, during the 16th Asian Chief Dental Officers Meeting held from 27 to 29 September in Kota Kinabalu, Malaysia. The meeting marked the midpoint of the 100-day sprint bolstering support for countries to develop essential oral health benefit packages that can be integrated into national universal health coverage plans. Convened by the two WHO regional offices and the Malaysian Ministry of Health as the Secretariat, the meeting brought together national oral health leaders from 20 Asian countries, staff from all levels of WHO, WHO collaborating centres and other development partners. Participating countries and areas included: Bangladesh, Bhutan, Brunei Darussalam, Cambodia, China, Hong Kong (SAR) China, India, Indonesia, Japan, Lao People’s Democratic Republic, Malaysia, Maldives, Mongolia, Nepal, the Philippines, Singapore, Sri Lanka, Thailand, Timor-Leste and Viet Nam. Participants reviewed progress and refined proposals using the WHO Service Package Delivery and Implementation (SPDI) Platform. Countries conducted bottleneck analyses across four key areas: service delivery, workforce, access to essential medicines and health products, and health financing. They identified practical actions to address implementation challenges and refined proposed revisions to their national oral health benefit packages. “There is no health without oral health. Through the 100-Day Sprint, countries are advancing the implementation of the Western Pacific regional implementation plan on oral health and strengthening progress towards universal health coverage,” noted WHO Regional Director for the Western Pacific Dr Saia Ma'u Piukala. Participants identified bottlenecks and proposed workable solutions to strengthen access to essential oral health care through primary health care, sharing experiences and discussing how best to translate policy commitments into feasible and sustainable action at the country level. Malaysian Minister of Health Datuk Seri Dr Dzulkefly Ahmad highlighted the importance of prevention and primary health-care approaches to improve oral health: “Oral diseases can have lifelong consequences, yet many are preventable. By integrating essential oral health care into primary health care and promoting prevention in schools and communities, we can improve oral health across the life course.”The WHO team led by Dr Huong Tran, Director of the Division of Health Promotion, Disease Prevention and Control of the WHO Western Pacific Region and national oral health leads from over 20 Asian countries visited the SK Pekan Putatan School, Sabah for school oral health programme including flouride mouth rinsing. © WHO / V. ChaudharyDr Huong Tran, Director of the Division of Health Promotion, Disease Prevention and Control for the WHO Western Pacific Region, emphasized key collaborative roles WHO can play. “Oral diseases are the most common noncommunicable diseases, yet many can be prevented and treated through essential oral health services delivered at the primary health-care level,” she said. “By sharing experiences and using WHO tools such as the SPDI Platform, countries are accelerating progress towards universal health coverage for oral health.” “Integrating oral health into broader health services is essential for reducing inequities, expanding access and recognizing oral health as an integral component of overall health and well-being. The 100-Day Sprint provides an important opportunity to translate this commitment into practical action and ensure that quality oral health services reach all people, especially those most in need,” said Dr Suman Rijal, Director of the WHO South-East Asia regional Department of Healthier Populations and Noncommunicable Diseases. As host of the meeting, Malaysia showcased ongoing efforts to strengthen oral health care through primary health care and prevention-focused approaches, while providing a platform for countries across the two WHO regions to exchange experiences and accelerate progress towards universal health coverage for oral health. “WHO is encouraged by Malaysia's leadership in addressing the burden of oral diseases and advancing universal health coverage for oral health through practical, country-led action,” said Dr Rabi Abeyasinghe, WHO Representative to Malaysia, Brunei Darussalam and Singapore. Countries will continue to refine and figure costs for national oral health benefits during the remaining sessions of the 100 days. These efforts support implementation of the WHO Global strategy and action plan on oral health 2023–2030, while also helping to expand access to essential oral health services through stronger and more equitable health systems across the WHO Western Pacific and South-East Asia regions.______________For more information, or to arrange media interviews, contact: WHO Regional Office for the Western Pacific: wprocom@who.int WHO Regional Office for South-East Asia: SEMediaRelations@who.int
Health insurance rates could increase 21%+ for Minnesotans in 2027
Minnesotans who buy their own health insurance or are covered through a small business could see significant rate increases in 2027.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Montrose Regional Health adds local artwork throughout hospital
New art committee selects pieces from local artists for hospital walls
Jiang Feng: The Unravelling of German & European Politics
A state election in eastern Germany has become a revealing test of the changing political landscapes of Germany and Europe, writes Jiang Feng, Professor and Chairman of the Council of the Shanghai Academy of Global Governance and Area Studies (SAGGAS) at Shanghai International Studies University. His analysis follows the decisive victory of the Alternative for Germany (AfD) (which has been classified as right-wing extremist by German authorities)in the state of Saxony-Anhalt on 6 September, in which it finished far ahead of its mainstream rivals. Jiang previously served as Minister-Counsellor at the Chinese Embassy in Berlin. The following article was published on 8 September 2026 on huanqiu.com, the online platform of the Global Times. On 6 September, the results of the state election in Saxony-Anhalt, Germany, were announced. The Alternative for Germany (AfD), classified as far-right by German authorities, made history by becoming the largest party in the state parliament, winning 43.8 per cent of the vote — twice its share in the previous election. The Christian Democratic Union (CDU), which had governed the state continuously for 24 years, won just 17.2 per cent, its worst result ever in Saxony-Anhalt. On the night the results were announced, the atmosphere at the CDU gathering was unusually calm. There was neither shock nor argument, as if the defeat had long been expected. Several veteran party members who had spent years working in the state government said: “Defeat is not a bad thing. It is time to make changes.” This state election has not only upended Saxony-Anhalt’s political landscape, but also laid bare the deep tensions between Germany’s traditional party structure and model of governance, on the one hand, and an increasingly polarised society on the other. Its repercussions are already being felt at the federal level, making Saxony-Anhalt a useful case study of the broader trend towards political polarisation and realignment in Europe. Governing Difficulties after Electoral Victory The most immediate consequence of the election is a historic setback for the mainstream party order that took shape in post-war Germany. In Saxony-Anhalt, the AfD has leapt from a peripheral party to the largest political force in the state. Its electoral base has expanded beyond the traditional category of “marginal protest voters” to take on the characteristics of a cross-class coalition. The party has not only consolidated its support in rural areas, but also attracted many middle-class voters and even members of the social elite with stable jobs, their own homes, and substantial incomes. It has thus evolved from a “protest party” into one with the potential to govern. Despite its commanding lead in the vote, however, the AfD faces an institutional obstacle to governing the state: the mainstream parties’ long-standing “firewall” against it. Neither of the two potential routes to forming a government appears likely to break the current political deadlock. The first would be a coalition of establishment parties, led by the CDU and bringing together the Social Democratic Party (SPD), the Greens, the Left Party (Die Linke) and the Sahra Wagenknecht Alliance (BSW) in a cross-camp government. In terms of parliamentary arithmetic, such a coalition could prevent the AfD from forming a government and preserve the outward stability of the traditional political order. Yet these parties are fundamentally divided over key issues including immigration, the energy transition, economic management, and cultural and education policy. Coalition negotiations would therefore be extremely difficult, and even if a government could be formed, it would most likely prove short-lived. More importantly, an alliance of establishment parties aimed at keeping the largest party out of government would play directly into the AfD’s narrative that “political elites are suppressing public opinion”. It could deepen perceptions of political unfairness, further strengthening the AfD’s political capital, and creating a dynamic in which “the more it is suppressed, the more people vote for it”. Ulrich Siegmund, the AfD’s candidate for state premier, has said that if efforts to form a government fail because other parties refuse to cooperate, the AfD will push for a fresh election, which he believes could deliver the party an absolute majority of seats. This points to more intense political battles ahead. The second option would be a coalition between the AfD and the BSW. Together, the two parties would command a simple majority in parliament, making this, on paper, the quickest route to forming a government. The BSW is the only elected party that has not ruled out cooperation with the AfD, and the two parties share some common ground, including on policy towards Russia. There is therefore a degree of political basis for cooperation. Were such a coalition to materialise, Germany would see its first state government jointly formed by a party defined as far-right and one with a far-left background, creating what might be called a “bipolar anti-establishment alliance”. Such an outcome would fundamentally break with the ideological boundaries of post-war German party politics. It is worth noting that even if the AfD ultimately fails to enter the state government, its roughly 47 per cent share of parliamentary seats would give it a powerful blocking minority. Without its consent, major decisions requiring a two-thirds majority — including constitutional amendments, significant budgetary adjustments, and state-level institutional reforms — would be extremely difficult to pass. Therefore, whoever ultimately forms the government, the AfD will be an unavoidable force in Saxony-Anhalt politics, with a direct influence on the state’s legislative process. Systemic Failures in Germany’s Governance Model The Saxony-Anhalt election result reflects a systemic failure of Germany’s post-war mainstream-party model of governance to adapt to rapidly changing socioeconomic conditions. It stems from multiple, mutually reinforcing structural tensions and highlights the existing political system’s difficulty in adapting to “an increasingly polarised society First, collective anxiety has replaced individual material hardship as a central driver of political mobilisation. The rise of the AfD can no longer be explained simply by poverty or social marginalisation. Its increasingly cross-class electoral base suggests that what is driving voters towards the party is, above all, concern about the broader direction of society. This anxiety about the future of the political community goes beyond individual gains and losses. In political discourse, economic anxiety has become closely intertwined with immigration, while immigration and refugee issues are, in essence, questions of social fairness. This perception turns conflicts over the distribution of social resources into negative assessments of governing parties, providing a broad social basis for far-right political narratives. Second, regional disparities and East German identity have undermined the strategy of addressing eastern Germany’s structural challenges at the regional level. More than three decades after German reunification, eastern states such as Saxony-Anhalt have experienced periods of economic growth, but their underlying economic structures remain weak, and household incomes and wealth remain significantly below those in western Germany. At the same time, they continue to face population outflow, an ageing population, labour shortages, and other structural challenges. At a deeper level, historical experiences — including the collapse of the former East German economic system, mass unemployment during the transition, and the westward shift of decision-making power over major issues — have left some residents with a sense of being “second-class citizens” and of being excluded. For years, the German government treated the “syndrome” of reunification as a regional problem to be gradually addressed at the local level. That approach is becoming increasingly unsustainable, as regional development disparities emerge as a core structural factor shaping national politics. Third, the erosion of institutional trust is perhaps the most decisive factor. AfD supporters tend to distrust establishment institutions, including parliament, government, and the mainstream media. Their concerns about economic security, pensions, and social fairness are significantly greater than the social average. Increasingly, their support for the AfD reflects not an expectation that the existing system can be improved, but a search for an alternative to the current political order. Such a systemic deficit of trust will be extremely difficult for the traditional parties to repair in the short term. Fourth, a generational shift in political mobilisation has amplified political polarisation. Unlike traditional parties, which rely heavily on offline rallies and mainstream media coverage, the AfD has developed a social-media mobilisation strategy built around “raising an issue — identifying who is responsible — offering a simplified solution — building a shared identity”. It turns complex social tensions into concise political narratives, rapidly channelling public sentiment into political support. The contrast on the eve of the election was particularly telling. The establishment parties, together with trade unions and churches, organised an offline march attended by more than 10,000 people, but its reach was largely confined to those present and to traditional media coverage. The AfD held a much smaller indoor event, yet livestreaming on TikTok, YouTube, and other platforms, combined with the involvement of online influencers, gave it a reach and mobilising capacity far beyond that of the march. The contrast illustrates how the traditional parties’ methods of political mobilisation are increasingly struggling to keep pace with a political environment transformed by changes in media technology. A Microcosm of Structural Political Change in Europe The shockwaves from the Saxony-Anhalt election quickly travelled beyond the state to the federal level. Calls for political accountability followed immediately after the results were announced. The governing CDU and SPD are now under enormous pressure, while Chancellor Friedrich Merz and Vice Chancellor Lars Klingbeil face an unprecedented test. Political polarisation in Germany is no longer simply a regional phenomenon. The post-war model of multiparty government by establishment parties is breaking down and being reshaped. Viewed in a broader European context, the Saxony-Anhalt election is part of a continent-wide wave of party polarisation, mainstream-party decline, and rising right-wing forces. Far from an isolated phenomenon, it is a microcosm of the structural political changes unfolding across Europe. Weak economic growth, cultural tensions over immigration, and declining trust in institutions are fuelling the rise of right-wing forces in several countries, challenging the liberal internationalist order established in post-war Europe. As a core member state of the European Union, Germany’s ability to adapt its political system and the direction of its politics will have profound implications for both European integration and the evolution of the international order. Subscribe [ Pekingnology China’s Germany watchers take stock of Berlin’s uneasy turn On 7 December 2025, nearly 50 Chinese scholars and policy researchers gathered in Beijing for the 2025年德国形势年终研讨会 “2025 Year-End Seminar on the Situation in Germany… Read more 9 months ago · 31 likes · 1 comment · YIRUI LI and Yuxuan JIA ](https://www.pekingnology.com/p/chinas-germany-watchers-take-stock?utm_source=substack&utm_campaign=post_embed&utm_medium=web&embedding_publication_id=1151841) [ Jiang Feng on Germany's 2025 and beyond: no easy exit ](https://www.eastisread.com/p/jiang-feng-on-germanys-2025-and-beyond) Yirui LI and Yuxuan JIA · Jan 24 The following is an op-ed by Jiang Feng, published on 29 December 2025 at Shanghai Observer 上观新闻, the digital platform of Jiefang Daily, the official newspaper of the Shanghai Municipal Committee of the Communist Party of China (CPC). [ Read full story ](https://www.eastisread.com/p/jiang-feng-on-germanys-2025-and-beyond)
Friedrich Merz fights for political survival after CDU debacle: 'Federal politics played a major role, and so did I'
Refusing to take sole responsibility for his party's defeats in the regional elections of September 6 and 20, the German chancellor has insisted he will not step down and has promised to reopen talks on reforms with his coalition partner, the Social Democratic Party (SPD).
AfD edges SPD in Meckpomm as Berlin swings left
Merz’s CDU slumps, with its worst-ever result in any election since the Second World War
16th Asian Chief Dental Officers Meeting: Advancing universal health coverage for oral health in the WHO Western Pacific and South-East Asia Regions
Session 3 of the 100-Day Sprint BackgroundOral diseases remain among the most prevalent noncommunicable diseases (NCDs) across Asia, affecting people throughout the life course and placing a significant burden on individuals, families and health systems. Countries across the World Health Organization (WHO) Western Pacific Region and South-East Asia Region have committed to strengthening oral health through regional action plans and by advancing universal health coverage (UHC). The 16th Asian Chief Dental Officers Meeting (ACDOM) serves as a regional platform for Chief Dental Officers in Asia to exchange experiences, strengthen collaboration and accelerate implementation of oral health commitments. For the first time, the meeting is being jointly organized by the WHO Regional Offices for South-East Asia and for the Western Pacific and the ACDOM Secretariat. This year's meeting introduces a 100-Day Sprint, bringing together oral health and UHC leads and technical experts to support countries in strengthening integration of oral health within national UHC benefit packages. Through the Sprint, participating countries will develop, refine, cost and operationalize country-specific essential oral health-care benefit packages using WHO tools, including the Service Package Delivery and Implementation (SPDI) Platform. The in-person 16th Asian Chief Dental Officers Meeting represents Session 3 and the midpoint of the 100-Day Sprint, providing an opportunity for countries to review progress, exchange experiences, identify challenges and refine their approaches before continuing with the remaining Sprint sessions. 100-Day SprintSession Date Format Title Session 1 (Day 0) 19 Aug Virtual Setting the Scene and Introducing Key Principles and Frameworks Session 2 16 SepVirtual Introduction to the SPDI Platform and Initial Mapping Exercise Session 3 27-29 Sep In-person, 16th Asian Chief Dental Officer Meeting, Malaysia Review and Refinement of Oral Health Service Packages Session 4 14 Oct Virtual Finalizing National Essential Oral Health Services Packages and Costing Exercise Session 5 (Day 100) 26 Nov Virtual Country Presentations and Closing of the 100-Day Sprint ObjectivesLeverage the 100-Day Sprint to define priority implementation actions for oral health in countries; Strengthen national capacity to design, cost and operationalize country-specific essential oral health care packages using SPDI platform; andExplore cross-country collaboration to expand access to essential oral health supplies and products, including harmonized specifications and pricing, and improve supply chains for essential dental preparations and medicines.Expected outcomesA draft country-specific essential oral health care benefit package developed using the SPDI platform and aligned with WHO’s Essential Oral Health Care packageA strengthened regional network in Asia of oral health and UHC leaders, fostering collaboration among South-East Asia and Western Pacific countries, WHO offices and WHO Collaborating Centres to support sustained implementation beyond the meetingParticipantsChief Dental Officers and national oral health programme leads;National focal points responsible for universal health coverage, health financing and health systems;Representatives from WHO country offices, regional offices and headquarters;WHO Collaborating Centres; andAcademic institutions and technical partners.
Is State Street SPDR S&P Health Care Services ETF (XHS) a Strong ETF Right Now?
Smart Beta ETF report for XHS
Shimano updates its road pedal system for the first time in 23 years
But new SPD-SLR pedal/cleat system is incompatible with current SPD-SL
Shimano releases new SPD-SLR pedal & cleat system in first shift from SPD-SL in 20 years
New SPD-SLR cleat system claims better engagement and lower stack, but isn't backwards compatible
Perinatal Mental Health Climb returns for 10th year at Wrightsville Beach
Families, healthcare providers and community advocates will gather to mark a decade of raising awareness and expanding local support networks for perinatal mental health next month.
Germany’s Political Tailspin: Your Weekly SPIEGEL Recap
It might be tempting to dismiss the results of last Sunday’s state election in Saxony-Anhalt, in which the far-right Alternative for Germany (AfD) party raked in 43.8 percent of the vote, as a rather unimportant extremist blip in a state that hardly anyone can find on the map. And you wouldn’t necessarily be wrong to do so. The state’s population – around 2.1 million – is a mere 2.5 percent of the German total. And while the state capital of Magdeburg was once the political heart of the Holy Roman Empire back when Otto the Great used to hang out there (more than a millenium … no … milennium … nope … millennium ago), it is today something of a backwater, albeit one with a ginormous cathedral in its center. We wanted to briefly interrupt this week’s newsletter to extend a heartfelt thank you to all of our subscribers, both new and old. And to remind you all that a free subscription gets you access to this newsletter every Saturday. A paid subscription, by contrast, gets you one DER SPIEGEL article every weekday, delivered to your inbox. We strive to select pieces that both demonstrate what Europe’s leading newsmagazine has to offer and provide an international audience – namely, you – with an insight into how Germany and Europe view the world. If you haven’t already signed up for a paid subscription, please consider doing so if you can. Our Substack channel relies entirely on reader support and we are excited to continue offering you the best of DER SPIEGEL. Subscribe But even beyond the fact that a huge percentage of the voters in the state decided to place an X next to a party with an ideological lineage that runs rather directly back to the right-wing extremist soup out of which the Nazi Party was born, the results are a perfect example of a phenomenon that has been plaguing German elections in recent years: the lack of an obvious path to a majority. Call it the Balkanization of German politics. There are a number of developments driving the phenomenon, but for the purposes of this newsletter, here are two of the most salient: Persistent voter frustration with the country’s two (former) big-tent parties – the Christian Democrats (CDU) on the center-right (17.2 percent in Saxony-Anhalt last Sunday) and the Social Democrats (SPD) on the center-left (9.3 percent). The presence of parties on the far left (Left Party), the populist left (the Sahra Wagenknecht Alliance – BSW) and the far right (AfD) with which mainstream parties are reluctant to form coalitions. So what happens now? Stories of the Week A Lack of Leadership The answer for many people in the country, and particularly within the CDU, is clear: pin (some of) the blame on Chancellor Friedrich Merz. According to a survey taken directly after the election in Saxony-Anhalt, 88 percent of respondents agreed with the statement that if the federal government in Berlin were doing a better job, the AfD wouldn’t be as strong. And it is true that the predominant impression of the federal government ever since Merz was sworn in on May 6, 2025, is one of ineffectiveness and bickering. His rather unique combination of bumbling-plus-bravado has also not exactly endeared him to the German public. Indeed, his standing in the country is so shaky that his popularity – according to recent polls – has now dropped even below the historic lows associated with his predecessor Olaf Scholz. The situation is such that the CDU even opted to keep him largely out of the campaign ahead of the Saxony-Anhalt vote. And since then, dissatisfied rumblings within the CDU have grown louder. DER SPIEGEL’s Swantje Karich notes that the problems with the CDU go much deeper than Merz. “The center-right has a trust problem. At a press appearance following the devastating election result in Saxony-Anhalt, Friedrich Merz said that the party wanted to ‘reach people more effectively’ through ‘emotional engagement.’ It sounded as though he were announcing a political program. On the basis of that statement, it is difficult to take his empathy seriously.” “The Chancellor’s chastened appearance did, at least, reveal where he stands: with his back to the wall. Elections will be held in Mecklenburg-Western Pomerania next week, and the CDU could fare even worse there. The party is polling at between 8 and 10 percent in the state.” “What is at stake is the political tradition that has lent stability to the Federal Republic since 1945: a democratic conservatism that understands what must be preserved, but also how to embrace progress and openness to the world. If the Union continues along its current path, it risks becoming politically irrelevant after the 2029 federal election – and Germany could soon find itself with a government of the far right.” The Trumpification of Political Debate? It is often said in Germany that to understand the political and social trends that will soon be dominant in Europe, one need only look across the Atlantic to the United States. When it comes to political debate, that has certainly proven true. Donald Trump understood early on that triggering mouth-foaming outrage among Democrats is an ideal way to both generate headlines and to secure loyalty among supporters. And he realized that far more quickly than the left side of the political spectrum understood that simply ignoring the old man might be the best recipe. To be sure, there have been signs recently that the US president may be over-relying on the strategy. Earlier this week, in an apparent grandpa-discovers-AI moment, Trump sent out 60 posts in the space of 10 hours, many of them AI-assisted images portraying him as a hero – or showing Iceland as part of the US (outrageous!!!). It was also during that slew of schlock that he explicitly backed the AfD with an “MGGA” post. In Germany, though, the outrage cycle remains in full swing, with much of the focus on those who would dare to vote for the AfD. They are alternately portrayed as being dim-witted, ungrateful, backward, racist or all of the above. That, argues DER SPIEGEL columnist Sabine Rennefanz, is not particularly helpful. “Everywhere on election night, people spoke of a watershed moment, a rupture, a turning point. But what is that supposed to mean in concrete terms? A watershed would imply an interruption, a moment of pause – perhaps even a willingness to rethink and learn. At first, there was little sign of that in the main television panels. Instead, the familiar rituals that had already shaped the election campaign continued: outrage, lecturing and abuse.” “That’s just the tone, one might object. They’re only talk shows. Given that the party’s state branch has been classified by domestic intelligence officials as confirmed right-wing extremist, there are more important problems than hurt feelings on television. Yet although the condescending tone is not the cause of the AfD’s success, it is an expression of the broader mood within the so-called political center – a kind of institutional blindness that too often treats material concerns as a communications problem.” “People have a pretty good sense of whether you like them – whether you approach them with curiosity or merely study, lecture and manage them as a problem group. They notice whether you genuinely want to understand their fears and pain, or whether you are simply waiting for the chance to correct them. They can also tell whether someone still has the energy to change things, or whether they have barricaded themselves behind platitudes and empty phrases.” “Anyone who wants an egalitarian democratic society cannot promise equality only to those whose language, tastes and moral convictions they share. They must also acknowledge the wounds, resentments and fears of those whose political conclusions they consider wrong. Acknowledging them does not mean agreeing with them. But a democracy that communicates with almost half its citizens only through warnings and labels gives up on political debate before it has even begun. An atmosphere must be created in which people can express their opinions without fearing that they will be canceled. We are currently a long way from that.” East-West? One of the clear undercurrents in the election last Sunday was, of course, Germany’s ongoing east-west divide, particularly as it pertains to the success of the AfD. Historically, the party has been far stronger in the former East German states than in former West German states. The fact that this generalization no longer reliably holds is certainly one of the primary concerns that many have about the party’s growth. And yet, there is still a distinct flavor of “stupid easterners, they don’t understand democracy” to the coverage. In the weeks before the vote, there was even a rather interesting back-and-forth in Germany’s culture pages about how ungrateful eastern Germans allegedly are for being pulled out of their pre-reunification backwardness and into the light of the West. DER SPIEGEL’s Jochen-Martin Gutsch has had enough. “Ten years ago, in 2016, elections were also held in Saxony-Anhalt. The AfD won more than 20 percent, which at the time rightly provoked outrage and incomprehension in western Germany. Today, in 2026, the AfD is also polling at around 20 percent in western German states, but this no longer provokes outrage and incomprehension. Instead, it is now regarded as proof of democratic conviction and civilizational resistance. After all, in the east, it’s 40 percent!” “This allows people to continue feeling morally superior to the East, but the wiser course would be to admit: if something doesn’t happen soon, the West will turn AfD-blue too. Or bluish.” “But will anything happen? The truly depressing thing about election night was not so much the AfD leaders intoxicated by their own success. It was the representatives of the other parties, who once again said that they were utterly shocked, needed some time to digest the result and would, of course, not simply return to business as usual. The SPD, a former big-tent party, celebrated its ‘stable’ result of 9.3 percent. Congratulations!” “For 10 years, the AfD has gone from one electoral success to the next. And still, the established parties remain ‘shocked’ and scratch their heads in astonishment. How long can they keep being shocked? Friedrich Merz says he may need to communicate his reform ideas in a more ‘emotional’ way. So the CDU’s political professionals sit down together after the election, mull over a strategy, and in the end come up with this: Fritz, try to be a little more relaxed, charismatic and emotional – or something. Beyond that: no political plan, no defiance, no promise of a future. That is frightening.” What was good, what was bad for democracy? Good: Voter turnout in Saxony-Anhalt was 77.8 percent, the highest ever recorded in the state. Whatever one thinks of the result, that figure is encouraging. Democracy needs citizens to take an interest. Bad: Although a strong AfD result had been expected in Saxony-Anhalt, many politicians from the mainstream parties – including in Berlin – appeared confused, helpless and overwhelmed in their initial reactions. That is not how they will win back voters’ trust. Last Week’s Highlights: 🗳️ Meet the Germans Who Voted for the AfD: Why would voters in a country like Germany, with its Nazi past, vote for a right-wing party? It’s a question only an editor in Berlin could come up with. On the ground, the view is different. 🟦 How the AfD Wants to Expand Its Power Across Germany: The far-right AfD is planning to decimate public broadcasting in Saxony-Anhalt, revamp education and install extremists in positions of power. And it is eyeing victory on the national stage as well. 🕯️ The Continuing Reverberations of September 11: It was a generational shock, and the consequences can still be felt today - from massive surveillance and significant increases in presidential power to violent excesses at ICE. 🤝 “For Europe, Canada Is the Preferred Partner in Trans-Atlantic Relations”: In an interview with DER SPIEGEL, Canadian Finance Minister François-Philippe Champagne discusses his country’s failed trade deal with the US and why Canada is looking to Europe. 🏛️ The True Historical Roots of the AfD: During the Weimar Republic in the 1920s, there were numerous parties on the extreme right espousing “Germany first” nationalism. The Nazis may not be the best comparison for today’s AfD. 🌊 AfD in a Landslide: Merz Is the Wrong Leader for Germany: The right-wing Alternative for Germany won in a landslide in Saxony-Anhalt state elections on Sunday. What does that mean for the country at large? Thank you for your continued support and have a wonderful week! Subscribe Share Leave a comment Your SPIEGEL Substack Team Compiled and edited by Charles Hawley
Big Three Entertainment Unions Back Trump's Film Tax Incentive | NewsRadio 1370 AM & 92.9 FM WSPD
Three major entertainment unions support President Trump's call for a federal tax incentive to boost U.S. film and TV production. The incentive aims to bring jobs back to America and compete with foreign subsidies. Unions emphasize the need for domestic production to sustain the industry and i...
UFC Shanghai Weigh-Ins Blunder as 3 Fighters Miss Weight
The UFC Shanghai weigh-ins featured a massive blunder as three fighters competing on Saturday’s card missed weight.The UFC travels to SPD Bank Oriental Sports Center for this weekend’s UFC Fight Night card, which features a five-round bantamweight bout between Umar Nurmagomedov and Song Yadong in the headliner.Thankfully, the main event is on, as both Nurmagomedov […] The post UFC Shanghai Weigh-Ins Blunder as 3 Fighters Miss Weight appeared first on HEAVY.
Germany's Climate Crisis: Why Politics Struggle To Keep Up
Germany is heating and drying up faster than ever. Yet climate change is not high on the agenda of many politicians. Together with sustainability researcher Maja Göpel and SPD climate spokesperson Jakob Blankenburg, DW’s Berlin Bureau Chief Max Hofmann examines the growing gap between climate reality and political action and asks: can Germany keep up with climate change?
ICYMI: here's the week's 7 biggest tech news stories from the Google Pixel 11 launch to Honor's revolutionary Robot Phone
Here's your firmware update for August 15, 2026
USA Wrestling Senior Sports Dietitian Nuwanee Tamaki contributes to American Sports and Performance Dietitians Association Women’s Wrestling Nutrition Guide
The American Sports and Performance Dietitians Association (ASPDA) has published a nutrition guide for women’s wrestling competitors, led by USA Wrestling Senior Dietitian Nuwanee Tamaki and Virginia Tech Associate Athletics Director for Sports Nutriti...
Under pressure over China backers, Mercedes CEO pledges to defend U.S. business
The U.S. Senate Commerce Committee approved legislation last week to toughen a ban on Chinese automakers entering the U.S. market.
Fort Smith Metro News Briefs: Physician, business award nominations sought, FSPD detectives recognized
Following are recent news brief items from the Fort Smith metro. Business Awards The University of Arkansas at Fort Smith Center for Economic Development (CED) and Jim Walcott Family Enterprise...
I Tried a Sensory Float Pod to Quiet My Mind—and It Was One of the Best Things I’ve Done For Myself in Years
After a four-day solo darkness retreat helped quiet my anxiety, I began seeking other wellness practices. Here’s what I learned.
SPDR Health Care ETF Tops iShares Biotech in Long-Term Returns
Compare portfolio diversity, risk profiles, and income potential as you weigh these two leading healthcare ETFs.
Tempo's Marina Mabrey ties WNBA records with 53 points and 9 3-pointers in rout of Sparks
Mabrey joins A'ja Wilson and Liz Cambage in the record books.
A Sweet End: Baton Rouge area bakery to close after years in business
A bakery in East Baton Rouge Parish is set to close this summer after its owners said they are pursuing careers that will allow them to spend more time with family.
Nothing new to report
Truly. Nothing new. Same ol’, same ol’ in this one. A 6-1 loss that felt pre-determined, or determined immediately after Pete Crow-Armstrong homered on the first pitch of the game thrown by Trevor McDonald. PCA continued to be a menace all evening: he collected two more hits, came up a triple shy of the cycle, […]
Powering Appalachia Expo connects business owners to valuable resources
Business owners from across the Mid-0hio Valley attended an expo aimed at connecting them to valuable resources.
Saints Jamie Meeks awarded ASPDA Service Award
Director of Sports Nutrition honored at American Sports and Performance Dietitians Association’s 18th Annual Conference
Two orphan manatees begin rehab at Bradenton's Bishop Museum of Science
IN BRIEF: Special blessing for new Epiphany Cathedral church bells; SPD supports Special Olympics; new Venice Middle School principal; Pinewood Derby.
Yankees announcer John Sterling passes away at 87
The sports world is mourning the loss of one of its most iconic voices. Longtime New York Yankees radio voice John Sterling has passed away at the age of 87. Sterling stepped into the Yankees broadcast booth in 1989 after spending much of the 1980s calling games in Atlanta for the Hawks and Braves. He…
Analysis | What Janet Mills’s failure to launch tells us about this political moment
The Washington Post’s essential guide to power and influence in D.C.
Ascension BioMedical Expands Cannabis Cultivation Capabilities in Oberlin, Ohio
The company is building a 28,000-square-foot facility and renovating a 19,000-square-foot facility.
Facebook removes page after William Shatner blasts 'horrible' AI-generated 'fake news' posts about him
Facebook removed a page containing AI-generated content after William Shatner blasted the 'horrible' posts circulating 'fake news stories' about him.
Exit polls suggest lead for Merz's SPD in key west German state
Far-right Alternative for Germany party (AfD) looks set for a record score in western Germany
Seattle business out $10K after burglary, owner blames SPD alarm policy
A Ballard business owner is out thousands of dollars after someone forced their way inside, and she says she feels little support from the city or police.
Businesses brace for crowds amid first St. Patrick’s Day with Redding Entertainment Zone
This marks the first St. Patrick’s Day since the Downtown Redding Entertainment Zone has gone live.
2026 Oscar nominations full list: 'Sinners' smashes record with 16 nods as 'Wicked: For Good' is snubbed entirely
Paul Thomas Anderson's "One Battle After Another" was second with 13 while Jon M. Chu's "Wicked" sequel was completely shut out.
Ravens shock NFL with aggressive Maxx Crosby trade
For the first time in the Ravens' history, the franchise will use a first-round pick to trade for a player.
Steelers to replace field at Acrisure after player backlash
According to Pittsburgh Post-Gazette’s Gerry Dulac, the Steelers are set to receive a new field at Acrisure Stadium.
$50,000 worth of Seahawks jerseys stolen from Seattle sports shop
The Seattle Police Department (SPD) says thieves stole over $50,000 worth of Seahawks jerseys from the Pro Image Sports shop next to Lumen Field on Sunday morning.
Geno Smith was a garbage time king in 2025
Las Vegas Raiders’ quarterback padded stats late in games
Evan Bouchard with a Goal vs. Washington Capitals
Evan Bouchard (Edmonton Oilers) with a Goal vs. Washington Capitals, 01/24/2026
2026 Oscar nominations full list: 'Sinners' smashes record with 16 category nods as 'Wicked: For Good' is snubbed entirely
Paul Thomas Anderson's "One Battle After Another" was second with 13 while Jon M. Chu's "Wicked" sequel was completely shut out.
Blues, Circa Sports to send two fans to Vegas for each remaining home win
To celebrate its new partnership with the St. Louis Blues, sports betting venture Circa Sports will award two lucky winners a trip to Circa Resort & Casino in Las Vegas for all home game wins at Enterprise Center the rest of the 2025-26 regular season. Circa Sports launched in the
Science Lab: The Unavoidable Facts of a Failed 2025
Welcome to "The Science Lab", a place where football facts and in-depth analysis always triumph over feelings.
Central Wisconsin officials earn Packers, WIAA November honors
Stratford and Stevens Point officials lead a group honored by Green Bay Packers and WIAA as November’s high school football crew of the month.
Mass. business confidence ticks up in November, but outlook still gloomy
AIM says resilient consumers and steady investment helped lift the index.