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Ascot reorganizes underwriting businesses, names division presidents
Ascot Group on Tuesday announced a reorganization that will bring its global insurance and reinsurance underwriting operations into a newly created division and establish a separate consumer lines…
Selling AI insurance was hard enough. Then they got into the cafe business
Corgi, valued at more than $5 billion, was forced to rein in its real estate expansion plans this month after a series of mishaps including a citation for rodents and departure of key dealmakers.
Axa XL launches dedicated excess and surplus insurer
Bermuda-headquartered Axa XL has launched Axa XL Excess and Surplus Lines Insurance Company, an entity dedicated to wholesale broker partnerships, Reinsurance News reported. It will begin underwriting…
How a bill intended to rein in NIL and 'protect' college sports could also save the US Olympic team
The Protect College Sports Act, passed by the Senate this week, aims to safeguard Olympic sports in the U.S. The bill addresses issues like name-image-likeness payments and requires colleges to maintain scholarships and roster spots for Olympic sports
Michael Douglas recalls conversations with Rob Reiner about having sons with ‘serious drug issues’
In his new memoir, Michael Douglas recalled conversations with Rob Reiner about having sons with ‘serious drug issues.’ Douglas’ son Cameron previously served a seven-year prison sentence for drug possession. Reiner’s son Nick wrote a semi-autobiographical film about his addiction.
Jayden Daniels returns to Commanders' practice, not concerned about potentially reinjuring elbow
Tekken 8’s Reina Teased as the Next Guest Character for Fatal Fury: City of the Wolves
Reina, who made her debut in Tekken 8, is coming to Fatal Fury: City of the Wolves. The announcement comes from a short teaser trailer from SNK Official.
Delaware or Texas? Business Court Dismisses Coinbase Shareholder Suit
The decision turned on a key difference between the two states. Because the company reincorporated in Texas, shareholders must follow Texas’ stricter requirement to demand board action and wait 90 days before filing a derivative suit, even when the alleged misconduct occurred while Coinbase was incorporated in Delaware.
Senate passes college sports bill that would rein in athlete payments and transfers
The Senate has passed a sweeping bipartisan bill that would regulate college sports.
Trendiana: New businesses in historic buildings
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How Extending CVS Distribution Through 2032 At Cardinal Health (CAH) Has Changed Its Investment Story
In October 2026, Cardinal Health announced it had entered into a binding Letter of Intent to extend its existing distribution agreement with CVS Health through June 30, 2032, maintaining the current scope of distribution services. This long‑dated extension reinforces the durability of Cardinal Health’s core distribution relationships, underscoring the importance of scale partnerships in its business model. We’ll now explore how the extended CVS distribution agreement through 2032 may...
Henrico Business Watch: Business license filings Sept. 24-30, 2026
Henrico County reported the following business license filings with start dates during the week. The filings are listed alphabetically by business or trade name, followed by a registered address and business industry classification. Better Health Psychiatry PLLC, 8206 Reinland Drive, Henrico – Nurse and personal care. C Squared Creations LLC, 5407
Republicans to spend $5 million in South Carolina Senate race as Trump plans trip there
The primary Senate Republican super PAC is sending reinforcements to South Carolina as President Donald Trump prepares to visit and boost Sen. Darline Graham | Newsradio 1140 WRVA
Expected Isaias losses unlikely to tip the market: Brokers
Preliminary projected insured loss estimates for Hurricane Isaias range in the mid-single-digit billions, as it moves toward the Eastern Gulf Coast on Friday, according to a reports by reinsurance…
Will AI kill the Asian entertainment industry, or reinvent it?
Studios in China are turning to models from ByteDance and Kling to generate 100-minute short dramas for less than $3000.
Collegiate sports reform bill is expected to pass in Senate, but House is unclear
The Senate is expected to pass the Protect College Sports Act to allow the NCAA to reinstate limits on athlete transfers and eligibility, opponents say it doesn't do enough to address rising spending.
Lexington restaurant reopens after health department reinspection. Why it closed
The restaurant was one of three closed by the health department last month. All are now back in business. What happened?
Inter Move Ahead of Milan for Cagliari Forward Paul Mendy
Inter have reportedly moved ahead of Milan in the race to sign Cagliari forward Paul Mendy, with the 2007-born attacker attracting interest from both sides of the city. No terms with Cagliari have bee...
90 Ideas in 90 Minutes: Dr. Teri Wahlig
Lead with purpose High-performing teams connect their work to something bigger. At ChildServe, we often talk about how every role fuels our mission, like a jet engine where each part matters. When people clearly see how their work contributes to lift-off, energy and alignment increase. Leaders can reinforce this by regularly linking day-to-day tasks to mission…
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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That will make it easier to assemble the majorities needed to amend the Constitution or impeach Supreme Federal Court justices. If elected, Flávio Bolsonaro could appoint four members of the Court, substantially altering its internal balance of power. What produced these results? How can the far right be prevented from consolidating them into a prolonged political hegemony? And what is the essential change of direction the left now needs? Explaining the Disaster Across the commercial media and the exuberant chaos of digital platforms, interpretations are multiplying. Some focus on specific episodes: Lula’s absence from the Globo debate, his very close relationship with Alexandre de Moraes, or his emphasis on issues supposedly remote from most people’s everyday concerns, such as rare earth minerals. Among the more systemic interpretations, three seem especially questionable. One argues that the principal defeat was not the left’s, since its congressional representation declined only slightly. The decisive movement captured at the ballot box, according to this view, was a shift within the right itself—from the more moderate and transactional forces of the Centrão toward the more ideological and radicalized forces of the PL and Novo. A second interpretation holds that the nature of electoral and political processes has changed. The material interests and aspirations of society, it argues, no longer play the central role they once did; they have given way to forms of subjective self-identification that the left has yet to understand. And a third concludes that, because of these two developments, we should expect a political winter: a prolonged period in which the far right and the broader right dominate Brazilian political life. There are important elements in all three interpretations. The problem lies in what they deny or leave out: Lula’s third government was a small-bore government. It offered the majorities that elected it neither a clearly better life nor reasons to believe again in politics and its power to transform society. These failures flowed from two fatal accommodations, which I will examine below. As a result, the government suffered a slow but steady erosion of support. And, as has happened in so many Western countries, it gave the far right the opportunity to present itself as anti-system and to benefit from popular frustration and distress. The interpretation that emphasizes the migration of votes from the center-right and traditional right toward the far right has been advanced, among others, by the courageous journalist Leonardo Sakamoto. In his UOL column on Monday, October 5, he highlights the miserable behavior of the traditional conservative parties. Over the past four years, they repeatedly joined forces with the “neo”-fascists, helping to “normalize” them—a criticism that could equally be directed at almost the entire corporate media. Believing they could use the far right as a stepping stone, they instead ended up partly devoured by it. This was especially true in the Senate, where the PL’s gain of 13 senators and Novo’s gain of two came at the expense of the PSD, which lost nine; the MDB, which lost two; the PSDB, which lost two; and the PP, which lost one. Sakamoto’s observation is accurate and necessary, but it leaves uncomfortable questions unanswered. Why did the erosion of the Centrão benefit the far right rather than, for example, producing growth for the left—as has happened so many times before, both in Brazil and elsewhere? The answer is not difficult. Throughout its four years in office, Lula’s third government was almost invariably associated with the Centrão. Here lies its first accommodation: accepting the limits imposed by conservative institutions; avoiding, as much as possible, any attempt to strain those limits through popular pressure; and believing only in the modest changes that could be squeezed through openings in Congress. The failure of the campaign to end the six-day workweek is emblematic. Lula could have electrified the presidential race by pairing it with a popular campaign for passage of the measure. Instead, he chose to place his hopes in the hands of Senate president Rodrigo Alcolumbre. He generated no mass mobilization, did not force his opponents onto an uncomfortable defensive, and won no victory. In September 2025, the government squandered the greatest of its many opportunities to shake up conservative power in Congress. Popular opposition to the so-called Shielding Amendment—which, if approved, would have restricted criminal proceedings against members of Congress—brought crowds into the streets, mobilized primarily by artists and social movements. This opened the possibility for a broader political education: a campaign that could begin exposing the limits and dysfunctions of Brazil’s political system while putting Bolsonaro’s movement on the defensive for its predictable support of political privilege. The amendment was defeated. But the executive branch then backed away from the fight. It remained associated with an institutional world widely seen as corrupt, elitist, and indifferent to ordinary people’s struggles. In doing so, it forfeited its credibility as a vehicle for the protest vote. On Sunday, it reaped the bitter fruits. Are We Doomed? Taking a different approach from Sakamoto, the philosopher Moysés Pinto Neto and other writers have drawn attention, in their first analyses of October 4, to the fragmentation of the public sphere produced by Big Tech platforms. Through their algorithms, these platforms present each person with a different view of social reality. As a consequence, it becomes much harder to identify common material problems and demands—for example, the fight for labor rights or for a properly funded public health system. Voters no longer embrace such demands, these authors argue, because they no longer see themselves as part of a collective. Instead, they tend to value the identities assigned to them by neoliberal subjectivity—the role of the entrepreneur, for example. On this interpretation, the left’s possible error lies in clinging to outdated illusions. Moysés’s warning is highly relevant and resonates with arguments such as Naomi Klein and Astra Taylor’s “Apocalyptic Fascism and the Billionaires’ Bet.” Unlike a century ago, the far right no longer promises a radiant future. It concentrates instead on resentment—especially that of young men. “They belong to a generation that fears it may never own a home, but compensates with the pleasure it gets from constantly provoking progressives online. Convinced their future has been stolen, they share memes romanticizing historical authoritarian regimes,” the authors write. But Moysés seems to confuse this danger with inevitability. He fails to see that the left’s answer cannot be adaptation. On the contrary, it must strengthen the possibility of politics as collective action. Nor does he recognize that precisely such a reversal is already becoming possible in some of the most promising mobilizations of the twenty-first century: the election, at the end of 2025, of the young Muslim Zohran Mamdani as mayor of New York, on a platform centered on the intensely material fight for an affordable city; the Left Party’s victory in Berlin two weeks ago, built around the demand to expropriate private real-estate corporations; and the very recent wave of demonstrations in Spain—including an occupation of Madrid’s Puerta del Sol—in which tens of thousands of young people mobilized by the Tenants’ Union have demanded limits on rents. By putting itself in the straitjacket of the “fiscal framework” in the first months of 2022, Lula’s third government adopted the second fatal accommodation of its term. Faced with conservative institutions and a country devastated by four years of Bolsonaro, increased public investment was the government’s remaining weapon for offering a more dignified life to the majority and forging an anti-conservative pact with them. The same state that disburses 1 trillion reais a year to enrich a small class of rentiers could instead spend money to extend the Family Health Strategy to every Brazilian, at a cost of 30 billion reais; provide full-day public schooling and childcare to all adolescents and children—and, especially, relief to their mothers; achieve universal sanitation while cleaning up polluted urban rivers; multiply metro systems; begin transforming the urban peripheries; and undertake many other urgently needed projects. In April 2023, an article in Outras Palavras warned that the fiscal framework could “shrink the Lula government and preserve the forces that condemn the country to inequality and regression.” A year later, another article showed that restraints on public spending were strangling policies vital to ordinary people and undermining the president’s popularity. In November 2024 came a reality check, in the form of the government’s humiliating defeat in the municipal elections. Even then, the fiscal lock was neither removed nor loosened. On the contrary: throughout the government’s four years, fiscal restraint remained central to its political narrative. The administration proudly proclaimed that it had “put the state’s accounts in order,” without grasping either how misleading that phrase was—given the payment of 1 trillion reais in interest—or how badly the message was hurting it politically. Lula finally woke up in September 2026. The increase in Bolsa Família benefits, after four years of being frozen; the announcement that anti-obesity drugs would be offered through Brazil’s public health system; and the ban on online betting showed that the state has the power to act decisively on behalf of the majority when those in government are willing to confront obstacles. The huge marches that closed the campaign in Fortaleza, Salvador, Rio de Janeiro, and São Paulo on the eve of October 4 showed how such initiatives can mobilize activists and the broader public. But it was too late—and too little to change the outcome of the first round. History has not ended The possibility of a turnaround in the three weeks leading up to November 25 cannot be ruled out. It will not be simple or easy. Lula must not only make up a deficit of 2.2 million votes; he must also offset the movement of voters who backed other right-wing candidates in the first round, most of whom are likely to move toward Flávio Bolsonaro. Pulling that off will require a broad, grassroots effort to win over voters, potentially reinforced by new initiatives from Lula. The coming hours and days will be decisive. If Bolsonaro’s movement also wins the presidency, the result will create a high-risk situation for Brazilian sovereignty and democracy. The enormous challenges posed by such an outcome would require the left to reexamine, in depth and with a genuine willingness to engage in self-criticism, its political projects—or its lack of them—and its practices. But would that mean we are condemned to the long winter of far-right hegemony that some analyses are beginning to forecast? It is far too early to say, suggests a recent text by Álvaro García Linera, the thinker who served as vice president of Bolivia under Evo Morales. His central hypothesis is that this political current will prove short-lived. At a moment when the entire world is once again talking about sovereignty and protecting national economies, the far right offers a stale, recolonizing neoliberalism. Its submission to the United States is as blatant and pathetic as Flávio and Eduardo Bolsonaro’s overtures to Donald Trump. Its project amounts to something like every man for himself: greater inequality, capitalism without limits, devastation, and supremacism. Will it work? In the United States, just two years into his second term, Trump himself is reaching record levels of unpopularity and may be on the verge of losing Republican control of both the House and Senate in November. Every new beginning is difficult. Whatever the outcome of the second round, the defeats of October 4 show how profoundly the Brazilian left will have to rethink and rebuild. But just as it would be foolish to underestimate the seriousness of its mistakes, it would be equally foolish to conclude that rebuilding a political project is no longer possible. History has not ended. The times are moving faster than ever. Originally published in Portuguese by Outras Palavras. English translation by Eric Blanc; I’ve added the subtitles. More We can’t stop the far right at home or abroad without a revitalized labor movement, which is yet another reason why you should become a sustaining supporter of the Emergency Workplace Organizing Committee (EWOC) — one of US labor’s pivotal bright spots. Relatedly, Jacobin published a short piece of mine reflecting on a decade of Bernie Sanders inspiring a whole new generation of young worker organizers.
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Credit: Matt Bradbury October 5, 2026 - By Isabella Backman - Anxiety disorders are the most common mental health challenges in youth. Left untreated, they can disrupt the lives of both children and their families. The good news is that with intervention, most children will overcome these conditions. Across Yale School of Medicine, scientists are working to understand anxiety at every level, from common anxious behaviors to molecular biomarkers in the brain. They are using their findings to develop and disseminate new evidence-based treatments for childhood anxiety. Today, the go-to treatment for childhood anxiety disorders is cognitive behavioral therapy (CBT). This is a form of psychotherapy that teaches children skills for confronting anxious thoughts and helps them practice managing situations that cause anxiety. While it is the gold-standard treatment backed by considerable scientific evidence, up to 50% of children will not see sufficient benefit from CBT alone. Wendy Silverman, PhD, Alfred A. Messer Professor in the Child Study Center, co-directs the Anxiety and Mood Disorders Program alongside Eli Lebowitz, PhD, associate professor in the Child Study Center. One of their main interests is learning how to improve outcomes beyond CBT. “We’re developing cutting-edge, research-based knowledge that can reduce the suffering that anxiety causes children and their families,” says Silverman. Changing parent behavior YSM experts are investigating how to improve CBT outcomes for children by involving the parents. Silverman’s research has uncovered two main components of parent intervention that improve childhood anxiety: not enabling children to completely avoid the things that make them anxious and taking steps to enhance their autonomy. Parents may unintentionally reinforce their child’s anxiety by allowing them to avoid what makes them anxious. They also may unintentionally limit the children’s sense of autonomy by being overly intrusive. “One of the things that we take pride in is that we’ve focused on trying to understand what parents need to do, and to test our ideas and see if changing the parents’ behaviors is enhancing the effects of CBT,” Silverman says. “Our findings thus far suggest that they do." As much as CBT can be helpful, it can also be challenging to get one’s child to do the necessary steps for CBT to work. This is one important reason why Lebowitz created a novel intervention program for parents named Supportive Parenting for Anxious Childhood Emotions (SPACE). Existing intervention programs often teach parents to act as therapists for their child, such as training them on how to practice breathing exercises. “It makes sense, but this doesn’t work very well in practice,” says Lebowitz. “And part of the reason, I think, is that it’s not easy to get your kid to do things, especially if they’re not excited about doing it.” SPACE is unique because it focuses entirely on parent involvement and changing parental behavior—children are not involved in the sessions. For example, parents learn how to use supportive messages that convey confidence that their child can tolerate and manage distress. “It might sound like a parent saying to a child, ‘I get that this is really hard for you, but I know that you can handle it,’” Lebowitz says. The program also works with parents to identify the ways in which they are accommodating anxious behaviors. “We’ll pick one thing that parents are doing that is an accommodation and help them make a detailed plan for how they’re going to change that,” Lebowitz explains. Treating Anxiety in Children and Adolescents Much of the existing research on SPACE has focused on parents of children under age 14. Ongoing studies are now exploring its use with parents of older teens. “Both anxiety and accommodation can interfere with normative developmental shifts during the teen years, including increased autonomy and individuation from parents,” says Rebecca Etkin, PhD, associate research scientist in the Child Study Center. “In this sense, SPACE may be particularly well-suited for anxious teens and their parents. We want to see whether it is effective during this distinct developmental window.” Unfortunately, many families in need of CBT face barriers, including limited availability of services and geographic constraints. One way to improve access is digital interventions. Silverman and her team are developing an evidence-based digitized intervention program for parents that they can access directly from their computer or smart phone. “The work we’re doing will be one of the very few parent interventions that is digitized and importantly tested for effectiveness,” she says. Creating interventions for anxiety-related challenges Silverman and Lebowitz recently received a generous gift to develop and test other interventions that help parents reduce other child anxiety-related behavioral and emotional difficulties, such as restrictive eating and unexplained somatic symptoms. One of these projects in particular focuses on understanding the risks of social media and its potential benefits, including offering a sense of connection. “A lot of research has focused on the idea that social media is harmful and the less of it the better,” says Lebowitz. “But we actually see is that this is not quite right—there are negatives, but there are also positives. So, we’re trying to get a little bit more nuanced of a picture.” The team is working with teens with social anxiety and their parents over an extended period to better understand their social media habits and how their anxiety levels affect engagement with different platforms. The teens will answer questions sent to an app on their phones about mood and social media usage in an effort to capture emotional responses as they unfold. “We hope to develop interventions that can help make the best of social media while protecting against the more problematic effects,” Lebowitz says. The brain’s role in anxiety Researchers are also testing therapies to address anxiety at the neurological and molecular levels. In collaboration with Dylan Gee, PhD, professor of psychology in Yale's Faculty of Arts and Sciences, and Hilary Blumberg, MD, John and Hope Furth Professor of Psychiatric Neuroscience at Yale School of Medicine, Lebowitz and Silverman are using brain imaging to identify changes in a child’s brain before and after parents enroll in SPACE. In one study, children viewed anxiety-inducing images while undergoing magnetic resonance imaging (MRI); the researchers conducted scans with and without the children’s parents nearby. Before SPACE, children’s brains were better able to activate the regulatory circuitry needed to turn off an anxious response when their parents were nearby. But after SPACE, children could activate this circuitry even without the parent around. “As parents work on gradually reducing some of their accommodations, you can see a child get better at regulating their own fear system in the brain,” Lebowitz says. “It’s remarkable.” Research into the molecular underpinnings of anxiety can also inform new childhood anxiety treatments. In a recent study, Lebowitz, Silverman, and Flora Vaccarino, MD, Harris Professor in the Child Study Center, discovered that a protein known as fibroblast growth factor 2 (FGF2) could be protective from the toxic effects of stress. FGF2 levels in children and their parents were linked to the children’s risk of developing anxiety and depression, the study showed. The findings could help explain why some children who are exposed to early life trauma such as poverty or abuse are more prone to developing mental health disorders. And FGF2 could be a target for treatment. “This is very novel because it starts to give a clue to what is the molecular chain that connects those lived experiences to the actual psychological outcomes,” Lebowitz says. New ways to study and treat childhood anxiety Michael Crowley, PhD, associate professor in the Child Study Center, collaborates with Silverman and Lebowitz to study the role that attention plays in development and maintenance of childhood anxiety. There is a large body of research that shows that anxious children, like anxious adults, are prone to focus on threatening stimuli such as angry faces compared with neutral faces. This has led to innovative interventions that involve attention retraining. The idea is that if experts train children to look away from threatening stimuli, it may reduce their anxiety—especially children with social anxiety who are most prone to attend to threats. The researchers have just completed a clinical trial for attention retraining with 10- to 14-year-olds with social anxiety disorders and are currently analyzing the findings. Besides this innovative attention retraining research, as Crowly notes, “I like to design tasks that are engaging to kids,” Crowley says. “My goal is to assess something without the kids knowing what we are assessing.” With this goal in mind, Crowley has created a virtual game, named Boom, to study threat processing in children with anxiety disorders. The game is similar to that of hot potato—the child and three digital players take turns virtually passing a ball to each other’s gloves. At some point, the ball turns into a bomb, and as the bomb lands in each player’s glove, the outline of the glove turns yellow. The goal is to avoid having the bomb go off in your glove. What isn’t obvious is that the game is designed to measure different types of threatening stimuli, both ambiguous and direct. In the game, the direct threat occurs as the bomb is traveling towards your glove. The ambiguous threat is the yellow outlined glove as it is unknown where the bomb will travel next. While children play the game, Crowley’s team measures their brain activity using electroencephalography (EEG). The researchers have discovered that in kids with anxiety, the brain reacts more strongly to ambiguous threats than it does in their peers, but less strongly to direct threats. They believe that the initial abnormally large brain response to not knowing where the bomb is going impairs the brain's ability to properly respond when the threat is actually traveling the child’s way. “The brains of children with anxiety are unable to differentiate between threats you need to do something about and those that are not your problem.” Michael Crowley, PhD, develops innovative games for studying anxiety in children and adolescents.Credit: Matt Bradbury Based on these insights, Crowley hopes to study whether interventions like attention training could restore appropriate threat processing. Crowley’s team is also working on a test called the Balloon Risk Avoidance Task, which evaluates risk-taking and avoidance behaviors. It features a digital balloon that is full of air and about to burst. Kids have six seconds to let air out of the balloon. The more air they let out, the less risk they face that the balloon will pop. But at the same time, the balloon becomes less valuable as it deflates. “The more air you keep in the balloon, the more points you get,” Crowley explains. So far, the researchers have found that when the balloons pop unexpectedly, teens with social anxiety show distinct brain responses. Studying these responses can help psychologists understand the underlying pathways driving the various manifestations of anxiety. The genetics of anxiety When Thomas Fernandez, MD, associate professor in the Child Study Center and of psychiatry, was still in training, there was a lot of excitement about understanding the genetics associated with autism spectrum disorder. Since then, scientists have identified around 250 genes associated with autism. The genetic contribution to anxiety disorders, on the other hand, has historically received less attention. Anxiety is less heritable than autism, but the genetic contribution for anxiety disorders that emerge in childhood may be higher than for anxiety disorders overall. While scientists estimate the heritability of anxiety disorders in general to be around 30% to 50%, some studies suggest higher heritability for certain childhood-onset anxiety presentations. “I saw firsthand how researchers in the field went about finding vulnerability genes for autism,” Fernandez says. “So, we’re using a very similar playbook for childhood anxiety.” “I saw firsthand how researchers in the field went about finding vulnerability genes for autism. So, we’re using a very similar playbook for childhood anxiety.” Thomas Fernandez, MD Associate Professor In the Child Study Center and in Psychiatry Now, Fernandez and Emily Olfson, MD, PhD, assistant professor in the Child Study Center, are studying children and their parents to identify genetic changes that are present in the child but not the parents, known as “de novo mutations.” “All of us have some de novo mutations—maybe about 50 to 100 sprinkled throughout the genome,” Olfson says. “But when they occur within the coding regions of genes, they can be really disruptive.” Previous research shows that people with autism have higher rates of damaging de novo mutations than the general population. In 2022, Olfson, Lebowitz, Silverman, and Fernandez published a study on 68 children and their families that found that children with anxiety had similarly high levels of these mutations. Studying de novo mutations can help point the researchers to where they should be looking for genes associated with anxiety. “The end game is using the genes to steer us toward the right part of biology that we can then target to come up with better treatments,” Fernandez says. Building on those findings, the team is now studying more families to better understand how these de novo mutations, along with other genetic and environmental factors, shape pediatric anxiety disorders. They recently received a National Institutes of Health grant to enroll 750 new families over the next five years. Olfson is the principal investigator, with co-investigators Lebowitz, Fernandez, Silverman, and Shuangge Steven Ma, PhD, department chair and professor of biostatistics at Yale School of Public Health. Neurodevelopment, Risk Genes, and Mental Health Conditions - The Olfson Lab Joel Gelernter, MD, Foundations Fund Professor of Psychiatry, is interested in how different anxiety disorders differ genomically. “We are studying social phobia, panic disorder, and generalized anxiety disorder, working to understand why people differ in their risk to these specific anxiety disorders and evaluating various risk factors,” he says. Gelernter was recently involved in one of the largest studies to date of the genomics underlying anxiety disorder. The study included around 122,000 people with anxiety disorders and around 730,000 without. It found that some genetic differences associated with anxiety were linked to signaling that helps reduce overactivity in the nervous system. Many anxiety medications available today work by targeting this process. “It’s nice when the biology that you get out of a large genome-wide study ratifies things that we already know because that can help increase confidence in further findings from the study,” Gelernter says. Uncovering the neurobiology of psychiatric disorders John Krystal, MD, Robert L. McNeil, Jr. Professor of Translational Research and chair of the Department of Psychiatry, is interested in the neurobiology of psychiatric disorders, including post-traumatic stress disorder (PTSD), of which anxiety is a major symptom. In the late 1980s, Krystal’s team discovered that the drug yohimbine activated symptoms in patients with PTSD. “This was the first time we could link a specific biological mechanism to the symptoms of PTSD,” Krystal says. At the time, he adds, this finding was highly controversial. “A lot of people felt that PTSD was a purely psychological syndrome that didn’t have an underlying biology.” Since then, Krystal has dived deep into understanding the neurobiology of PTSD to learn how to better treat it. His team is evaluating the use of ketamine and psychedelics. These would be among the first treatments to be developed specifically for PTSD. They may also be applicable for other disorders including anxiety disorders, Krystal adds. An important gap in PTSD treatment is the absence of biological tests that inform how to best help patients manage their PTSD symptoms. A doctor doesn’t diagnose cancer based on how they feel. Rather, they use tests of the biology of the cancer to determine the best course of treatment. “And we can’t do that in any psychiatric disorder other than Alzheimer’s disease,” Krystal says. “But now we are building a foundation for this approach to the treatment of anxiety disorders for the first time.” Source: Yale School of Medicine
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Navigating the American Dream: How Integrated Financial Tools, Credit and Rewards Can Help Small Businesses Succeed
(Feature Impact) Owning a small business has been a cornerstone of the “American Dream” for generations. It represents the chance to transform a passion into a livelihood and legacy. However, turning dreams into reality is rarely a smooth or easy process and requires more than ambition alone. Today’s business owners need support and access to tools that enable them to overcome challenges and keep growing.#placement_678081_0_i{width:100%;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid678081 = window.pid678081 || rnd;var plc678081 = window.plc678081 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=678081;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid678081+';place='+(plc678081++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');Recent research conducted by the Capital One Insights Center shows 75% of more than 1,000 surveyed small business owners with more than one employee and annual revenues of up to $20 million are confident about the future, and 69% believe their business is actively primed for growth.While this optimism is promising, 47% of business owners still said their operations either stayed the same or became less efficient over the past year, citing issues like back-office friction and fragmented financial systems that make it difficult to get a clear picture of the health of their businesses.If you’re a small business owner eager to grow but not sure how to get there, start with this advice from real small business owners and experts at Capital One.Identify Sources of FrictionBefore you can pour effort into growth, you must understand what barriers are holding you back. Take time to look under the hood of your business to identify where time and energy is being lost.For example, you may be among the 78% of small business owners who feel stressed and uncertain about expense management – think hours spent hunting for receipts, manually entering numbers into software and reconciling accounts. Operational challenges aren’t just a hassle; they also pull attention away from important priorities like serving your customers and planning for growth. “We were focused on making as many candles as possible, especially during the busy season,” said Katie Roering, co-owner of Fontana Candle Co. “A lot of the back-office tasks like procurement, raw material purchasing, forecasting – all the really important things – were done at 3 a.m., 8 p.m. or on Saturday and Sunday, and there really just was not enough time in the day to get everything done that we needed to. We just knew as we continued to grow, we needed to streamline our processes, build out our team and keep moving forward.”Use Integrated Tools to Manage FinancesInstead of balancing 10 different tracking and analysis tools, you can turn to one-stop solutions to improve efficiency. Time gets lost when you’re forced to manually gather and interpret relevant data before you’re able to act. You need a platform that handles the busywork for you.Integrated, or “all-in-one,” financial tools – like accounting and bookkeeping platforms with automation capabilities or business credit cards featuring built-in analytical tools – allow you to easily stay on top of cash flow and day-to-day operations. For small businesses where every hour and dollar makes a difference, consolidating and automating systems can have an immediate impact. In fact, 51% of survey respondents said integrated tools have already fueled their growth.Leverage Credit Access and Rewards WiselyGrowth requires capital, so access to credit is a game-changer for many business owners, with 77% describing it as a key factor in achieving business resilience. Having funds accessible when you need them makes your business more capable of weathering storms such as equipment failures and seasonal slowdowns. It also puts the power in your hands to act when an exciting opportunity presents itself, like an inventory flash sale or the chance to advertise in a new market.Access to credit comes with another advantage: rewards. By using credit cards for your daily business expenses, you can earn cash back, points or travel rewards. Whether you redeem these to cover everyday expenses, book business trips or reinvest in the business, they can act as a bonus source of income. Learn to maximize rewards like the 84% of small business cardholders surveyed so you aren’t leaving money on the table.To learn more about how small business owners can identify obstacles, employ integrated financial tools and use credit as a tool for growth, read the full report at capitalone.com/about/insights-center.Photos courtesy of Shutterstock
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Husted's data center bill collides with campaign season politics
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Blades expect to avoid points deduction
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Democrats for office, Republicans for policy?
My prediction for this election: Voters will vote against … themselves. Voters will elect Democrats to run virtually everything — and then approve ballot measures telling those Democrats to stop doing virtually everything. Democrats for office. Limited government for policy. Colorado has reinvented ticket splitting without the inconvenience of electing Republicans. We used to split […]