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Grants for pioneering Surrey farms which use lasers and GPS
A Surrey vineyard, cattle farm and beekeeping business are among firms awarded a share of £500,000.
Omata Classic Analog Cycling Computer is Back, Updated and Now Built by Silca!
The beautifully simple Omata analog GPS cycling computer is now owned & made by Silca in the USA in strictly limited edition numbers!
Inside Business Matters: A transplant’s perspective on CNY, plus news on a local AI startup (how to sign up)
Every Thursday, the Business Matters newsletter gathers Syracuse.com’s most insightful, noteworthy business journalism for readers.
Chinese scientists say they spotted possible Israeli electronic warfare units
PLA scientists publish algorithm used to estimate sources of GPS spoofing around Israel using flight data.
Google announces $179 Fitbit Edge tracker with display, GPS
Google is following the Fitbit Air launched in May with a second tracker that features a screen called the Fitbit Edge.
The science, instinct and hard work behind Roosters’ success
Enter your email address to get each Tribune edition sent to your inbox Subscribe There’s a fair bit of unseen work that goes into winning an NRL premiership, dating back many months - just ask Simon Jones. The Sydney Roosters Head of Performance, who hails from Southland, has been in the thick of it. He played a lead role in guiding the 2026 champions through a marathon campaign that ended with a grand final win over the Newcastle Knights. The Roosters had to navigate the lengthy round-robin competition, including the pre-season, before playing through all four weeks of the finals series. It was a demanding stretch that tested the players and the staff responsible for keeping them on the field. “It is a hell of a beast, mate, to be honest,” Jones told The Roar Podcast. “There’s such a great group of staff there that know what they’re doing, and the boys are pretty professional.” Jones believed the Roosters managed the physical demands well, pointing to the health of the squad throughout the campaign and the decision to rest a significant portion of the playing group in the final round of the regular season. That call, made by head coach Trent Robinson and his coaching staff, proved valuable as the Roosters entered the finals with some energy in reserve. “We did finish the season physically where we needed to be, and we’d sort of had a pretty healthy squad all year,” Jones said. “To the team that do that, mate, mission accomplished, really.” It is the sort of work that often goes unnoticed when the spotlight falls on the players scoring tries and making match-winning plays, but Jones knows the cumulative effect of those decisions can be significant over a long season. After a win over Penrith had helped establish them as premiership favourites, losses to the Wests Tigers and Dolphins were followed by a defeat to the Panthers in the opening week of the finals. Rather than panic, the club refocused to position itself to challenge for the title. “The Tigers’ performance was probably the only one where you’re really quite disappointed because it’s hard to get to the top of the competition,” Jones told The Roar Podcast. “We had proof that we could; we knew what we needed to do. We just had to get back to that.” For Jones, the answer was not necessarily a radical change to the programme. It was about executing the basics consistently, both on the field and in preparation. “We just do the basics better than anybody else,” he said. “Whether that is actually the way you play the game or how you’re preparing, it’s just be really consistent, do the basics really, really well.” Like many professional sports teams, the Roosters are entrenched in sports science and performance data. The club has access to a range of information, including players’ sleep, GPS metrics and neuromuscular scores, helping staff assess how individuals are coping with training and competition. “We are very science-backed, and some people would say data-driven, but it’s people first,” he said. “The reason you collect all this data is to try and be the best for that person.” Jones said the club was also prepared to reconsider testing methods if they were not generating useful discussions or helping staff make better decisions. In an environment where technology is continually evolving, he believes experience and gut instinct remain important. “The data is no good unless you have conversations,” he said. “When you strip it right back, mate, trust the gut still and obviously, you know, just doing the basics really, really well.” The return of halfback Sam Walker provided a further example of the importance of individual determination and the work of the club’s medical team. Walker underwent ankle surgery late in the regular season, with his premiership campaign appearing in doubt. However, he was determined to return for the preliminary final. Jones said Walker was back at the training ground three days after surgery, walking freely enough to surprise those around him. While the surgeon’s work was crucial, Jones credited the halfback’s mindset as a major factor in the remarkable turnaround. “He was quite clear with Robbo after he got the surgery that he was going to make it back for the prelim finals,” Jones said. The Roosters’ performance programme also sits within a wider club culture that Jones believes is central to their success. Each season, players develop their own team mantra through a lengthy process facilitated by Robinson. It provides principles that the squad can connect to its actions on the field. Rather than simply carrying over the previous year’s wording after a successful campaign, the club repeats the process because the players’ ownership of it is what gives it meaning. “When it’s led, player-owned and player-led, mate, it’s really powerful,” Jones said. Get more from Logan Savory in the Substack app Available for iOS and Android Get the app Jones joined the Roosters in 2024 and said the environment had evolved as experienced players departed and younger members of the squad took on greater responsibility. Maintaining continuity in the club’s culture and preparation had helped the group navigate those changes. The premiership was a significant achievement for Jones, who acknowledged how difficult it was to win the NRL’s ultimate prize. However, he is already looking at how the performance programme can improve. “There’s still things within my role and things that I’d like to help improve at the club,” he said. For Jones and his team, the challenge now is to review the season, refine their systems and prepare for another campaign. The celebrations may have followed a memorable title win, but the work behind the scenes never really stops. The Southland Tribune is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Sports Overtime: Week 7 (Friday, Oct. 9, 2026)
Watch highlights and view scores from Week 7 of the 2026 NSAA football season.
Self-service health check machine in Essex workplaces refers to GPs
London Stansted Airport says one employee's life has been saved by using the mobile sit-down unit.
Bengoa: Ten years on how much further forward is Northern Ireland's health care system?
Hospital waiting lists, access to GPs and the state of social care suggest the job is far from finished.
Oklahoma drunk driver at center of 'political favoritism' scandal back in prison
Admitted drunk driver Sara Polston, whose case has spurred protest and policy changes around Oklahoma’s GPS ankle monitoring program, is back in prison and facing charges of illegal voting.
Top Ranking for Bellevue University's Counseling Master's
CounselingPsychology.org ranked Bellevue University's Master of Science in Clinical Mental Health Counseling program No. 2 among counseling master's programs in Nebraska for 2027. The ranking recognizes Bellevue University's CACREP-accredited program and its online format designed to support students preparing for counseling careers and licensur...
Pokémon card collector used GPS device to track delivery woman
After 30 years, Pokémon remains among the most desirable collectible franchises in fandom and auctions regularly prove the cards' growing value. But one collector went too far in his efforts…
DARPA wants to give the military something much better than GPS
GPS can be jammed. DARPA is making clocks that could keep military systems running without it and eventually enable completely new capabilities.
Apple Watch Ultra 2 vs. Ultra 4 Buyer's Guide: Should You Upgrade?
The Apple Watch Ultra 4 arrives three years after the Ultra 2. Across those two generations, Apple added satellite connectivity, a larger display, new health sensors, and longer battery life. Are those changes enough to justify replacing an Ultra 2 or paying more for the newest model? Both watches retain a 49mm titanium case, an Action button, a siren, a 3,000-nit display, dual-frequency GPS, and support for recreational diving to 40 meters. The Apple Watch Ultra 4 starts at $799 in the U.S.
72-Year-Old Ohio Man Put A GPS Tracker On Pokémon Delivery Driver's Vehicle
Pokémon card value is at an all-time high
My 13-year-old refused to let me track him. I realized he was right.
I grew up with little parental supervision. When my teen objected to GPS tracking, I realized how much modern parenting had changed me.
What happened to the ‘Eight Is Enough’ cast? See the stars nearly 50 years later
Nearly 50 years after ‘Eight Is Enough’ premiered, see what became of Dick Van Patten, Betty Buckley, Grant Goodeve, Dianne Kay, Willie Aames, and the rest of the Bradford clan.
Vandalia Health to host nursing expo in Fairmont
Vandalia Health will host a free nursing expo Sept. 23 in Fairmont for nursing students and recent graduates. Attendees can explore jobs, externships, residency programs, education benefits and professional development opportunities.
Paul Walter Hauser has bizarre explanation for pin he wore to recent premiere
Paul Walter Hauser explains the meaning behind the pin he wore to the ‘Resident Evil’ premiere in Los Angeles earlier this week.
SCOTUS to decide whether to hear Maine lobsterman's challenge
Maine lobster fisherman Frank Thompson filed a lawsuit against the state's marine resources department over the GPS tracker requirement. He argues it constitutes unreasonable search and seizure.
Precision for All: Closing the Gap Between Science and Life
Biopharma innovation is moving fast, yet according to Ryan Keeling, CEO of Diaceutics, the industry continues to face a fundamental challenge: too many eligible patients never reach the therap | Why are so many eligible patients still missing the therapies designed for them?
Casio’s new G-Shock watch with step tracking now available in more markets
Following its Japan launch last year, Casio has now officially listed the G-Shock GBA-950-1A in the UK. Designed for runners, the watch features GPS-linked distance tracking, step counting, Strava compatibility, and 200 m (20 bar) water resistance. Plus, it also supports dual time zones.
UC Riverside scientists develop tool to predict future earthquake sites
Researchers used GPS data to measure where energy was building up in faults, correctly predicting where an 8.8 magnitude earthquake later occurred in Russia last year.
UC Riverside scientists develop tool to predict future earthquake sites
Researchers used GPS data to measure where energy was building up in faults, correctly predicting where an 8.8 magnitude earthquake later occurred in Russia last year.
UC Riverside scientists develop tool to predict future earthquake sites
Researchers used GPS data to measure where energy was building up in faults, correctly predicting where an 8.8 magnitude earthquake later occurred in Russia last year.
Apple Announces Apple Watch Series 12 With S11 Chip, Upgraded Health Sensors and Ceramic Models
Apple today announced the Apple Watch Ultra 4, featuring a new S11 chip, a redesigned health sensing system, and a larger battery that Apple says delivers two days of battery life. With improved power efficiency, Ultra 4 offers up to 18 hours of workout tracking with full GPS and heart rate monitoring, or 45 hours in its maximum extended workout mode. It comes in Black and Natural titanium, alongside new band colors and a new titanium Hermès band.
Scientists Say They Can Now Pinpoint Where Big Quakes Might Hit
A GPS-based algorithm is used to identify where stress has been building up.
Boston 25 News
Rosanne Cash postpones shows due to health. Discover her musical journey and Johnny Cash's influence.
A Solar Storm Knocked GPS Off by 33 Feet Across the US and Scientists Had Never Seen This Kind of Disruption
The event exposed a hidden weakness in systems that depend on precise positioning.
Sports Overtime: Week 2 (Friday, Sept. 4, 2026)
Watch highlights and view scores from Week 2 of the 2026 NSAA football season.
GPS Glitched Across The US by as Much as 33 Feet. Scientists Have Never Seen This Before.
This shouldn't have happened.
GPS Glitched Across The US by as Much as 33 Feet. Scientists Have Never Seen This Before.
This shouldn't have happened.
Colorado Sues EarnIn For “Immoral, Unethical, Oppressive and Unscrupulous” Business Practices
Hey all, Jason here. When this hits your inbox, I should be en route to the airport — not to go anywhere myself, just to pick up my better half. I must admit, it’s been strange to be home alone (well, with two dogs) for two weeks! Really lets me “optimize” to spending more time on reading/writing/working, whether that’s healthy or not! Looking forward to getting back into a (somewhat) more balance routine. Subscribe or Support by Upgrading Compare Notes With the People Who Built Modern Fintech Partner content: Remitly CEO Sebastian Gunningham. Increase founder Darragh Buckley. Linda Du, Co-founder & President at Valon. They’ll unpack the decisions behind building and scaling major financial products: what they got right, what broke, what they would do differently, and how AI and new infrastructure are changing the operator playbook. Most events tell you where fintech is going. NerdCon puts the people who built the present in the room and asks them what comes next. Expect an operator-led conversation grounded in real products, real trade-offs and lessons earned the hard way. Fintech Business Weekly readers save 20% on Regular tickets with code FBW20 before standard pricing ends September 11. Meet the Builders Things To Know & Other Good Reads Advent and Stripe Abandon $50 Billion Pursuit of PayPal (Bloomberg) Trump Family’s New Crypto Bank Is Backed by Abu Dhabi Sheikh (Wall Street Journal) The multiplying risks of financing data centres (FT) Let the Bond Market Speak (Wall Street Journal) Did we waste a crisis? Modest proposals to reform deposit insurance. (Fintech Takes Banking) Untangling Guggenheim: How Private Credit Built Its Own Universe (Net Interest) The Hater’s Guide To Circular Financing — Part One (Ed Zitron) Fiat Ventures Rebrands to FGV Capital, Announces $35M Oversubscribed Fund II (BusinessWire) Socure Announces Strategic Growth Investment at $5.2B Valuation and Acquires Agentic Operations Platform Fravity (Socure) Listen: When Consumer Protection Disclosures Work Too Well (Consumer Finance Monitor Podcast) Colorado Sues EarnIn For “Immoral, Unethical, Oppressive and Unscrupulous” Business Practices When Andreessen Horowitz led EarnIn’s $39 million Series B in 2017, Alex Rampell, a partner at the storied venture capital firm, described EarnIn’s small-dollar advance product as “free,” relying on “entirely on voluntary contributions instead of fees.” Rampell favorably compared EarnIn’s approach to typical payday loans, writing, “Payday loans historically have had the potential to be a slippery slope for consumers into financial distress: opaque systems and steep fees that are hard to repay and set individuals back further than where they started. For many Americans living paycheck to paycheck, that kind of slide into debt can be extremely difficult to recover from.” But EarnIn’s product — which, the company says, isn’t a “loan,” legally speaking — ends up being anything but free for most users. While it is technically possible to take a no-fee advance from the company, most users incur “Lightning Speed” (instant funding) fees and/or ostensibly optional tips that combined can equate to annualized percent rates that can reach over 1,000%. With an average term of 9.77 days, even fees and tips that are small on an absolute dollar basis are equivalent to high APRs on an annualized basis. A lawsuit filed last week by Colorado Attorney General Phil Weiser against EarnIn describes the company and its product and business practices quite differently than Andreessen’s Rampell; “EarnIn’s business practices are unfair because they are immoral, unethical, oppressive and unscrupulous,” the complaint, filed in District Court in Denver, Colorado, says. EarnIn’s marquee product, Cash Out, isn’t a loan, the company says, as Cash Out is not “[f]orward [l]ooking” because “[t]he money is transferred based on earnings to date,” does not carry a mandatory fee to access funds, and is “non-recourse,” meaning EarnIn cannot pursue recovery from users who don’t repay advanced funds. EarnIn is sometimes referred to as an “Earned Wage Advance” service. Though, unlike some others in the broader category, EarnIn does not integrate with employers’ payroll or time and attendance systems. Rather, EarnIn attempts to verify a user’s income and employment, by examining direct deposit transaction data in their linked external bank account, by using GPS location and Bluetooth data to estimate a user’s time spent at work, if they work in a fixed location, and/or by having a user provided a work email address. While repayment is theoretically optional, as EarnIn would have no recourse, such as reporting non-payment to the credit bureaus or a collections agency, this is anything but clear to users of the EarnIn app, Colorado’s complaint argues. During the process of taking a Cash Out, users must agree to a preauthorized debit of the amount advanced, plus any expedited funding fee and/or tips. Though users technically can revoke this ACH authorization, the fact that they have this right isn’t presented to users during the Cash Out process, but rather is included in linked terms and conditions few users are likely to actually read. And users who do wish to revoke their ACH authorization must do so three or more days before the scheduled transaction date by emailing EarnIn’s customer support. Similarly, EarnIn’s marketing claims that it carries “no interest” and “no mandatory fees” is technically true, but is not the reality for many of the app’s users, the Colorado complaint argues. Further, EarnIn has extensively marketed to users the ability to “access your pay today,” to get “instant” funds, and to get funds “the same day you work” — when, in reality, this speed of access was only possible by paying the additional, undisclosed Lightning Speed fee. The Colorado complaint highlights this contradiction specifically, noting: EarnIn tells consumers that they can ‘Make any day payday with EarnIn’ and that there no ‘hidden’ or ‘mandatory fees.’ For a consumer to access their pay on the same day requested, they would have to pay the Lightning Speed fee. In the fine print of the advertisement EarnIn discloses that ‘[f]ees apply to use Lightning Speed,’ a direct contradiction to the larger text of the advertisement, and a fact that would not be immediately understood by a consumer as ‘Lightning Speed’ is not defined nor explained. Like other small-dollar lending services, rather than explicitly charge interest, EarnIn collects a markup on the optional Lighting Speed fee, which, given the nature of the transactions, many users opt for, as well as offering users the option to leave “tips.” EarnIn leverages either Real-Time Payments (RTP) rails or push-to-card via debit rails if a user opts for the optional Lightning Speed. But while these capabilities cost EarnIn, on average, $0.075 or $0.20 per transaction, respectively, EarnIn charges users significantly more. Initially, EarnIn charged as little as $1.99 for Cash Outs up to $24. But EarnIn has hiked these fees multiple times, and now charges $4.99 for Cash Outs up to $75 and $6.99 for those over $75. According to the Colorado complaint, EarnIn leverages “dark patterns” to manipulate users and to make it more difficult to avoid tipping. Examples of these “road blocks” highlighted in the complaint include: As of 2023, in the EarnIn app, a consumer attempting to get a loan under the default settings had to make at least eighteen separate taps to complete the transaction and reduce the tip to $0. There is an alternative method to leave a $0 tip, via the “Custom tip” feature, but EarnIn made this option difficult to access by visually deemphasizing it and positioning it near devices’ “home” button. Using language and imagery such as “Tip to pay it forward,” “Your generosity supports the service + helps,” “Your tips make a difference,” and “[t]he APR for this cash out is 0%. Your tips help support us.” While Lightning Speed and tipping are, in theory, both optional, in practice, users nearly always ended up paying something. According to the Colorado suit, users were charged either a tip or an expedite fee for more than 92% of transactions, with an average APR of nearly 388%. And, although the advances are “non-recourse,” EarnIn successfully collects on nearly all transactions — 99.18%, according to the complaint, which, Colorado argues, “demonstrat[es] that EarnIn’s advances function as high cost loans, not voluntary payments.” The share of EarnIn users incurring fees — despite the product being marketed as 0% APR — is hard to reconcile with Andreessen investor Rampell’s favorable description of EarnIn vs. “opaque systems and steep fees” associated with payday loans, which, Rampell says, can be “extremely difficult” for borrowers to extricate themselves from. According to Colorado’s suit, EarnIn’s Cash Out product “trapped many consumers in extreme cycles of high-cost reborrowing.” The suit gives an example of one consumer in the state, who took out a whopping 1,151 loans, paying a total of $4,038.50 in Lightning Speed expedited funding fees on loans that averaged the equivalent of 1,421% APR. Another Colorado user, the suit says, took out 1,033 loans, paying $8,561.22 in tips and fees at an average APR of 1,539% . These types of usage patterns demonstrate “the severe and repeated financial harm caused by EarnIn’s illegal lending model,” the Colorado complaint argues. In aggregate, from January 2023 through July 2025, EarnIn extended 3.1 million loans to 56,778 users in Colorado — an average of nearly 55 transactions per person during the time period. EarnIn lent more than $300 million and collected more than $16 million from Colorado users in Lightning Speed fees and in tips. Ultimately, the Colorado complaint argues that “EarnIn’s Cash Outs are loans under Colorado law, and EarnIn’s contention that its product is not a loan based on its disclaimer of any legal repayment obligation lacks any real-world significance given how the Cash Out transactions actually operate in practice.” Colorado further argues that “EarnIn was not working with companies here in providing consumers with funds but acted as a third-party lender and charged illegally high rates, used deceptive design strategies to extract some charges, and trapped consumers in repeat borrowing. Colorado will continue to stand up for consumers and hold companies accountable when they violate our credit laws or attempt to evade them through misleading practices.” Colorado’s suit alleges EarnIn assesses finance charge in excess of that permitted by Colorado law, that EarnIn failed to make legally required disclosures to Colorado borrowers, that EarnIn made supervised loans to consumers without obtaining the requisite license, that EarnIn violated the state’s Deferred Deposit Loan Act, that EarnIn engage in unfair and deceptive trade practices, and that EarnIn made false or misleading statements concerning price. The suit seeks a court order enjoining EarnIn from violating relevant Colorado laws, for EarnIn to refund amounts charged in excess of state law, fees, costs, and penalties, and other relief the court deems to be just. Fintech Business Weekly is made possible by the generous support of paying subscribers — bringing you independent analysis of banking, fintech, and crypto without fear or favor. You can support my work by becoming a paying subscriber if you aren’t already. Paying subscribers enjoy: access to the entire archive of nearly six years of newsletters extended versions of the weekly newsletter, with additional content and analysis and (for founding member tier) quarterly personal 1:1 fintech Q&A / strategy calls with me, tapping into my unparalleled knowledge of the intersection of banking and fintech and experience working in the sector, including helping to launch Goldman Sachs’ retail bank Marcus Support Fintech Business Weekly You can also support Fintech Business Weekly by sponsoring a newsletter or podcast, putting you in front of 93,000+ of the most influential decision makers in banking, fintech, and crypto. Learn more about sponsor opportunities or request a media kit by dropping me an email. Q2 Quarterly Banking Profile: Five Quick Takeaways The FDIC released its quarterly banking profile, which is always worth a read, for the second quarter. The profile provides an aggregate snapshot about the overall health of the 4,238 institutions whose deposits are insured by the FDIC, who, collectively, hold more than $26 trillion in assets and saw a total net income of more than $90 billion in the second quarter. Net income was up 12% vs. Q1 2026, with lower provisions and realized gains on securities helping to drive the improvement, somewhat offset by increases in non-interest expense and applicable income taxes. Overall net interest margin was basically flat quarter over quarter (up 1 basis point vs. Q1 2026), though community banks saw NIM grow by 10 basis points, to 3.81%. Unsurprisingly, given that interest rates haven’t changed, unrealized losses on securities changed little, edging up slightly to $326.7 billion vs. $325.1 billion in Q1 2026. Aggregate credit quality has remained benign, with asset quality actually improving slightly in Q2. Overall, institutions reported a 9 basis point decline in their past-due and non-accrual rate, to 1.44%. Net charge off rate also declined by 2 basis points, to 0.57%. And finally, the FDIC’s deposit insurance fund stands at $161.1 billion, making the DIF reserve ratio 1.48% — above the statutory minimum of 1.35%, but still below the designated target reserve ratio of 2%. [Paid Subscriber Exclusive] Nissan Withdraws ILC App, State Associations Plan BankChain Alliance, FDIC Defines “Unsafe or Unsound Practice” For First Time Automaker Nissan withdrew its application to charter a Utah industrial loan company and its corresponding application to the FDIC for deposit insurance last week, on August 19th. Nissan’s application had been outstanding for more than a year, as it originally applied in June 2025. Recent applications to the OCC to form national banks have been decisioned, one way or the other, substantially more quickly than has historically been the case.
Sports Overtime: Week 1 (Friday, Aug. 28, 2026)
Watch highlights and view scores from Week 1 of the 2026 NSAA football season.
Google’s Pixel Watch 5 is promising — but it isn’t finished
Think of this as part one of the Pixel Watch 5 review as most of the new features aren’t out yet. That said, GPS rocks.
Hackers Stalked Me by Hijacking a Smartwatch for Kids
Security researchers tracked and eavesdropped on a WIRED reporter using vulnerabilities in a pink plastic smartwatch. It’s just one piece of a deeply insecure supply chain of GPS-enabled gadgets.
Paramount CEO David Ellison: The critics are wrong about my politics
Paramount CEO David Ellison: The critics are wrong about my politics. The issue is whether I can be trusted as a steward of CNN.
IndyCar race at Nashville Superspeedway postponed after heavy rain
The IndyCar Nashville Music City Grand Prix has been postponed until July 20 due to heavy rain.
The Future of Sports Prep Is Here: Nebraska Robot Prepares National Archery Stage
A robot made by a Nebraska company is helping prepare the stage for some of the country’s top young archers.The Lincoln Sports Foundation is using a GPS-guided
Move over, GPS: Navigation satellites in low Earth orbit are making a comeback
Xona aims to deploy 258 satellites into low Earth orbit as a GPS alternative.
Everyone Has Phoenix Suns' Khaman Maluach Situation All Wrong
Learning behind Mark Williams for at least one more season is what's best for the Phoenix Suns and Khaman Maluach.
Scientists thought ravens followed wolves for food. A 2.5-year GPS study told a different story.
For decades, biologists believed ravens found their next meal by shadowing wolves across the landscape until the predators made a kill. A new study in and around Yellowstone National Park suggests the birds are using a far more sophisticated strategy.
This satellite constellation transformed earth science by creatively tuning in to GPS signals
When NASA's Cyclone Global Navigation Satellite System, or CYGNSS, launched into orbit in 2016, none of the University of Michigan Engineering researchers who developed the system expected it to transform ...
Scientists Thought Ravens Followed Wolves for Food. They Were Wrong. Ravens Predict Them
New GPS tracking suggests ravens navigate Yellowstone using a mental map of wolf kills.
This satellite constellation transformed earth science by creatively tuning in to GPS signals
Governments and companies have launched similar constellations to use the method, called GNSS-R, to monitor and forecast wildfires, flooding and more.
This satellite constellation transformed earth science by creatively tuning in to GPS signals
Key takeaways —The first constellation to produce high-quality data by picking up GPS microwaves reflecting off Earth, called CYGNSS, is featured in the Smithsonian National Air and Space Museum's Living in the Space Age exhibit. —Distortions in the reflected signals can reveal information about Earth, including hurricane wind speed and the distribution of moisture in soil, and the constellation provided unprecedented coverage in both time and space. —GNSS-R data is useful for mon
Hall of Fame GM Expresses Concerns About Extending Vita Vea
As a lucrative "hold-in" intensifies, Bill Polian warns that committing massive capital to an aging nose tackle could backfire for a Tampa Bay roster already in transition.
Dennis Herrera, fixture of SF politics, to retire
The former six-term city attorney and current head of the Public Utilities Commission will leave office in December.
Houston Rockets jersey history No. 18 - Thabo Sefolosha (2019-20)
During his time suiting up for the Rockets, Sefolosha wore only jersey No. 18 and put up 2.2 points and 2.3 rebounds per game.
John Tortorella not returning as Golden Knights head coach after run to Stanley Cup Final
UFC White House post-fight press conference video
Justin Gaethje wins UFC lightweight title at UFC White House main event
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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