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Engrams Embedding Entendre: Codesign for Efficient DRAM/SSD Offloading
Engram extends standard token embeddings with learned multi-token lookups. Recurring local patterns retrieve vectors directly, reducing the need to reconstruct them through attention and feed-forward layers. With Engram model architecture optimization, it allows for lower HBM capacity to be needed for models at the same quality. This does not mean there won’t be an insane demand for HBM but it just means that model architecture will continue to innovate around constraints. This model architecture design is naturally codesigned for parameter offloading: each token accesses a few embedding rows whose addresses depend on token IDs, not hidden states. The runtime can prefetch those rows from host DRAM while earlier layers compute, keeping the table outside HBM without transferring entire weight matrices. Our Memory model contains our latest estimates of quarter by quarter HBM, DRAM, & NAND supply and demand. Offloading frees HBM for model weights and KV cache, potentially supporting larger batches or more concurrent sessions. When DRAM becomes the next constraint, NVMe offers another tier. Recommendation systems already cache frequently or recently accessed embedding rows in faster memory while backing colder rows with SSDs. After NVIDIA roadmap had to change due to massively despec’ing Rubin Ultra from 1024GB to now ~200GB of HBM per chip, model architecture optimizations like emgram maybe helpful. Our DeepSeek-V4.1-Flash configuration uses roughly 189 GiB of memory for Engram. We replace it with a memory-mapped (mmap) file and measure serving performance with offload to SSD. Later on in our report, we will show our Engram offloading experiments along with the official InferenceX agentic inference serving results on Engram models like DeepSeekv4.1 Flash across all 6 NVIDIA GPU SKUs along with MI355X. Unsurprisingly, the CUDA Moat is still mogging MI355X on the ultra popular DeepSeekV4.1 Flash model. We also show how even on high capacity HBM SKUs, offloading emgrams to DRAM could result in even better performance for most of the pareto than keeping the emgram in HBM. Our benchmark has been widely reproduced, validated and/or supported by almost every major buyer of compute from Google Cloud to Microsoft Azure to Oracle, to Meta and many more. Furthermore, it has the support of the ML community including from vLLM, LMCache, SGLang, PyTorch, Huggingface and the support of major labs like OpenAI, MiniMax, ZAI, Qwen, Moonshot Kimi, etc. Star the InferenceX GitHub repository if you find the open-source benchmark and data useful!. InferenceX is the only inference benchmark in the world to have TPUv7, Jalapeño, Nvidia Rubin NVL72, AMD, and soon, SambaNova and Trainium. Due to how realistic AgentX scenario is to real world agentic inference workloads, AMD has committed to collaborating on MI455X UALoE72 too. DeepSeek did not release the original paper’s two trained Engram models. We replicated its setup on fineweb-edu using the released code and training hyperparameters, at an estimated 6E18 FLOPs per run. We observed the same U-shape scaling: Engram improved performance over pure MoE baselines. We also reproduced DeepSeek’s results, where earlier-layer representations with Engram resembled those of later layers. Like the original Engram paper, it is possible to probe Engram’s gate scores to see what n-grams DeepSeek-V4.1-Flash makes the most use of. Our gate scan finds names, code fragments, relational phrasing, and boilerplate. These examples prioritize interesting-ness over gate strength. One unexpected result was Wright : Ace Attorney. These examples suggest learned memory optimizes the training objective, not a judgment of which facts deserve storage. Licenses, bibliography fragments, API scaffolding, and website furniture can provide prediction shortcuts, so the value of additional Engram capacity may depend on what survives data preparation. This does not show that table capacity is “wasted”: the evaluation-corpus scan establishes neither training exposure nor the capacity occupied by each category. For offloading, strong gates do not identify cache-hot rows. Low gates do not automatically save reads either: computing the gate requires the retrieved key and undoes the performance gain of a fused kernel. Skipping reads would require a separate usefulness predictor before retrieval. In the original paper’s inference-time ablation, factual-knowledge benchmarks retained just 29–44% of their original performance, while reading comprehension retained 81–93%. This is due to the training–inference mismatch. The resulting degradation therefore measures this trained model’s dependence on Engram, not the performance difference between models trained with and without it. In our ablations, suppressing Engram worsens token likelihood across all evaluated domains, especially encyclopedia text and several code corpora. Surprisingly, GSM8K accuracy stays within measured run-to-run variation and removing Engram has no effect. Engram is not a detachable dictionary beside an unchanged MoE. Removing it changes downstream features and expert selection. We tested whether rerouting hurts or compensates by holding tokens fixed in a teacher-forced experiment on CRUXEval, a code-reasoning benchmark of small Python functions where the model predicts a function’s output from its code and an input, and scoring the reference answer. Removing Engram raised answer loss from 0.2848 to 0.3093 bits/token. Forcing the ablated model to use the original Engram-on expert choices made it worse still, at 0.3375 bits/token. Rerouting partially compensates for the missing memory. Memory features and expert selection work together, rather than following a clean “memory stores facts; experts reason” division. On the same CRUXeval, removing Engram during either phase reduced accuracy and increased generated tokens; removing it throughout produced the largest changes. Keeping Engram for prefill leads to more correct answers than keeping for decode likely due to semantically richer KV cache transferred to decode workers, allowing it to mitigate some of the performance loss. Engram’s table is large, but each lookup is small. DeepSeek-V4.1-Flash requests 24 rows at each of two Engram layers, about 12.4 KiB per processed token position across the model, or 3.1 KiB per GPU when split across four GPUs. Currently as of Day 7 since Model Release, MI355X is still 2-4x worse performance per dollar compared to B200 even when normalized by Mi355X’s lower TCO. Our full total cost of ownership breakdown comes from our AI Cloud TCO Model along with monthly market surveys of over 100+ gpu clouds & gpu cloud customers. On the Day 0 release of DeepSeekv4.1 Flash, NVIDIA vLLM works out of the box with zero issues across all 6 SKUs: H100, H200, B200, B300, GB200, GB300! This was thanks to the amazing work by the NVIDIA & Interact teams! In comparison, AMD vLLM did not work on day 0 for DeepSeekv4.1 Flash.Source: SemiAnalysis InferenceX AMD’s vLLM documentation points to using vllm/vllm-openai-rocm:deepseekv41-flash-0909, but from hour 0 of the model release to hour 23, AMD has not publicly released the image. AMD claims, “SPEED IS THE MOAT,” yet it has still not released it by the 23rd hour. We wish that, going forward, the AMD team has a better process for hour 0 model releases. Eventually when they did publicly release for “day 0” image support, performance-wise, it is currently up to 14.8x worse perf per dollar than H200 and up to 42x worse perf per dollar than B200/B300. The power of the CUDA MOAT is NVIDIA’s collaboration with its massive 6 million-developer community ecosystem including most of the vLLM & SGLang & Tokenspeed maintainers which means that CUDA is optimized on day 0. Overall, AMD did make significant improvements but the performance per dollar is still currently 2-4x worse than B200. AgentX Engram DRAM Offloading Improving Performance The HBM and DRAM offload use the same GPU kernel to select and dequantize rows. With HBM, it reads GPU memory; with Unified Virtual Addressing (UVA), it reads pinned host memory directly. Both support full decode graphs. Moving the table into HBM accelerates only the sparse lookup, leaving decoder computation and communication unchanged, resulting in little overall benefit while consuming memory otherwise available to KV cache. Another benefit of Engram offloaded to DRAM which means you can reduce the communication overhead by using less HBM GPUs per replica. For example, when enabling Engram offloading on B300, we are able to switch from TP4 to now TP2 which improves the pareto curve by up to 1.6x. When iso-model quality, less HBM is required as the engrams could be offloaded to host DRAM. Thus HBM bandwidth matters way more than HBM capacity. For inference workloads where memory bandwidth matters the most, 4-hi HBM provides the best $/bandwidth and therefore lowest cost per token. If China continues to make more and more revolutionary model architecture innovations, soon it could potentially 0Hi HBM stacks. [ ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) [ Long Live the Short King: Why 4-hi HBM Wins ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) Myron Xie, Bryan Shan, and 3 others · Sep 13 [ Read full story ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) Moreover, on B300 and week-0 stack, moving the Engram table back to HBM did not improve results and stay within run-to-run variance. This is a result of the work optimizing DRAM offload, such as async, and overlap. SSD Offloading On B200, we created a unoptimized vLLM fork and stored the Engram tables in memory-mapped files on local SSDs. File backing lets the OS reclaim table pages when other applications need RAM. Pages already cached in memory can be served without reading the SSD again. Furthermore, note that we were unable to turn on GDS The unoptimized SSD implementation changes how rows reach the GPU. It copies row IDs to the CPU, deduplicates them, gathers the requested rows into pinned buffers, copies those rows back to the GPU and dequantizes them. This work runs between segments of the GPU execution graph. Native UVA performs row selection and dequantization directly on the GPU, avoiding the CPU round trip. A warm filesystem cache removes physical SSD reads, but leaves the coordination, row gathering and transfers. This is why a file already cached in RAM can still perform worse than a pinned DRAM table. The comparison measures the whole serving path; it does not separate the time spent on each of these operations. B200 DRAM dominates both measured SSD serving curves in total tokens per dollar and P90 interactivity. Near 125 tokens/s/user, DRAM delivers 121 million total tokens per dollar versus 52 million for SSD. For production serving, SSD offloading is likely not worth the tradeoff. On the B200 configurations we measured, SSD offloading loses on both measures: every observed SSD point has a DRAM alternative that delivers higher P90 interactivity and more total tokens per dollar. The only points where Cheaper storage does not automatically produce a cheaper inference service. Moving Engram to SSD leaves the same four expensive GPUs and the rest of the server in place. Reclaiming RAM only creates an economic benefit if it enables a cheaper server configuration or additional useful capacity. The current unoptimized path provides neither benefit, and the filesystem cache still consumes RAM when table pages are resident. Next we will look at the mechanisms and specific implementation of ngrams from DeepSeekv4.1 Flash, LongCat, Qwen3.8 Flash Next.
Companies pledge free software and computing for AI in science
The European Commission has announced that a group of companies and foundations will offer free services, such as software or access to supercomputers, to European scientists using AI in their research.Unveiled on October 15 at a conference in Dublin, the initiative is the latest step by the Commission to try to help researchers use the technology. Scientists have used forms of AI, such as machine learning, for decades. But advances in deep learning in the past decade, and the wider interest in large language models since the release of ChatGPT in 2022, have spurred governments to invest in new AI tools that could help the scientific process.In July, the US announced it is spending $5 billion on the Genesis Mission, which it describes as a “national effort to harness AI for science,” funding 278 projects across areas such as autonomous labs or new AI tools in astronomy. The Commission has also identified AI in science as a priority, but the €107 million it pledged from Horizon Europe in 2025 does not come close to US spending levels. That said, the vast majority of public research spending in the EU comes from national funds. Today’s announcement at the European AI in Science Summit doesn’t commit any new public money. Instead, it launches the AI in Science Enablers Initiative, a set of voluntary contributions from companies and foundations. The idea is that the companies also benefit by getting access to scientific ecosystems, and feedback on how their tools work. Google, for example, has put up €3 million of cloud computing credits to European researchers. The Novo Nordisk Foundation intends to make its supercomputer, Gefion, available to European researchers, according to the Commission statement. The chipmaker Nvidia said it would provide access to tools, compute, training and collaborative projects.The publisher Elsevier also offered complementary licenses to some of its AI tools, plus AI training for PhD, postdoctoral and master’s students. The French AI firm Mistral will provide the European research community with access to its open-weight models, Vibe seats and application programming interface credits, according to the Commission’s statement. Vibe is one of the firm’s chatbot models. The idea is that more firms and foundations will come on board in the future as the initiative grows.
Building the future: UMass celebrates $125M Computer Science Laboratories
AMHERST — Inside a room at the Physical Computing Makerspace on the University of Massachusetts campus, a 3D printer is fabricating a chalk case that a teaching assistant will use to carry writing utensils. The case’s design started as a computer file, drawn up nearby by Bennett Gillig, a UMass graduate student pursuing a master’s […]
LRZ Hosts TPC Europe Hackathon on AI for Science and Supercomputing
Agentic AI is currently a hot topic in the scientific community: during the Trillion Parameter Consortium’s autumn hackathon at the LRZ, teams presented practical solutions designed to make supercomputers more accessible and research projects more efficient. Sept. 24, 2026 — In the seminar rooms of the Leibniz Supercomputing Centre (LRZ), small groups stand in front […]
Quantum teleportation breakthrough: Scientists crack a 25-year entanglement challenge
Scientists have developed and experimentally demonstrated a long-sought method for identifying W states, an important form of multi-photon quantum entanglement. The technique could make complex entangled systems much easier to measure, opening new possibilities for quantum teleportation, communication, and computing.
Trump admin to receive $100 million in compute credits for AI science initiative
The credits are intended to give Genesis Mission researchers access to computing power that smaller labs and companies struggle to secure as major AI firms lock up capacity.
NVIDIA Joins European Commission Initiative to Expand AI Resources for Science
Oct. 15, 2026 — Much of today’s scientific progress begins with computation. But turning accelerated computing’s potential into scientific progress — modeling climate systems, designing molecules, simulating materials and more — depends on more than breakthrough technology. Especially for smaller labs, early-career scientists or science-based startups, the hardest part of research can be everything that […]
Nvidia commits $1 billion to U.S. science and quantum computing
The chipmaker announced the commitments Thursday at a Washington event tied to the Trump administration's Genesis Mission program
Trump Mocks Data-Center Opponents as Wanting to Stay ‘Backwards and Poor’
The giant computing sites that power A.I. are increasingly opposed by communities across the country, a signal of voters’ concern about a changing economy.
NVIDIA Commits $1B to Advance US Science Over the Next 5 Years
Commitments Will Strengthen Fields Critical for US Leadership Including Quantum Computing, Healthcare and Energy Security SANTA CLARA, Calif., Oct. 8, 2026 — NVIDIA today announced commitments valued at $1 billion to build out the United States’ capacity for artificial intelligence research and development in fields critical for U.S. leadership, including quantum computing, healthcare and energy […]
Business hopes South Chicago sees growth with new quantum computing campus
Google's $5 AI plan is now even more tempting
Google AI plans now include premium Colab benefits, offering faster computing, GPU access, and more for subscribers.
EU science policy wonks debate prospect of stronger ties with Canada
Europe’s research and innovation sector has started asking questions on how European Commission President Ursula von der Leyen’s offer to make Canada “the first associate member of the EU” would actually work in practice, and who will get to shape priorities in a transatlantic relationship that is getting stronger. The Commission says it wants “a new model of association” under which the EU and Canada will aim to develop “a shared space” to face ongoing challenges. “Working in close coordination with our member states and the European Parliament, we will aim to create a new form of partnership that has not existed until now, building the closest imaginable form of association with a partner outside Europe,” a spokesperson told Science|Business.Locked in an escalating trade war with US President Donald Trump, who has repeatedly talked of annexing Canada, Prime Minister Mark Carney has been looking east, but full EU membership was never in play. Taking the floor a day after von der Leyen’s proposal, he agreed to strengthen ties under “an alliance of the future” but reined in enthusiasm on the new label. He also suggested expanding Canada’s involvement in the Erasmus+ student mobility scheme, to which it currently has limited access, and the next iteration of Horizon Europe. Canada joined the present Horizon Europe in 2024, but only contributes to collaborative projects.Neither side has detailed the next practical steps in developing this new relationship. “I think nobody at the moment truly knows how this will work,” said Michael Browne, chief executive and founder of Crowdhelix, a global collaborative network that connects players in research and innovation. “It’s more of a statement of intent for closer collaboration, which requires legislative frameworks and approval processes, which have not started.”Kurt Deketelaere, secretary general of the League of European Research Universities, said von der Leyen’s pitch to Canada is “politically significant, but the legal content still has to be negotiated and constructed.”Mattias Björnmalm, secretary general of the Cesaer university group, agreed that she had only opened “a political door” to Canada, as “associate membership does not come with a predefined set of rights in the EU institutions.”Not only does this status not currently exist as a legal category in the two treaties that set up how the EU functions, but the Commission president cannot unilaterally create a new category of EU membership.According to Deketelaere, Article 217 of the Treaty on the Functioning of the EU, which allows the bloc to make association deals with non-EU countries involving reciprocal rights and duties, is “the most obvious existing legal basis for building a much deeper EU-Canada relationship.”Getting universities involvedNo matter how this new cooperation takes shape, Liviu Matei, who heads the School of Education, Communication and Society at King’s College London, hopes to see universities involved in discussions from an early stage.“Its primary motivations, entirely justifiably, are political and geopolitical,” he said. “In the area of higher education, however, restricting the initiative to political and geopolitical considerations would limit the scope of cooperation and lead to distorted frameworks and counterproductive implementation.”It is all the more important since academic interests on the two sides of the Atlantic are “neither identical nor fully aligned,” Matei added. “This is not insurmountable; it simply requires work to articulate the details of this privileged cooperation, including its governance and funding frameworks, as well as its substantive content in education and research.”Related articlesCanada looks to deepen research and education links with the EUZaharieva hopes for a Horizon Europe deal in 2026Canada might participate in European Research Council schemes, for example, which was not on offer in the present Horizon Europe association agreement. But “there would have to be something in it for the EU,” Browne said. “They don’t want to be funding projects outside of the EU where intellectual property is going to sit outside of the EU. There has to be some kind of transfer of knowledge.”But access to funding will not by itself resolve all the practical difficulties of working together, said Björnmalm. “For researchers and students, these include visas and residence arrangements, recognition of qualifications and study periods, and the conditions for pursuing a research career across borders,” he said. “For universities, there is scope for more predictable access to shared laboratories, computing and research data, and stronger support for joint doctoral training and long-term institutional partnerships.”Linda Doyle, provost and president of Trinity College Dublin, said Europe should strive for the “closest possible expression” of this new political alliance. “If Europe is serious about recovering its voice and its place in the world, it needs to be strongly allied with countries who share its values and its vision for a stable, rules-based, peaceful world.”
Is International Business Machines (IBM) A Bargain Or Fully Priced?
International Business Machines has delivered a strong multi year share price run. With the stock recently at US$232.14 and cash flows in focus, the live question is whether that price still lines up with what the business can earn and return over time. Over the past 5 years the share price has gained 130.1%, which puts a lot of weight on the idea that IBM’s future cash flows can justify a much higher valuation than in the past. Fresh commitments in areas such as quantum computing and...
Assistant Professor of Climate Data Science | The Journal of Blacks in Higher Education
Boston University invites applications for a faculty position at the rank of Assistant Professor in the Department of Earth Environment. This tenure-track position in Climate Data Science , beginning on July 1, 2027, is part of the ongoing cluster hire in Environmental Data Science and complements faculty searches within the Faculty of Computing and Data Science.rnrnWe particularly welcome candidates whose research focuses on the physical basis of climate, climate variability, and climate change, and who employ data science methodologies to deepen our understanding of how the climate system is changing and how these changes affect the global environment. Areas of interest include—but are not limited to—the changing frequency and intensity of extreme weather events; interactions between the atmosphere and terrestrial, oceanic, biospheric, and cryospheric systems; and improved understanding of Earth system predictability at seasonal, decadal, and longer time scales. We envision this position playing a central role in connecting and enhancing existing departmental strengths in climate-related research and teaching, including terrestrial and marine biogeosciences, land surface and coastal processes, paleoclimatology, energy and economic policy, and environmental sustainability. This faculty member will also contribute to university-wide interdisciplinary initiatives — including the Urban Biogeoscience and Environmental Health (URBAN) program, the Institute for Global Sustainability, and the Center for Climate and Health at the School of Public Health — and is expected to develop collaborative ties with the Faculty of Computing and Data Sciences, where shared interests in machine learning, large-scale data analytics, and Earth system modeling provide natural ground for joint advising, co-teaching, and grant development. This hire reflects our commitment to advancing interdisciplinary scholarship at the intersection of climate and data science. This position contributes to the University convergence themes of Global Sustainability as well as Artificial Intelligence, Data Science, Computing that are core pillars of BU's cross-disciplinary research priorities.rnrn Position Qualifications:rn Candidates should have a PhD or equivalent degree, demonstrated ability to obtain external funding to support their program of research and scholarship, and a commitment to excellence and innovation in teaching, education, and mentorship of students. The successful applicant will be expected to supervise graduate research in Ph.D. programs, teach at all levels in the Earth Environment curriculum, and maintain an externally funded research program. We seek applicants whose research complement strengths in the Department and around the University. For more information about the Department, see
RUNC: Advaith Cheruvu
The senior strives to make next-generation computing technologies more powerful and practical.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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New quantum chip taps into weird quasiparticles to get qubits to communicate over long distances
Scientists have developed a new type of architecture for quantum computing chips, and it could pave the way for machines capable of large-scale processing.
What can AI do for science? Four Argonne interns investigate
This summer, four Argonne interns used AI to advance research on vaccine development, weather forecasting and high performance computing. Their work shows how AI can speed discovery and help tackle major scientific and public health challenges.
Georgia Institute of Technology professor Munmun De Choudhury discusses AI, mental health and humanity
On Wednesday evening, students, faculty and community members gathered in Mills Hall to hear Munmun De Choudhury, a computer scientist, social scientist and professor of interactive computing at the Georgia Institute of Technology, speak as part of the Hastings Initiative lecture series. De Choudhury’s research focuses on digital mental health and the effects of emerging […]
Quantum in Business Conference Highlights Commercial Quantum Applications
EPB Quantum’s Chattanooga conference highlighted business use cases for quantum computing, networking, cybersecurity and energy optimization.
Argonne: Building Scientific Computing Ecosystems for AI-Enabled Discovery
Trustworthy AI-enabled scientific discovery depends on software, people, institutions and community action. Oct. 1, 2026 — Artificial intelligence (AI) is changing scientific computing rapidly. AI systems can now generate and analyze code, synthesize information, assist with hypothesis generation and carry out complex reasoning tasks within scientific workflows. Alongside advances in computing architectures and data-intensive research, […]
Can researchers trust that AI models won’t leak their ideas?
Research funders are asking how they can stop confidential scientific ideas in grant proposals from leaking out through large language models (LLMs), for example if reviewers use AI to help them judge applications. Last week, a row erupted in mathematics after OpenAI announced it had solved a notoriously difficult problem, only for another mathematician to demand answers over whether the company had used ideas he had fed into its models. The spat, and the broader issue of idea leakage through AI models, was discussed by funders at an R&D policy conference held in Paris on September 14. At worst, it threatens to undermine the correct attribution of breakthroughs, one of the foundations of modern science. The mathematics dispute around OpenAI is “certainly something we're looking at” Jason Gallo, head of the newly established Office of Metascience at the US National Science Foundation (NSF), told the Blue Sky Forum, hosted by the Organisation for Economic Co-operation and Development. The controversy started on September 8, when OpenAI announced it had cracked a mathematical problem that had gone unsolved for 90 years. Using a swarm of AI agents, millions of dollars’ worth of computing power and a new internal model, the company said it had finally proved that a long-used formula for modelling fluid dynamics breaks down under certain conditions. However, Tristan Buckmaster, a New York University mathematician who had been independently working with collaborators on the same problem using OpenAI’s Codex tool, hit back with a statement questioning whether the company had snooped on his Codex sessions to gain an advantage. OpenAI has always denied it looked up the “specific user data” of Buckmaster and colleagues. However, the company initially admitted that “while unlikely, we cannot rule out that de-identified data derived from their usage of our products helped improve our models,” although its proofs “differ significantly” from Buckmaster’s. The firm later said that, following an investigation, it concluded that Buckmaster’s Codex prompts “could not have influenced the [OpenAI] system in any way, including through training.”Funder concernYet OpenAI’s initial admission that its model might have ingested Buckmaster’s ideas, then spat them out to its own mathematicians, has scientistsworriedthat their work could leak out if shared with AI. Some AI tools give users an opt-out option to stop their sessions from training the model. If such guarantees can be trusted, this gives scientists some confidence they can use an LLM to develop an idea without the risk of it leaking out.But there’s a bigger potential vulnerability. To win money to investigate ideas, scientists have to share them with funding bodies. These grant proposals are normally kept strictly confidential, to prevent other scientists from scooping them, or to protect commercially valuable intellectual property. To preserve this confidentiality, when the NSF uses AI models, “we have to be sure that it's not making server calls out to an external party, leaking that data,” said Gallo to delegates in Paris. Leaks through reviewersHowever, funders normally use external academic reviewers to assess proposals. And there are growing worries that these reviewers are feeding grant ideas into AI models to help them make a judgement. Research funders have noticed that peer review reports and funding recommendations have “suddenly become much longer, more detailed and complex,” said Diogo Machado, head of the data science unit at Technopolis, a science and technology-focused consultancy. “The sense is that reviewers are increasingly using generative AI in their review work, even where guidelines sometimes forbid it,” he told Science|Business. “This is very difficult for funders to control or prove.” Happening at scaleThis sharing of confidential proposals with AI models is “happening at scale already,” said James Wilson, executive director of the Research on Research Institute, based at University College London, during the debate in Paris. In response, Gallo said the NSF had “strict guidance” around the uploading of proposals to AI models. But he added the NSF was mulling new types of assessment to make sure applicants were truly the originators of their ideas, such as following a short-form proposal with an oral presentation, which would allow the foundation to “really interrogate the investigator on their intellectual contribution.” Related articlesHow can Europe cope with a flood of AI-assisted research grant proposals?The risks and benefits of AI in screening research grant proposals Viewpoint: AI could make scientific overload worse“For us as funders, a lot of the ways to ensure that the application remains the applicant's own intellectual contribution, those ways are quite regressive,” Peter Clifford, head of strategy at Research Ireland, told delegates. “They're maybe ten or 15 or 20 years old, and they don't scale particularly well.” Disputes over the origin of ideas are as old as modern science. Isaac Newton and Gottfried Wilhelm Leibniz spent more than a decade arguing over who invented calculus, for example. And long before LLMs emerged, academics would agonise over how much of their early work to reveal at conferences, in case their colleagues scooped them, Jack Leahy, a senior metascience advisor to the UK government, told delegates. But AI was “accelerating” the “problems of the system,” he said.
LRZ Hosts TPC Europe Hackathon on AI for Science and Supercomputing
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Tiny sound waves could help solve a major quantum computing problem
Researchers at Harvard have demonstrated a way to protect quantum information using microscopic sound waves. By continuously surrounding a diamond-based qubit with mechanical vibrations, they extended its coherence time by roughly threefold. The same phonons could eventually both transmit and protect quantum information, opening the door to compact sound-based quantum networks on chips.
ALCF Service-Enabled Science Series Explores Experiment-Time Computing and the DIII-D Digital Twin
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Arm CEO says AI could cure cancer but data centers are a bottleneck
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RUNC: Advaith Cheruvu - College of Arts and Sciences
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National Compute Grid Launches to Pool Idle AI Capacity Across Providers
For all the talk about a shortage of AI computing power, and the need for more powerful chips and bigger data centers, there’s another side to the story. A significant amount of existing capacity isn’t being used. While tech companies race to build massive new data centers, expensive GPUs in other facilities can sit idle […]
As tech reshapes workplaces, University of Tennessee rethinks education
The Institute for the Future of Business was born out of the growth of artificial intelligence, nuclear energy and quantum computing.
NSF and UKRI Commit $10 Million in Joint Funding for Molecular Quantum Information Science
The U.S. National Science Foundation (NSF) and UK Research and Innovation (UKRI) have launched a joint $10 million (£7.4 million) research initiative supporting eight transatlantic research teams. Funded via $5 million from the
MIT welcomes David Siegel SM ’86, PhD ’91 as its next Innovation Fellow
Computer scientist, entrepreneur, and philanthropist David Siegel has joined MIT as an Innovation Fellow, where he will collaborate with the MIT Schwarzman College of Computing to advance AI and scientific discovery.
Genesis Mission: SYNAPS-I Brings Agentic AI to Experimental Workflows
With support from ALCF computing resources and AI services, the SYNAPS-I team demonstrated a new agentic AI platform that uses natural-language instructions to automate complex experimental workflows as part of the DOE Genesis Mission. Oct. 8, 2026 — Science has increasingly used artificial intelligence (AI) as a kind of microscope — sorting data, analyzing images […]
QuEra Scientists Named Co-Principal Investigators on Three of Nine Teams in Department of Energy's Quantum Chemistry Program, Now Underway
/PRNewswire/ -- QuEra Computing, the leader in quantum computing, today announced that its scientists will work with three of the nine teams selected for the...
European Open Science Cloud opens first 13 research hubs
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This new qubit could be 100 times less error-prone in superfluid quantum computer breakthrough
A proposed qubit made with superfluid helium could cut quantum computing error rates by around 100 times by shielding quantum information from common forms of electromagnetic noise. If experiments confirm the predictions, the technology could eventually work alongside today’s superconducting qubits or serve as a new kind of quantum memory.
Caltech’s tiny new chip can steer light in 74 quadrillionths of a second
A new Caltech device can redirect a beam of light in just 74 femtoseconds using another beam and a nanoscale silicon metasurface. The breakthrough could pave the way for dramatically faster photonic communications, computing, and sensing technologies.
NVIDIA Denies RTX 5090 Discontinuation Rumors, Admits Supply Is Tight
NVIDIA has finally responded to reports that the GeForce RTX 5090 is being discontinued. Jeff Fisher, senior vice president of NVIDIA's personal computing business, told Taiwanese media after the RTX Spark launch party in Taipei on October 16 that the rumors aren't true, as reported by 4Gamers...
War Department’s $350 Million Quantum Push
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DOE releases national quantum computing roadmap following field-wide effort led by SCAC subcommittee
Quantum computing is becoming a revolutionary tool for scientific discovery.
Akamai Stock Surges On Anthropic AI Computing Agreement
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Trump’s $6 Billion Science Plan Targets AI, Moon and Mars
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S&T experts contribute to state energy plan
Dr. David Borrok, center, vice provost and dean of S&T’s College of Engineering and Computing, and Dr. Joseph Newkirk, right, professor and chair of nuclear engineering and radiation science, participate in the Missouri Advanced Nuclear Energy Task Force, appointed by Gov. Mike Kehoe in May. Governor Mike Kehoe and the Missouri Department of Natural Resources...Continue Reading S&T experts contribute to state energy plan
Novel material’s magnetism could improve electronics’ speed, efficiency
A material thinner than a human hair may foster faster computing devices that demand less energy and store more data, according to a multi-institutional team led by researchers in the Penn State College of Earth and Mineral Sciences.
Weaving data and computing into a nationwide fabric supporting science
Building on decades of experience advancing research computing, the FabAID project is bringing high-throughput, data-intensive computing — and as many scientists as possible — into the age of AI.
D-Wave Quantum Secures Up To $100 Million In CHIPS And Science Act Funding
D-Wave Quantum has finalized a definitive agreement with the U.S. Department of Commerce providing access to up to $100 million in CHIPS and Science Act funding to accelerate development of its annealing and gate-model quantum computing technologies.
Is International Business Machines (IBM) Stock Worth More Than Its Cash Flow Suggests?
International Business Machines has almost doubled shareholders' money over the past 5 years, yet after a sharp setback this year and fresh headlines around quantum computing and AI, the key issue for you is whether the current share price lines up with the cash the business is expected to generate. With IBM stock now around US$227 a share, the gap between the recent price path and its cash flow story matters more than ever. IBM has delivered a 99.1% total return over 5 years, which puts...
Nvidia Commits $1B To US Science As CEO Jensen Huang Backs Trump’s Genesis Mission
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AI behaves more like a brain than a database – cognitive science’s role in its origin story helps explain why
When people think about what ChatGPT or other large language models are doing behind the scenes, it’s common to reach for the language of computing. You might assume there is
UCLA receives $75 million in NSF grants for quantum technology
Two UCLA quantum computing institutes received grants from the National Science Foundation worth a combined $75 million Aug. 25. The institutes – Fault-Tolerant Quantum Systems, Architectures and Applications and Challenge Institute for Quantum Computation – aim to advance quantum technologies, which function faster than classical computers or standard digital devices.
Georgia Tech secures $5m Google.org commitment for AI science | ETIH EdTech News
Georgia Tech has received $2.25 million toward a $5 million Google.org commitment to expand AI research access across US institutions. ETIH’s edtech news coverage details plans for 15 research projects, shared computing tools and training for more than 300 researchers and faculty.
A Stealth Startup Thinks It Just Hacked the Memory Shortage
Kepler Computing claims a new approach to chip design—and a proprietary material—can help end the supply bottlenecks that have sent memory prices surging.
Democrats try to ride data center backlash to election victory in rural US Midwest
Mounting public anxiety about AI, cloud-computing infrastructure has transformed data center construction into a contentious midterm elections issue
LZ Sees Surprising Result in Search for Dark Matter
Key Takeaways Dark matter is the mysterious substance that accounts for the vast majority of matter in our universe. LUX-ZEPLIN (LZ) is a world-leading dark matter detector and specializes in searching for WIMPs, or weakly interacting massive particles. A new LZ study found one particle interaction that is difficult to explain with known background processes and could potentially have been caused by a WIMP. LZ continues to run to see if additional data strengthens or weakens the hint of a dark matter interaction. For the better part of a century, people have been trying to understand dark matter. This invisible substance makes up roughly 85% of the mass in the universe but has never been directly detected. Determining exactly what it is remains one of the biggest questions about our world. Now, a new analysis from the LUX-ZEPLIN (LZ) experiment has recorded a single particle interaction that researchers have great difficulty explaining with known background signals from normal matter. The result does not yet meet the statistical threshold required to claim a discovery, but is the most compelling hint of dark matter reported by the experiment to date. LZ is an international collaboration of 250 scientists and engineers from 39 institutions. The detector is managed by the U.S. Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) and operates nearly one mile below ground at the Sanford Underground Research Facility (SURF) in South Dakota. The experiment uses 10 tonnes of ultrapure liquid xenon to search for dark matter and is optimized to look for WIMPs, or weakly interacting massive particles. The results were presented in a scientific talk at the 2026 TeV Particle Astrophysics conference in Japan. The paper will be released on the online repository arXiv and submitted to the journal Physical Review Letters. “We’re very intrigued to see this event in the data, in the region where we expect dark matter to show up and the competing backgrounds are very low,” said Rick Gaitskell, a professor at Brown University and the spokesperson for LZ. “With only one event, we don’t want to get ahead of ourselves. We are not claiming to have seen dark matter. But we have seen something interesting that we want to share with the scientific community for their input.” The LZ collaboration studies experimental data in batches. In the new result, researchers analyzed 220 live days of data collected between March 2023 and April 2024. The collaboration had previously searched this dataset for faint signals from the simplest kinds of WIMP interactions. The new analysis searched for a broader range of possible WIMP interactions that could deposit more energy in the detector. LZ is particularly sensitive to such signals while also minimizing false positives. “This was a detailed study in a region we hadn’t explored within this dataset, and we spent months of additional effort to understand all the possible causes of background events,” said Sam Eriksen, a senior research associate at the University of Bristol in the U.K. and lead author of the study. “We understand our detector and the backgrounds so well that even a single outstanding event, like the one we found, is important. We expect dark matter events to be extremely rare, so only a handful could mark the first detection of WIMP dark matter.” If the anomalous event was caused by dark matter, the WIMP that generated it would likely have a mass of at least 200 GeV/c2 (gigaelectronvolts), or more than 200 times the mass of a proton. It would also suggest a specific type of interaction between WIMPs and ordinary matter beyond the simplest model. The LZ results have not reached “5-sigma” significance, the statistical threshold considered a discovery in physics. The new analysis is 2.6 sigma, meaning there is approximately a 0.5% chance that the event could be explained by known backgrounds. With additional data, researchers can test whether the finding continues to grow in significance or fades away. LZ has already accumulated the world’s largest dark matter dataset and will continue to accrue WIMP search data at SURF, substantially improving their search statistics. LZ searches for dark matter by looking for signature flashes of light from energy deposited in the detector. The collaboration leverages multiple methods to prevent or account for particle interactions caused by normal matter. This includes the mile of rock that shields the detector from cosmic rays from space, a water tank and outer detectors that protect the central detector from background neutrons, and a suite of computational tools that disentangle particle interactions and reject dark matter mimics. “Outlier events in the data are not unexpected, but they usually stand out as a background of some kind when you look at them deeper,” said Aaron Manalaysay, a physicist at Berkeley Lab and the chair of LZ’s Institutional Board. “This is the first example in any experiment I’ve worked on of an outlier that appears valid in every way. Of course, we’re still twisting our brains trying to think if there’s a rare background mechanism we could’ve missed, but it’s thrilling to wonder if this could be the first hint of a dark-matter observation.” LZ is supported by the U.S. Department of Energy, Office of Science, Office of High Energy and Nuclear Physics, and the National Energy Research Scientific Computing Center, a DOE Office of Science user facility. LZ is also supported by the Science & Technology Facilities Council of the United Kingdom; the Portuguese Foundation for Science and Technology; the Swiss National Science Foundation; the Australian Research Council Centre of Excellence for Dark Matter Particle Physics; and the Institute for Basic Science, Korea. Thirty-nine institutions of higher education and advanced research provided support to LZ. The LZ collaboration acknowledges the assistance of the Sanford Underground Research Facility. ### Lawrence Berkeley National Laboratory (Berkeley Lab) is committed to groundbreaking research focused on discovery science and solutions for abundant and reliable energy supplies. The lab’s expertise spans materials, chemistry, physics, biology, earth and environmental science, mathematics, and computing. Researchers from around the world rely on the lab’s world-class scientific facilities for their own pioneering research. Founded in 1931 on the belief that the biggest problems are best addressed by teams, Berkeley Lab and its scientists have been recognized with 17 Nobel Prizes. Berkeley Lab is a multiprogram national laboratory managed by the University of California for the U.S. Department of Energy’s Office of Science. DOE’s Office of Science is the single largest supporter of basic research in the physical sciences in the United States, and is working to address some of the most pressing challenges of our time. For more information, please visit energy.gov/science.
Aixia delivers AI infrastructure to leading Swedish player in media and entertainment, worth 2 MSEK
White Pearl Technology Group AB (publ) ("WPTG" or the "Group") announces that Aixia Group AB (publ) ("Aixia"), a company within the Group, has received an order from a well-known Swedish player in the media and entertainment industry. The order relates to the delivery of modern AI-adapted computing…
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Photo by UNCPUNC Pembroke’s Bachelor of Science in Computer Science program has earned initial accreditation from ABET’s Computing Accreditation Commission, providing independent recognition of the quality and rigor of the program as it prepares students for careers and advanced study in computing.The accreditation, which extends through Sept. 30, 2032, comes as UNCP continues to expand its computing programs amid rapid growth in artificial intelligence, cybersecurity, data science and other emerging technologies.ABET accreditation is a voluntary, peer-reviewed process that evaluates academic programs against established standards for quality. The review examines curriculum, student outcomes, faculty qualifications, assessment practices, student support and continuous improvement.“Earning initial ABET accreditation is a significant milestone for our Computer Science program because it provides external recognition of the quality of our program and validates our commitment to continuous improvement,” said Dr. Haitao Zhao, assistant professor in the Department of Mathematics and Computer Science, in a press release. “For our department, this achievement reflects the hard work and dedication of our faculty and staff and gives our students greater confidence in the quality of their education and preparation for careers and graduate study.”For prospective students, the accreditation provides independent assurance that UNCP’s program meets standards established for computing education and is preparing graduates to enter technical fields in the global workforce.Earning the accreditation required faculty and staff to conduct a comprehensive review of the program, including its curriculum, educational objectives, student learning outcomes and assessment processes. The review included a detailed self-study, documentation and an on-site evaluation.The accreditation arrives as UNCP looks toward the next phase of growth in computing. The department plans to continue strengthening its computer science curriculum while expanding hands-on learning and research opportunities for students. It also plans to pursue ABET accreditation for its information technology and cybersecurity programs.Future plans include developing new opportunities in artificial intelligence and graduate education, including an AI track and a Master of Science in Computer Science with a focus on AI and cybersecurity.
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EU membership bid gives boost to Moldova’s fledgling R&D landscape
Moldova’s push to join the EU is having the spillover effect of helping to improve the country’s R&D landscape, which in recent years has suffered from fragmentation, decreasing personnel and a lack of research infrastructure.The country became an EU candidate country in 2022, alongside Ukraine, and officially began accession negotiations in 2024. With a pro-EU government, Moldova has been actively carrying out reforms to align with EU standards. This has helped accelerate the development of R&D, said Igor Chiosa, acting head of the Research and Innovation Policy Directorate at Moldova’s Ministry of Education and Research. “Our R&D landscape is moving up, and we are more and more involved in the European Research Area,” he said. “The support we receive from the EU is very important, not only financially, but also because of incentives, consultation and capacity building.”The R&D landscape in the former Soviet republic is still relatively underdeveloped, despite attempts at improvement going back to a 2004 law on science and innovation and later reforms in 2017 and 2018. But the system remains in a “precarious situation” and “in the process of contraction,” according to an assessment carried out by the government for the current National Programme for Research and Innovation, which runs from 2024 to 2027. The analysis highlights in particular the declining number of researchers and PhDs, which has been continuously falling, as well as limited research funding. This is around 10 times lower than the EU average and “insufficient to maintain a level of research activity that supports higher education and meets the needs of the economy.” The mechanisms for allocating research funds are also described as inefficient, as well as the general fragmentation of the landscape, with research and innovation activities being carried out in 67 different places. The lack of strategic vision for research infrastructure is also noted. The strategy sets out to address these issues and is being fuelled by reforms linked to EU accession. Moldova now has a regulation on open science and gender equality. There is also a new support mechanism for technology transfer offices and a business-academia roadmap. In 2025, the country also became the first Eastern Partnership country to approve a Smart Specialisation strategy, which will coordinate its R&D efforts to focus on strengths, within a European context. “We’ve done a lot in terms of normative acts,” Chiosa said. Horizon Europe successMoldova is also seeing more success in the EU’s flagship R&D programme, Horizon Europe. The country has now won nearly €15 million in funding, already double the amount won under the previous programme, Horizon 2020, and more than the €10 million target set by the government. Chiosa said the priority has shifted now to winning more research-centred projects, rather than those related to support and capacity. Moldova is also targeting further involvement in large European projects. Last year, it joined the EuroHPC Joint Undertaking giving Moldovans access to Europe's supercomputing network. The country is also a member of Danubius-RI, a European research infrastructure focused on river and sea research. Despite these efforts, Moldova’s research capacity is still shackled by its limited R&D budget, which equates to 0.23% of its GDP. This is around half of what its neighbour Romania spends, which is the lowest in the EU. According to Chiosa, the research budget is increasing year-on-year, jumping by €6.34 million between 2024 and 2025. But this doesn’t show up when looking at it as a proportion of GDP. “Of course, it’s difficult,” he said. “That is why we are putting more emphasis on collaboration between business and academia, as well as participation in Horizon Europe, to try to diversify our sources of funding.”A World Bank loan of €30 million, plus a grant of €7.8 million, was agreed in 2025 to support the modernisation of Moldova’s universities. As part of this, a call was launched this year to provide universities grants of up to €900,000 to develop their research infrastructure. Moldova is also collaborating closely with Romania, with which it shares a common language, funding 100 joint projects in 2023 and 2024. This support has been instrumental. “They are helping with sharing their expertise, inviting us into consortia, and lots more,” Chiosa said. Looking forward, Moldova is eagerly anticipating joining the EU. “We are looking closely at what the EU is doing and will shape our future national programme in research innovation accordingly.”EU accession “blocked at a technical level”Moldova is aiming to join the EU by 2028, but despite its swift and eager efforts to meet the accession criteria, there remain obstacles outside of the country’s control. For a country to join the EU, it must have certain legislation in place and meet specific standards in various areas. This is categorised into six thematic clusters containing 33 chapters. Moldova and the EU have so far opened two of the clusters, numbers one and six. The first covers fundamental laws, such as the judiciary, security and financial legislation. The sixth covers external relations. The remaining four clusters are still unopened. This includes the third cluster, on competitiveness and growth, which contains the chapter on science and research.Related articlesQ&A: Albania’s ambition to become a ‘moderate innovator’Data corner: Horizon success rates are droppingThe European Commission has confirmed that these clusters are ready to be opened, with an official saying that the Commission is encouraging EU governments, who have the final say, to move forward on the matter. However, both clusters two and three remain blocked by the EU Council’s working party on enlargement and countries negotiating accession to the EU, a different official, representing the Council, confirmed.This working party is set to meet several times in the coming weeks, with a Council meeting scheduled for mid-October in which enlargement, and Moldova’s bid, will be discussed. But there is no certainty that these talks will lead to progress. According to the Council source, it is “completely impossible to foresee if and when the file will be unblocked,” citing the sensitivity of the matter. Moldova’s situation is particularly complicated. One factor is that it borders Ukraine and is increasingly embroiled in Russia’s war, with drone incursions occurring more often on its territory. Another is Transnistria, a Russian-backed breakaway state that lies within the territory of Moldova. It is unclear how the EU would be able to accept Moldova into the bloc while this situation remains unchanged. While there is no direct reason to delay opening cluster three with Moldova, as it covers matters unrelated to security, it could be that the EU is reluctant to speed through accession negotiations without first resolving broader, geopolitical issues.Chiosa is confident that, if and when the chapter on science and research is opened, Moldova will be able to finalise it quickly. It doesn’t require any legislative changes and is only a matter of proving certain standards, which Chiosa believes Moldova is well prepared to do. “We hope that chapter 25 on science and research will be one of the first chapters opened and closed,” he said.
Amazon is selling a 2-in-1 laptop and tablet for $60 that comes with a 5-piece accessories bundle
It's great for everyday computing tasks.
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Fall 2026 Collaboratorium Connects Midwest Researchers with Business Expertise - Polsky Center for Entrepreneurship and Innovation
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Cleveland Clinic, RIKEN and IBM Team Advance to Finals for 2026 ACM Gordon Bell Prize
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