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From Bedrock to Business: The Last Mile of Agentic AI - SPONSOR CONTENT WEBINAR FROM AWS AND WORKATO
Sponsor Content Webinar from AWS and Workato.
Andor Health Earns 2026 Frost & Sullivan Competitive Strategy Leadership Recognition for Agentic AI-Based Care Orchestration
/PRNewswire/ -- Andor Health, the leading AI-native clinical services company, today announced it has received Frost & Sullivan's 2026 Competitive Strategy...
OpenAI CFO Sarah Friar Sees Cybersecurity As Potential 'Big Driver' Of Business Amid Rising AI Demand
Friar also discussed increasing agentic AI usage in Europe, while acknowledging that the region trails somewhat in adoption.
Confido Health nabs $12.5M to scale agentic AI across PE-backed medical groups
Confido Health is expanding beyond AI voice agents to build out an agentic AI operating system that can execute administrative workflows across a medical practice. | The company secured a $12.5 million series A extension following its $10 million series A round announced in September to continue scaling an AI platform for end-to-end healthcare operations.
NTT DATA Business Solutions launches "Elevate", its Agentic AI-powered delivery framework, to help accelerate SAP transformations
NTT DATA Business Solutions, a leading global IT service provider and specialist in SAP solutions, today announces the launch of "Elevate", its next-generation Agentic AI-powered delivery framework. Elevate brings together the company's secure AI-enabled platform NTT DATA aXet, Natuvion's data transformation capabilities and SAP technologies, including SAP's Agent-Led Toolchain and SAP Business AI Platform. Elevate is designed to maximize the value clients gain from their investments in SAP and
HSBC’s Synopsys Upgrade Bets on a Business Model Shift. Can It Justify $700?
HSBC upgraded Synopsys Inc. (NASDAQ:SNPS) to Buy from Hold on September 25 and raised its price target from $490 to $700, implying a multiple of nearly 35 times HSBC’s fiscal 2027 EPS estimates. According to analyst Frank Lee, the company is evolving beyond its traditional slow-growth software profile as its licensing-plus-royalty model and agentic AI […]
Weekly Rundown: Nextech taps Assort Health, EliseAI for agentic AI; Elsevier rolls out clinical AI tool for nurses
Stay up to date on the latest in health tech, digital health and health AI news with this weekly brief. Read below for news from the week of Oct. 5 to 9. | The latest news from Nextech, Assort Health, EliseAI, Elsevier, Arcadia, Solera Health and more.
Genesis Mission: SYNAPS-I Brings Agentic AI to Experimental Workflows
With support from ALCF computing resources and AI services, the SYNAPS-I team demonstrated a new agentic AI platform that uses natural-language instructions to automate complex experimental workflows as part of the DOE Genesis Mission. Oct. 8, 2026 — Science has increasingly used artificial intelligence (AI) as a kind of microscope — sorting data, analyzing images […]
Google brings agentic AI to Gemini, starting with businesses
Google is turning Gemini into an AI agent that can plan, execute tasks, and work across business apps and systems. The agent can delegate work to subagents, use multiple AI models, and even gets its own workplace identity, complete with an email address.
Charm Security Appoints Dr. Elizabeth Huppert as Behavioral Science Director
Former JPMorgan Chase Vice President and Behavioral Scientist joins to advance behavioral science in agentic AI for fraud, scams, and cybercrime.NEW YORK, NY / ACCESS Newswire / October 6, 2026 / Security today announced the appointment of Dr.
ASUS Announces New 64GB Configuration of the Ascent GX10
ASUS today announced a new 64 GB configuration of ASUS Ascent GX10, expanding the lineup alongside the existing 128 GB model. This compact AI supercomputer is designed to bring local agentic AI development within reach of more developers, researchers and data scientists. Based on the NVIDIA DGX...
HP Work Relationship Index 2026: Workplace Health Rebounds as Workers Turn to Agentic AI, Skills-Building, and Better Tech Tools
Today, HP Inc. (NYSE: HPQ) released the fourth annual HP Work Relationship Index, a global study of more than 19,000 desk-based workers across 15 countries. This year’s study finds that workers with the healthiest relationship with work are becoming more confident in how they navigate uncertainty.
Xsight Group Featured in Harvard Business Review on AI Agent Orchestration Across Silos
HONG KONG, Sept. 28, 2026 /PRNewswire/ -- Xsight Group (known as Xsight), a Hong Kong–headquartered cross-border technology group founded in 2004, has been featured as a research case in "How AI Agents Orchestrate Work Across Silos," a special report published in the September–October 2026 issue of Harvard Business Review. The article examines how a new generation of AI systems can connect functions and reduce the coordination friction that slows companies down, citing Xsight's practice of decomposing complex cross-departmental decisions into modular tasks and building a layered agentic AI orchestration system as a valuable model for cross-border organizational coordination.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Digital Science's 2026 Catalyst Grant Seeks "Agentic AI Workflows You Can Trust"
Up to £25,000 to be won for early-stage solutions building research agents - with audit, governance and provenanceLondon, United Kingdom--(Newsfile Corp. - September 1, 2026) - Digital Science, a leading technology company serving stakeholders across the research ecosystem, today launches its Catalyst Grant round for 2026 to support innovative technology ideas. This year's theme is: Agentic Workflows You Can Trust.Up to £25,000 will be awarded equity-free to individuals, startups or research...
Digital Science's 2026 Catalyst Grant seeks agentic AI workflows
Up to £25,000 to be won for early-stage solutions building research agents – with audit, governance and provenance
Digital Science's 2026 Catalyst Grant seeks agentic AI workflows you can trust
Digital Science today launches its Catalyst Grant round for 2026 to support innovative technology ideas. This year's theme is: Agentic Workflows You Can Trust.
Run NVIDIA BioNeMo NIM Microservices for Protein Structure Prediction in Claude Science
Agentic AI is changing how research is done. AI scientists can read papers, propose hypotheses, call models, and determine which experiments to prioritize next. First proving their value in software…
Perplexity launches a local AI agent with zero token costs
Perplexity has launched "Portable Computer" — a new agentic AI that runs locally on NVIDIA hardware and saves token costs.
Intel Crescent Island GPUs Pack Up To 32 Xe3P Cores, Optimized For Agentic AI With Low-Cost LPDDR5X That Reaches Up To 480 GB Capacity
Intel has given the rundown on its next-gen AI inference accelerator, Crescent Island, which packs 32 Xe3 cores and 480 GB of LPDDR5X memory.
Why Agentic AI Could Expose the Leadership Gaps Holding Businesses Back
Agentic AI can boost productivity while exposing leadership gaps that require stronger guidance, accountability, and decision-making.
SAP Completes Dremio Acquisition to Expand Business Data Cloud for Agentic AI
SAP has completed its acquisition of Dremio, bringing Iceberg-native lakehouse, federated data access, and semantic capabilities into SAP Business Data Cloud to support enterprise analytics and agentic AI.
The Real Reason AI Investments Fail To Transform The Business
Why AI strategies stall, and how leaders can improve AI ROI, redesign workflows and operating models, and turn agentic AI into lasting business transformation.
[Galaxy Unpacked July 2026] A First Look at Galaxy Z Fold8 Ultra, Galaxy Z Fold8 and Galaxy Z Flip8
At Galaxy Unpacked July 2026 in London, Samsung Electronics unveiled the eighth-generation Galaxy Z series. Combining agentic AI that understands users with
How To Get Your Business Data Ready For AI Agents
Discover four practical steps for making business data ready for agentic AI while reducing risks around governance, compliance and accountability.
Dell Deskside Agentic AI cuts token costs by up to 87%
Dell, with Nvidia, introduces Deskside Agentic AI to manage token costs, enabling local trillion-parameter model runs and reducing cloud expenses.
Google Is Expanding Access To Its Gemini Spark Agentic AI Assistant
Gemini Spark is now available to more users.
Agentic AI in biomedical research: What is it and can it expedite science?
Researchers are venturing into a new area of collaboration that relies on agentic AI, co-scientists that can act independently and help humans ideate, hypothesize and speed up scientific exploration.
Ray Veeraraghavan joins L7 Informatics as VP science and AI
Indian American health executive to advance agentic AI platform across scientific workflows at life sciences firm.
How Clean, Accessible Data Powers Agentic AI Workflows and Better Business Decisions
Over the past few months, conversations with customers, partners, and peers — including at the recent Databricks Data + AI Summit — have surfaced a consistent set of shifts happening across the analytics and data landscape.
With ERP.net’s New App Builder, Businesses Can Create Applications Directly Inside Their ERP System
Bulgaria, July 3, 2026 -- European enterprise software company ERP.net has introduced App Builder - a new Agentic AI-native platform that enabl...
Gemini Spark Comes To Google's Gemini App For macOS
The Gemini macOS app now has access to Google’s Spark agentic AI assistant.
There's Now An OpenClaw App For iOS And Android Phones
Smartphones are welcoming the agentic AI overlords.
Microsoft Discovery Aims To Advance The Era Of Agentic Science
The cloud-based agentic AI platform aims to help human researchers overcome resource constraints and complex data challenges to accelerate science at scale.
Why Small Businesses Are Winning The AI Race With Agentic AI
Small businesses building agentic AI from scratch are outpacing larger competitors. The obstacle was never the technology, but ownership and trust.
Prosper AI lands $30M backed by Andreessen Horowitz to build AI workforce for healthcare operations
Nine months after announcing its seed funding round, Prosper AI banked $30 million to scale its agentic AI platform to power administrative tasks from patient scheduling to insurance verification a | Prosper AI banked $30 million to scale its agentic AI platform to power administrative tasks from patient scheduling to insurance verification and patient billing.
Doceree Recognized in the Gartner® Hype Cycle™ for Life Science Enterprise Technologies, 2026
Doceree, the only healthcare marketing platform that can measure and adapt to the actual clinical intent of both physicians and patients, has been recognized as a Sample Vendor in the Trusted Conversational AI in Life Sciences profile for the Hype Cycle™ for Life Science Enterprise Technologies, 2026. For Doceree, this recognition reflects the growing role of Agentic AI in life sciences.
Modernizing Front Desk Operations In Health And Wellness Practices
An administrative pain-point for patients and practices alike, agentic AI platforms are creating a seamless process to navigate health and wellness.
Modernizing Front Desk Operations In Health And Wellness Practices
An administrative pain-point for patients and practices alike, agentic AI platforms are creating a seamless process to navigate health and wellness.
I'm glad Apple isn't hyping up agentic AI (yet)
Apple is more focused on delivering usable features with Siri AI, instead of hyping up agentic AI. That's a good thing.
EHR vendor notebook: Elsevier, athenahealth and PointClickCare ramp up agentic AI
Also: Epic, Elation Health and Glooko activate high-need artificial intelligence integrations while Enzo Health launches an AI-native EHR for home health.
Apple Intelligence Can Change Your Passwords for You When You Get Hacked
Agentic AI and security are normally at odds, but this Apple Intelligence feature could be a lifesaver.
Elation Health acquires Aster as it ramps up agentic AI for primary care
Health tech company Elation Health acquired startup Aster to propel the company's development of an agentic AI operating system for primary care. | Health tech company Elation Health acquired startup Aster to propel the company's development of an agentic AI operating system for primary care.
How ASUS Is Bringing AI into Healthcare Workflows
Move from pilot to production with ASUS AI Hub and NVIDIA NemoClaw. Deploy scalable, secure on-premises enterprise Agentic AI with robust data governance and custom knowledge RAG workflows.
The price of Nvidia RTX Spark PCs is going to hurt
Here’s what we know so far about price and launch dates for these upcoming premium computers, which have been designed for an agentic AI world.
The Intelligent Health Care Enterprise: Driving Measurable Business Value with Agentic AI - SPONSORED CONTENT FROM AWS
Webinar Sponsored by AWS
Google delivering on Gemini promises means Apple Intelligence can do the same
Tests to determine whether Google’s agentic AI system Gemini Spark can deliver on the promises made on stage at last...
MSI shows MEG Vision X2 AI+: "The World’s First Gaming Desktop with Agentic AI Companion"
MSI MEG Vision X2 AI+ desktop adds a cylindrical AI display MSI has announced the MEG Vision X2 AI+, a new flagship gaming desktop that will be shown at
Google's Agentic AI Tool Gemini Spark Is Now Available
Gemini Spark is currently only available to Google AI Ultra subscribers in the US, meaning you’ll need to spend at least $100 per month to access it.
BMW Group: Agentic AI is part of our daily business
BMW Group: This article explores agentic AI and how it simplifies workflows, supports teams and makes processes even more intelligent.
Omni, Pics, and a Big Search Overhaul: Everything You Missed at Google I/O 2026
Google's Tuesday I/O keynote was jam-packed with news about AI, AI, and more AI, from agentic AI in search and Gemini enhancements to details about the Google-Samsung smart glasses.
Alteryx Puts Business Logic at the Center of Agentic AI, Enabling Enterprises to Operationalize AI at Scale
/PRNewswire/ -- Alteryx, Inc., a leading AI-ready data and analytics company, today unveiled new product capabilities that advance agentic automation across...
Google announces agent-optimized Gemini 3.5.Flash and a do-anything model called Omni
Google says its more efficient Gemini 3.5 Flash is the key to your agentic AI future.
With Gemini 3.5 Flash, Google bets its next AI wave on agents, not chatbots
Google launched Gemini 3.5 Flash, its most powerful coding and agentic AI model yet, at the company's annual developer conference. It is capable of autonomously executing complex tasks and building software from scratch.
The new CEO flex: Bragging about how much AI code your company shipped
CEOs like Meta's Mark Zuckerberg can't stop talking about how agentic AI is changing how engineers code — and it's not just the Big Tech bosses.
Cloudflare announces 1,100 layoffs amid AI focus shift
Cloudflare announced 1,100 layoffs as it restructures for the age of agentic AI, sending shares tumbling.
Global Health & WASH: May 2026 Funding Opportunities (14 new opportunities!)
The May update for Global Health & WASH brings new calls that cluster around three distinct shifts: LMIC research leadership moving from funder encouragement into a hard eligibility constraint, pharmaceutical and corporate-linked funders running structurally independent education and use-inspired research portfolios at substantial scale, and AI adoption shifting decisively from speculative tool to operational capability across health and WASH systems alike. In LMIC Research Leadership as Eligibility, Not Encouragement, Wellcome anchors the dominant signal of the month with three separate major calls that all require or strongly center LMIC leadership in their basic eligibility architecture. Wellcome’s ESIC Hubs (£1.5-£1.9M per hub over 3-5 years) explicitly requires an LMIC-based lead applicant, treating Global South leadership as a design constraint rather than a participation goal. Wellcome’s Infectious Disease Clinical Trial Development Award funds transdisciplinary teams whose lead must be a mid-career or established researcher based at an organization in Africa, South Asia, or Southeast Asia. Wellcome’s larger Infectious Disease Clinical Trial Award (£1M-£8M for optimizing licensed interventions) requires the administering organization to be in eligible LMIC regions and at least 50% of applicants based there. Around Wellcome, the same pattern shows up at smaller scale and across funders: CHINNOVA channels $1M into West and Central African research institutions for climate-health work; IBRO’s Neuroscience Training Grants explicitly tier ceilings by region of residence with Africa receiving the highest amount ($5,000); IHME’s GBD Emerging Researcher Award reserves at least one of its two annual awards for an LMIC researcher; Sidaction’s HIV Cure call funds research teams across France, the Netherlands, and eligible African countries with a minimum two-country collaboration requirement. Taken together, these calls signal a meaningful shift in how research equity is being operationalized — not as encouragement language at the bottom of a call, but as a structural feature of who can lead, where the work must be administered, and what proportion of the team must be regionally rooted. In Pharma-Funded Independent Medical Education and Use-Inspired Research, the lineup this month is unusually deep. Pfizer alone runs four parallel calls under independent education and quality improvement frameworks: a Migraine and Women’s Health RFP (200K x 2-year, $500K pool), Migraine IME ($200K, $1M pool), JAK Inhibitor evidence-based education ($100K), and Maternal Vaccination HCP Education in Saudi Arabia ($75K), plus a separate Pediatric Pneumococcal Surveillance research call in Saudi Arabia ($400K per project). Novo Nordisk Foundation runs four parallel calls of its own at substantial scale: Infectious Diseases Catalyst Grants (DKK 60M pool, up to DKK 7M collaborative), Non-Diabetic Endocrinology Collaborative Grants (DKK 53M pool, DKK 5-10M per project), Pioneer Innovator Grant Health (DKK 1.1M), and Distinguished Innovator Grant Health (DKK 6.8M). LEO Foundation deploys DKK 2-4M per project for dermatology research excellence. Pfizer’s framing across calls deliberately separates the funding from product promotion, emphasizing measurable practice-relevant change and structural distance between scientific outputs and commercial activity. Novo Nordisk’s “use-inspired” hard filter pushes researchers toward a credible translation pathway from mechanism to deployable tool. The pattern: industry-aligned funders are running structurally independent portfolios at meaningful $ that fund implementation evidence, not promotion. In AI as Operational Capability, Not Speculation, several calls this month explicitly treat AI adoption as a near-term operational question with real evidence and governance requirements, rather than a speculative trend to be watched. Wellcome’s ESIC Hubs frames AI as “the accelerator” for evidence synthesis, asking hubs to translate technical innovation into adoption-ready workflows that can match real-world policy timelines. UNICEF Venture Fund’s new Climate Tech for Children’s Health call funds for-profit startups deploying AI, machine learning, and blockchain in low-resource environments, with a strict requirement that solutions must already have a working prototype with promising pilot results. The Water Research Foundation has launched two simultaneous AI calls treating reproducibility, cybersecurity guardrails, and human-in-the-loop deployments as core design constraints rather than nice-to-haves: one on GenAI and Agentic AI in water utilities ($200K), one on alternatives to water shutoffs that explicitly screens for implementation economics evidence. Nordic Innovation’s quantum technology call (NOK 4.5M) extends the same logic into life science and healthcare, demanding consortium-stage projects mature enough to test with real users. TEF-Health offers €300K in subsidized testing infrastructure for European healthcare AI and robotics SMEs. The pattern: funders are converting AI pilots into playbooks, requiring transfer evidence and risk controls before AI can move from experimentation to sector-wide operational practice. For LMIC-based researchers in infectious disease or evidence synthesis, the three Wellcome calls together represent the deepest concentration of LMIC-led research capital in recent memory — pair the Infectious Disease Clinical Trial Development Award (£200K, deadline May 19) as a strategic pipeline feeder into the larger Infectious Disease Clinical Trial Award (£1-£8M, deadline June 2), since the development award functions explicitly as a track into the larger trial scheme. For Nordic researchers, the four Novo Nordisk Foundation calls plus LEO Foundation and Nordic Innovation Quantum represent ~$30M in regional research capital this cycle, all with deadlines clustered in May-August. For WASH practitioners, the three Water Research Foundation calls together (each up to $200K) are a cluster worth reading across — one on AI deployment, one on shutoff alternatives, one rewarding applied innovation — and the strongest applicants will articulate how their work bridges utility operations to policy-relevant evidence. For US-based clinical researchers and educators, the four Pfizer calls plus the APF Portfolio’s 80+ programs form an unusually accessible recurring pipeline; APF’s prohibition on indirect costs is a meaningful structural feature for early-career applicants whose institutions might otherwise absorb significant overhead. Snapshot of New Opportunities Total Estimated Funding Pool: $100 Million+ USD The grants are organized into three categories: Open Calls: Current grant and opportunities with a deadline. Grants are listed by closing date. 39 open opportunities- 14 new! Rolling Applications: current grant and opportunities with rolling applications (but it’s still best to submit as early as possible). 14 rolling opportunities- 1 new opportunity! Long term planning: Grants that have closed their current rounds, but are expected to open new windows. 4 long term opportunities! A quick tip for returning readers: if you want to jump straight to the newest additions, use CTRL F to search for “New!” and navigate quickly to the latest funding opportunities This post is for paid subscribers. This helps support the time and effort it takes to curate and organize these opportunities. Subscribe To keep this accessible to everyone who needs it, we’re happy to offer pay what you can rates. You can find more details here. Open Calls: Migraine Competitive Grant Program: Migraine and Women’s Health (Quality Improvement and/or Research RFP), Pfizer.*Closing soon!* Pfizer, in collaboration with the American Headache Society, is seeking independent quality improvement and research projects that close persistent gaps in migraine care for women across the United States. The funding logic centers on measurable, practice-relevant change: proposals should generate actionable evidence, tools, or system improvements that can be shared and used widely, not just within a single site. Priority areas span menstrual migraine and screening in women’s health settings, the role of hormonal fluctuations across the lifespan, sex-specific risk factors, comorbidities and quality-of-life burden, and disparities in outcomes by race, ethnicity, and socioeconomic status. The call is structured as a two-step competitive process with an initial Letter of Intent, with the strongest concepts expected to translate scientific insight into implementable improvements in diagnosis, management, and equity. Geographies: United States. Who can apply: U.S.-based organizations (not individuals), including professional schools, healthcare institutions, professional organizations, and other entities focused on healthcare improvement. Funding amount: Up to USD $200,000 total over 2 years; total pool USD $500,000. Targeted Sectors / SDGs: Health; Focus areas: migraine, women’s health, quality improvement, clinical research, menstrual migraine, health disparities. Deadline: LOI: May 5, 2026; Full proposal (by invitation): August 28, 2026. Learn more and apply here. This RFP rewards “shareable impact”: the most competitive submissions will pair rigorous methods with a clear plan for system uptake and dissemination beyond the originating institution. ReSSARC: Strengthening the Health Sector and Food Security in the Central African Republic (AID 013381/01/0) Call for Proposals, Italian Agency for Development Cooperation (AICS). *Closing soon!* AICS is seeking a limited set of high-capacity humanitarian partners to deliver an integrated package that stabilizes essential health services while reducing acute malnutrition and strengthening food security resilience in priority areas of the Central African Republic. The funder’s logic is explicitly nexus-based: proposals should meet urgent, life-saving needs while reinforcing local systems, coordination mechanisms, and community-level capacity so results persist beyond the emergency window. AICS emphasizes inclusion and protection outcomes, expecting gender-sensitive design and explicit measures for groups facing compounded vulnerability, including women, children under five, internally displaced people, and people with disabilities. The call also signals a localization pathway, encouraging stronger collaboration with national NGOs and balanced partnerships, alongside clear coordination with existing cluster and humanitarian actors to minimize duplication and improve coverage. Geographies: Central African Republic (Bangui, Ombella-Mpoko, Ouham, Ouham-Pende, Lim-Pende, Lobaye). Who can apply: Non-profit organizations registered with AICS, plus eligible non-profits without an office in Italy that have a pre-existing collaboration agreement with an AICS-listed organization. Funding amount: Total pool EUR €1,800,000; max EUR €800,000 (single applicant) or EUR €1,000,000 (ATS). Targeted Sectors / SDGs: Health; Focus areas: malnutrition prevention and treatment, maternal and child health, community health services, food security and resilience, localization partnerships Deadline: May 5, 2026. Learn more and apply here. This call is structured to reward partners who can link frontline service delivery to system durability and localization, not just short-term coverage gains. Contracts for Innovation in drug and alcohol addiction healthcare, Innovate UK. *Closing soon!* Innovate UK, on behalf of the Office for Life Sciences Addiction Healthcare Goals program, is procuring R&D to accelerate innovations that can improve treatment outcomes, strengthen recovery, and reduce harm and deaths linked to drug and alcohol addiction. The competition is positioned as a market-facing readiness push: selected projects are expected to advance solutions toward later-stage validation, generate evidence of user acceptability and UK market fit, and map credible routes through regulatory and certification requirements. Innovate UK signals a preference for innovations that can be field-tested in relevant UK settings and progressed to TRL 6 or 7, with practical plans for commercialization after contract completion. This structure favors applicants that can execute most work in-house, co-develop with service providers and people with lived experience, and translate technical progress into deployable tools for addiction healthcare delivery. Geographies: United Kingdom. Who can apply: Single organizations of any size (including EU, EEA, or international) leading delivery, with most work and key deliverables carried out in the UK; subcontractors for specialist skills only. Funding amount: GBP £200,000–1.5 million per project (inclusive of VAT); Total pool: GBP £20 million (across two strands). Targeted Sectors / SDGs: Health; Focus areas: Mental Health, Health Systems Strengthening, Research & Development, Technology Access. Deadline: May 6, 2026 (11:00am). Learn more and apply here. This call uses procurement to pull near-market addiction innovations toward operational proof and adoption pathways in UK services.
Amazon’s chip business scores another major win
Amazon’s stock jumped toward a record high Friday, after the company announced that Meta plans to use tens of millions of the company’s Graviton chips for agentic AI workloads.
Vodafone Business Launch New AI and Cybersecurity Solutions to Accelerate Small Business Digital Transformation in Partnership with Google Cloud
Cloud Next '26 -- Today Vodafone Business and Google Cloud announce an expansion of their strategic partnership with two new solutions to equip small-and medium-sized businesses (SMBs) with advanced cybersecurity and agentic AI.
Vodafone offers small businesses cybersecurity, AI capability with Google tie-up
European mobile and broadband operator Vodafone said it would offer its small business customers advanced cybersecurity and agentic AI through its $1 billion strategic tie-up with Google Cloud agreed in October 2024.
CFC pilots agentic AI system that underwrites in seconds
London firm is testing AI on live cyber business, marking what it calls a first for the industry
Time for government, business leaders to figure out AI cybersecurity regulation
Experts say capabilities of agentic AI rising, along with risk to personal data, economy, national security.
Microsoft Plans to Bring Copilot Into the Agentic AI Age
An always-on Copilot could sort out your inbox and calendar.
Meet CAS Newton: Agentic AI built for science
/PRNewswire/ -- CAS, a division of the American Chemical Society, today announced the launch of CAS Newton℠, science-smart agentic AI built specifically for...
Gemma 4 and what makes an open model succeed
Having written a lot of model release blog posts, there’s something much harder about reviewing open models when they drop relative to closed models, especially in 2026. In recent years, there were so few open models, so when Llama 3 was released most people were still doing research on Llama 2 and super happy to get an update. When Qwen 3 was released, the Llama 4 fiasco had just gone down, and a whole research community was emerging to study RL on Qwen 2.5 — it was a no brainer to upgrade. Today, when an open model releases, it’s competing with Qwen 3.5, Kimi K2.5, GLM 5, MiniMax M2.5, GPT-OSS, Arcee Large, Nemotron 3, Olmo 3, and others. The space is populated, but still feels full of hidden opportunity. The potential of open models feels like a dark matter, a potential we know is huge, but few clear recipes and examples for how to unlock it are out there. Agentic AI, OpenClaw, and everything brewing in that space is going to spur mass experimentation in open models to complement the likes of Claude and Codex, not replace them. Especially with open models, the benchmarks at release are an extremely incomplete story. In some ways this is exciting, as new open models have a much higher variance and ability to surprise, but it also points at some structural reasons that make building businesses and great AI experiences around open models harder than the closed alternatives. When a new Claude Opus or GPT drops, spending a few hours with them in my agentic workflows is genuinely a good vibe test. For open models, putting them through this test is a category error. Something else to be said about open models in the era of agents is that they get out of the debate of integration, harnesses, and tools and let us see close to the ground on what exactly is the ability of just a model. Of course, we can’t test some things like search abilities without some tool, but being able to measure exactly the pace of progress of the model alone is a welcome simplification to a systematically opaque AI space. Share The list of factors I’d use to assess a new open-weight model I’m considering investing in includes: Model performance (and size) — how this model performs on benchmarks I care about and how it compares to other models of a similar size. Country of origin — some businesses care deeply about provenance, and if a model was built in China or not. Model license — if a model needs legal approval for use, uptake will be slower at mid-sized and large companies. Tooling at release — many models release with half-broken, or at least substantially slower, implementations in popular software like vLLM, Transformers, SGLANG, etc due to pushing the envelope of architectures or tools. Model fine-tunability — how easy or hard it is to modify the given model to your use-case when you actually try and use it. The core problem is that some of these are immediately available at release, e.g. general performance, license, origin, etc. but others such as tooling take day(s) to week(s) to stabilize, and others are open research questions — with no group systematically monitoring fine-tunability. In the early era of open models, the days of Llama 2 or 3 and Qwen pre v3.5, the architectures were fairly simple and the models tended to work out of the box. Some of this was due to the extremely hard work of the Llama, Qwen, Mistral, etc. developer teams. Some is due to the new models being genuinely harder to work with. When it comes to something like Qwen 3.5 or Nemotron 3, with hybrid models (either gated delta net or mamba layers), the tooling is very rough at release. Things you would expect to “just work” often don’t. I’ve been following this area closely since we released Olmo Hybrid with a similar architecture, and Qwen 3.5 is just starting to work well in the various open-source tools that need to all play nice together for RL research. That’s 1.5 months after the release date! This is just to start really investing more into understanding the behavior of the models. Of course, others started working on these models sooner by investing more engineering resources or relying on partially closed software. The fully open and distributed ecosystem takes a long time to get going on some new models. All of this is lead-in for the most important question for open models — how easy is it to adapt to specific use-cases? This is a different problem for different model sizes. Large MoE open-weight models may be used by entities like Cursor who need complex capabilities in their domain, e.g. Composer 2 trained on Kimi K2.5. Other applications can be built on much smaller models, such as Chroma’s Context-1 model for agentic search, built on GPT-OSS 20B. The question of “which models are fine-tunable” is largely background knowledge known by engineers across the industry. There should be a thriving research area here to support the open ecosystem model. The first step is to understand characteristics of different base and post-trained models to understand what they look like. The second step is to tune pretraining recipes for open models so they’re more flexible. Interconnects AI is a reader-supported publication. Consider becoming a subscriber. Subscribe For The ATOM Project and other Interconnects endeavors, we’ve put in substantial effort to measuring adoption trends in the open ecosystem. Everything takes a long time to unfold after a model is first publicly available — and adaptability is why. What we know for sure now, when Qwen has been going from strength to strength with its releases, is that technical staff across the industry has gotten comfortable working with Qwen models. Countless research methods and datasets were made to work with Qwen. It’ll take patience for any other model family to get to this point — a patience I’m not sure many open model builders have. This takes us to Gemma 4, Google’s latest open models. Gemma 3 was released more than a year ago, in March of 2025, and is a bit underrated. Gemma 4 comes in 4 sizes for now, with a bigger, MoE model of over 100B total parameters rumored but not released yet. The models we have today come in sizes of ~5B dense, 8B dense, 26B total 4B active MoE, and 31B dense. I’m most excited that they’re finally adopting a standard Apache 2.0 open source license. This’ll massively boost adoption. The standard of better licenses for strong open-weight LLMs was set by mostly Chinese open model labs in the last 1-2 years, and now U.S. companies are following suit. I will personally be so happy if the horrible Llama licenses and Gemma terms of service were an ~18-month transient dynamic of the industry being nervous about releasing strong open models. The Gemma 4 scores look very solid, the small models have incredible benchmark scores (especially in general domains like LMArena) and the 31B model rivals the recent Qwen 3.5 27B, which is the leading member of that class. The ~30B size range is an important one, as it’s accessible both to researchers and to enterprises looking to deploy the model in real use-cases. Where the 7B model scale is the default for tinkering and research, a 30B model is the default for seeing if an open model can unlock substantial value in your specific workflow — a good mix of intelligence, low price, tractability for downstream training, etc. This takes us back to the above adoption criteria I mentioned for open models and the bigger question — do I think Gemma 4 will be an overwhelming success? Previous Gemma models have been plagued by tooling issues and poorer performance when being finetuned. Gemma 4’s success is going to be entirely determined by ease of use, to a point where a 5-10% swing on benchmarks wouldn’t matter at all. It’s strong enough, small enough, with the right license, and from the U.S., so many companies are going to slot it in. I’m cautiously optimistic that Gemma 4 is going to work better here. Winds are shifting for open models built in America. We saw GPT-OSS go through a bumpy launch to become an overwhelming success. There’s a collective energy around the likes of Reflection, Arcee, Nemotron, Gemma, Olmo, and peers that show substantial demand for building new stacks around open models. There’s capital to be spent on AI stacks across the economy by those who want more ownership of everything, including the model. After launching The ATOM Project 240 days ago, the conversation is shifting into the next stage. Summer of 2025 was a crisis moment where the U.S. AI scene realized it can’t wait and figure out open models after building AGI. The two markets will capture different areas and proceed in parallel. Now that more companies in the U.S. are releasing strong models, we need to improve the ecosystem so that these models are easy to use, understand, and build value around. It’s the hard work to build another inflection point in these adoption plots I’ve been updating consistently, but that’s the work to be done. Join me in it. More data coming soon! Here’s a sneak peek:
Samsung Browser for Windows is now official, and it really wants to replace Chrome
Samsung's PC browser comes with agentic AI features powered by Perplexity.
Samsung Takes Its Browser Beyond Mobile, Extending Agentic AI Across Devices
Seamlessly connecting the mobile and PC browsing experience while simplifying complex web tasks with new agentic AI capabilities
'Claude, Resize These Photos' - Anthropic's Agentic AI Will Run Photoshop For You
It can perform boring tasks.
Paradigm Launches Surface, an AI-Native Platform That Connects Culture to Business Performance
Paradigm, the talent and culture intelligence company, today announced the launch of Surface, an AI-native platform that gives talent and culture leaders a unified view of what's shaping their organizations, benchmarks their efforts against peers, and translates insights into action with the industry's first agentic AI.
Alibaba launches agentic AI tool for businesses with Slack, Teams integration plans
Alibaba unveiled a new enterprise artificial intelligence tool on Tuesday amid a series of other developments in the company's AI space.
UiPath Expands Into Healthcare AI As Valuation Lags Analyst Targets
UiPath (NYSE:PATH) has launched agentic AI automation tools tailored for healthcare providers and payers. The company is partnering with Genzeon to target data management and revenue cycle workflows. Use cases include medical records summarization, claim denial prevention, and prior authorization processing. For investors following NYSE:PATH, this move takes the company deeper into healthcare, a sector where many workflows still rely on manual processes and fragmented systems. UiPath built...
The train has left the station: Agentic AI and the future of social science research
A new era of agentic AI agents has begun. What does it mean for social scientists? Solomon Messing and Joshua Tucker discuss.
Everything announced at Samsung Unpacked 2026: Galaxy S26 Ultra, Privacy Display, Buds 4 Pro
From the Galaxy S26 phones to new earbuds and agentic AI, here's everything unveiled at Samsung Unpacked this week.
5 Business Technology Trends Leaders Can’t Ignore in 2026
AI is no longer about pilots and promise. Leaders must focus on execution, using agentic AI, smart automation and disciplined cloud and security strategies to deliver business value.
Agentic AI and the rise of in silico team science in biomedical research
Nature Biotechnology - This study examines the emerging use of agentic artificial intelligence (AI) in biomedical research, highlighting the challenges and opportunities that may inform the design...
Provenir Launches Comprehensive Decision Intelligence Platform with New Agentic AI Features to Supercharge Business Performance and Agility
PARSIPPANY, N.J., February 13, 2026--Provenir, a global leader in AI risk decisioning, today announced the launch of its comprehensive decision intelligence platform with new agentic AI features to supercharge business performance and operational agility.
IntelePeer Introduces SmartAgent Collections, Automated Revenue Recovery Solution for DSOs and Specialty Healthcare Providers
DANIA BEACH, Fla., February 09, 2026--IntelePeer introduces SmartAgent Collections, an automated Agentic AI solution that improves revenue recovery for DSOs and healthcare providers.
Vendor Notebook: Tackling deployment gaps with agentic AI
Epic, Oracle and Humana have all announced new integrated capabilities. Meanwhile, Corti says through its new infrastructure on NVIDIA that healthcare organizations can create artificial intelligence agents and scale without clinical risk.
What International Business Machines (IBM)'s New Enterprise AI Platform Push Means For Shareholders
IBM recently announced several AI initiatives, including IBM Enterprise Advantage for building internal AI platforms, an enterprise-grade agentic AI collaboration with e&, and GRAMMY IQ built with watsonx to power interactive fan experiences using historical Recording Academy data. Together, these moves highlight IBM's push to embed governed, agentic AI across both mission-critical enterprise workflows and high-visibility consumer-facing experiences, underscoring its ambition to be an...
AI Has A Brand Problem And Entertainment Is The Fix
AI is reshaping brand strategy. As agentic AI scales content marketing, brands must build entertainment fields, creating loyalty and gravity beyond transactions.
How digital business models are evolving in the age of agentic AI
As businesses adopt AI, they need to rethink how they make money. Understanding these four new businesses models is a place to start.
How Broadcom's IT Leverages Tanzu Platform to Achieve Enterprise-Scale Agentic Business Transformation - Broadcom News and Stories
Broadcom’s Global Technology Organization is rolling out agentic AI engineering tools to boost productivity and ROI for thousands of developers. By adopting the VMware Tanzu Platform, Broadcom can deliver safer and compliant coding assistants powered by MCP servers, while centralizing governance, performance tuning, cost control, and AI safety across the enterprise.
69% Global Executives Predict AI Agents will Reshape Business in 2026, According to DeepL Research
The age of the AI agent has arrived. New research from DeepL, a global AI product and research company, reveals that 2026 will mark a decisive shift from AI experimentation to agentic automation with a majority (69%) of global business leaders expecting agentic AI to transform their operations in the year ahead.
After Elsa, FDA rolls out 'agentic AI' for staff
In this edition of STAT's Health Tech newsletter: FDA rolls out agentic AI for staff, and news about a radiology acquisition, chatbots.