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Iowa Business Council predicts economically positive third quarter

A new survey from the Iowa Business Council reports a positive economic prediction for the next six months. The IBC’s Economic Outlook Survey (EOS) for the third quarter was 0.1 points higher than the report for the second quarter, now reaching 64.91 points. If the points are higher than 50, the survey is reported positive. […]

Oct 8 • 1:04 PM EDT • Business • corridorbusiness.com

Iowa Business Council survey shows postive outlook on state's economy

The Iowa Business Council (IBC) has released its third quarter Economic Outlook Survey that gauges the outlook for the next six months. IBC President Joe Murphy says it’s based on a 100 point scale. “Our overall survey score was 64.91 index points, so just under 65 points, relatively flat, virtually no movement on the overall […]

Oct 7 • 4:07 PM EDT • Business • radioiowa.com

Apple’s new M6 Mac Mini is over $100 off

The first price reduction on the M6 model.

Oct 5 • 11:08 AM EDT • Technology • theverge.com

Brazil Heads to Lula-Bolsonaro Runoff as Right Gains Ground in First Round

With nearly 99 percent of votes counted, Bolsonaro had about 47 percent of valid votes, compared with 44.9 percent for Lula.

Oct 5 • 3:06 AM EDT • Politics • politicstoday.org

Not Completely Out Of The Blue: Introducing The Longines Spirit Pilot And Spirit Pilot Flyback With Blue Dials

✓ Not completely out of the blue ✓ Introducing the Longines Spirit Pilot and Spirit Pilot Flyback with blue dials in fan-favorite sizes ✓

Oct 3 • 1:00 AM EDT • Technology • fratellowatches.com

Business: Pioneer Connect rolls out lower internet pricing across all service tiers

Pioneer Connect announced permanent internet price cuts, dropping its gigabit fiber package to $84.95 a month and adding a no-contract "Price for Life" guarantee.

Oct 2 • 8:44 AM EDT • Business • philomathnews.com

Pay $34.99 Once for a PDF Tool Built for Business Workflows

Edit, convert, sign, and organize PDFs.

Sep 30 • 11:50 AM EDT • Business • entrepreneur.com

Brookfield Business (TSX:BBUC) Rebound Hopes Meet A Fair Value Reality Check

Brookfield Business (TSX:BBUC) has been drawing attention after its share price closed at CA$35.96, with recent returns showing mixed momentum over the past week, month, and past 3 months for investors tracking the stock. For context, Brookfield Business is coming off a weak stretch, with the share price down 27.31% year to date and 15.15% over the past 3 months. However, the 3-year total shareholder return of 84.94% still points to a much stronger longer-term outcome than the recent pullback...

Sep 28 • 2:09 AM EDT • Business • finance.yahoo.com

Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL

Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Sep 26 • 9:36 AM EDT • Technology • newsletter.semianalysis.com

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Sep 2 • 5:30 AM EDT • Technology • theverge.com

Is Oscar Health (OSCR) Fully Priced Following Raised 2026 Guidance?

Oscar Health (OSCR) recently reported record first half 2026 results and raised its full year guidance, a combination that appears to have supported renewed investor attention on the stock this month. At a share price of US$30.47, Oscar Health has seen some short term volatility, with a 7 day share price return down 4.9%. However, the 90 day share price return of 37.07% and 3 year total shareholder return of 363.07% suggest momentum has been strong over a longer stretch as investors react to...

Aug 29 • 4:13 PM EDT • Health • finance.yahoo.com

New Official Nintendo 64 Game Launches to Strong 4.9/5 Reviews

A new game officially releases on original Nintendo 64 hardware and also receives strong reviews from players.

Aug 28 • 12:30 PM EDT • Technology • gamerant.com

Apple TV Price Hike: Streaming Service Raises Monthly and Annual Plans

The streaming service now costs $14.99 per month, with Apple One rising to $21.95 per month.

Aug 28 • 9:23 AM EDT • Technology • hollywoodreporter.com

Apple TV Streaming Service Receives Price Increase Today

As reported by Deadline, Apple TV has received a price increase today. In the U.S., the streaming service now costs $14.99 per month, up from $12.99 per month. The annual price for Apple TV is now $119, up from $99. The annual price for Apple TV is now $119, up from $99.

Aug 28 • 9:10 AM EDT • Technology • macrumors.com

Apple TV Hikes Price, Will Now Cost $14.99 A Month In U.S.

Apple TV is the latest streamer to raise rates. Its monthly subscription price will increase by $2 to $14.99. on August 28.

Aug 28 • 9:04 AM EDT • Technology • deadline.com

Record $4.95 million raised for heart health in Alberta as Miyu Yamashita wins CPKC Women's Open

The 2026 CPKC Women's Open raised a record $4.95 million to support heart healthcare in Alberta, while on the golf course, Miyu Yamashita concluded a historic performance on Sunday to capture the 2026 CPKC Women's Open and her fourth LPGA Tour victory.

Aug 23 • 10:49 PM EDT • Health • finance.yahoo.com

Scientists in Iceland drilled straight into 900°C magma by accident — so energy-dense was the well that resulted, it could produce nearly ten times the power of a conventional geothermal well

An accidental breakthrough in Iceland reveals how to tap into magma itself, potentially unlocking geothermal energy at scales previously thought impossible.

Aug 23 • 5:30 AM EDT • Science • spacedaily.com

Scientists in Iceland drilled straight into 900°C magma by accident — so energy-dense was the well that resulted, it could produce nearly ten times the power of a conventional geothermal well

An accidental breakthrough in Iceland reveals how to tap into magma itself, potentially unlocking geothermal energy at scales previously thought impossible.

Aug 23 • 5:30 AM EDT • Technology • spacedaily.com

This platform gives you ChatGPT, Gemini, Claude, and 17+ other AI models for life for $54.97

20+ AI models for a one-time fee

Aug 16 • 5:00 AM EDT • Technology • mashable.com

I looked inside an AI generated movie, and the best parts were all human

A deep dive into Higgsfield’s new AI-generated movie.

Aug 13 • 11:30 AM EDT • Entertainment • theverge.com

India's Mahindra to transfer truck, bus business to SML Mahindra

Mahindra & Mahindra said on Wednesday it would transfer ​its truck and bus ‌business to listed subsidiary SML Mahindra for 5.25 billion ​rupees ($54.92 million), consolidating the ​group's commercial vehicle operations under ⁠a single entity.

Jul 29 • 4:39 AM EDT • Business • reuters.com

Apple Retires iPhone Upgrade Program for Klarna-Backed Leases

Apple today launched Apple Upgrade, a new U.S. leasing program for iPhone, iPad, Mac, and Apple Watch. Apple partnered with Klarna for Apple Upgrade, and it replaces the current iPhone Upgrade Program and iPhone Payments. Apple Upgrade has lower base prices than the iPhone Upgrade Program, with iPhones available starting at $17.99 per month and the Apple Watch available starting at $11.99 per month. Macs can be leased starting at $24.99 per month, and iPads start at $11.99 per month.

Jul 28 • 8:20 AM EDT • Technology • macrumors.com

Visualize Group LP Takes $14.93 Million Position in Live Nation Entertainment, Inc. $LYV

Visualize Group LP bought a new stake in shares of Live Nation Entertainment, Inc. (NYSE:LYV - Free Report) in the first quarter, according to the company in its most recent Form 13F filing with the Securities and Exchange Commission. The institutional investor bought 97,922 shares of the company'

Jul 27 • 6:01 AM EDT • Entertainment • marketbeat.com

Is Tencent Music Entertainment Group (TME) Undervalued After Its CTF Life Awards Deal?

Tencent Music Entertainment Group (TME) is back in focus after CTF Life agreed to become the exclusive title sponsor of the 2026 TMElive International Music Awards, bringing the event to Hong Kong for the first time. See our latest analysis for Tencent Music Entertainment Group. Despite the CTF Life partnership putting Tencent Music Entertainment Group back in the headlines, the stock’s recent performance has been mixed, with a 1 month share price return of 4.95% contrasting with a year to...

Jul 18 • 3:20 PM EDT • Entertainment • simplywall.st

Health insurers propose double-digit-percentage price increases for Illinois exchange plans

For 2027, the state’s largest health insurer, Blue Cross and Blue Shield of Illinois, is proposing an average price increase of 14.9% across its exchange plans.

Jul 9 • 2:18 PM EDT • Health • chicagotribune.com

Surprise rival knocks Costco's famous rotisserie chicken off its perch as best bird

Consumer Reports named Sam's Club's rotisserie chicken the best warehouse club bird, edging out Costco's iconic $4.99 Kirkland Signature option.

Jul 2 • 6:38 PM EDT • Business • foxbusiness.com

Elden Ring Tarnished Pack DLC will cost 4.99 Euros

Bandai Namco details how to get new Elden Ring classes, weapons, and Torrent skin customizations on PS5, PC, and Xbox.

Jul 2 • 10:52 AM EDT • Technology • rpgsite.net

Downtown Clearwater site cleared for $50M EVO entertainment complex

Developers cleared the site for a $50M EVO entertainment complex in downtown Clearwater, advancing the project toward construction.

Jun 29 • 10:47 AM EDT • Entertainment • tbbwmag.com

Sony’s New Blu-ray & DVD Player Upscales DVDs to Near-HD Quality - Bring Your Old DVDs To Life Again

In a time when streaming services continue to raise prices, fragment content libraries, remove content, and push intrusive ads, many households are rediscovering the reliability and ownership of physical DVDs and Blu-rays. Sony has answered this shift with the release of its latest affordable disc player: the Sony BDP-S1700U. Priced at just $114.99, this sleek […]

Jun 28 • 8:58 AM EDT • Technology • cordcuttersnews.com

Samsung will soon start charging to access its smart home API

Regular users could get caught by Samsung’s new $4.99 monthly charge for individual developers.

Jun 26 • 7:38 AM EDT • Technology • theverge.com

Google’s new rules for the app store will allow alternative billing next week

The new rules are (almost) here.

Jun 24 • 1:36 PM EDT • Technology • theverge.com

The Apple Watch SE 3 is just $199 for Prime Day

The SE 3 was a massive upgrade, and now, it’s at an all-time low price.

Jun 22 • 2:00 PM EDT • Technology • theverge.com

FTC sues leading transgender medical group over pediatric care statements

The Federal Trade Commission (FTC) and four states on Wednesday sued the leading medical organization focused on transgender health for allegedly making false and unsubstantiated claims to parents …

Jun 17 • 2:29 PM EDT • Health • thehill.com

Walleye Weekend brings together fishing, entertainment and family fun

(WFRV)- Since its start as a small fishing festival in 1978, Walleye Weekend has grown into a major event, offering not only competitive fishing but also days of family fun. In this segment, Aaron …

Jun 12 • 11:57 AM EDT • Entertainment • wearegreenbay.com

Early Prime Day Apple deals start at just $14.99, save up to $300

With Prime Day 2026 fast approaching, Apple deals are heating up, and some of the lowest prices on record are available on new releases.

Jun 11 • 3:07 PM EDT • Technology • appleinsider.com

GeForce NOW annual plans drop to $64.99 and $129.99 in summer sale

Ultimate annual plan drops to $129.99 during summer sale. NVIDIA has launched a summer promotion for GeForce NOW memberships.

Jun 11 • 1:54 PM EDT • Technology • videocardz.com

Google's AI Plus plan drops to $4.99 and doubles storage to 400GB, making premium AI finally worth it

It's a good time to give it a try

Jun 8 • 3:15 PM EDT • Technology • androidpolice.com

Google AI Plus gets price drop to $4.99 and storage bump

Google announced today that its AI Plus subscription is getting a price drop to $4.99 per month and now includes...

Jun 8 • 1:21 PM EDT • Technology • 9to5google.com

Welcome to Night Vale host Cecil Baldwin shares his tech pet peeves

Let the man watch movie credits in peace!

May 30 • 12:00 PM EDT • Entertainment • theverge.com

The man behind the legendary MPC, Roger Linn, stays focused with a single browser tab

Only one tab at a time? Madness.

May 23 • 11:00 AM EDT • Technology • theverge.com

Anker's New Prime Charging Station Returns to Low Price on Amazon

Anker's new Prime 3-in-1 Wireless Charging Station has been marked down to $104.99 on Amazon, down from $149.99. This is one of Anker's newest accessories, and Amazon's sale today is a match of the all-time low price. This deal, and many of the others shared below, is being matched at Anker.com, with additional savings applied for members. Note: MacRumors is an affiliate partner with some of these vendors.

May 13 • 10:17 AM EDT • Technology • macrumors.com

This 4.9kg Evolve Bike Undercuts Western Brands by Thousands

It didn't even take a headline-breaking lightweight frame to build a bike that's lighter than anything offered by major Western brands — for thousands less than you'd expect.

May 13 • 4:09 AM EDT • Technology • velo.outsideonline.com

Seattle small business owners devastated by break-ins as commercial burglary cases flood King County courts

Several defendants faced arraignment in King County court Monday on commercial burglary charges, cases that prosecutors said illustrate an ongoing problem devastating small business owners.

May 11 • 12:53 PM EDT • Business • mynorthwest.com

Discord is back after a major outage.

For more than an hour on Friday, many people were having trouble connecting to Discord, with the platform showing a message saying that there were “increased API errors.” Discord confirmed it was investigating issues at 3:08PM ET, and by 6:38PM ET, it reported that all “critical functionalities have recovered for all users.” Updates: Discord says the issues are resolved. [Image: https://platform.theverge.com/wp-content/uploads/sites/2/2026/05/slack-upload-1778269131728.png?quality=90&strip=all]

May 8 • 3:40 PM EDT • Technology • theverge.com

The science behind social media’s peptide obsession

As peptide “stacking” takes over social media feeds, we separate the science from the hype of the Internet’s latest wellness obsession

May 8 • 6:00 AM EDT • Science • scientificamerican.com

Google shuts down Project Mariner

Google might be making room for more features at I/O.

May 6 • 5:21 PM EDT • Technology • theverge.com

Clearwater left in the dark on Scientology-linked entertainment project

Clearwater officials say a $50M EVO project lacks approvals or a formal proposal, despite public messaging that suggests it is moving forward.

May 5 • 8:00 AM EDT • Entertainment • tbbwmag.com

Is Sphere Entertainment Co. (SPHR) Building the Next Global Entertainment Empire?

Ariel Investments, an investment management company, released its “Ariel Fund” Q1 2026 Investor Letter. A copy of the letter can be downloaded here. The fund declined 1.48% in the quarter, underperforming both the Russell 2500 Value and Russell 2000 Value indices, which returned 4.77% and 4.96%, respectively. The S&P 500 posted its worst quarterly decline […]

May 3 • 11:47 AM EDT • Entertainment • finance.yahoo.com

Is Flutter Entertainment (NYSE:FLUT) A Potential Opportunity After Prolonged Share Price Weakness?

Wondering whether Flutter Entertainment at around US$106 per share still lines up with its underlying worth, or if the recent price leaves a margin of safety on the table. The stock has been choppy, with a 4.9% decline over the last week, a 3.3% gain over the past month, and year to date returns of a 51.4% decline, alongside a 1-year return of a 57.3% decline and 3-year and 5-year returns of 45.9% and 48.2% declines respectively. Recent coverage has focused on Flutter Entertainment's...

May 2 • 12:33 PM EDT • Entertainment • simplywall.st

Nvidia's $4.9 trillion chip empire has a Google and Amazon problem

Taking on Nvidia won't be easy, but one analyst said the process of companies diversifying their chips is underway and "irreversible."

Apr 30 • 12:59 PM EDT • Business • businessinsider.com

Centene Foundation Reports $34.9 Million Invested in Community Health, Education and Social Services in 2025

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Apr 23 • 8:00 AM EDT • Health • investors.centene.com

Clearwater $50M entertainment project takes shape

A $50M entertainment project in downtown Clearwater will feature a seven-screen multiplex, dining and attractions aimed at boosting activity along Cleveland Street.

Apr 21 • 11:49 AM EDT • Entertainment • tbbwmag.com

Controversial leader of powerful SF political group steps down

His six-year tenure as executive director was marked by controversy and major influence on local politics.

Apr 16 • 5:37 PM EDT • Politics • sfstandard.com

Amazon launches its slimmest ever streaming device, the Fire TV Stick HD

The more portable HD streaming stick will be available in more than a dozen countries, starting at $34.99 in the U.S.

Apr 15 • 8:50 AM EDT • Technology • aboutamazon.com

How The Narrative Is Shifting For Flutter Entertainment (FLUT) After Guidance Reset And Target Cuts

Flutter Entertainment’s fair value estimate has been reduced from US$207.44 to US$197.35, lowering the modeled upside by about 4.9%. That change aligns with more cautious research following weaker Q4 results and lower 2026 guidance. At the same time, analysts continue to discuss long term execution and valuation questions from both bullish and bearish perspectives. Read on to see how these revised targets fit into the evolving story and what to watch as new data emerges. Stay updated as the...

Apr 11 • 11:11 PM EDT • Entertainment • finance.yahoo.com

Sling TV Launches Sling Essentials – An Unbeatable Price for ESPN, Family Entertainment, & More

Exceptional Value: The new Sling Essentials delivers top-tier sports, family programming, and classic TV favorites for just $19.99 per month.An Unbeatable Price for ESPN: Sling Essentials offers the most cost-effective way to live stream ESPN and ESPN2.Ultimate Flexibility: Subscribers can bundle Sling Essentials with Sling Select for a comprehensive sports and entertainment combo starting at $34.99/month. ENGLEWOOD, Colo., April 09, 2026 (GLOBE NEWSWIRE) -- Sling TV, the most flexible TV stream

Apr 9 • 7:30 AM EDT • Entertainment • finance.yahoo.com

China Star Entertainment (SEHK:326) Valuation After Full Year Results Confirm Widened Losses

Full year results and confirmed pressure on earnings China Star Entertainment (SEHK:326) released full year 2025 results that confirmed earlier guidance, with sales of HK$404.92 million and a net loss of HK$443.76 million, compared with HK$351.93 million a year earlier. See our latest analysis for China Star Entertainment. Despite the widening loss, investor sentiment has been strong, with a 47.58% 1 month share price return and very large 1 year total shareholder return, suggesting recent...

Apr 6 • 3:06 PM EDT • Entertainment • finance.yahoo.com

Mayor Wu proposes $4.9 billion budget as health care costs grow, federal funding dips

Boston Mayor Michelle Wu is proposing a $4.9 billion budget for the next fiscal year, a 2% increase despite big jumps in health care costs and less federal funding.

Apr 6 • 8:51 AM EDT • Health • wbur.org

Billionaire Aloke Lohia’s Indorama Ventures, Blackstone-Backed EPL To Merge Indian Packaging Business In $2 Billion Deal

The proposed merger comes a year after Indorama Ventures—controlled by petrochemicals billionaire Aloke Lohia—bought an initial 24.9% stake in EPL from Blackstone for $219 million.

Mar 30 • 4:56 AM EDT • Business • forbes.com

Anker's New Prime 3-in-1 Foldable Charging Station Hits $104.99 Low Price on Amazon

Anker's new Prime 3-in-1 Wireless Charging Station has been marked down to $104.99 during Amazon's Big Spring Sale, down from $149.99, with no need for a coupon. This accessory just launched last month, and Amazon's sale today represents a new all-time low price. Note: MacRumors is an affiliate partner with some of these vendors. When you click a link and make a purchase, we may receive a small payment, which helps us keep the site running.

Mar 28 • 11:04 AM EDT • Technology • macrumors.com

Progress in reducing child deaths slows as 4.9 million children die before age five

An estimated 4.9 million children died before their fifth birthday in 2024, including 2.3 million newborns, according to new estimates released today. Most of these deaths are preventable with proven, low-cost interventions and access to quality health care.

Mar 17 • 8:00 PM EDT • Health • who.int

Cattle futures higher waiting on direct business

At the Chicago Mercantile Exchange, live and feeder cattle were higher, getting ready for the week’s direct business and Friday’s On Feed report. April live cattle closed $1.97 higher at $235.22 and June live cattle closed $1.82 higher at $233.70. April feeder cattle closed $4.95 higher at $354.80 and May feeder cattle closed $5.07 higher at […]

Mar 17 • 5:00 PM EDT • Business • brownfieldagnews.com

Every Business Owner Needs This Password Manager for Just $24.97

Sticky Password Premium stores passwords safely for businesses, and is on sale for $25.

Mar 15 • 9:00 AM EDT • Business • entrepreneur.com

How Investors May Respond To Flutter Entertainment (FLUT) Earnings Miss Amid New US$250 Million Buyback

Flutter Entertainment’s latest results showed Q4 revenue of US$4.74 billion, up 24.9% year on year but below analyst forecasts for both revenue and earnings per share. On the same day, the company also launched the fifth tranche of its multi‑year share repurchase program, authorizing Goldman Sachs to buy back up to US$250 million of shares to reduce its share count. We’ll now examine how Flutter’s Q4 earnings miss against analyst expectations reshapes the previously optimistic investment...

Mar 14 • 9:23 PM EDT • Entertainment • simplywall.st

$3.5K to $4.9M: See 21 latest business-related, apartment, acreage, land sales

See a list of property sales in Onondaga County other than residential homes.

Mar 9 • 7:07 AM EDT • Business • syracuse.com

Evolent Health (NYSE:EVH) Reports Q4 CY2025 In Line With Expectations

Healthcare solutions company Evolent Health (NYSE:EVH) met Wall Street’s revenue expectations in Q4 CY2025, but sales fell by 27.5% year on year to $468.7 million. The company’s full-year revenue guidance of $2.5 billion at the midpoint came in 4.9% above analysts’ estimates. Its non-GAAP profit of $0.08 per share was 62.7% above analysts’ consensus estimates.

Feb 24 • 4:46 PM EST • Health • finance.yahoo.com

Slash Software Costs: Upgrade Your Business Toolkit With Microsoft Office 2021

Get lifetime access to essential productivity apps for just $34.97.

Feb 19 • 9:00 AM EST • Business • entrepreneur.com

Anti-system voters are turning on Trump over Epstein

And young Republicans are particularly enraged.

Feb 16 • 6:00 AM EST • Politics • vox.com

UFC's first Paramount+ fight card averages nearly 5 million views

UFC's first fight card on Paramount+ averaged nearly 5 million views, making it the streaming platform's largest exclusive live event since it launched in March 2021. UFC 324 from Las Vegas on Saturday averaged 4.96 million for the main card and saw a global household average of 7.18 million, according to Adobe Analytics and Channel Partner Data. Adobe Analytics and Nielsen also said Saturday's card reached more homes than any other live UFC event in nearly a decade across linear, broadcast and streaming.

Jan 26 • 6:32 PM EST • Sports • sports.yahoo.com

UFC Makes Paramount+ Debut Averaging 4.96M Live Streaming Views

The UFC’s heavily promoted debut on Paramount+ delivered an average minute audience of 4.96M viewers on Saturday night, per data from parent company Paramount Global on Monday. The company says that UFC 324, which saw Justin Gaethje defeat a bloody Paddy Pimblett in the main event, marked the biggest exclusive live event on Paramount+ to-date. According …

Jan 26 • 4:00 PM EST • Sports • sports.yahoo.com

Penguins Acquire Big Defender From Avalanche

Jan 20 • 2:09 PM EST • Sports • thehockeynews.com

Stream Smarter for $14.97: Unlimited Entertainment for Busy Entrepreneurs

Learn why entrepreneurs are ditching multiple streaming subscriptions.

Jan 10 • 9:00 AM EST • Entertainment • entrepreneur.com

The new Ultraloq smart lock uses both your face and your palm to let you in

Xthings is launching a smart lock that reads your palm and a new camera that works on HaLow Wi-Fi for extended range at CES

Jan 4 • 9:00 PM EST • Technology • theverge.com

Legion Go systems joins MSI and ASUS with Xbox Full Screen Experience

Legion Go update enables Xbox Full Screen Experience Legion Space version 1.3.4.9 is rolling out with Windows Full Screen Experience (FSE) compatibility,

Dec 27, 2025 • 7:00 AM EST • Technology • videocardz.com

Stardew Valley – Nintendo Switch 2 Edition now available

Stardew Valley – Nintendo Switch 2 Edition is now available via Nintendo eShop for $14.99. Users who own the Switch version can upgrade to the Nintendo Switch 2 Edition via a free “Upgr…

Dec 25, 2025 • 11:03 AM EST • Technology • gematsu.com

Ikea has made some of its Matter-compatible smart home devices even cheaper.

As the cost of some electronics continues to skyrocket, Ikea has dropped the price of several of its new smart home accessories. The Myggspray motion and Klippbok water sensors are now down to $7.99 from $9.99, and while the three-pack of the colorful two-button Bilresa remotes launched in the US for $19.99, they’re now $14.99. [Image: Two of Ikea’s new Matter-compatible smart home sensors and its two-button remote are now cheaper in the US. https://platform.theverge.com/wp-content/uploads/sites/2/2025/12/ikea_matter.jpg?quality=90&strip=all]

Dec 23, 2025 • 10:14 AM EST • Technology • theverge.com

TKL advises Onza Entertainment on its sale to Culture Cap7

The law firm TKL Abogados has advised Onza Entertainment, a leading independent production and distribution company in the Spanish audiovisual sector, on its sale to the private equity fund Culture Cap7 Fund I. Onza is responsible for some of the most renowned titles in the national audiovisual industry, such as the series El Ministerio del […]

Dec 19, 2025 • 5:37 AM EST • Entertainment • iberianlawyer.com