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Families and healthcare providers reunite at Nebraska Medicine's annual NICU reunion
Families and healthcare providers shared hugs, appreciation and gratitude; celebrating the bond between them.
Michigan State QB Alessio Milivojevic talks after loss to Nebraska
Check out what MSU QB Alessio Milivojevic had to say after the loss to Nebraska.
Michigan State Injuries Pile Up In Nebraska Loss
Cam Edwards left on a cart and he was not the only Spartan down Saturday. #GoGreen
Three instant takeaways from Nebraska football’s win at Michigan State
Nebraska football (4-0) started conference play with a dominating win at Michigan State (2-2), 31-14, on Saturday, Sept. 26. After sweeping the non-conference slate for the third straight year, NU improved to 4-0 for the first time in 10 seasons. The Huskers earned their first win in East Lansing since 2012.
Report Card: Defense leads the way for Nebraska football at Michigan State
Nebraska (4-0, 1-0) passed its first real test of the season in East Lansing, forcing turnovers and using a big-play offensive attack to work past Michigan State, 31-13.
Mount Dora restaurant says nearby roundabout construction is cutting off business
A Lake County restaurant owner said nearby construction is keeping customers away and cutting into sales; that's why he's asking for help.
Can you be healthy if you eat ultra-processed foods? I asked a dietitian
UPFs are linked to a range of health problems. But no-one seems to be able to agree why.
Group mocks Nebraska Gov. Jim Pillen on $2.5M no-bid contract with $5,000 business grants
Nebraska Gov. Jim Pillen, after criticism from opponents for the state budget, now faces mockery from a new group over the $2.5 million no-bid contract he steered to a lobbyist.
Nebraska vs Michigan State
Big Ten play! I am probably wearing a suit and tie by now. I wonder if I’ll get to watch the game in any way. I bought a Starlink mobile just to get internet at this place we’re going to. I hope it works. HOW TO WATCH Time: 4:00pm CST Location: Memorial Stadium, Lincoln, NE Surface: Hellas Turf […]
Game Thread: Michigan State Vs. Nebraska
Hang out with your TOC friends while enjoying some Spartan football
Scientists believe avian keratin disorder is cause of fishhook beaks in Alaska chickadee population
The virus is causing “the highest concentration of (visible) deformities ever recorded in a wild bird population.”
How ex-staffers’ allegations of hostile behavior by Peltola might affect Alaska’s key U.S. Senate race
Alaska political commentators said in interviews that the accusations appear to have left many of Democrat Mary Peltola’s supporters unswayed as she seeks to unseat Republican Sen. Dan Sullivan.
House Democrats plan vast oversight of Trump administration. Impeachment is an option
Rep. Jamie Raskin (D., Md.), who is in line to become the chairperson of the Judiciary Committee, characterized the issues involved as “gargantuan.”
Gilmour builds perfect midfielder including Pirlo and McTominay
Napoli and Scotland international Billy Gilmour was asked to create his ultimate midfielder, picking elements from Andrea Pirlo, Scott McTominay and more.The player sat down with DAZN to go through th...
Singing River Health System announces first recipients of Clinical Courage Award
The Singing River Health System announced the first recipients of the Clinical Courage award. The award is presented by the Professional Development and Education Department, recognizing nurses who advocate for their patients, speak up, ask questions, and do what’s right. The recipients are Heather Mitchell and Hannah Talley. Singing River says they are proud to recognize both for the award...
Alaska to launch second funding round for Rural Health Transformation Program
The federal program is meant to produce long-term transformation, but strict rules are leading to short timelines.
Afognak takes majority stake in Alaska trucking, fuel companies
Afognak Native Corporation acquired a majority stake in three Alaska trucking and fuel companies, expanding its commercial portfolio.
Tre White’s Return Gives Kansas Basketball Another Experienced Piece
Tre White’s Return Gives Kansas Basketball Another Experienced Piece
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Small business owners and aspiring entrepreneurs are invited to attend the September Small Business RoundTable at Bladen Community College, featuring a practical discussion on one of the most important challenges facing entrepreneurs: finding the right funding for a business.The September RoundTable, “The Funding Toolbox,” will be held Monday, Sept.28, from 5:30–7 p.m. in Building 14, Room 135, at Bladen Community College.Sponsored by the Bladen Community College Small Business Center (SBC) and the Elizabethtown-White Lake Area Chamber of Commerce, the event will bring together experts familiar with the Small Business Center and SSBCI programs to help participants better understand the funding resources available to entrepreneurs and small businesses.Rather than focusing on one type of financing, “The Funding Toolbox” will explore a variety of funding tools and resources that may be available depending on a business's stage, needs and goals. Participants will have an opportunity to learn about available programs, how they work, what lenders and funding organizations look for, and how business owners can prepare to seek financing.Topics will include:Funding options for startups and existing businessesLoans and other financing resourcesSSBCI-supported funding opportunitiesHow to determine which funding option may fit your businessWhat lenders and funding organizations look forPreparing financial information and documentationResources available to help businesses become funding-ready“The Funding Toolbox” is designed for both aspiring entrepreneurs and established small business owners who are considering starting, expanding or investing in their businesses.The Small Business RoundTable provides an informal setting where local entrepreneurs can learn, ask questions, share experiences and connect with business-resource partners. The program is part of the ongoing efforts of the Bladen Community College Small Business Center and the Elizabethtown-White Lake Area Chamber of Commerce to strengthen and support small businesses throughout the community.The September RoundTable is free and open to the public.For more information or to register, contact the Bladen Community College Small Business Center at 910-879-5572.Event DetailsWhat: Small Business RoundTable – The Funding ToolboxWhen: Monday, Sept.28, 2026 | 5:30–7 p.m.Where: Bladen Community College, Building 14, Room 135Cost: FreeSponsors: Bladen Community College Small Business Center and Elizabethtown-White Lake Area Chamber of Commerce
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Anthropic's AI for Science Program has awarded the UC Santa Cruz team $50,000 in API credits to fund the development of an automated wavelength-calibration algorithm for astronomical spectra.
Quick hitters: O-line health, safety depth and Dan Campbell’s first days in Detroit with Glenn
Allen Park — Detroit Lions coach Dan Campbell and quarterbacks coach Mark Brunell met with the media on Friday. Here are the noteworthy items from those conversations. Healthier up front, banged up in the back It’s good news, bad news on the injury front. First, the offensive line is going to be far closer to full strength with starters Blake Miller (knee) and Christian Mahogany (hip) on track to return to the lineup. That provides stability the offense lacked against Buffalo, particularly at right tackle, where backup Larry Borom allowed 11 quarterback pressures and committed a trio of penalties. Subscribe However, with that same unit, veteran Ben Bartch (foot) is likely to miss Sunday’s matchup with the Jets. The left guard competition that’s been ongoing since May has effectively been whichever option is healthy that week. In the back end, safety Thomas Harper (ankle) is also unlikely to be available on Sunday. That leaves the team precariously thin at the position following Avonte Maddox going on injured reserve this week. Christian Izien is expected to get the start alongside Chuck Clark. “Izzy's been working a lot back there and had a full week,” Campbell said. “And he's gotten a ton of work this week, a ton of reps, full-speed reps. ‘This is what you're going to do, this is the calls’ and just dousing him with full-speed reps and he's done a good job this week.” Safety depth is the bigger concern. The team is expected to count on some combination of Jalen Mills, who signed to the practice squad on Monday, Bishop Fitzgerald, the undrafted rookie poached off the Steelers’ practice squad on Tuesday, and rookie cornerback Keith Abney, who doesn’t have experience at safety. “I'll say this about Abney, man, for a rookie, he's a pretty dang smart, conscientious, aware football player that's got a ton of room to really take off,” Campbell said. “…He's young. He's another one, he just needs reps and reps. But, if we need it, that'll be a guy who may have to go in for us.” You can check here for the full injury report, with game designations, later this afternoon. Reflecting on the past Responding to comments made by Jets coach Aaron Glenn this week, Campbell reflected on his earliest days with the Lions, before the coaching staff had been fleshed out and it was just he and Glenn at the facility working through what they wanted things to look like. “It was just he and I in the lab,” Campbell said. The coach said the two would fill the whiteboard that remains in current coordinator Kelvin Sheppard’s office top to bottom with notes about philosophy, coaching style, team identity and the type of players they wanted to target. “He looks different than me,” Campbell said. “I'm taller, I'm whatever. He's quicker. All these different things, man, but we're really the same. I mean we're so much the same. And he's the defensive version, I'm the offensive version. He was my right hand man. …It was fun, man. Those were good days.” Campbell said it was one of the best and worst days of his life when the Jets hired Glenn to be their coach. “AG means the world to me,” Campbell said. “He's one of my dearest friends because I know what he's made of. “…It's because you know you're losing a little piece of you. That's what he meant to me and to us. So, that's hard.” Traits under center A couple of weeks back, Sheppard noted that Brunell had identified Saints quarterback Tyler Shough as the best prospect at the position ahead of the 2025 draft. On Friday, Brunell confirmed his evaluation and explained what he looks for when studying a young quarterback. Here’s the full answer: “Young quarterbacks, you have to look at everything, you know? I look at guys coming out of college just like I look at any free agents that we might be looking at, or guys that we might add to our roster. Do they take care of the ball? Are they on time? How is their decision-making? How are their feet? “It's tough because you look at a college player, you don't understand what they're trying to do offensively, what their reads are, but you can identify when a guy is accurate, obviously, and when the ball's getting there on time. If there are a lot of interceptions, it raises a red flag. And I think with a lot of the spread offenses of what you're seeing, when you see a young player and they're running some pro concepts and he's having to make protection calls, and he's getting the right play out of the run game, and when there's a lot on his plate and he's executing it very well, and he's managing all of that, that really jumps out at you. It’s really hard to find. “That's one thing we saw with Luke Altmeyer. He had a lot of experience. We call it, ‘Hey, he's playing quarterback.’ And what does that mean? It's not just completing passes. It's getting guys lined up, getting the right play, getting the protection call right, just fixing some problems, being able to progress (through reads). And there's still some young guys out there that can do that at a high level, which is good to see.” Regarding Altmyer, who competed for the team’s backup job through the offseason and currently resides on the practice squad, Brunell acknowledged physical development slows once the season starts, because there aren’t reps to go around. However, there’s still extensive mental development that’s ongoing. “The key for him is approach the game as if you're the starter, mentally,” Brunell said. “And that's really all you can do. Approach the game as if you're the starter and be good in the (class)room. You come in alongside Jared (Goff), and you come in alongside Josh (Dobbs) and (do) whatever they need. And if you get an opportunity to talk to Luke, he'll tell you he does have a lot of responsibilities besides just getting donuts for us on Saturday. “For him, it's mentally staying focused, and even though there's really no chance this Sunday of him playing, he has to approach it as if he's taking the first snap and playing the whole game. So what's our game plan? What are our checks? What are we anticipating? And then during the game, we keep him involved as far as looking at coverages and pressures. And so, really, for him, it's just a mental game. And for now, that's all we can do.” Reason for more zone The Lions have significantly increased their usage of zone coverage on defense this season. I asked Campbell if that was a reaction to their personnel or driven by the focus to generate more turnovers, given it can be easier to produce interceptions when you can keep eyes on the quarterback while playing zone. “I think it was a little bit of both,” Campbell said. “We just felt like this would suit us a little bit better up to this point, and then be disruptive and get takeaways, which worked well Week 1. We had two (opportunities) last week against Buffalo we weren’t able to get, but they’re there.” I followed up by asking how much the combination of heavy blitzing with the back end playing zone has contributed to some of the early-season coverage woes, since adding extra players to the pass rush means leaving the coverage short-staffed. “I mean, it’s challenging, and that’s why a lot of the things we’ve done in zone, for the most part, have been to reduce that stress level back there,” Campbell said. “But that also requires the front getting there. And if you don’t get there, we already kind of talked about that, but there (has to be) a trust there.” The alternative, Campbell explained is sending four and it taking longer for the rush to get home, which can create different problems for a defense. “You can bleed yards,” Campbell said about the strategy. “It gets a little longer and it’s dink-and-dunk and run after catch. …So, we do what we think is right by what we feel like our personnel (does well). But also the game plan, who you’re going in to play, the matchups, their offense. “We’re not stuck on one way.” Detroit Football Network is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
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Pioneer of China NewCo model sued in US over trade secret misuse, double-dealing
A legal feud unfolding in New York is putting a spotlight on the work of a business development veteran who is credited for pioneering one of biopharma’s hottest dealmaking mechanism: the China “NewCo” model. In a lawsuit originally filed in New York state court and recently moved to federal court, China’s Lepu Medical Technology has alleged that biopharma business development consultant Su Zhang, who was hired to help shop its GLP-1 weight-loss candidates to Western partners, engaged in corporate double-dealing and trade secret leaks. According to the complaint, while acting as Lepu’s primary dealmaking liaison for a group of obesity and metabolic disease drug candidates, Zhang was secretly double-dipping as the acting chief business officer for a direct competitor, BrightGene Pharmaceutical. “She never adequately disclosed the role, never sought Lepu’s consent, and never proposed any safeguard,” Lepu alleged in its complaint, which was filed in July after Zhang’s consulting firm, CoDevCo, sought certain transaction-based success fees from its angry customer through an arbitration process in Singapore. Lepu, the parent company of Lepu Biopharma, has asked Zhang to pay back its $500,000 retainer and disgorge all benefits she received during the alleged breaches of fiduciary duty, plus other damages and relief. The company has also requested the court grant injunctions to protect Lepu’s trade secrets. The ill-fated partnership officially kicked off in December 2024, when Lepu tapped CoDevCo as its “exclusive business development mechanism” to identify collaborators for the company’s drug candidates. According to Lepu’s complaint, Zhang personally negotiated and signed the agreement as managing director for CoDevCo, which used her home address. Before the Lepu deal, Zhang made a name following a short stint as the global head of business development for Hengrui Pharmaceuticals. It was during her tenure that Hengrui signed a landmark deal granting exclusive rights for a portfolio of GLP-1 assets to Hercules, which was at that time newly established by a group of private equity and venture capital firms. In addition to the regular upfront and milestone payments, Hengrui also gained an equity stake in Hercules, which later became Kailera Therapeutics. The Hengrui-Hercules deal opened a new paradigm, where a Chinese biopharma company spins off certain early-stage assets to investors for further development through the creation of a new company abroad. The “NewCo” model quickly came into vogue as it allows Western investors to access high-potential assets originating from China at an early stage while giving the Chinese licensors an opportunity to reap long-term benefits through equity stakes in the new firms. The NewCo model proved its value when Kailera staged a record-breaking $625 million IPO on Nasdaq this April, merely two years into the Hengrui deal. Related Kailera CEO 'knew we were in a good spot' before obesity biotech's record-breaking $625M IPO On her LinkedIn page, Zhang described her work at Hengrui as “[b]uilding team and capability from the ground up,” forming NewCo and major pharma partnerships worth billions of dollars. Lepu clearly wanted that kind of track record to help boost its own cardiometabolic portfolio, which includes a range of assets for obesity, Type 2 diabetes, fatty liver disease and muscle preservation during weight loss treatment. “Lepu’s pipeline is very valuable, but only if Lepu could secure the right international partner to expand into the overseas market during the available commercial window,” the company argued in its complaint. The Chinese biotech said it had little knowledge of U.S. laws, customs or business practices in the business development field, and therefore “needed to rely entirely” on the expertise of Zhang and her team as the firm’s first engagement of a U.S.-based BD consultant. “Zhang’s dominating influence on the business development strategy is further evidenced by the fact that she personally controlled the business-development communications on behalf of Lepu with potential partners,” Lepu said in its complaint. After entering the deal, Zhang introduced Lepu to her four associates. According to Lepu’s version of events, all of them were allegedly employed at different time points to perform similar jobs at other Chinese companies that Lepu described as its competitors, while having access to Lepu’s confidential information. As such, Lepu described Zhang’s team as “a roster of individuals whose primary professional loyalty, by virtue of their concurrent full-time employment, ran to Lepu’s competitors.” As well as the specific examples set out in the case, a look at Lepu’s deals over the period suggests Zhang may have been involved in at least one transaction. During their partnership, Lepu, through its subsidiary Shanghai Minwei Biotechnology, also out-licensed its GLP-1/GIP/FGF21 agonist MWN105 to a NewCo called Sidera Bio in the fall of 2025. The deal included an upfront and near-term payment of $35 million, up to $1.01 billion in milestones, and a 9.99% stake in the Danish startup. It seems likely that Zhang facilitated the Minwei deal given that Lepu is on record as having used CoDevCo as its “exclusive business development mechanism.” The big shock for Lepu came in the form of a news article on June 25, 2025. The article, reporting on phase 2 data for BrightGene’s GLP-1/GIP receptor agonist BGM0504, identified Zhang as acting chief business officer of the Lepu rival. Blindsided by her association with BrightGene, Lepu confronted Zhang in July 2025. “Lepu was given assurances that there was nothing to be concerned about and told that Zhang would explain the matter to Lepu,” Lepu alleged in its complaint. “Zhang never did.” Lepu claimed that Zhang had the motive and opportunity to steer potential prospective partners toward BrightGene or other competitors. Later, in February 2026, one of Zhang’s associates joined BrightGene as the vice president for global business development, according to the complaint. Around the same time, Lepu sent written demand letters asking Zhang to account for her BrightGene role, identify what confidential data were shared with the rival firm, and provide any conflict-of-interest or firewall policies during the engagement. According to Lepu, neither CoDevCo nor Zhang answered the questions in their responses. Related Novo vs. KBP: How a $1.3B deal turned into a fraud accusation and an international legal fight In a motion to dismiss filed with the U.S. District Court in the Eastern District of New York on Sept. 4, Zhang’s legal team argued that Lepu’s agreement was signed with CoDevCo, and that an employee of the contractor does not owe fiduciary duties to the client. In its complaint, Lepu said: “That CoDevCo was the contracting entity does not insulate Zhang from personal liability for duties she personally undertook and personally breached.” Taking the argument one step further, the defending party argued that the consulting agreement “does not create a fiduciary relationship even between CoDevCo and Lepu; instead, it identifies CoDevCo as an independent contractor retained to market Lepu’s business to potential western partners.” Although CoDevCo was Lepu’s exclusive business-development contractor, there were no terms stipulating that the consulting firm should serve only Lepu, Zhang’s lawyer noted. As to Lepu’s claims that Zhang misappropriated trade secrets, the defendant argued that Lepu authorized the use of the information so Zhang’s team could perform their service per the agreement. In a rebuttal filed on Sept. 11, Lepu’s lawyer set out why they believe the Chinese biotech satisfied New York law’s misappropriation definition by alleging that the defendant used a trade secret “in breach of a duty or through improper means.” As an alternative to dismissing the suit, the defendant suggested the action should be stayed pending outcomes from the arbitration of a separate case in Singapore. While NewCo pioneer Zhang is defending her business arrangements, momentum behind the NewCo trend has continued unabated into 2026. Through August, Chinese biotech assets have spurred 15 NewCo deals this year, according to local trade publication PharmaDJ.
Can the Left Make America Fun Again?
Hi friends, I’ve got a piece in The New York Times today about how collective joy — participatory, youthful, anti-corporate — can defeat Trumpism and transform our lives. The basic argument is that politics used to be embedded in communal life: dances, sports leagues, union halls. As that infrastructure disappeared — and more of everyday life was atomized and privatized — politics became something broadcast at people rather than something they did together. NYC-DSA and Zohran provide another model, where socials and face-to-face organizing are tied to a fight vs the corporations that fenced off so much of the good life. Rebuilding that kind of collective fun, I argue, could help bring young people back into politics and, by redistributing America’s wealth, make everyday life more joyful. I would super appreciate it if you’d read the piece, share it, or post comments on it. Thank you! p.s. FYI, Opinion writers don’t get any say over their headlines! More Take action to support the fight of licensed deck officers at Alaska Tanker Company and Overseas Shipholding Group to win a first union contract. This is one of the most important, and underreported, unionization campaigns in America: these workers have a huge amount of power over domestic energy distribution and maritime supply chains, and they’re still without a contract two years after having voted overwhelmingly to unionize. Please sign the public petition here, and if you’re an academic you can sign this support letter.
Arsenal's scouting and failure to strengthen up front
Richard asked: Are the reports of the sporting director not using the club scouts true? Alex: It is true that Andrea Berta is not as outgoing or as open as Edu, but he still involves others in the work he is doing. It might not be as much as his predecessors, but Berta does still lean on the scouts for some of the work he needs done.
Arzana raises $4.3M to automate factory paperwork
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First in entrepreneurial excellence: FSU celebrates local businesses at inaugural Impact Awards Gala
The Entrepreneurial Impact Awards Gala provided a formal night out for Fayetteville’s business community. The event took place at the Rudolph Jones Student Center on Thursday, Sept. 10. Photo by GFBJ. Fayetteville State University (FSU) and the Fayetteville-Cumberland Regional Entrepreneur and Business HUB (FSU HUB) came together to celebrate Fayetteville’s business community. The two organizations rolled out the blue carpet at the Rudolph Jones Student Center for their inaugural Entrepreneurial Impact Awards Gala held on Thursday, Sept. 10.The gala honored outstanding entrepreneurs and business leaders who demonstrate excellence, foster growth and inspire the next generation of innovators within the FSU and broader business community.FSU HUB Director Dr. Tamara Colvin was able to highlight that this new milestone was a great way to show local success stories, not just tell.“That one-stop shop that’s across the street, we never promised that everyone would be successful, but what we did promise was access. Four years ago, we opened up an entire ecosystem: counseling, capital, contracts, connections, certifications,” shared Colvin. “I want to thank the judges who took up hard work for choosing tonight’s honorees. That’s never an easy task when the whole region is full of people worth recognizing at the HUB. We practice what we preach: Res Non Verba: Deeds, not words.” A few of the inaugural recipients of the awards shared their statements with the Greater Fayetteville Business Journal.STUDENT ENTREPRENEUR Boolean Wiring LLC, Esean Rose, owner “I am truly honored and grateful to receive the Student Entrepreneur of the Year Award. I want to thank Fayetteville State University, the judges and everyone who has supported me throughout this journey. This award represents more than recognition for where Boolean Wiring is today. To me, it represents the potential of where we are going. I am excited about growing the company, creating jobs, serving our community and building something that can have an impact far beyond Fayetteville.”VETERAN-OWNED BUSINESS SpeediPrint Inc., Dazrell Fleming, owner “I’m honored to accept the Veteran-Owned Business Award on behalf of the entire SpeediPrint team. A special thank you to Dr. Tamara Colvin for creating this opportunity through the Entrepreneurial Impact Awards, and to my mentor, Mr. Julius Cook, whose guidance during the Boots to Business program truly paid off. This recognition reflects the hard work of my staff and the trust our customers place in us every day — I’m grateful to serve this community and excited for what’s ahead.”MULTI-GENERATIONAL EXCELLENCE BJL Construction, Cleopatrice Robinson, president“This award is especially meaningful because we are more than a business — we are the continuation of a family legacy built through faith, hard work, craftsmanship, integrity and service. I gratefully acknowledge my grandfather, Deacon Benjamin “BJ” Lacy, Jr., whose example helped establish the foundation upon which our family’s entrepreneurial legacy was built. I also honor my father, the late Dr. Wilson Lacy, former president of BJL Construction. Working alongside him was both an opportunity and an education. He taught me that a business’s reputation had to be earned on every project through honesty, excellence, quality and service. As the current president, I recognize that I did not arrive at this moment alone. I stand on the shoulders of those who came before me, and I am sustained by those who continue to walk beside me.”MICRO BUSINESS Maybridge Development, LLC, Latisha Perkins, owner “I accept this award with so much pride and a whole lot of gratitude. First and foremost, I want to thank my higher power for continuing to guide me and give me the strength to keep going.When I first started this business and moved here to Fayetteville, I had no clue what I was getting myself into. This business has turned me every which way but loose, and I definitely had some moments where I was ready to just pack it up and head back to Georgia. I want to thank my Maybridge team, my village, The Hub, the FCEDC team and all the people and organizations here in Fayetteville who have believed in me and Maybridge and helped us get here.”COMMUNITY IMPACT Greater Life of Fayetteville, Georgeanna Pinckney, CEO & executive director “We are deeply honored to be recognized by FSU and the FSU HUB with the Community Impact Award presented to Greater Life of Fayetteville. I am especially grateful for this recognition because it tells us that you see what we do – and, more importantly, why we do what we do. Our commitment is to serve, empower and create meaningful opportunities for youth and families in our community. Most importantly, we give God first and foremost all the glory. We thank Him for giving us the wisdom, strength, vision and unity to continue doing this great work in our community.” SMALL BUSINESS OF THE YEAR Crowder Trucking LLC, Carlos & Valerie Morrison Crowder, owners “I want to thank God for always keeping his hands on Crowder Trucking. I’m truly honored and grateful to receive the Small Business Award from the FSU HUB. Running a small business is not always easy. There are long days, difficult decisions, unexpected challenges and plenty of moments when you have to remind yourself why you started. But there are also incredible moments like this one that remind you that the hard work is worth it,” shared Valerie Morrison Crowder.OTHER WINNERS INCLUDE: Alumni Entrepreneur - The Two-Six Project, Grant Bennett, founder and president Fayetteville State University Faculty Award - Dr. Christy Swinson Emerging Business Award - Genuine Luxury Beauty Salon Legacy Award - Gillis Farms Inc. Industry Titan of the Year - Eaton Corporation Entrepreneur of the Year- Let Me Cater to You, Chef Judith Cage, owner
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State police investigating after John Deere tractor stolen from Western Pennsylvania business
Police said an unknown-aged male wearing a mask, a hat, jeans and a hoodie stole the tractor that was parked outside.
Advanced Health Tech Research Continues to Protect Astronaut Health
Advanced health research, including ultrasound scans, blood tests, and exercise studies, using the latest technology in microgravity was on Thursday’s schedule for the Expedition 75 crew. The orbital residents also continued their ongoing cargo operations and maintenance tasks aboard the International Space Station.
Bobby Webster says there will be “natural basketball …
Bobby Webster says there will be “natural basketball …
Meet the Muse mascot, Jolly. Who doesn't love a little guy?
Jolly joins a long line of mascots tasked with making companies feel more approachable.
Judge orders White House to lift Trump's ban on CNN, MS NOW and Politico — but reporters say they were still denied access
The news outlets asked the court for an immediate hearing after some of their journalists reported being turned away despite the ruling.
CPD continue search for suspect after robbery at High Street business over the summer
Columbus police are asking for the public’s help identifying a suspect accused of threatening an employee during a robbery at a business on the city’s north sid
Military Spouse Commission Holds First Meeting, Identifies Top Issues
The commission, which President Donald J. Trump established via executive order Aug. 3, is tasked with advising and assisting the president on policies that affect military spouses and families.
New task force aims to address aging small business owners
The Employee Ownership Task Force will look at how the state can expand employee ownership opportunities, especially as thousands of business owners in Vermont get ready for retirement.
EU science policy wonks debate prospect of stronger ties with Canada
Europe’s research and innovation sector has started asking questions on how European Commission President Ursula von der Leyen’s offer to make Canada “the first associate member of the EU” would actually work in practice, and who will get to shape priorities in a transatlantic relationship that is getting stronger. The Commission says it wants “a new model of association” under which the EU and Canada will aim to develop “a shared space” to face ongoing challenges. “Working in close coordination with our member states and the European Parliament, we will aim to create a new form of partnership that has not existed until now, building the closest imaginable form of association with a partner outside Europe,” a spokesperson told Science|Business.Locked in an escalating trade war with US President Donald Trump, who has repeatedly talked of annexing Canada, Prime Minister Mark Carney has been looking east, but full EU membership was never in play. Taking the floor a day after von der Leyen’s proposal, he agreed to strengthen ties under “an alliance of the future” but reined in enthusiasm on the new label. He also suggested expanding Canada’s involvement in the Erasmus+ student mobility scheme, to which it currently has limited access, and the next iteration of Horizon Europe. Canada joined the present Horizon Europe in 2024, but only contributes to collaborative projects.Neither side has detailed the next practical steps in developing this new relationship. “I think nobody at the moment truly knows how this will work,” said Michael Browne, chief executive and founder of Crowdhelix, a global collaborative network that connects players in research and innovation. “It’s more of a statement of intent for closer collaboration, which requires legislative frameworks and approval processes, which have not started.”Kurt Deketelaere, secretary general of the League of European Research Universities, said von der Leyen’s pitch to Canada is “politically significant, but the legal content still has to be negotiated and constructed.”Mattias Björnmalm, secretary general of the Cesaer university group, agreed that she had only opened “a political door” to Canada, as “associate membership does not come with a predefined set of rights in the EU institutions.”Not only does this status not currently exist as a legal category in the two treaties that set up how the EU functions, but the Commission president cannot unilaterally create a new category of EU membership.According to Deketelaere, Article 217 of the Treaty on the Functioning of the EU, which allows the bloc to make association deals with non-EU countries involving reciprocal rights and duties, is “the most obvious existing legal basis for building a much deeper EU-Canada relationship.”Getting universities involvedNo matter how this new cooperation takes shape, Liviu Matei, who heads the School of Education, Communication and Society at King’s College London, hopes to see universities involved in discussions from an early stage.“Its primary motivations, entirely justifiably, are political and geopolitical,” he said. “In the area of higher education, however, restricting the initiative to political and geopolitical considerations would limit the scope of cooperation and lead to distorted frameworks and counterproductive implementation.”It is all the more important since academic interests on the two sides of the Atlantic are “neither identical nor fully aligned,” Matei added. “This is not insurmountable; it simply requires work to articulate the details of this privileged cooperation, including its governance and funding frameworks, as well as its substantive content in education and research.”Related articlesCanada looks to deepen research and education links with the EUZaharieva hopes for a Horizon Europe deal in 2026Canada might participate in European Research Council schemes, for example, which was not on offer in the present Horizon Europe association agreement. But “there would have to be something in it for the EU,” Browne said. “They don’t want to be funding projects outside of the EU where intellectual property is going to sit outside of the EU. There has to be some kind of transfer of knowledge.”But access to funding will not by itself resolve all the practical difficulties of working together, said Björnmalm. “For researchers and students, these include visas and residence arrangements, recognition of qualifications and study periods, and the conditions for pursuing a research career across borders,” he said. “For universities, there is scope for more predictable access to shared laboratories, computing and research data, and stronger support for joint doctoral training and long-term institutional partnerships.”Linda Doyle, provost and president of Trinity College Dublin, said Europe should strive for the “closest possible expression” of this new political alliance. “If Europe is serious about recovering its voice and its place in the world, it needs to be strongly allied with countries who share its values and its vision for a stable, rules-based, peaceful world.”
China warns Arizona not to develop political ties with Taiwan
The warning came in multiple letters obtained by KJZZ from China's L.A. consulate asking Arizona Gov. Katie Hobbs to protest the opening of the Taipei Cultural and Economic Office in Phoenix.
Ask the Expert: How AI Is Changing Health Care
GREENVILLE, S.C. (WSPA) — Artificial intelligence is front and center in many conversations right now—whether you love it or hate it—some doctors argue it can be used to benefit the healthcare system greatly. As part of the “Ask the Expert” series, in partnership with Bon Secours St. Francis, 7NEWS spoke with a doctor to learn […]
The Daily Mauling: 9/24/26
Kansas Jayhawks News Tre White seems to have an extra year of eligibility. Michael Swain if 247 writes about what it might mean for Kansas Speaking of guys from least year’s team wanting one more year of eligibility, here’s the latest on the Melvin Council, Jr Through the Phog writes that there’s a men’s basketball […]
Struggling Lesbian Bar Drops Saturday Mask Rule — and Its Business Problem Gets Worse
A struggling Massachusetts lesbian bar made one night a week mask-optional in hopes of attracting more customers. Instead, the change unleashed hundreds of angry comments, boycott calls and even a com...
Fall weather, community service signal Grizzlies season is near
Memphis Grizzlies basketball season is closing in as players return to the city and participate in community events.
Sporticast: It’s Fat Bear Week. Where Are the Chicago Bears?
On the 590th Sporticast episode, hosts Scott Soshnick and Eben Novy-Williams discuss some of the biggest sports business stories of the week, including Sportico‘s recent list of the highest-paid players in the NFL. First, however, they talk about Fat Bear Week. The viral creation from Alaska’s Katmai National Park & Preserve allows people to vote …
Calling all current and future scientists: Kiel is the place to be this week
This week, Kiel has become a meeting place for science in Europe. Researchers, school pupils, young scientists and members of the public are coming together through a series of major events led or co-organised by Kiel University.At the centre of it all are around 150 of Europe’s most talented young researchers, aged 14 to 20, who have travelled to Kiel from nearly 40 countries for the 37th European Union Contest for Young Scientists (EUCYS). Running from 22 to 27 September, the European Union’s flagship competition for young scientists brings together winners of national science competitions to present around 100 original research projects across fields ranging from engineering and computer science to medicine, environmental research and the social sciences. The winners will be announced at the Award Ceremony on Saturday.For Kiel University, hosting EUCYS is both an honour and a natural extension of a much longer story. Germany’s northernmost comprehensive university has invested for many years in supporting young scientific talent and bringing research into dialogue with society. The Kiel Science Factory gives school pupils opportunities to experience research first-hand, while programmes such as Rent-a-Scientist send researchers directly into local classrooms. Major annual public events including Kiel Week and the European Researchers’ Night take science beyond the campus through talks, exhibitions and hands-on activities.That long-standing commitment has increasingly taken on a European dimension – and this week, many of those efforts are coming together.One of the foundations for this success is the European Researchers’ Night (ERN), which celebrates its tenth edition in the Kiel region this year. The initiative is funded through the Marie Skłodowska-Curie Actions, with Kiel University developing the successful EU proposals and securing the funding, while regional partner KielRegion coordinates the many activities on the ground. Together with research institutions, schools, companies, local authorities and civil society, they have built ERN into a major platform for public engagement.Over the years, Kiel’s ERN programme has grown far beyond a single evening into a whole “Science Summer”, beginning with “Science Shopping” in spring and culminating tomorrow, 25 September, in Science Day.“We have developed a wide range of public engagement formats, often together with the other research institutions in the region, the city and regional authorities, schools, companies and civil society,” says Eckhard Quandt, Kiel University’s vice president for research, academic infrastructure and transfer. “Over the past decade, we have increasingly taken this commitment to the European level.”That combination of European funding expertise and strong regional partnerships also helped Kiel University take the next step. Drawing on its experience with ERN and its European networks, including the SEA-EU University Alliance, the university brought together Brest in France and Split in Croatia for a successful bid to the EU’s new Science Comes to Town initiative. Throughout 2026, the three cities are serving as Europe’s first Science Ambassadors, with more than one thousand activities bringing science into schools, public spaces, cultural venues and everyday life.EUCYS is perhaps the clearest example of how Kiel University is using Science Comes to Town to create new connections between major European initiatives. From the outset, the university deliberately planned the contest for the week of European Researchers’ Night and opened the EUCYS exhibition to the wider Science Day audience. Tomorrow, that means thousands of visitors can encounter the next generation of scientific talent first-hand, while the young researchers themselves gain a much bigger public stage.“Because we opened EUCYS up for European Researchers’ Night, there will be a lot of people actually visiting the exhibition,” says organiser Stefanie Altemark of Kiel University.“We wanted Europe’s most talented young scientists not only to compete with one another, but also to become visible to the wider public. At the same time, people in Kiel will have the opportunity to see what the next generation of scientists are already capable of,” says Quandt.“We’ve shown over the last years that science is a big part of Kiel, and it’s always been the goal to not only show that to people in Germany, but also to show it to people all over Europe. Thanks to Kiel University’s expertise in European funding programmes, we have been able to turn that ambition into reality,” says Sünje Fock, who is coordinating the Science Summer at KielRegion.The model is characteristic of Kiel University’s approach: combining European funding expertise and international networks with strong regional partnerships to give major initiatives greater reach and visibility.This year also marks the 30th anniversary of the Marie Skłodowska-Curie Actions, giving Kiel University the special opportunity to welcome Vanessa Debiais-Sainton, Head of Department for the Marie Skłodowska-Curie Actions at the European Research Executive Agency, to Kiel tomorrow. Her visit brings together two priorities that have shaped Kiel University’s work over the past decade: supporting researchers and bringing science closer to society. Debiais-Sainton emphasises how closely the two are connected: "For thirty years, the Marie Skłodowska-Curie Actions (MSCA) have given more than 150,000 researchers the chance to pursue their dreams and open up new fields. Doctoral Networks and Postdoctoral Fellowships give them the freedom to move, to connect, to train and to follow their curiosity across borders, sectors and disciplines. But excellence cannot live only in laboratories. Researchers’ Night takes science out of the lab and into the city, to the families, the schoolchildren and the curious minds who will become the next generation. Kiel shows what that looks like at its best. That is the MSCA promise: open science, open borders, open doors."For Kiel University, these activities are not separate endeavours. They are part of a broader understanding of academic excellence in which outstanding research, talent development, international cooperation, knowledge transfer and engagement with society strengthen one another.“For me, one of the most important lessons from the past decade is that scientific excellence, knowledge transfer, talent development and engagement with society cannot be treated as separate tasks,” stresses vice president Quandt. “They reinforce one another.”That philosophy is also reflected in Kiel University’s current bid for Germany’s Excellence University status. The designation is part of Germany’s national Excellence Strategy, which provides substantial long-term funding to selected universities to strengthen internationally competitive research and their overall institutional development. A successful outcome would provide new opportunities to build on what has already been created: deepening international cooperation, creating more opportunities for knowledge exchange and public engagement, and extending the university’s reach across the region and beyond. “If we are successful, it would allow us to take what we have built in Kiel considerably further – including expanding our networks and transfer activities beyond the region and increasingly across the Baltic area,” says Quandt.This week’s events offer a glimpse of what that could mean in practice: a university using its research strength, European expertise and regional partnerships to create opportunities for scientists at every stage of their careers while making science more visible, accessible and exciting to the wider public.
Alaska Science Forum: Mapping tsunamis, building trust
While taking a quick shower before her son’s fourth birthday party on Dec. 26, 2004, tsunami scientist Elena Troshina heard the phone ring. Deciding it was worth jumping out, she picked it up — with kids, you never know.
Warren demands Trump officials explain removing a ban on interference in census data
Democratic Sen. Elizabeth Warren asked Trump officials to explain why the Census Bureau's parent agency cut a ban on political interference from its scientific integrity policy, as NPR first reported.
'Please stay' or 'must leave'?
With Martin O'Neill taking stock of his future following three defeats in a row, you asked you whether the Celtic manager should stay or go. Any manager has to take some responsibility for these shabby displays. With Jota, Alistair Johnson and Yang back plus the next transfer window for the suits to back him, O'Neill will be a bigger legend than he already is.
Opinion: Kobach's politics of tragedy underline our nation's immigrant crime double standard
When a native-born American commits a murder, we generally understand the concept of individuality perfectly well. We ask about motive, rage, domestic conflict, ideology, drugs, mental illness, opportunity or the peculiar facts of that person's life.