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Mayor Sarno joins Health Commissioner Caulton Harris to bring greetings at Department of Elder Affairs Hispanic Heritage Month Luncheon at the Ray Jordan Senior Center
Mayor Domenic J. Sarno was honored to join Health & Human Services Commissioner Helen Caulton Harris and the Springfield Department of Elder Affairs team on Friday to bring greetings at a special Hispanic Heritage Month Luncheon celebration with our seniors at the Raymond A. Jordan Senior Center. This special luncheon is a collaboration between the Raymond A. Jordan Senior Center and the North End Senior Center and celebrated Hispanic heritage and the valued contributions of our senior community. Members of the senior centers were invited for a vibrant day of music, dance, food, and culture. El Morro bakery provided lunch to members by our kind and dedicated Elder Affairs staff. Grupo Erupxion performed live music. Special thanks to host/emcee Joanna, the Springfield Department of Elder Affairs and the Council on Aging team for bringing us together to celebrate the beautiful mosaic of our Springfield. Mayor Sarno states, “We are always proud to celebrate the vibrancy and beautiful mosaic that is our Springfield community. On behalf of the City of Springfield, we celebrate and welcome the continued contributions of Hispanic Americans toward our community, including their cultural heritage, public service, and entrepreneurial spirit. I commend and appreciate this collaboration between the North End Senior Center and the Ray Jordan Senior Center to host this special luncheon in celebration of Hispanic Heritage Month for all our seniors to enjoy. ‘Que tenga buena salud y Dios te bendiga’ – Good health and God Bless.”
Newcastle Creates New Senior Role After Major Recruiting Changes
Newcastle United’s football operation has undergone significant change over the past year, with Ross Wilson overseeing another stage of the club’s restructuring following the departures of experienced figures including Steve Nickson and Andy Howe. Jack Ross has now confirmed that he has become Newcastle’s Assistant Sporting Director, effectively placing him directly beneath Wilson in the […]
Will Ipswich stay in the Premier League?
Cameron asked: Will Ipswich stay in the Premier League this season? Also, what are your opinions on summer transfer business? Graeme: Obviously I can't say for certain that Town will stay up, but I am confident they will.
Business pitch reveals deeper ties between Sneed, consultant
Plus: Helene exposed gaps in health care; Stitching together Queens and Elon; Saint-Maximin fuels Charlotte FC's offense; CMS cabinet officer charged with DWI; Union calls for changes after airport worker death
Teladoc Health (TDOC), Why Is It Back In The Spotlight?
Teladoc Health (TDOC) just announced a change in its legal leadership. Longtime Chief Legal Officer Adam Vandervoort plans to step down in early November, and current senior legal executive Jonathan Dorfman is set to take over. At around US$6.09 per share, Teladoc Health has seen its 90 day share price return fall about 28%, and the 1 year total shareholder return decline roughly 26%. This suggests momentum has been fading even as management refreshes its legal leadership and continues to...
High-level Lithuanian delegation visits Miami to strengthen links in tech and business
In the European Union, Lithuania stands out as the country that issues the most licenses for fintech companies and as a growing hub for diverse tech ventures.
Peyton and Peter’s Power Hour: Professional athletes and their political opinions
What’s more important in fandom: an athlete’s play or what they say?
How Scientists Can Shape Public Opinion Over A.I. Risks
Artificial intelligence workers may have leverage to make the world safer.
Lawyer who left corporate does AI training to supplement his practice
Ron Masciantonio left his job at Five Below and started his own legal practice. He says AI training is great for filling in the gaps between clients.
After Taxi Driver Deaths, Union Pushes Mamdani for Health Fund
Several New York City cabbies were recently found dead in their cars. A taxi union is seeking to revive a fund that would provide medical screenings, disability insurance and other benefits.
Opinion | Sherry Turkle says, with AI, we've entered 'a state of emergency'
The MIT professor’s new book examines the hazards of ‘pretend empathy.’
Opinion: It’s time to put political ads on pause and think.
A cloud has descended over the United States of America. I’m not talking about an actual weather system, of course, but a phenomenon that has shaken the nation to its core. As long as you are near any screens, you will find yourself a target for waves of mass messaging campaigns. That’s right, it’s everyone’s...
Opinion: Duplicate billing fix can lower cost of health care
Addressing duplicative billing in healthcare is critical for New England’s Medicare beneficiaries -- and for taxpayers.
Maria: owner of her own business
Testimony by Maria Pires, Brazil, at the event: ‘A Path to Regeneration: 35 Years of the Economy of Communion’, held in Buenos Aires in May 2026.
NIO Stock Jumps Overnight As $2.4B Nio Power Deal Brings Geely Into Its Battery Swap Business
The companies are also discussing wider use of battery swapping across Geely-related vehicles, though plans remain preliminary.
Game Recap: What went most wrong in Texas A&M’s loss at LSU?
KBTX senior Texas A&M sportswriter Travis L. Brown and sports director Tyler Shaw break down what went wrong and what is the Aggies most urgent fix before they face Arkansas next Saturday.
Iran's Supreme Leader Khamenei has no 'specific' health issues: President
Masoud Pezeshkian said despite US claims senior cleric was injured, he has held 2 meetings with Ayatollah Mojtaba Khamenei, and calls him 'completely healthy' | Anadolu
Wes Moore’s AI framework is missing a healthcare pillar
Opinion: Healthcare should be a central focus of AI governance in Maryland, writes Sreedhar Potarazu.
Xavi gets first win as Netherlands boss, Denmark beat Wales
The Netherlands gave Xavi Hernandez his first win as head coach with a 2-1 Nations League victory over Serbia in Belgrade on Sunday, while Denmark saw off Wales.In League B, Austria made it two wins from two as David Affengruber, Junior Adamu and Carney Chukwuemeka scored in a 3-1 win over Kosovo in Vienna.
Erling Haaland and Kylian Mbappé battle for international scoring milestones
thenews2.com/Depositphotos Erling Haaland and Kylian Mbappé lead world scoring Erling Haaland and Kylian Mbappé remain among international soccer’s leading scorers in 2026. Haaland is Norway’s career goals leader, while Mbappé holds the same distinction for France. As of September 27, Haaland has scored 64 goals in 56 senior appearances for Norway. Mbappé has scored 67…
QB Drew Sheridan sees system fit, special atmosphere at Pitt
Pittsburgh had Dearborn (Mich.) Divine Child quarrterback Drew Sheridan on campus for an unofficial visit on Saturday. The junior signal-caller saw the Panthers defeat Bucknell. He had been to campus in the past, but this gameday visit allowed him a different experience than his previous trips.
Can Science Solve Smoke Taint?
With wildfires an increasing problem worldwide, Chris Boiling investigates the solutions to smoke taint. Read the latest wine news & opinion on wine-searcher
Glucosamine, a popular joint supplement, linked to faster Alzheimer’s progression
A large health-record analysis found that glucosamine use was associated with a 25% higher likelihood of mild cognitive impairment progressing to dementia. Lab experiments suggest the popular joint supplement may intensify an abnormal sugar-tagging process in the Alzheimer’s brain, although researchers say clinical trials are needed to determine whether it actually causes harm.
Glucosamine, a popular joint supplement, linked to faster Alzheimer’s progression
A large health-record analysis found that glucosamine use was associated with a 25% higher likelihood of mild cognitive impairment progressing to dementia. Lab experiments suggest the popular joint supplement may intensify an abnormal sugar-tagging process in the Alzheimer’s brain, although researchers say clinical trials are needed to determine whether it actually causes harm.
Arsenal to sign striker as ‘priority’
Arsenal are looking to sign a striker as a priority for the coming transfer windows, with Eli Junior Kroupi among the options being considered.Photo by Eddie Keogh/Getty ImagesFabrizio Romano reports ...
Liverpool Monitoring Boca Junior’s Tomas Aranda
Could Tomas Aranda be another exciting young prospect to join the Liverpool ranks.
Opinion: A proven way Pa. can bring down healthcare costs
Opinion: High hospital prices are a leading driver of both high and rising health care costs and of insurance premium growth.
Opinion: Remembering Hurricane Helene, recognizing climate change, regardless of politics
Two years after Hurricane Helene devastated Asheville, the author argues leaders are ignoring climate change.
Logan Health nurses union ratifies new contract with major across-the-board raises
Nurses at Logan Health in Kalispell say their newest union contract includes "life changing" pay raises that benefit both tenured and new nurses.
Guest opinion: Partisan judges bad for Montana businesses
Partisan money threatens to infect our courts with fickle partisan politics, and that’s bad for business in Montana.
FUTURE-HEALTH
Future Health – A Global Initiative by Abu Dhabi convened Ministers, senior government representatives, and global health leaders in New York on the sidelines of the 81st Session of the
Women Sluggers Are No Longer in a League of Their Own
As a group of players from an all-women’s baseball league in the 1940s and ’50s gathered at a recent reunion, the future of women’s baseball looks bright again.
Families and healthcare providers reunite at Nebraska Medicine's annual NICU reunion
Families and healthcare providers shared hugs, appreciation and gratitude; celebrating the bond between them.
Mental health & safety concerns brought up by neighbors after shooting by bar downtown
MVDs: Oklahoma Edition
You don’t unceremoniously sink the Sooner Schooner without a total team effort. But even then some Bulldogs are bound to stand out above the crowd for their efforts. Those dandy ‘‘Dawgs are your MVDs, the Most Valuable Dawgs from Georgia’s 41-13 victory over Oklahoma. Offense: Talyn Taylor. Taylor’s 4 catches for 110 yards represented a […]
Two senior FBI agents ousted over investigation into alleged harassing calls to wife of Trump adviser Stephen Miller
Two veteran FBI agents overseeing counterterrorism operations in the nation’s capital have been removed from their jobs and reassigned over the handling of an investigation involving Katie Miller, the conservative podcaster and wife of senior White House adviser Stephen Miller, according to two people familiar with the move.
Cavan Sullivan makes USMNT history with first start
By Ari LiljenwallCavan Sullivan's rapid rise has reached the international stage.The 16-year-old Philadelphia Union homegrown midfielder was named to Mauricio Pochettino's starting XI during Saturday'...
San Antonio's Michelle Beadle joins Matthew Berry for new Roku sports show
The two-hour talk series will stream live and free on the Roku Sports Channel Monday through Friday from 11 a.m. to 1 p.m. CST.
Full Court Magic Episode 35: Major Takeaways Before Media Day
New head coach Sean Sweeney faces immense pressure to instill discipline as Jeff Weltman bets big on roster continuity and a veteran reunion to escape postseason stagnation.
Union: CDC Lost a Third of Its Workforce In One Year
Under Trump 2.0, the country's premier public health agency has been "zombified."
Zaniolo out of Italy squad for Nations League games
Udinese man Nicolò Zaniolo has left the Italy training camp due to an injury, so will not feature in Nations League games against Turkiye or France.The forward had been one of the strong candidates t...
OU-Georgia: Live updates, TV details
Availability: The final Southeastern Conference gameday availability report dropped ahead of kickoff with junior defensive lineman David Stone listed as a gametime decision and senior linebacker Kip Lewis set to
Opinion | Genova: Three political platforms, three visions
American politics includes competing approaches to the economy, energy, immigration, abortion, taxation, transgender rights and the structure of our government. Comparing the published programs of the Democratic Socialists of America (DSA), the Democratic Party and...
Scientists reveal surprisingly easy exercise that may boost your mood in just 10 minutes
A University of Tsukuba study found that a slow 10-minute jog boosted attention, self-control and mood in young adults by activating the prefrontal cortex.
Opinion: Liberal Democrats reflect profound political change in Britain
British politics today is fracturing into multiple parties, no longer 2 or even 3
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Viking Derby Victory: Nusa Announces Himself Against Denmark
Antonio Nusa’s creative flair and Ørjan Nyland’s crucial saves propelled a rising Norwegian side past their rivals, signaling a new era of dominance behind Erling Haaland’s brilliance.
Player status report, presented by Orlando Health: Orlando City SC at Philadelphia Union
Here is the Player Status Report, presented by Orlando Health, for Saturday's away match at Philadelphia Union
OPINION: The importance of critical political media analysis
OPINION: I spent the back-half of my summer watching as young Wisconsinites fell victim to deceptive political information. Now, I caution others not to do the same.
Opinion: Prop. 40 will make California’s health care challenges even worse
A one-time tax on top earners creates a funding cliff, leaving the safety net with deep fiscal holes.
Opinion | ‘The MAGA Flag Is in Tatters’
This week in politics: Midwest realignment and what’s next for conservatives.
Video: Opinion | Will the Midterms Bring a Political Realignment?
This week in politics: Midwest realignment and what’s next for conservatives.
Opinion: Prop. 40 is the key to preserving health care access and saving lives
Passing this ballot measure forces the super-rich to fund emergency rooms, preventing disastrous statewide closures.
Brentford's Summer Signings Graded After Unbeaten Premier League Start
Brentford brought in five senior players during the summer and remain unbeaten after five Premier League games. Some of the newcomers have already made a considerable impression.
Saindon, Thombs Seek House Seat in Warren, Union, Hope
Residents of Warren, Union, and Hope will have a new state representative in December.
MotoGP Makes More Leadership Changes
Boardroom draws from F1, the NFL, UFC and the Premier League Liberty Media continues to reshape MotoGP’s front office, appointing new executives with backgrounds from a diverse range of sports and entertainment properties such as Formula 1, the NFL, the Premier League, and UFC. The series announced four senior appointments this week, coming after Carlos Ezpeleta stepped up to Deputy CEO in August, and Liberty’s own CEO Derek Chang was appointed President of the MotoGP Group earlier this month. [
Helenio
“Internazionale one, Independiente nil. Corso has scored! Six minutes into extra time!”The Intercontinental Cup, or World Cup, had existed for four years. The competition was essentially created b...
SSM Health Dean Medical Group nurses at outpatient centers vote to unionize
MADISON (WKOW) -- SSM Health Dean Medical Group nurses at ten outpatient centers in the Madison area have voted to unionize with SEIU Wisconsin.
New Business: Lithermans Limited Brewery adds pinball; NH Doughnuts coming to Londonderry
A brewery in Concord has a new offering for those of all ages: pinball machines. For those 21-plus, the machines are equipped with cup holders for a pint of favorites
Family of paralyzed Marine vet allegedly shot by migrant speaks out as health issue could delay testimony
Jimmy Friesenhahn, a Marine veteran paralyzed in a San Antonio shooting, faces a health crisis before trial, his family told Fox News Digital.
Weekly Portland women’s sports wrap up (9/25)
Weekly Portland women’s sports wrap up (9/25) presented by Rebound Orthopedics and Neurosurgery and Rivermark Community Credit Union.
Oklahoma School of Science and Mathematics opens free enrollment for STEM-focused students
The Oklahoma School of Science and Mathematics is accepting applications for its tuition-free residential program, offering high school juniors and seniors a unique STEM education experience.
QC Senior Expo brings free health screenings, services to local older adults
QC Senior Expo: Free health checks, haircuts offered at Golden Leaf Center More than 50 vendors gathered at the Golden Leaf Banquet Center in Davenport for the fifth annual QC Senior Expo, providing Quad Cities seniors with free vaccines, health screenings, and personal care services under one roof. #Davenport #QuadCities #QCA #KWQC #SeniorCare #Healthcare #LocalNews
Missing 'Widow's Bay'? Consider the Matthew Rhys pipeline.
To be obsessed with "Widow's Bay" is to be obsessed with Rhys, the man of the hour and — in my humble opinion — the "it" man of television.
‘Other so-called improvements might even backfire’
Opinion, comment and editorials of the day
Spurs' Dylan Harper Rookie Card Sells for Record $2.88 Million
Dylan Harper's one-of-one Rookie Debut Patch Autograph sold for $2.88 million, smashing the previous public record for a card featuring the Spurs guard.
Let’s fix healthcare costs before the socialists try to do it
Senior fellow Dr. Clifford Porter proposed a series of 11 federal reforms aimed at lowering healthcare costs and increasing patient control.
Atlético-MG defender comments on relationship with Domínguez
Having come through Atlético-MG’s youth academy since the age of 12, center-back Vitão reached the peak of his transition to professional football by scoring his first goal for the senior team at ...
CMMC nurses in Lewiston vote to form union
The situation prompted Gov. Janet Mills earlier this week to call on Prime Healthcare to reinstate the nurses fired or suspended.
Sports quiz of the week: Fury v Joshua, Zinedine Zidane and England’s run
Have you been following the big stories in boxing, football, NFL, golf, college sports, darts and rugby union?
Coding a Community for Women in Computer Science
For Colgate University students interested in computer science, finding a community can be just as helpful as developing technical skills. Women in Computer Science (WCS) provides students with opportunities to create meaningful connections, develop professional skills and support other women in the computer science department. For senior and WCS co-president Frankie Williams, being a computer...
Can the Left Make America Fun Again?
Hi friends, I’ve got a piece in The New York Times today about how collective joy — participatory, youthful, anti-corporate — can defeat Trumpism and transform our lives. The basic argument is that politics used to be embedded in communal life: dances, sports leagues, union halls. As that infrastructure disappeared — and more of everyday life was atomized and privatized — politics became something broadcast at people rather than something they did together. NYC-DSA and Zohran provide another model, where socials and face-to-face organizing are tied to a fight vs the corporations that fenced off so much of the good life. Rebuilding that kind of collective fun, I argue, could help bring young people back into politics and, by redistributing America’s wealth, make everyday life more joyful. I would super appreciate it if you’d read the piece, share it, or post comments on it. Thank you! p.s. FYI, Opinion writers don’t get any say over their headlines! More Take action to support the fight of licensed deck officers at Alaska Tanker Company and Overseas Shipholding Group to win a first union contract. This is one of the most important, and underreported, unionization campaigns in America: these workers have a huge amount of power over domestic energy distribution and maritime supply chains, and they’re still without a contract two years after having voted overwhelmingly to unionize. Please sign the public petition here, and if you’re an academic you can sign this support letter.
Scotland’s New Era Under Pocognoli: Bold Choice Sparks Fresh Hope
Scotland kicks off a new UEFA Nations League campaign this weekend, and for the first time in over two decades, a foreign manager is in the dugout. Sébastien Pocognoli, a 39-year-old Belgian with barely two years of senior coaching experience, replaces Steve Clarke after his own team’s group-stage exit at the World Cup. It’s a […] The post Scotland’s New Era Under Pocognoli: Bold Choice Sparks Fresh Hope appeared first on HEAVY.
Should FSU bring back Jimbo Fisher? History offers a cautionary tale
Florida State is reportedly weighing a Jimbo Fisher reunion. We studied 18 coaches who made a second run with a school. Almost none were successful.
Trump admin using AI to deny medical care for seniors in disastrous experiment
Vendors rolling out AI have an "incentive to deny as many claims as possible."
Community: A coffee club reunion, club luncheons, Rotary officers and a party for Orion queen
Here's what local organizations are doing...
Opinion: New Hampshire deserves science on kratom
Jenn Mercier argues against New Hampshire's potential kratom ban, highlighting existing studies and the need for botanical vs synthetic distinction.
Opinion | Young Democrats Are Putting the Party Back in Politics. It’s Working.
Fun, free events communicate a larger goal: that everyday people should be able to afford a joyful life.
Business schools and the leadership divide
Despite years of progress on diversity, women remain under-represented in senior business school leadership. Removing the barriers limiting advancement is becoming a strategic priority for institutions seeking stronger leadership, broader talent pipelines and more inclusive decision-making
AI Presents Science with a ‘Ship of Theseus’ Problem
Opinion | AI can replace each part of the scientific process, leaving the enterprise recognizable but devoid of human judgment.
Wellness kiosk in the Memorial Union makes it convenient for OSU community to buy basic healthcare products, STI tests and more
A new vending machine in the basement of the Memorial Union on Oregon State University’s Corvallis campus is now stocked with a variety of over-the-counter healthcare products, from cortisone to contraceptives to COVID tests.
Editor Score Predictions: Nebraska vs. Michigan State
Husker football is entering the start of their season 3-0, with their next game coming up this Saturday against Michigan State. The Daily Nebraskan sports senior staff share their thoughts and predictions for the game.
Walking to end stigma: NAMI Greater San Antonio hosts annual mental health walk
NAMI Greater San Antonio hosts NAMIWalks San Antonio and a Resource Fair Saturday at Morgan’s Wonderland, 8 to 10 a.m. University Health sponsors; SAPD Chief Jesse Salame and advocates join to fight stigma.
This San Antonio veteran is building a tech company — and she wants other vets to do the same
SIH holds health fair in Marion, Ill.
Junior high students got an up-close look at what it’s like to work in the medical field at a fair in Marion, Illinois.
Milan senior fair connects residents with health, wellness resources
The Milan community has wrapped up a day focused on senior health and services.
How one Oregon politician plans to use his power to keep the Trail Blazers in Portland
Oregon's senior U.S. senator is calling on other NBA owners to make sure Tom Dundon doesn't relocate Portland's franchise.
Jonathan Fortney, Dan Costa honored by American Geophysical Union
Astronomy and astrophysics professor Jonathan Fortney receives 2026 Whipple Award and ecology and evolutionary biology professor Dan Costa named 2026 AGU Union Fellow
Montana State Employee Health Plan Costs Change Under New Union Agreement
The State of Montana Benefit Plan faces rising medical and prescription drug costs. The state says its self-funded plan is expected to see nearly double-digit h
Chicago health officials warn of additional possible measles exposures at Union Station
MPA, Unions Back `Motion Picture, Television, and Entertainment Revitalization Act'
The bipartisan legislation would establish federal tax credits for qualifying film, television, and visual effects (VFX) projects that are produced in the United States
Conflict mapping research group founded by OSU researcher wins national award for open science
The American Geophysical Union has awarded the 2026 Open Science Recognition Prize to the Decentralized Damage Mapping Group, an international research team co-founded by Oregon State University Professor Jamon Van Den Hoek and postdoctoral scholar Corey Scher.The prestigious award is in recognition of DDMG’s contributions of satellite mapping data of regions beset by war, conflict or natural disasters to the public sphere, particularly to aid in humanitarian response and provide journalists with up-to-date information.
San Antonio-area Week 5 high school football schedule
There are plenty of good matchups on the slate this weekend as teams begin their march to the Texas high school football playoffs. The headliner is a showdown between Boerne and Alamo Heights.
How Ryan Richter sparked Philadelphia Union's stunning turnaround
By Charles Boehm“Richter’s at the wheel, at the wheel. Richter’s at the wheel!”Sports Illustrated Stadium emptied quickly after the Philadelphia Union’s 3-1 win over Red Bull New York on Aug...
Computer science student embraces opportunity and aims high as Bone Scholar
Senior computer science major Neer Jain is one of 14 Illinois State University students named Robert G. Bone Scholars for 2026-27.
Rising prescription and supplement use poses health risks for seniors
Older Americans are increasingly taking multiple prescription medications and dietary supplements. Although the prevalence of potentially major drug-drug interactions has declined slightly, more than 1 in 5 older adults are potentially at risk, according to a USC-led study published September 24 in JAMA.
Unionized doctors reach tentative deal with Allina Health after four-day strike
The agreement follows a four-day strike, believed to be the first by inpatient doctors at a private-sector hospital in U.S. history.
‘I didn’t notice any tangible benefits from the union’
Opinion, comment and editorials of the day