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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?

Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.

Jun 14 • 3:14 PM EDT • Technology • newsletter.semianalysis.com

Justin Trudeau skipped Canada World Cup opener because girlfriend Katy Perry performed at US game

Former Canada Prime Minister Justin Trudeau attended the United States’ World Cup opener against Paraguay rather than his own nation’s game vs | KCBS All News 106.9FM and 740AM

Jun 14 • 12:17 PM EDT • Entertainment • audacy.com

Side-by-side size comparison of Samsung's upcoming foldable lineup leaked

A new leak reveals alleged screen protectors for Samsung’s Galaxy Z Flip 8, Z Fold 8 and Z Fold 8 Ultra, suggesting a wider, shorter Fold 8 design and clearer differentiation across the foldable lineup. While expectations are high that the Fold models will bring some significant changes, the same cannot be said for the Flip.

Jun 13 • 9:30 PM EDT • Technology • notebookcheck.net

AMD goes after Apple Macbook Neo, says 15 out of 20 top PC games do not even work on Apple system

Ryzen 5 220 comparison uses a 2025 Hawk Point processor.

Jun 13 • 12:07 PM EDT • Technology • videocardz.com

Halo: Campaign Evolved Comparison Shows Difference Between Xbox Series X And Ally X

Based on early pre-release footage, of course

Jun 11 • 2:30 PM EDT • Technology • purexbox.com

Video: Kingdom Hearts 3 Nintendo Switch 2 vs. PS5 vs. Steam Deck graphics comparison

Watch a brand new Kingdom Hearts 3 graphics comparison video for the Nintendo Switch 2, PS5, and Steam Deck versions.

Jun 10 • 2:48 PM EDT • Technology • nintendoeverything.com

Entertainment Highlights: Marketing director makes directorial debut with ‘Circle Mirror Transformation’

Discover the transformation of J. Bailey Burcham's perspective on community theater as he directs 'Circle Mirror Transformation' at Parish Players.

Jun 10 • 2:35 PM EDT • Entertainment • vnews.com

Trump, 79, Desperately Trying to Avoid One Comparison as Health Declines

The near octogenarian doesn’t want to seem old.

Jun 10 • 12:48 PM EDT • Health • thedailybeast.com

Lincoln Parish and the Long Road From Band Member to Auteur Producer

After helping shape Cage the Elephant’s early sound, Parish found a second act in Nashville studios, where he now works with emerging artists as a producer, mixer, and mentor. For a lot of fans, Linco...

Jun 10 • 11:34 AM EDT • Entertainment • yahoo.com

What voters need to know about BREC’s millage renewal

The millage funding BREC's maintenance and operation of parks, facilities and recreation services throughout East Baton Rouge Parish is heading to the ballot for renewal, with early voting set to begi… Already an INSIDER? Sign in. Already an INSIDER? Sign in

Jun 9 • 3:52 PM EDT • Business • businessreport.com

Google teams up with Paris Hilton to showcase Android and AI app building

In what is now her second big partnership around Android, Google has named Paris Hilton as an “Icon in Residence”...

Jun 9 • 1:40 PM EDT • Technology • 9to5google.com

Here’s what’s impacting the Ascension land market

Industrial expansion and retail demand are the main drivers in Ascension Parish’s land market as residential developers become more selective, according to Peter Laville with Elifin. Laville says Ascension’s strongest momentum is currently tied to industrial growth in Geismar and along the west bank, where major projects such as Hyundai Steel are creating demand for […]

Jun 9 • 1:01 PM EDT • Business • businessreport.com

Who's building and who's buying in Greater Baton Rouge

A look at the latest property transactions and issued permits in East Baton Rouge Parish. Los Angeles investor Andrew Fay purchased an industrial property at the corner of South Choctaw Road and … Already an INSIDER? Sign in. Already an INSIDER? Sign in

Jun 8 • 2:58 PM EDT • Business • businessreport.com

Baton Rouge brick company rebrands through Ascension acquisition

Cocreham Brick has rebranded as The Brick Company and acquired Gonzales-based Economy Brick, a move that expands the Baton Rouge company’s footprint into Ascension Parish and strengthens its position in Louisiana’s building materials market. The company, which has operated in Louisiana under the Cocreham Brick name for more than 75 years, announced the rebrand and […]

Jun 8 • 2:54 PM EDT • Business • businessreport.com

Politics, Pubs, Parades, and the Parish: Joan Quigley

Quigley reflects on her upbringing in an Irish-American family in Jersey City, her early involvement in civic activism

Jun 7 • 10:52 PM EDT • Politics • insidernj.com

Simone Biles reveals health scare, calls it one of the "scariest" moments of her life

Team USA gymnastics great Simone Biles has not competed in nearly two years, last featuring at the Olympic Games in Paris.

Jun 7 • 8:46 AM EDT • Health • olympics.com

Fecteau orders Maine House investigation

The committee last met in 2021 when it voted to reprimand former Paris Rep. John Andrews, who at the time was a Libertarian, for refusing to wear a face covering on the House floor.

Jun 5 • 10:16 AM EDT • Politics • spectrumlocalnews.com

West Ham’s Mohamadou Kanté attracts Ligue 1 interest

Mohamadou Kanté (20) could leave West Ham United this summer and a return to his native France is an option, as per a report from The Athletic. Kanté joined West Ham from Paris FC back in 2024. La...

Jun 5 • 5:20 AM EDT • Sports • sports.yahoo.com

AC Milan’s Alessandro Longoni set to join PSG

Paris Saint-Germain are reportedly on the verge of finalising the signing of young Italian goalkeeper Alessandro Longoni (18), according to L’Équipe.A member of AC Milan’s reserve team and an Ita...

Jun 4 • 6:25 AM EDT • Sports • sports.yahoo.com

Monetary compensation becomes key sticking point in Iran deal as Trump bristles at comparison to Obama agreement

One of the key sticking points remaining in negotiations between the US and Iran centers on monetary compensation, as President Donald Trump is eager to strike a deal that will be viewed as superior to a prior agreement inked during the Obama administration, a US official familiar with the talks told CNN.

Jun 3 • 3:07 PM EDT • Politics • cnn.com

Paris match a chance to grow rugby league

Wigan Warriors' trip to Paris to face Catalans Dragons will be a perfect stage to showcase rugby league to a wider audience, says Oliver Partington.

Jun 3 • 12:02 PM EDT • Sports • sports.yahoo.com

Video: Rayman Legends original vs. Retold remake graphics comparison

Check out a graphics comparison for the brand new Rayman Legends Retold remake, showing how it compares to the original.

Jun 2 • 9:20 PM EDT • Technology • nintendoeverything.com

What's being built, bought and planned in Ascension Parish

Here are the latest property transactions, issued permits and upcoming business-related events in the parish. Issued permits A new construction permit for a 12,000-square-foot office and warehouse building on Copperhead Road in Geismar. The project is valued at $400,000 with RW Construction Inc. as the contractor. A demolition permit for the demo of the gym […]

Jun 2 • 6:45 PM EDT • Business • businessreport.com

Straight Talk with Ascension Chamber President and CEO Donnie Miller

Ascension Parish is in the midst of a significant growth period, fueled by billions of dollars in industrial investment, rapid population gains and a diverse business landscape. As businesses navigate workforce shortages, infrastructure demands, rising operating costs and new opportunities tied to major projects, the Ascension Chamber of Commerce is working to help employers stay […]

Jun 2 • 5:08 PM EDT • Business • businessreport.com

Pope Leo plays tennis religiously as part of an Augustinian devotion to sports and spirituality

PARIS (AP) — When Pope Leo XIV was elected last year and it emerged that he was a tennis player, his love of the sport was quickly celebrated during an audience with top-ranked Jannik Sinner.

Jun 2 • 4:03 AM EDT • Sports • wral.com

PSG in Talks for Yan Diomande Amid Bayern, Liverpool Interest

Paris Saint-Germain accelerates efforts to sign 19-year-old RB Leipzig winger Yan Diomande.

Jun 2 • 12:06 AM EDT • Sports • sports.yahoo.com

One fat helped pancreatic cancer grow while another cut disease in half

A surprising new study suggests that when it comes to pancreatic cancer, the kind of fat you eat may matter more than how much. Researchers found that oleic acid—the main fat in olive oil and several other common foods—sped up tumor growth in mice predisposed to pancreatic cancer, while omega-3-rich fats from fish oil dramatically slowed disease development.

Jun 1 • 8:00 PM EDT • Science • sciencedaily.com

I went to a Roland-Garros watch party, felt like a launch for US Open

The first Roland-Garros NYC Experience promised to transport fans to Paris as the French Open's official watch party. It kinda felt like the US Open.

Jun 1 • 5:19 PM EDT • Business • businessinsider.com

Veolia Completes Clean Earth Deal, Doubling Its U.S. Hazardous Waste Business and Expanding Its Growth Platform

PARIS, June 01, 2026--Veolia Completes Clean Earth Deal, Doubling Its U.S. Hazardous Waste Business and Expanding Its Growth Platform

Jun 1 • 10:04 AM EDT • Business • finance.yahoo.com

Carolina’s Cap Comparison: Linebackers

How much money are the Panthers spending on their linebackers compared to the rest of the NFL?

Jun 1 • 10:00 AM EDT • Sports • sports.yahoo.com

Arsenal and France defender William Saliba could miss World Cup

Wiliam Saliba (25) played all 120 minutes of Saturday’s UEFA Champions League final as Arsenal lost to reigning champions Paris Saint-Germain on penalties. However, Foot Mercato understands that t...

Jun 1 • 6:30 AM EDT • Sports • sports.yahoo.com

The records PSG can still claim 👀

The job isn’t -completely- finished.Winners of a second Champions League in less than a year this Saturday against Arsenal, Paris Saint-Germain have entered for eternity into the great and glorious ...

Jun 1 • 5:21 AM EDT • Sports • sports.yahoo.com

Marquinhos will be allowed to leave PSG

As was the case at the end of last season, Marquinhos (32) will be allowed to leave Paris Saint-Germain this summer, as per a report from L’Équipe.There was a feeling of a mission being completed ...

Jun 1 • 5:10 AM EDT • Sports • sports.yahoo.com

How California Redistricting Shrunk the Competitive Map

The state now has just four congressional districts considered safe for Republicans, and four seen as competitive. The rest of its 52 members of Congress are all but certain to be Democrats.

Jun 1 • 5:02 AM EDT • Politics • nytimes.com

Patients find help with therapy donkeys at psychiatric hospital near Paris

Therapy donkeys are helping patients with mental health conditions at a psychiatric hospital near Paris.

Jun 1 • 12:42 AM EDT • Health • seattletimes.com

Lamine Yamal Reveals Messi, Ronaldo-Themed Goal After Superstar Comparisons

Barcelona prodigy Lamine Yamal has addressed the constant comparisons to Lionel Messi and Cristiano Ronaldo, outlining his personal ambitions as he continues to break records for club and country.

May 31 • 10:59 PM EDT • Sports • foxsports.com

Ben Shelton bounced from French Open in second-round stunner

Ben Shelton is done in Paris after just two rounds of play at the French Open. The former Gator fell in straight sets on Thursday.

May 31 • 10:39 PM EDT • Sports • sports.yahoo.com

Champions League final 2026 in pictures as PSG beat Arsenal

The Champions League trophy will remain in Paris after PSG retained their crown by beating Arsenal in a penalty shootout in the 2026 final. The Gunners put themselves in a great position to win the c...

May 31 • 5:55 AM EDT • Sports • sports.yahoo.com

🥐Joy, chaos, tension, emotion... Sunday's 5️⃣ stories

From PSG’s joy to chaos in Paris during the celebrations, along with major moves in the transfer market.Luis Enrique and a legendary PSGThe French side won their second consecutive Champions League ...

May 31 • 3:38 AM EDT • Sports • sports.yahoo.com

Victor Wembanyama's backup Luke Kornet jokingly accepts LeBron James comparison after chasedown block in Game 7

May 31 • 12:39 AM EDT • Sports • sports.yahoo.com

Paris Saint-Germain Wins Champions League After Penalty Shootout Against Arsenal

Paris Saint-Germain won back-to-back Champions League trophies by beating Arsenal on penalties in a dramatic final in Puskas Arena on Saturday.

May 30 • 3:27 PM EDT • Sports • foxsports.com

Champions League final: Arsenal take on holders PSG in Budapest

Follow live text coverage and radio commentary as Arsenal face Paris St-Germain in Champions League final.

May 30 • 9:19 AM EDT • Sports • sports.yahoo.com

I went to Mistral's summit and heard a clear message about AI

I attended Mistral's first AI summit in Paris. Here's what executives and attendees said about Europe's AI moment.

May 30 • 6:31 AM EDT • Business • businessinsider.com

The chance for history awaits Arsenal

Arsenal are back in the Champions League final for the first time in 20 years and are on the cusp of a historic double. After lifting the Premier League title after a 22-year wait last week there had been a suggestion that this match against Paris St-Germain (17:00 BST kick-off) is something of a free hit. Arsenal fans have travelled to Budapest in their thousands such is the magnitude of this match.

May 30 • 5:05 AM EDT • Sports • sports.yahoo.com

Windows PC Industry Reacts to Apple's Most Affordable MacBook Ever

A few months ago, Apple released the MacBook Neo, its most affordable MacBook ever. At the time, an ASUS executive admitted that the laptop came as a "shock" to the Windows PC industry, which is now in the process of responding. Acer today introduced a Swift Air 14 laptop, with U.S. pricing starting at $699. By comparison, the MacBook Neo starts at $599 with a 256GB SSD and 8GB of RAM, or at $499 for college students and educational staff.

May 29 • 11:30 AM EDT • Technology • macrumors.com

Champions League Finalists Arsenal, PSG Worth Combined $10B+

Global soccer heavyweights Arsenal and Paris Saint-Germain face off Saturday in the Champions League final in Budapest, Hungary. They are both chasing history, with Arsenal looking for its first top-tier European crown, and PSG eyeing back-to-back titles, something only Real Madrid has accomplished since the tournament was rebranded as Champions League in 1992. The game …

May 29 • 9:00 AM EDT • Sports • sports.yahoo.com

Fertitta Entertainment Agrees to Acquire Caesars Entertainment in $17.6B Deal

HOUSTON, LAS VEGAS AND RENO, NEV. — Fertitta Entertainment Inc., a private holding company controlled by the NBA’s Houston Rockets governor (i.e. owner) Tilman Fertitta, has entered into a definitive agreement to acquire casino and gaming giant Caesars Entertainment (NASDAQ: CZR) for $17.6 billion. Fertitta Entertainment plans to finance the acquisition through a combination of equity, assumed Caesars’ outstanding debt (approximately $11.9 billion) and new committed debt financing arranged by a consortium of 10 banks. Under terms of the agreement, Caesars shareholders will receive $31 in cash for each outstanding share, which represents a 49 percent premium to the company’s unaffected stock price on Feb. 25 (the last trading day before rumors of a potential transaction were reported) — $20.77 per share. Upon completion of the transaction, shares of Caesars Entertainment common stock will no longer be listed on the NASDAQ stock exchange. Caesars operates several major Las Vegas Strip properties, such as Caesars Palace, Harrah’s, Paris Las Vegas, Planet Hollywood, Horseshoe, The LINQ Hotel, Flamingo and The Cromwell. Fertitta Entertainment owns Golden Nugget Hotels & Casinos and operates more than 450 full-service restaurants around the world, including Landry’s, Rainforest Café and Morton’s. According to the press releases issued by both companies,…

May 29 • 7:48 AM EDT • Entertainment • rebusinessonline.com

Business for Good: Paratodo

Francis Young’s menswear line Paratodo is heading back to Paris Fashion Week, but makes its biggest impact on hyper-local causes

May 29 • 5:55 AM EDT • Business • thephiladelphiacitizen.org

Arsenal aiming to dethrone dynasty-chasing PSG

Arsenal seek to finally conquer Europe by wresting the Champions League crown from holders Paris Saint-Germain, who are themselves targeting back-to-back titles in Budapest on Saturday."Paris Saint-Germain have the experience of knowing what it is to win it."

May 29 • 2:15 AM EDT • Sports • sports.yahoo.com

Vikings’ Jauan Jennings Makes Surprising Kevin Durant Comparison Amid OTAs

Jauan Jennings dropped an intriguing Kevin Durant comparison for how he feels as part of the Vikings receiving corps.

May 28 • 3:18 PM EDT • Sports • sports.yahoo.com

Black Women Political Candidates Are Expected to Be 'Likable,' Qualified and Tireless. Men Aren’t.

What I had experienced during that run wasn’t entirely unfamiliar to me. The year before, in 2013, I had run for president of the Young Democrats of America (YDA), a national political party office role, against a popular opponent. The opponent was a Black man, so race wasn’t a factor in the election; however, gender was. Before my campaign, I was vice president of YDA and had heard only good things about my service: my fundraising efforts, the partnerships I had engineered with progressive organizations, and programming coordination for the membership. However, when I decided to run for president, I instantly became ‘difficult to work with’ and ‘mean.’ Research on women candidates confirms that voters are less likely to vote for a woman if they don’t like her; by comparison, voters don’t need to like men to elect them. But when I was running as the Black woman candidate in a seven-candidate primary for public office, with two other women in the race, I noticed almost nothing about my being ‘difficult’ and more about my ability and work ethic. My experience running for public office reflected the systemic bias and double standards not just for women candidates, but Black women candidates who dare to aspire to any sort of political leadership—and that needed to change. We need more progressive Black women in public office for a myriad reasons, but we also specifically need the younger generation of Instigators in office, candidates who understand the times in which we live currently. Electing more Black women will take real investment in changing the biases and attitudes (conscious and unconscious) of mostly white donors, media, campaign staff, consultants and institutional leaders to help shift the culture and systems. But this support needs to be substantively increased so that we can rebuild an inclusive, multiracial democracy with the leaders we want and need. (Excerpted from The Instigators: How Black Women Have Been Essential to American Democracy by Atima Omara.)

May 28 • 10:23 AM EDT • Politics • msmagazine.com

Andrea Pirlo interview: Legendary Italy midfielder on PSG and how football has changed | 'You need players who are fast'

Ahead of the Champions League final, legendary midfielder Andrea Pirlo speaks to Sky Sports about what makes Paris Saint-Germain and their playmaker Vitinha so good, why Arsenal can still win in Budapest, and how football has changed since he retired...

May 28 • 3:30 AM EDT • Sports • skysports.com

“Emily in Paris” star Pierre Deny dies at 69 after 'sudden' ALS battle

The veteran French actor starred as fashion boss Louis de Léon, the father of Paul Forman's Nicholas de Léon.

May 27 • 10:50 AM EDT • Entertainment • yahoo.com

'Emily in Paris' star Pierre Deny dies at 69 after ‘sudden’ ALS battle

Pierre Deny, who starred on 'Emily in Paris' as fashion boss Louis de Léon and father to Nicholas de Léon, has died. He was 69.

May 27 • 10:50 AM EDT • Entertainment • ew.com

Carolina’s Cap Comparison: Offensive Line

How much money are the Panthers spending on their offensive line compared to the rest of the NFL?

May 27 • 8:00 AM EDT • Sports • sports.yahoo.com

Inside the program shaping Ascension’s next generation of leaders

For 30 years, Leadership Ascension has worked to develop the next generation of civic and business leaders in one of Louisiana’s fastest-growing parishes, pairing leadership training with hands-on community impact projects. The Ascension Chamber-affiliated program, which runs from January through November, accepts a class of roughly 30 to 36 participants each year representing businesses of […]

May 26 • 6:35 PM EDT • Business • businessreport.com

P2 Science Closes $23 Million Round to Accelerate Commercial Momentum and Expand Green Chemistry Platform into New Markets

P2 Science, Inc., a leading green chemistry company transforming sustainable feedstocks into high-performance ingredients, today announced the close of an oversubscribed $23 million up round led by Sofinnova Partners. Sofinnova is a leading European life sciences venture capital firm based in Paris, London, and Milan. The financing will accelerate P2's commercial growth in beauty and personal care ingredients and expand the company's green chemistry platform into new markets, including aroma tec

May 26 • 9:30 AM EDT • Science • finance.yahoo.com

Z386: An Open-Source 80386 Built Around Original Microcode

There are many ways you can implement an Intel i386 CPU on an FPGA, with the use of original microcode probably being one of the most interesting approaches. This is what [nand2mario]’s z386 …

May 25 • 7:00 PM EDT • Technology • hackaday.com

Everything We Know About <i>Emily In Paris</i> Season 6

Emily In Paris Season 6 is the end of an era. We've rounded up everything you need to know about the Lily Collins-led Netflix final season.

May 25 • 2:56 PM EDT • Entertainment • refinery29.com

Parts of Europe Swelter in Record May Heat as Deaths at Amateur Sports Events Spur Warnings

PARIS (AP) — Europe is baking under unseasonal heat that is shattering temperature records, including in the United Kingdom on Monday, and prompting government warnings after deaths were reported at amateur sports events in France. The French sports minister, Marina Ferrari, posted condolences to ...

May 25 • 11:47 AM EDT • Sports • usnews.com

Politics, Pubs, Parades, and the Parish: Senator Bernie Kenny, Part IV

Former Senator Bernie Kenny of Hoboken in this fourth and final edition of Politics, Pubs, Parades, + the Parish ties together Irish heritage

May 25 • 8:38 AM EDT • Politics • insidernj.com

Unreal Engine 6 announced with Rocket League reveal

Psyonix revealed a “new era” of free-to-play vehicular soccer game Rocket League at Rocket League Championship Series 2026: Paris Major, which showcased the game running on Unreal Engin…

May 24 • 1:01 PM EDT • Technology • gematsu.com

Rocket League On Unreal Engine 6 Announced At Paris Major

Epic Games and Psyonix have announced the future of Rocket League in Unreal Engine 5.

May 24 • 12:23 PM EDT • Technology • thegamer.com

Prime Minister Sir Keir Starmer urges TNT Sports to make Champions League final free-to-air

Sir Keir Starmer has urged broadcaster TNT Sports to allow football fans to watch Arsenal's Champions League final showdown with Paris Saint-Germain for free.

May 23 • 12:43 PM EDT • Sports • espn.com

Starmer asks TNT Sports to make Champion League final free to view

Match between PM’s favourite Arsenal and Paris Saint-Germain marks first time British fans will be unable to watch final free of charge

May 23 • 12:00 PM EDT • Sports • theguardian.com

Champions League: Keir Starmer urges TNT Sports to make final free-to-air

UK Prime Minister Sir Keir Starmer calls on TNT Sports to make next Saturday's Champions League final between Arsenal and Paris St-Germain free-to-air.

May 23 • 12:00 PM EDT • Sports • bbc.com

Keir Starmer urges TNT Sports to make Arsenal’s Champions League final free to watch

For the first time in 30 years, UK viewers will have to pay to watch the Champions League final between Arsenal and Paris Saint-Germain.

May 23 • 12:00 PM EDT • Sports • nytimes.com

A familiar fight returns to Stockton politics

Morning Briefing:*|DATE:F j, Y|* DONATE Good morning, Stockton. A new Stockton City Council race is already drawing comparisons to one of the city’s more

May 23 • 9:00 AM EDT • Politics • stocktonia.org

LEGO Batman Comparison Shows Difference Between Xbox Series X And Series S

How the Xbox versions stack up

May 22 • 1:00 PM EDT • Technology • purexbox.com

Lessons from the Vogue Business Global Summit: Chantilly

This year’s European Global Summit was held at the beautiful Château du Chantilly just outside of Paris. The two-day event saw industry leaders discuss the future of luxury, AI, and new growth markets.

May 22 • 10:55 AM EDT • Business • vogue.com

Behind the scenes at the Vogue Business Global Summit: Chantilly

This year’s European Global Summit was held at the beautiful Château du Chantilly just outside of Paris. The two-day event saw industry leaders discuss the future of luxury, AI, and new growth markets.

May 22 • 10:01 AM EDT • Business • vogue.com

Famitsu sales (5/11/26 - 5/17/26) - big Nintendo Switch 2 sales ahead of price increase

The latest Japanese hardware sales from Famitsu are as follows: Switch 2 – 217,922 Switch Lite – 8,303 Switch OLED – 7,804 PS5 Digital Edition – 6,902 Switch – 5,285 PS5 Pro – 1,747 PS5 – 594 Xbox Series X – 193 Xbox Series X Digital Edition – 191 Xbox Series S – 47 For comparison’s sake, here are the...

May 21 • 11:21 AM EDT • Technology • nintendoeverything.com

Maternity care deserts are common in Louisiana. Compare states, parishes

Nearly one-third of Louisiana parishes face limited or no access to maternity care, impacting maternal and infant outcomes. Figures from Tulane University's Newcomb Institute reveal stark disparities across the state.

May 21 • 5:00 AM EDT • Health • nola.com

It Feels Like Google Is Downplaying Smart Glasses With a Screen in Them

Probably for the best if it's trying to avoid comparisons to Google Glass.

May 20 • 9:11 PM EDT • Technology • gizmodo.com

Spurs, Victor Wembanyama will play regular-season games vs. Pelicans in Paris, Manchester in January 2027

May 20 • 2:23 PM EDT • Sports • sports.yahoo.com

Northwestern professors navigate politics, pedagogy in Trump-era classrooms

As history Prof. Michael Allen lectured about the Vietnam War in his American Wars class this quarter, he drew a connection between South Vietnamese police tactics and present-day immigration enforcement in the U.S.: that police force can alienate civilians rather than winning them over. He said this comparison was not meant to tell students what...

May 19 • 2:46 AM EDT • Politics • dailynorthwestern.com

Politics, Pubs, Parades, and the Parish: Senator Bernie Kenny, Part III

Former Senator Bernie Kenny of Hoboken in this third edition of Politics, Pubs, Parades, + the Parish shares advice.

May 18 • 12:07 AM EDT • Politics • insidernj.com

🚨 Ligue 1: how relegation and Europe stand

Although marred by some Nantes ultras, who caused their match to be suspended, the final matchday in Ligue 1 was well worth it.At the top, Paris Saint-Germain, already champions, lost 2-1 away to thei...

May 17 • 5:11 PM EDT • Sports • sports.yahoo.com

Arsenal in the race for Bradley Barcola, Liverpool interest cooling?

Bradley Barcola (23) could leave Paris Saint-Germain at the end of the season amid reports that the Ligue 1 champions are looking to add another forward to their squad this summer, as per a report fro...

May 17 • 9:40 AM EDT • Sports • sports.yahoo.com

Google Health Premium vs. Basic Features Comparison

The launch of Google Health, its new app, and the Fitbit Air is around the corner. In fact, for many of you, the new Google Health app should start showing up on your phones as an update as early...

May 15 • 6:34 PM EDT • Technology • droid-life.com

Craft Academy students expand learning through travel

Morehead State’s Craft Academy students spent spring break learning beyond the classroom with trips to Washington, D.C., and Paris.

May 15 • 1:08 PM EDT • Science • moreheadstate.edu

Community: Assumption High rodeo raises funds for FFA program

Rodeo fans enjoyed a weekend of fun, festivities and western entertainment at the 14th annual Assumption High School FFA Benefit Rodeo at the Assumption Parish Agriculture Complex April 24-25.

May 15 • 6:30 AM EDT • Entertainment • theadvocate.com

Forza Horizon 6 Comparison Shows Difference Between Xbox Series X And Series S

How the Xbox versions stack up

May 14 • 11:30 AM EDT • Technology • purexbox.com

Rooney weighs in on Steelers playing Saints in Paris

The NFL officially announced on Wednesday that the Pittsburgh Steelers will play the New Orleans Saints in Paris on Oct. 25.

May 14 • 9:33 AM EDT • Sports • sports.yahoo.com

Kevin McKernan is helping St. Louis keep its local flavor, one business at a time

Kevin McKernan owns a half-dozen of the kind of classic neighborhood businesses that feel increasingly endangered. He and his wife Erin own Donut Drive-In, the unpretentious shop in Lindenwood Park. They own Epiphany Lanes, a low-key bowling alley once run by the Catholic parish that still shares its parking lot. He founded The Improv Shop […]

May 14 • 6:47 AM EDT • Business • stlmag.com

NFL schedule: Breaking down a strong slate of international games, including Steelers-Saints in Paris

May 13 • 9:40 AM EDT • Sports • sports.yahoo.com

Innate Pharma Reports First Quarter 2026 Business Update and Financial Results

MARSEILLE, France, May 13, 2026--Regulatory News: Innate Pharma SA (Euronext Paris: IPH; Nasdaq: IPHA) ("Innate" or the "Company") today reported its business update and consolidated financial results for the quarter ending March 31, 2026.

May 13 • 1:00 AM EDT • Business • finance.yahoo.com

A once-popular Livingston Parish business event is returning after seven years

The Livingston Parish Chamber of Commerce is reviving its community expo and job fair after a seven-year hiatus. The free event is scheduled for Tuesday from 4 p.m. to 7 p.m. at the Suma Hall C… Already an INSIDER? Sign in. Already an INSIDER? Sign in

May 12 • 10:58 AM EDT • Business • businessreport.com

Can The Jumper Be Hacked? Inside Basketball's Next Arms Race

In the summer of 2024, during the WNBA’s Olympic break, several Atlanta Dream players who weren’t competing in Paris had gathered for a midseason training camp of sorts. Anyone watching would have seen what looked like a typical 3-on-3 scrimmage. In reality, it was anything but. The Dream weren’t playing in any ordinary gym, but…

May 12 • 9:01 AM EDT • Technology • defector.com

Fitbit Air vs. WHOOP Size Comparison

The Fitbit Air went up for pre-order last week and we're now all waiting to get one on the wrist as soon as possible. For some lucky folks who live near a physical Google Store, that can actually...

May 11 • 9:42 AM EDT • Technology • droid-life.com

New Rocket League Paris Major Bundle: All Net Sales Going to Competing Players & Teams

Net sales from the Paris Major Bundle will go directly to competing players and the teams that got them there.

May 11 • 8:00 AM EDT • Technology • rocketleague.com

Carolina’s Cap Comparison: Wide Receivers

How much money are the Panthers spending on wide receivers compared to the rest of the NFL?

May 11 • 8:00 AM EDT • Sports • sports.yahoo.com

Politics, Pubs, Parades, + the Parish: Senator Bernie Kenny Part II

Former Senator Bernie Kenny of Hoboken in this second edition of Politics, Pubs, Parades, + the Parish talks about his roots in politics.

May 11 • 7:13 AM EDT • Politics • insidernj.com

Figure1_YukiNagao_20260511

Figure 1: A visual comparison showing how interfacial proton transport, previously merged in conventional measurements, can now be separated and measured at each interface.

May 11 • 1:22 AM EDT • Science • eurekalert.org