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Movies to watch in Seattle’s indie theaters in October 2026
Fall brings classics alongside Halloween fare to Seattle’s independent cinemas.
Sutter Opens New Urgent Care in San Francisco's Mission Bay
New clinic brings same-day care to one of San Francisco’s fastest-growing neighborhoods SAN FRANCISCO – Residents, workers and visitors in Mission Bay now have a new option for same-day medical care with the opening of Sutter Health’s newest urgent care clinic near Oracle Park. Located at 240 King St., the 2,156-square-foot clinic has four exam […]
Buffalo Museum of Science unveils permanent Bills, Sabres and Bandits exhibit
The Buffalo Museum of Science opened the $3M Science Stadium interactive, a permanent exhibit that focuses on the Bills, Sabres and Bandits and brings the science and engineering behind professional sports to life.
Valley National to acquire Bluevine for $340M
Valley National Bancorp announced its plan to acquire Bluevine, a digital banking platform for small businesses, for $340 million. The acquisition aims to strengthen Valley's funding base, expand its small-business offerings, and accelerate its artificial intelligence capabilities to enhance its position in the digital banking sector.
‘Can’t even’: Man spends $168 on a birthday dinner at Disney Springs. Then the surprise arrives on an empty plate
A $168 birthday dinner should come with a decent ending. However, one man celebrating at Disney Springs got a surprise that nobody at his table seemed prepared for. Even an expensive birthday dinner c...
Femme in STEM event brings hands-on science to Wilmington mall
The North Carolina Aquarium at Fort Fisher brought hands-on science to shoppers at Independence Mall for its annual “Femme in STEM” event.
Jess McKenna and Zach Reino are a force to be toured with
Known for their work on an improvised musical podcast and Dropout TV, this duo brings “Off Book” to the Barrymore in Madison on Oct. 17.
After 25 Years In Hollywood, Jamee Natella Is Writing Her Own Chapter
Producer Jamee Natella's WorldRide Impact, guided by a youth board, brings global culture to kids through travel, food, art and sport, a bet on the next generation's IP.
Steve Sweeney to return to Middleborough for comedy show
Comedian Steve Sweeney brings his observational humor to the Alley Theatre in Middleborough for an October show.
Merck's holistic HIV health hive buzzes with the help of actress Debbie Allen
Merck’s newly unveiled HIV education program “Your Hive of Whole Health” is buzzing with the help of a queen bee in famed actor and HIV advocate Debbie Allen. | Merck's "Your Hive of Whole Health" brings together a hoard of educational resources and tips to promote holistic health for those living with HIV.
Oscar Health (OSCR) Shares Moved, What Is Catching Investors' Attention?
Why Oscar Health’s latest product push matters now Fresh commentary around Oscar Health (OSCR) centers on management’s push for higher earnings per share through tighter medical loss ratios, new offerings such as the Lucy Healthcare Marketplace, and wider use of AI tools. At a share price of $29.60, Oscar Health has pulled back over the past week with a 7 day share price return of down 5.4% and a 30 day share price return of down 2.9%. However, the 90 day share price return of 3.8% and year...
What Panera Bread’s Founder Wants CEOs To Consider About Their Health
Panera Bread founder Ron Shaich asks CEOs to look years ahead. His question also brings a more personal decision about health into focus.
What Panera Bread’s Founder Wants CEOs To Consider About Their Health
Panera Bread founder Ron Shaich asks CEOs to look years ahead. His question also brings a more personal decision about health into focus.
NIO Stock Jumps Overnight As $2.4B Nio Power Deal Brings Geely Into Its Battery Swap Business
The companies are also discussing wider use of battery swapping across Geely-related vehicles, though plans remain preliminary.
Siloam Springs business owner raises concern over water leaking into basement of historic structure
SILOAM SPRINGS -- When a leak was noticed in the basement of Park House Kitchen + Bar, staff checked for plumbing leaks, drainage issues, air-conditioning runoff and anything else they could think of that might be causing the issue, according to business owner Alma Sanchez.
Experimental Emulator Brings Nintendo Switch Games to Jailbroken PS5 Consoles
An unofficial port of the Eden Nintendo Switch emulator is now running natively on jailbroken PlayStation 5 consoles. Developer BlackBearReloaded released ProsperoEden, which adapts Eden, itself a fork of the now-defunct Yuzu project, to run directly on Sony's hardware as homebrew rather than...
PAHO Walk for Health brings together staff, families, partners and delegates ahead of 63rd Directing Council
Washington, D.C., September 27, 2026 (PAHO) — On the eve of the 63rd Pan American Health Organization (PAHO) Directing Council, PAHO staff, families, friends, delegates from Member States, partners and community members came together for the 2026 PAHO Walk for Health, highlighting the importance of physical activity, healthy environments and social connection.
Yampa Valley Community Foundation fills $110K mental health gap for Steamboat students
The Yampa Valley Community Foundation has closed a $110,000 gap in the Steamboat Springs School District for school-based mental health services, ensuring the district can maintain all contracted mental health providers through the 2026-27 academic...
Presidents Cup 2026: Sunday Singles Pairings, Tee Times
Get the full rundown for Sunday singles at the Presidents Cup as the International team looks to stun Team USA. The post Presidents Cup 2026: Sunday Singles Pairings, Tee Times appeared first on HEAVY.
‘All of Us’ Block Party brings health care, resources directly to local residents
COLUMBUS, Ohio (WCMH) — Nearly 70 organizations brought health care and other resources directly to Columbus’ Near East Side Saturday as part of the second annual “All of Us” Block Part…
True North festival brings 17 chefs to Madison's Duck Pond
MADISON, Wis. — Seventeen chefs gathered at the Duck Pond on Saturday to prepare a feast for the True North Food and Music Festival.
Bad language: profane Trump brings presidential swearing out into open
President has let rip with swearwords in recent months, redefining norms about acceptable language in public office
New Iberia’s Beneath the Balconies brings live performances, dancing to Main Street
Organizers say the event is about more than entertainment, but also an opportunity to bring visitors into New Iberia when they otherwise wouldn’t have.
NFL Sunday Night Football best bets Week 3
Sunday Night Football brings a fascinating matchup between the Los Angeles Rams and Denver Broncos, with several key storylines shaping the betting market. Puka Nacua’s availability remains a major question, while Denver’s defense has played well through two weeks. On…
It's Your Business | Couple brings gym to Fisher with Jacked Rabbit Fitness
Travis Enghausen and Ashley Warlow hope to have a grand opening on the weekend of Nov. 14 for their business, which they’ve decided to call Jacked Rabbit Fitness — perfectly
In a mysterious reversal, Earth’s atmosphere has gotten less dusty
The amount of dust in the atmosphere has fallen over the last 20 years, recent research shows. Could that explain why the planet has been warming faster than expected?
Andy Burnham brings good vibes to Labour’s annual conference but tough choices are coming
LONDON (AP) — British Prime Minister Andy Burnham has been in the job for two months, and so far his party isn’t demanding his head. These days, that’s an accomplishment.
Andy Burnham brings good vibes to Labour’s annual conference but tough choices are coming
British Prime Minister Andy Burnham has been in the job for two months, and so far his party isn’t demanding his head. The governing Labour Party opens its annual conference beside the River Mersey i...
Andy Burnham brings good vibes to Labour’s annual conference but tough choices are coming
British Prime Minister Andy Burnham has been in office for two months, and his party seems content for now | KNSS Radio
UFC Vegas 121 Bonuses! Officer Hernandez Brings Home The Bacon
Raul Rosas Jr. punched his ticket to the bantamweight rankings last night (Sat., Sept. 26, 2026) at UFC Vegas 121 LIVE on Paramount+ from inside Meta Apex in Las Vegas, Nevada, earning a scary knockout win over veteran Raoni Barcelos in the main event of the evening (see it HERE). In addition to bantamweight headliner, […]
HCA Florida hospitals celebrate Hispanic Heritage with family health event
HCA Florida Healthcare hospitals are celebrating Hispanic Heritage. Hospitals in Ocala and West Marion hosted a family health and wellness event at the Silver Springs Shore Community Center.
Four Chord Music Fest brings nearly 30 acts to Pittsburgh for 12th year
For 12 years, Four Chord Music Festival has called Pittsburgh home, and this weekend, thousands of fans packed F.N.B. Stadium for another year of music, merchandise and memories.
Femme in STEM event brings hands-on science to Wilmington mall
Exhibitors from UNCW, local colleges and WECT’s First Alert Weather Team offered interactive experiments to spark curiosity.
My husband and I skip holiday and birthday gifts; give surprises
We focus on date nights, trips, and surprises instead of birthday and holiday gifts. Once, he gave me diamond earrings on a random day "just because."
Jennifer Lopez brings diva wattage to Dolce & Gabbana runway show
Jennifer Lopez has brought her diva wattage to Dolce & Gabbana’s Spring Summer 2027 runway show.
Jennifer Lopez brings diva wattage as Dolce & Gabbana refreshes its Sicilian inheritance
Jennifer Lopez has brought her diva wattage to Dolce & Gabbana’s Spring Summer 2027 runway show | Newsradio 1140 WRVA
Jennifer Lopez brings diva wattage as Dolce & Gabbana refreshes its Sicilian inheritance
Jennifer Lopez has brought her diva wattage to Dolce & Gabbana’s Spring Summer 2027 runway show | Talk 1370
Jennifer Lopez brings diva wattage as Dolce & Gabbana refreshes its Sicilian inheritance
Jennifer Lopez has brought her diva wattage to Dolce & Gabbana’s Spring Summer 2027 runway show | WWJ Newsradio 950
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Colorado Politics Calendar Sept. 28-Oct. 4
CoPo’s weekly political calendar will help you find political and public-policy events throughout Colorado. It includes candidate and issue campaign events, public policy meetings, court hearings, state and local party conventions, assemblies, debates, rallies, parades, speaking engagements, traveling dignitary appearances, water meetings, book signings, county commission hearings, city council meetings and more. As a subscriber, […]
From finance to science, Burke brings experience to Putnam County
Dear Editor, With so many struggling with the triple whammy of high taxes, high food prices and high energy costs, it is good news indeed that a triple threat candidate – a...
QC Senior Expo brings free health screenings, services to local older adults
QC Senior Expo: Free health checks, haircuts offered at Golden Leaf Center More than 50 vendors gathered at the Golden Leaf Banquet Center in Davenport for the fifth annual QC Senior Expo, providing Quad Cities seniors with free vaccines, health screenings, and personal care services under one roof. #Davenport #QuadCities #QCA #KWQC #SeniorCare #Healthcare #LocalNews
Mid-sized shopping center to include Thai restaurant. Here's what we know.
Renderings show the 9,660-square-foot development will be built at 101 Gerald Drive and would house Bangkok Thai restaurant, currently housed at 3904 Johnston St.
Health Brief: The business of treating Alzheimer’s
Plus: FDA takes aim at a major compounding pharmacy’s GLP-1 offerings
Health Brief: The business of treating Alzheimer’s
Plus: FDA takes aim at a major compounding pharmacy’s GLP-1 offerings
Black Women. Health. Power.: Creating Space for Connection, Community and Collective Calls to Action
This year marked the 55th anniversary of the Congressional Black Caucus Foundation’s Annual Legislative Conference (ALC). The conference convenes policymakers, advocates, organizers, faith and community leaders in Washington, D.C. to identify the priorities of Black communities that demand legislative action. In the same spirit that brings thousands of changemakers to D.C. for this annual event, […]
Supporting the mental health of those who provide mental health care in Maine schools
The start of each new school year always brings attention to the mental health needs, including anxiety and stress, of students and their families. However, it can also be a stressful time for those who support them, like school social workers, counselors, teachers, and clinicians.
Game on for Science Stadium at Buffalo Museum of Science
The Buffalo Museum of Science has opened its $3 million Science Stadium interactive exhibit. Developed in partnership with the Buffalo Bills, Buffalo Sabres, and Buffalo Bandits, the permanent exhibit brings
Smith Entertainment Group Welcomes Fans Back to the Delta Center with Elevated Offerings for 2026-27 Season
More than 1,500 full-view seats added to the upper levels for Utah Mammoth games. Fan-friendly enhancements include new menu items, expanded ticket offers and a free rewards program
Smith Entertainment Group Welcomes Fans Back to the Delta Center with Elevated Offerings for 2026-27 Season
More than 1,500 full-view seats added to the upper levels for Utah Mammoth games. Fan-friendly enhancements include new menu items, expanded ticket offers and a free rewards program
Musco expands testing capabilities with new Oskaloosa facility
Oskaloosa-based Musco Lighting has opened a new 30,000-square-foot product testing facility at 601 First Ave. W, expanding its ability to design, test and support lighting solutions. The facility brings testing and certification in-house, providing additional resources to evaluate and improve product performance as lighting and electronics become more complex. The opening coincides with Musco’s 50th…
Glen Cove Street Fair brings nearly 100 vendors, entertainment and community together
For one September Saturday, downtown Glen Cove became a gathering place for neighbors, families and visitors as the annual Street Fair filled Glen Street, School Street and Village Square with …
Players Sports Center Brings Indoor Sports Back To Logan Square
The center, located in the former The Windy City Fieldhouse, has six indoor sand volleyball courts, two basketball courts, two regulation pickleball courts and an indoor turf soccer field.
New rock production brings its own legends lineup
“Ikons of Rock” has moved into The Strat Theater, where it is getting loud.
Microsoft unveils Copilot super app, targeting business users with AI agents
Microsoft is launching its super app as a central interface through which customers can chat with AI bots, write code, and access a new "Autopilot" feature that brings agentic capabilities to its flagship AI app.
Smith takes helm of Des Moines schools
A national search could have been launched by the Des Moines school board in its search for a new superintendent. Instead, the board turned to Matt Smith, an education leader with 16 years of experience in the district who brings a deep understanding of its challenges and a plan for its future. The Sept. 15…
Science Museum of Minnesota Permanently Protects 130 Acres Along St. Croix River
It brings the museum's total conserved land near the river to more than 300 acres.
Shore football schedule, scoreboard, results for Week 4 games
The Week 4 schedule brings us the third consecutive week of divisional play among Shore Conference high school football teams.
National Forensic Science week brings attention to CSI investigators
BAY COUNTY, Fla. (WMBB) – CSI teams are sometimes an under-recognized part of many law enforcement agencies. But investigating crimes takes precision, skill, and focus. “Evidence doesn&…
Branson Fall Fest brings entertainment downtown Sept. 26-27
Downtown Branson is hosting Fall Fest on Sept. 26 and Sept. 27, according to Rick McEwan, who has lived in Branson for 42 years.
Murphysboro BBQ festival brings teams from near and far
MURPHYSBORO — The 39th annual Praise the Lard Barbecue Cook-off is this weekend's hottest ticket, with participating teams planning months in advance for one of the national circuit's biggest contests.
SPONSORED The Place: Branson Fall Fest brings entertainment downtown Sept. 26-27
Downtown Branson is hosting Fall Fest on Sept. 26 and Sept. 27, according to Rick McKeown, who has lived in Branson for 42 years.
2026 Game IV: Iowa State versus No. 15 Utah preview
The first top 15 opponent of the Jimmy Rogers era arrives Saturday at Jack Trice Stadium. No. 15 Utah comes to Ames riding a perfect 3-0 record under first year head coach Morgan Scalley and brings with them one of the most complete rosters in the Big 12. This is not a tune up game. […]
Sponsored Content: The Big E Brings Big Names and Nonstop Entertainment
Discover the exciting entertainment lineup at The Big E, featuring headline concerts, local performers, family-friendly shows, strolling acts, and nonstop live entertainment across the fairgrounds.
Dems shamed as DHS brings ICE shooting reciepts after politician called ICE officers ‘liars with masks’
The Department of Homeland Security accused Democrats and media of spreading lies about the ICE shooting in Austin as protests erupted citywide.
This Tiny Audiophile Gadget Brings CD-Quality Hi-Fi to Your iPhone
iPhones don't stream the best audio quality over Bluetooth. The good news? You can change for less than $100.
Business Insider brings Tech Insider to San Francisco Tech Week
Business Insider will host two events, Tech Insider: Growth Mode and AI Insider: A Roundtable Dinner, during San Francisco Tech Week 2026.
Spokane's Teleport Block Party brings local businesses together
A writer goes to Spokane's Teleport Block Party and highlights two local businesses.
She Matters: Women’s Health Night Brings Health Education, Shopping and Community Connections to Sartell
(KNSI) - The Sartell Community Center will host an event focused on women and wellness. She Matters: Women's H...
Between the Notes: Carlos Santana brings the family and the nostalgia
My wife was dancing in her chair. Then "Evil Ways" brought the crowd and me to our feet. It was in my key, too.
NAB Show New York 2026 Brings Media’s Biggest Business and Technology Shifts to the Stage Oct. 21-22
More than 150 speakers to explore the business and technology shaping broadcast, creators, sports, streaming and the future of media.
Matchday 28: Eastern Conference playoff races take center stage
By Ari LiljenwallWith the Audi 2026 MLS Cup Playoffs fast approaching, the stakes continue to rise across the league.Matchday 28 brings another packed slate, highlighted by pivotal Eastern Conference ...
Rooted in science: Rooted Owl brings science-backed solutions to the pet supplement category
The company offers nine different targeted capsule supplements, along with five hemp-derived products.
Business Briefs: Sept. 25, 2026
Western Mass EDC names new chief marketing officer SPRINGFIELD — The Western Mass Economic Development Council has named Justin Roberts as its new chief marketing officer. Roberts will work with President and CEO Aaron Vega to expand regional storytelling, increase collaboration among members and partners, and build a long-term marketing and communications strategy. Roberts brings […]
Memphis People in Business for Sept. 24, 2026
A look at promotions, hirings, movers and newsmakers in the Memphis area business scene.
Wednesday’s LSU and Texas A&M injury report: Key defender questionable
First injury report of the week brings questions regarding secondary
Calling all current and future scientists: Kiel is the place to be this week
This week, Kiel has become a meeting place for science in Europe. Researchers, school pupils, young scientists and members of the public are coming together through a series of major events led or co-organised by Kiel University.At the centre of it all are around 150 of Europe’s most talented young researchers, aged 14 to 20, who have travelled to Kiel from nearly 40 countries for the 37th European Union Contest for Young Scientists (EUCYS). Running from 22 to 27 September, the European Union’s flagship competition for young scientists brings together winners of national science competitions to present around 100 original research projects across fields ranging from engineering and computer science to medicine, environmental research and the social sciences. The winners will be announced at the Award Ceremony on Saturday.For Kiel University, hosting EUCYS is both an honour and a natural extension of a much longer story. Germany’s northernmost comprehensive university has invested for many years in supporting young scientific talent and bringing research into dialogue with society. The Kiel Science Factory gives school pupils opportunities to experience research first-hand, while programmes such as Rent-a-Scientist send researchers directly into local classrooms. Major annual public events including Kiel Week and the European Researchers’ Night take science beyond the campus through talks, exhibitions and hands-on activities.That long-standing commitment has increasingly taken on a European dimension – and this week, many of those efforts are coming together.One of the foundations for this success is the European Researchers’ Night (ERN), which celebrates its tenth edition in the Kiel region this year. The initiative is funded through the Marie Skłodowska-Curie Actions, with Kiel University developing the successful EU proposals and securing the funding, while regional partner KielRegion coordinates the many activities on the ground. Together with research institutions, schools, companies, local authorities and civil society, they have built ERN into a major platform for public engagement.Over the years, Kiel’s ERN programme has grown far beyond a single evening into a whole “Science Summer”, beginning with “Science Shopping” in spring and culminating tomorrow, 25 September, in Science Day.“We have developed a wide range of public engagement formats, often together with the other research institutions in the region, the city and regional authorities, schools, companies and civil society,” says Eckhard Quandt, Kiel University’s vice president for research, academic infrastructure and transfer. “Over the past decade, we have increasingly taken this commitment to the European level.”That combination of European funding expertise and strong regional partnerships also helped Kiel University take the next step. Drawing on its experience with ERN and its European networks, including the SEA-EU University Alliance, the university brought together Brest in France and Split in Croatia for a successful bid to the EU’s new Science Comes to Town initiative. Throughout 2026, the three cities are serving as Europe’s first Science Ambassadors, with more than one thousand activities bringing science into schools, public spaces, cultural venues and everyday life.EUCYS is perhaps the clearest example of how Kiel University is using Science Comes to Town to create new connections between major European initiatives. From the outset, the university deliberately planned the contest for the week of European Researchers’ Night and opened the EUCYS exhibition to the wider Science Day audience. Tomorrow, that means thousands of visitors can encounter the next generation of scientific talent first-hand, while the young researchers themselves gain a much bigger public stage.“Because we opened EUCYS up for European Researchers’ Night, there will be a lot of people actually visiting the exhibition,” says organiser Stefanie Altemark of Kiel University.“We wanted Europe’s most talented young scientists not only to compete with one another, but also to become visible to the wider public. At the same time, people in Kiel will have the opportunity to see what the next generation of scientists are already capable of,” says Quandt.“We’ve shown over the last years that science is a big part of Kiel, and it’s always been the goal to not only show that to people in Germany, but also to show it to people all over Europe. Thanks to Kiel University’s expertise in European funding programmes, we have been able to turn that ambition into reality,” says Sünje Fock, who is coordinating the Science Summer at KielRegion.The model is characteristic of Kiel University’s approach: combining European funding expertise and international networks with strong regional partnerships to give major initiatives greater reach and visibility.This year also marks the 30th anniversary of the Marie Skłodowska-Curie Actions, giving Kiel University the special opportunity to welcome Vanessa Debiais-Sainton, Head of Department for the Marie Skłodowska-Curie Actions at the European Research Executive Agency, to Kiel tomorrow. Her visit brings together two priorities that have shaped Kiel University’s work over the past decade: supporting researchers and bringing science closer to society. Debiais-Sainton emphasises how closely the two are connected: "For thirty years, the Marie Skłodowska-Curie Actions (MSCA) have given more than 150,000 researchers the chance to pursue their dreams and open up new fields. Doctoral Networks and Postdoctoral Fellowships give them the freedom to move, to connect, to train and to follow their curiosity across borders, sectors and disciplines. But excellence cannot live only in laboratories. Researchers’ Night takes science out of the lab and into the city, to the families, the schoolchildren and the curious minds who will become the next generation. Kiel shows what that looks like at its best. That is the MSCA promise: open science, open borders, open doors."For Kiel University, these activities are not separate endeavours. They are part of a broader understanding of academic excellence in which outstanding research, talent development, international cooperation, knowledge transfer and engagement with society strengthen one another.“For me, one of the most important lessons from the past decade is that scientific excellence, knowledge transfer, talent development and engagement with society cannot be treated as separate tasks,” stresses vice president Quandt. “They reinforce one another.”That philosophy is also reflected in Kiel University’s current bid for Germany’s Excellence University status. The designation is part of Germany’s national Excellence Strategy, which provides substantial long-term funding to selected universities to strengthen internationally competitive research and their overall institutional development. A successful outcome would provide new opportunities to build on what has already been created: deepening international cooperation, creating more opportunities for knowledge exchange and public engagement, and extending the university’s reach across the region and beyond. “If we are successful, it would allow us to take what we have built in Kiel considerably further – including expanding our networks and transfer activities beyond the region and increasingly across the Baltic area,” says Quandt.This week’s events offer a glimpse of what that could mean in practice: a university using its research strength, European expertise and regional partnerships to create opportunities for scientists at every stage of their careers while making science more visible, accessible and exciting to the wider public.
Hispanic Heritage Festival offers full day of celebration in Elkhart
The Hispanic Heritage Festival brings music, food vendors, family activities and fireworks to downtown Elkhart on Sept. 26.
Angry outbursts, slurs and firings: Tumult rocks a key Senate campaign
Democrats hope that Mary Peltola can flip a Republican Senate seat in Alaska. Former aides describe a campaign and congressional office marked by chaos.
China-Russia space camp in Malaysia opens to youth in Southeast Asia
Private initiative brings together a Russian astronaut trainer and a Chinese science museum to teach ethics and space science in Penang.
Phoenix Wright Ace Attorney: Dual Destinies VR Announced For Meta VR Glasses & Quest
A new VR release in Capcom's visual novel adventure series brings courtroom drama to Meta VR Glasses and Quest in 2027.
Biophysical Therapeutics brings longevity science to skincare with its new IF1 brand
From equations and experiments in the laboratory to exclusive skincare for skin longevityWILMINGTON, Del., Sep. 23,
South Korea’s weight-loss obsession and the health risks it brings
South Korean women face higher underweight rates than men, with experts warning that social pressure to be thin and weight-loss drugs may pose health risks.
Meta Brings FDA-Cleared Hearing Enhancement To Its Smart Glasses
After a free trial it'll cost $150 to add on, or require a Meta One subscription.
As AI reshapes the workplace, Google brings training to Berkeley County businesses
Small business owners from across Berkeley County gathered Wednesday for a free workshop hosted by Google and Berkeley County Economic Development
G&F brings science learning to life for Eastside second-graders
Second-grade students at Eastside Elementary recently traded their classroom for a hands-on science experience with the Wyoming Game and Fish Department as part of a new partnership designed to connect
THE RAIL IN LEXINGTON ANNOUNCES PEACHTREE ENTERTAINMENT AS CO-OWNER AND EXCLUSIVE OPERATOR, PLUS NEW RENDERINGS UNVEILED
/PRNewswire/ -- National concert promotion company Peachtree Entertainment, in partnership with The Commons, has been announced as co-owner and exclusive...
What science says about ultraprocessed foods and the aging brain
The colorings, additives and preservatives added to food products, as well as food processing techniques, are a source of concern in 2026 because they are ubiquitous worldwide, yet their effects on metabolic ...
Alamo Museum Brings Karankawa History to Life for Students
Homeschool students received a hands-on lesson in Texas Indigenous history Sept. 22 as Maria del Pilar Garza Museum Director Alejandro Oyoque shared his knowledge of the Karankawa people and guided students in building a bow.
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Breaking down new rules for healthy aging
The old idea that aging brings inevitable decline is outdated, according to doctors at Oak Street Health. They say people can take a proactive approach to how they age.
Breaking down new rules for healthy aging
The old idea that aging brings inevitable decline is outdated, according to doctors at Oak Street Health. They say people can take a proactive approach to how they age.
Princess Kate returns to the red carpet at Tom Cruise's 'Digger' premiere with a rarely seen royal heirloom
The Princess of Wales's purple Jenny Packham gown was complemented by Princess Diana's earrings and a necklace from 1923.
Robert Pattinson brings 'To Catch a Predator' to life in new film 'Primetime'
Robert Pattinson stars in “Primetime,” a film inspired by NBC Dateline's “To Catch a Predator.” | WBBM Newsradio 780 AM & 105.9 FM
Robert Pattinson brings 'To Catch a Predator' to life in new film 'Primetime'
Robert Pattinson stars in “Primetime,” a film inspired by NBC Dateline's “To Catch a Predator.”.
Robert Pattinson brings 'To Catch a Predator' to life in new film 'Primetime'
Robert Pattinson stars in “Primetime,” a film inspired by NBC Dateline's “To Catch a Predator.”.
BizTrip AI Brings Business Travel Booking Directly Into Claude and ChatGPT
SAN FRANCISCO, September 23, 2026--BizTrip AI, makers of agentic AI for corporate travel management, today announced that its core trip-planning and booking experience is now available natively inside both Claude and ChatGPT. The integration uses the Model Context Protocol (MCP) — specifically MCP "apps," which support rich, interactive rendering directly in a chat conversation — allowing travelers to search, compare, and book business travel without switching to a separate app or website.
Bay Area sports calendar, Sept. 23-24
Jeffrey Springs and the A's will host the Angels at 6:30 p.m. Wednesday. (NBCSCA)
PRINT ONLY Autumn brings a full season of events
The cooler weather brings more than fall colors — festival season is about to reach a fever pitch. Start planning your weekend excursions now. See a full list of fall