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The Michael Miller Show: Greater Kendall Business Association & Upcoming Business Expo
Getting your Trinity Audio player ready... On this episode of The Michael Miller Show, Michael Miller welcomes Carlos Ribeiro from the Greater Kendall Business Association (GKBA). They discuss how GKBA has connected local business owners, entrepreneurs, and professionals through networking and relationship-building for nearly 20 years. 🤝 They also highlight the upcoming Greater Kendall Business […]
Rock group to bring acoustic tour to Hershey: How to get tickets
"The intimate format brings fans closer to the lyrics and stories," the website reads, "connecting the catalog that built the band with the heavier, more emotionally exposed music defining them today.”
Winning Her Fight Against Endometrial Cancer with Broward Health
Scott Jordan, M.D., and Lizbeth Muller Sept 29, 2026 – Miami businesswoman Lizbeth Muller, 60, proudly holds the title of endometrial cancer survivor. The most common type of gynecologic cancer, endometrial cancer affects the lining of the uterus (endometrium). Lizbeth was diagnosed in 2023 after noticing some unusual symptoms. “I stopped having periods years earlier, […]
Virginia Tech leads multimillion-dollar project for women's health
A team of researchers from across the country will investigate the connection between hormones and vaginal tissue health in a project funded by the National Institutes of Health.
Meta is expanding its AI agent Muse to small businesses
The tech giant says the agent can help owners run their business and find new customers.
Where Healthcare Knows Your Name
See how two Health Mart pharmacies connect patients to medications, services and personalized support while helping keep care close to home.
Waltz Health and Fresenius Kabi Expand Direct Access to Biosimilars Through Waltz Connect Platform
/PRNewswire/ -- Waltz Health®, an EVERSANA® company developing technologies and services that support better-informed decisions on prescription care and...
Geotab receives Business Intelligence Group's 2026 Sustainable Transportation Award
/PRNewswire/ -- Geotab Inc. ("Geotab"), a global leader in connected operations, video telematics and AI-powered insights, today announced it has been named a...
Meta gives small businesses an AI agent that knows their work
Meta's Muse for Small Business connects business tools and accounts to help owners plan campaigns, manage tasks and get more done.
New laws make incremental tweaks to California’s mental health court, while bigger changes nixed
Gov. Gavin Newsom signed two laws designed to help CARE Court better connect Californians with mental health care.
Brisket is missing from Texas menus. A Democrat blames Republicans.
Vicente Gonzalez releases a new ad connecting high beef costs to the loss of an important South Texas tradition.
Magic in Store: This month, a witchy business will put you in the right spirit
Abby Minnich is a planetary scientist who puts complex concepts into plain language. “I like to connect with the earth,” she said. “Trying to figure out how things came to be. I would say that is my purpose, almost, trying to figure it out and sharing it.” Which leads her to visit metaphysical shops like […]
b.well Connected Health Awarded on TIME's List of the World's Top HealthTech Companies 2026 List
/PRNewswire/ -- b.well Connected Health, the infrastructure powering AI-driven consumer health experiences, today announced it has been named to TIME's World's...
Meta is expanding its Muse AI agent to target small businesses
The new Muse for Small Business connects to tools including Canva, Slack, and Intuit, and links to Meta ad accounts and business profiles
Penn and Community College of Philadelphia launch an academy for West Philadelphia businesses
The program, aimed at businesses with a connection to West Philadelphia, is tuition-free and helps business owners make plans to grow.
He Picked Up Trash For $4 An Hour. Now He Runs A $1 Billion Construction Business
How a 12-year-old’s door knock connected him with now billionaire mentor —and launched a fast-growing construction empire powering tech giants like Google, Apple and Microsoft.
How fishing is helping these Georgia men talk about mental health
Atlanta nonprofit Fishing the Good Fight uses fishing, the outdoors and community to help men connect, build friendships and talk openly about mental health.
Darby Fox warns of smartphone, AI dangers to youth mental health
Child and adolescent family therapist Darby Fox warns of youth mental health risks linked to early smartphone ownership and AI companionship. Fox explains studies connecting technology to higher eating disorder risks and loneliness.
FTSE 100 rises as AstraZeneca lifts healthcare sector
London's FTSE 100 rose on Tuesday, lifted by pharmaceutical stocks after AstraZeneca agreed to take a $2 billion stake in Summit Therapeutics to advance cancer research.
Meta launches Muse for Small Business as Zuckerberg pushes beyond consumer AI market
Following the success of its Muse personal AI agent, Meta is introducing a specialized version for small businesses.
‘The story is always the same’: NC officials confront broken involuntary commitment system
State leaders are pursuing reforms to cut unnecessary commitments, expand voluntary treatment and improve follow-up mental health care.
How an obscure government code unlocks opportunity for businesses
What rhymes with "snakes" and helps the government classify economic activity? NAICS — or the North American Industry Classification System. These codes categorize every industry from artificial turf installation to zucchini farming. But they’re not exactly easy to get. Today we look at one business’ quest for a NAICS code and what makes them so valuable. Fact checking by Leyla Doss. Your Next Listen — How to take the temperature of the US consumer Connect with The Indicator — Sign up for The Indicator’s weekly newsletter! — Buy the Planet Money book — Find our socials, YouTube and more! — For sponsor-free episodes, subscribe to NPR+ Support public media with NPR+ and enjoy perks for over 25 podcasts like this one. This show’s perks include sponsor-free listening. Learn more at plus.npr.org.
Anthropic warns of ‘existential risks to humanity’ from AI; AstraZeneca makes $2bn cancer drug tie-up
Rolling coverage of the latest economic and financial news
DEA Highlights the Integral Role of Forensic Science in Addressing the Synthetic Drug Crisis
As synthetic drugs continue to evolve and threaten American lives, DEA chemists and forensic science professionals play an essential role in helping the U.S. Drug Enforcement Administration identify emerging threats, connect evidence to investigations, and provide timely information that can save lives. From analyzing suspected fentanyl and other novel synthetic drugs to examining fingerprints and…
Connections: Sports Edition today: Hints and answers for Sept. 29, 2026, puzzle No. 736
Welcome to Connections: Sports Edition Coach — a spot to gather clues and discuss (and share) scores.
Harvard and Yale miss top 10 for computer science in 2027 US university ranking
Carnegie Mellon University, the Massachusetts Institute of Technology (MIT) and Stanford University tie for first in U.S. News & World Report's 2027 ranking of undergraduate computer science programs, released Sept. 22.
IBM is Building a Bigger Software Business. Can Its Balance Sheet Keep Up?
On September 24, International Business Machines Corporation (NYSE:IBM) announced two key capabilities designed to strengthen its digital asset infrastructure for tier-one financial institutions, governments, and regulated entities. In a new beta rollout, IBM Digital Asset Haven clients can connect to SWIFT’s blockchain-based shared ledger, linking into a cooperative network of over 12,500 financial institutions across […]
Political Connections Florida September 28 2026
Political Connections airs each weeknight at 7 p.m. on Spectrum News.
Gemini app adding Google Wallet integration for ‘personalized insights’
The latest Gemini Connected App is Google Wallet for “information and personalized insights based on your saved info.”
How to get involved in research at Eckerd College
Research at Eckerd College is not a commodity limited to students with prior experience, but instead something that is available and should be taken advantage of by all students.
Lamont, Fazio answer questions on business climate in Connecticut
NEW HAVEN, Conn. (WTNH) — The two men running for governor made their case to the Amity Chamber of Commerce Monday morning. News 8’s Kent Pierce was the moderator of a conversation betw…
Deadline Wednesday: Free business training for Central Oregon veterans, families
BEND, Ore. (KTVZ) -- Applications are open through Wednesday, Sept. 30, for Startup Training Resources to Inspire Veteran Entrepreneurship (STRIVE), a free eight-week business training program for military veterans and their family members. The in-person program is designed to assist military-connected entrepreneurs in developing skills to create and sustain small businesses. Offered in collaboration with
‘An opportunity to compete’: DC-area small businesses connect with big institutions
Small minority-owned construction businesses in the D.C. area connected with large contractors at an event at Georgetown University’s Capitol Campus Monday.
UConn Health Launches Cutting-Edge CAR-T Cell Therapy Program
New program brings potentially lifesaving treatment for certain blood cancers closer to patients in Connecticut and the region.
SLV community foundation receives major grant from Colorado Health Foundation
Three-year grant award to help connect nonprofits and residents, develop leadership programs in San Luis Valley, Colorado.
Meta’s Smart Glasses PR Cleanup Campaign Is in Full Swing
This year's Meta Connect was all about public perception.
2 men charged with arson in connection with fire at Kansas City business
Two men have been charged with arson in connection with a fire at a Kansas City business earlier this month.
Bose launched wired, yes, wired, earbuds with ANC for $99
The new Bose Noise Cancelling Wired Earbuds connect via USB-C and work with almost any device. Bose wants to get...
Compeer Rochester launches new campaign to end loneliness, improve mental health
Compeer Rochester just launched its "Scroll Less, Connect More" volunteer campaign. The group's research found American adults spend an average of 64 hours on screens per month. The campaign asks Rochesterians to put their phones on pause for just four of those hours to make a new friend and support a person struggling with a mental health diagnosis.
At Michigan Ross, A $4.9M Grant Is Connecting Business With Climate Action
Ross receives a $4.9-million gift to boost its environmental and sustainability programming and resources
CT Business Blend: Sept. 28, 2026
Hartford Business Journal’s Greg Bordonaro and WTIC’s Brian Shactman explore the people, companies and trends shaping Connecticut’s business scene every Monday at 8:30 a.m. on WTIC 1080 AM.
A $6 Lead And 15,000 Women Reveal A Healthcare Market Failure
Xella Health integrates multi-omic diagnostics, AI, and Oura wearable data into a connected precision health platform. CEO Kelly Lacob on closing the diagnostic gap.
Commentary: Civic preparedness has never been more critical
Comprehensive civic education is necessary to navigate our digital democracy and excel in postsecondary pursuits.
Justin Herbert and Patrick Herbert’s Unexpected Football Connection Revealed
Patrick Herbert spent years building his own football career away from his famous brother Justin Herbert. He went undrafted, worked through practice squad rosters, and kept fighting for his opportunity. That relentless grind reached a defining moment when Los Angeles promoted the tight end to the active roster. The move sets up a rare family […] The post Justin Herbert and Patrick Herbert’s Unexpected Football Connection Revealed appeared first on Gridiron Heroics.
Dominique Lewis, Spotlighted By Influential Women, Connects Life Science Expertise With Holistic Wellness
A Career Rooted in Scientific Knowledge, Personal Growth, and Meaningful Transformation Washington, DC – Dominique Lewis has developed a distinctive
How a UTC professor is helping first-year chemical engineering students explore career paths
What does a chemical engineer do? How can a student prepare for medical or pharmacy school? Where can students find people and resources to help answer those questions? Dr. Bradley Harris, head of UTC’s Department of Civil and Chemical Engineering in the College of Engineering and Computer Science (CECS), is helping students begin those conversations through A Moc’s First Year, a campuswide program designed to help incoming first-time, full-time undergraduates make connections to UTC, Chattanooga and one another.
Blumenthal, Lamont: Trump blocking CT grants for political reasons
Blumenthal and Lamont say $53 million in Connecticut energy grants remains withheld after court rulings found the terminations were illegal.
Politics and Pop Culture: A love-hate relationship
Recent shows and movies seem to have more overt political messaging. Is it necessary?
A $6 Lead And 50,000 Women Reveal A Healthcare Market Failure
Xella Health integrates multi-omic diagnostics, AI, and Oura wearable data into a connected precision health platform. CEO Kelly Lacob on closing the diagnostic gap.
ICE enforcement around healthcare facilities in Pa. leads to fears for immigrants of seeking care
Advocates warn that as word of raids near hospitals and medical centers spreads, so can fears of seeking healthcare services in immigrant communities. Medical workers too have warned that more aggressive immigration enforcement has led to immigrants delaying or refusing necessary care.
Students weigh in on rhetoric in Maine political advertisements
It is no secret that the Senate race in Maine is hotly contested. Republican incumbent Susan Collins and former Maine Senate President Troy Jackson, a…
What to Stream: Quavo album, 'East of Eden' series and 'Minecraft Dungeons II'
A limited series adaptation of “East of Eden” and a new album from Quavo are among streaming releases coming in October. “Teenage Sex and Death at Camp Miasma” premieres Friday
Connections: Sports Edition today: Hints and answers for Sept. 28, 2026, puzzle No. 735
Welcome to Connections: Sports Edition Coach — a spot to gather clues and discuss (and share) scores.
Xsight Group Featured in Harvard Business Review on AI Agent Orchestration Across Silos
HONG KONG, Sept. 28, 2026 /PRNewswire/ -- Xsight Group (known as Xsight), a Hong Kong–headquartered cross-border technology group founded in 2004, has been featured as a research case in "How AI Agents Orchestrate Work Across Silos," a special report published in the September–October 2026 issue of Harvard Business Review. The article examines how a new generation of AI systems can connect functions and reduce the coordination friction that slows companies down, citing Xsight's practice of decomposing complex cross-departmental decisions into modular tasks and building a layered agentic AI orchestration system as a valuable model for cross-border organizational coordination.
Former Don Pedro's manager arrested after allegedly robbing South Side restaurant, affidavit says
Blanca Velasquez, 43, was arrested last Tuesday and charged with aggravated robbery in connection with an aggravated robbery at Don Pedro’s.
Teyana Taylor’s Transparent 2026 VMAs Look Featured a Plunging Neckline and Dramatic Details
Teyana Taylor turned heads on the 2026 MTV VMAs red carpet in a transparent black look with a plunging neckline. See photos here.
Losing the Same Weight Didn’t Produce the Same Health Benefits
Among several diets tested in a clinical trial, a ketogenic diet produced the greatest improvements in liver and metabolic health. Losing the same amount of weight does not necessarily produce the same metabolic benefits. In a randomized clinical trial, three very different diets helped adults with obesity lose about 10% of their starting weight, but
Presley Gerber’s ex says they’re ‘connected for life’ in emotional tribute 1 week after his death
Gerber, the only son of Cindy Crawford and Rande Gerber, died of a “suspected overdose” at age 27 on Sept. 20.
What role does high school play in mental health? Feeling connected to other students and staff is key
By the time an Australian student is 15, they will have already spent as many as 11,000 hours at school. What happens here matters for their wellbeing.
PAHO Walk for Health brings together staff, families, partners and delegates ahead of 63rd Directing Council
Washington, D.C., September 27, 2026 (PAHO) — On the eve of the 63rd Pan American Health Organization (PAHO) Directing Council, PAHO staff, families, friends, delegates from Member States, partners and community members came together for the 2026 PAHO Walk for Health, highlighting the importance of physical activity, healthy environments and social connection.
Connections: Harps Food Stores, Freeman Health announce promotions
Recent Springdale-based Harps Food Stores promotions include Will McDoniel being promoted from meat and seafood category manager to director of AI strategy and innovation. NEW HIRES Healthcare Dr. Colin Carr...
Connections: Harps Food Stores, Freeman Health announce promotions
Recent Springdale-based Harps Food Stores promotions include Will McDoniel being promoted from meat and seafood category manager to director of AI strategy and innovation. NEW HIRES Healthcare Dr. Colin Carr...
Scientists Found a Hidden Brain Circuit That May Explain Why Heart Attacks Get Worse After They Happen
The story of a heart attack does not end when blood flow is restored. New research suggests the body continues a complex response after the injury, and scientists have identified a brain-connected pat...
Robert Pattinson reveals his favorite meme of himself: ‘It makes me feel like a boomer’
King of memes, Robert Pattinson, reveals his personal favorite of his many, many popular memes. His ‘Primetime’ director, Lance Oppenheim, also weighs in on meme culture and its deep connections to the film.
📚 The Inoculation Project 9/27/2026: Reading and Science
This week, we’re again helping a Connecticut elementary school teacher get some books and STEM materials, and a North Carolina high school teacher get materials for a most excellent lab.
Flying With Gamma-Ray Counters: Another Test Or Two Of The Radiacode Zero
Yesterday I traveled all day, moving my family back to Lulea from Padova. The trip is long because there is no direct connection from Venice to Stockholm (Norwegian has one, but I prefer to avoid them
Minecraft is getting its first new dimension in 14 years, and it's called The Sift
Mojang has announced The Sift, Minecraft's first new dimension in more than 14 years.
New York Jets Flight Connections 09/27/26
Happy Sunday, Jets fans! The Jets visit the Detroit Lions today looking to bounce back from a tough overtime loss to the Green Bay Packers. A win puts the Jets at 2-1 and would put the loss to Green Bay into the rear view mirror. This won’t be an easy game, but if the Jets […]
The GL.iNet Mango 2 Is A Pocket-Sized Wi-Fi Travel Router With VPN
With its slim design, easy setup, VPN support and multi-device connectivity, the Mango 2 is made for travelers who need reliable connectivity in a portable form factor.
Connections: Sports Edition today: Hints and answers for Sept. 27, 2026, puzzle No. 734
Welcome to Connections: Sports Edition Coach — a spot to gather clues and discuss (and share) scores.
Ireland's Controversial Nations League Fixtures: The Inescapable Connection Between Sport And Politics
On Sunday, the national men’s European football teams of Israel and the Republic of Ireland will face each other at a stadium in Hungary. A week later, they will meet once more, this time in Serbia. The very existence of these two games has created a lot of controversy, especially among Irish fans. Politics related […] The post Ireland’s Controversial Nations League Fixtures: The Inescapable Connection Between Sport And Politics appeared first on Stadium Rant.
Why rheumatoid arthritis pain may persist even when inflammation is under control
Pain and fatigue in rheumatoid arthritis can persist even after inflammation improves, with depression, poor sleep, obesity, smoking, and chronic pain potentially helping sustain symptoms. Researchers say identifying these hidden drivers could prevent unnecessary medication changes and lead to more personalized treatment.
Falcons offensive tackle fined by NFL for unnecessary roughness
The NFL has fined Falcons LT Jake Matthews $11,941 for unnecessary roughness
Blood test could gauge if a baby has a dangerous infection in 15 minutes
Feverish babies in hospital are often assumed to have a serious bacterial infection and are treated with antibiotics. But a test that gauges whether the infection is bacterial or viral, which tend to be milder, could prevent unnecessary drug use
Missouri State Football’s Growing Connection to the Lone Star State
Missouri State head coach Casey Woods and several players with Texas roots prepare to lead the Bears into a matchup against SMU in Dallas, marking the team's third consecutive trip to the state.
Sooners trying to get back in the game, trail 28-6 in third quarter
Mateer connects with Rocky Beers for Sooners first score: Mateer, still trying to shake off a tumultuous first half, connected with tight end Rocky Beers for a 17-yard score. OU
45th annual Catface Turpentine Festival is set for Saturday, October 3
From a parade and rosin potatoes to Turpentine soap and a street dance, the Catface Turpentine Festival promises a day of entertainment for the whole family. This year marks the 45th anniversary of the event, hosted by the Portal Heritage Society.
Minecraft Is Getting A New Dimension Called The Sift In 2027
The Sift will first be released with Minecraft Dungeons 2 later this month before arriving in the base game.
Minecraft Dungeons II’s New Dimension Coming to Minecraft Java & Bedrock Edition
At Minecraft LIVE, Mojang announced that the first new dimension in 14 years - The Sift - will be coming to both Minecraft Dungeons II and Minecraft Java & Bedrock Edition. Learn more inside.
The Camilla Foundation to host 3rd annual "Cultivating Hope: An Evening for Children's Health" on October 6
The Camilla Foundation will host its third annual "Cultivating Hope: An Evening for Children's Health" on Tuesday, October 6, 2026, at The Botanic Garden at Georgia Southern University in Statesboro. The public event will raise funds and awareness for children's mental health services in Bulloch County.
In science fiction thriller, civil engineer focuses on our vulnerabilities in the age of AI
J. Luke Bennecke's book, "Blackout" blends science fiction with real U.S. infrastructure vulnerabilities.
Minecraft LIVE September 2026 Live Report — All the News as It Happens
It’s time for another Minecraft LIVE, and this one is expected to feature some big reveals as Mojang’s all-conquering sandbox game heads towards the end of 2026 and beyond. Check out out live report for everything announced.
Germany coach Klopp support nation's plans to host Olympics
Germany coach Jürgen Klopp showed his support for the nation's plans to host Olympic Games with an emotional anecdote. "All my memories of sports actually begin with the Olympic Games," Klopp told broadcasters ARD.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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