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Rockford Park District Sports Facilities Generate $14.1 Million Annually
New data highlights Rockford Park District sports facilities as powerful economic engines that attract visitors, generate tourism spending, and elevate the region's national profile.
What are the health implications of the Everglades wildfires, and will World Cup spectators and players be affected?
Dr. Roberto Lucchini works with first responders exposed to carcinogens in the World Trade Center attacks. He discusses how airborne toxins from South Florida fires could impact residents, visitors.
The Role of Immigrants in the U.S. Health Care Workforce
This issue brief provides data on immigrants’ role in the U.S. health care workforce, including within key industries such as direct long-term care and the hospital workforce.
Number of Americans who afford high-quality healthcare has dropped
Only about half of US adults could afford their healthcare and had access to quality care last year, according to new data.
States file to stop DOJ from demanding patient data from providers
California and 18 other states are asking the court to bar the U.S. Department of Justice from accessing the protected health information of minor patients as part of a federal investigation into gender-affirming care.
Legislation overhauling college sports faces a major test in the Senate
A bipartisan bill top lawmakers and athletic leaders have described as the best chance to stabilize college sports is facing a key test in the Senate.
SpaceX wants to build AI data centers in space. Will it work?
The race to build data centers in space is gaining momentum as AI drives unprecedented demand for computing power. Orbital facilities could tap into abundant solar energy and avoid many of the environmental challenges faced on Earth. Yet space remains a harsh and expensive place to operate, with major hurdles including cooling, maintenance, radiation exposure, and orbital debris.
Analyst Perspectives on Oracle’s Strategy to Help Customers Secure Business Data against AI Threats
Oracle today announced its AI security strategy based on three principles: secure at source, secure at speed, and secure through resilience. To help customers accelerate and strengthen their security posture Oracle is making several of its most widely deployed and battle-tested database security, patching, testing, and lifecycle management tools available at no cost for a limited time, or at a 90% discount on one-year term licenses. This move has been positively received by leading industry analysts and reaffirms Oracle’s leadership in equipping enterprises to maximize their resilience in the face of increasing AI-era security threats.
Dentsu Expands Fandom Intelligence Globally to Guide Brand Partnerships in Entertainment
Little Black Book, Platform, first created in 2020, combines Japanese fandom data with new proprietary research across the US, UK, India and the Greater China market, covering 200 entertainment titles and more than 21,000 fans
Metro Health reports 94 heat-related illnesses in San Antonio since May
Metro Health has reported 94 heat-related illnesses from May through this Saturday, a reminder that dangerous temperatures can quickly become a medical emergency.
How many Americans can afford high-quality healthcare? A new poll finds the number has fallen
New data from the West Health-Gallup Affordability Index shows that only about half of U.S. adults could afford their healthcare and had access to quality care last year.
Poll: Only about half of Americans say they can afford quality healthcare
New data from the West Health-Gallup Affordability Index shows that only about half of U.S. adults could afford their healthcare and had access to quality care last year.
Vance, skeptical of foreign wars, becomes the face of Trump's tentative deal to end war with Iran
Vice President JD Vance has embraced the role of being the chief defender of the agreement he and President Donald Trump signed with Iran over the weekend.
Small Business Owner and Former Cultural Affairs Commissioner Jeannine Wisnosky Stehlin Launches Bid for Culver City Council
Small Business Owner, Former Cultural Affairs Commissioner, and longtime community volunteer Jeannine Wisnosky Stehlin today declared her candidacy for the Culver City Council. Wisnosky Stehlin is running to be a voice for residents and community members who want strong, collaborative leadership at City Hall. "People come to Culver City because the...
New Detroit restaurant, event center opens with focus on food, entertainment, and community
Fort Bend County to conduct aerial mosquito spraying amid public health emergency
Fort Bend County officials will conduct aerial mosquito spraying next week as part of an emergency effort to reduce mosquito populations and help protect residents from mosquito-borne illnesses.
Rumble Announces Realignment into Two Core Business Units and Renames Newly Acquired Cloud And AI-Infrastructure Business “Quake AI”
Post-merger, Rumble Cloud Renamed Quake AI, Integrating Northern Data OfferingsRumble to Remain the Video and Media Platform’s Core Brand NameCorp...
The economy looks steady on paper. Small businesses see something else.
New data shows small business owners are struggling with uncertainty, which could signal a wider economic slowdown.
iPadOS 27 Hands-On: Everything New for iPad
Like iOS 27, iPadOS 27 gains a smarter, more capable version of Siri, the Siri app, and new Apple Intelligence features in apps, but there are a few iPad-only standouts. Subscribe to the MacRumors YouTube channel for more videos. Siri AI on iPad has all of the same features as Siri AI on the iPhone, so it can access your personal data, search the web for answers, complete tasks in apps, and answer questions about what's on your screen.
Rumble Announces Realignment into Two Core Business Units and Renames Newly Acquired Cloud And AI-Infrastructure Business “Quake AI”
Post-merger, Rumble Cloud Renamed Quake AI, Integrating Northern Data Offerings Rumble to Remain the Video and Media Platform’s Core Brand Name Corporate Parent to be Renamed RUM Group Inc. and Will Oversee Two Business Units: Rumble and Quake AI LONGBOAT KEY, Fla., June 17, 2026 (GLOBE NEWSWIRE) -- Rumble (NASDAQ: RUM) today introduced a new business unit and legal name for the company following the closing of its acquisition of Northern Data AG (“Northern Data”). Effective June 18, 2026, under
FIU professor selected as a lead scientist aboard cutting-edge ocean research vessel
Mark Bond has been selected as a lead scientist for the maiden voyage of REV, one of the world's most advanced research vessels dedicated to ocean science and conservation.
Applications for business help in Detroit now open -- Here’s how it works
April business inventories rise 0.1%
CNBC’s Rick Santelli breaks down the latest economic data to cross the tape.
June 17 Playbook: Data Centers Scrambling PA Politics
🌞 It’s Wednesday! The halfway mark Headlines. Fight Over US Datacenters Is Scrambling Pennsylvania Politics. Energy Future A Defining Issue in Gubernatorial Race. PA Supreme Court Blasts Philly DA’s Office. “Charm Pricing” 🎶 Your Morning Pick Me Up. We’re Not Gonna Take It. Twisted Sister PA Weather☀️ Meadville | Mostly…
Marvel Rivals - The Super Hero Team-based PVP Shooter
Play for free Now!! Get ready to Ignite the Battle with Marvel Rivals!
April, May mark overdose death low in SF
April saw the lowest on record since 2020, according to preliminary data.
Trade association formed for data center, AI policies
The Arkansas Connected Communities Association (ARCC) announced Tuesday (June 16) its formal establishment as a 501(c)(6) trade association dedicated to advancing data center and artificial intelligence infrastructure policy in Arkansas....
Survey: Staff say school-based telehealth cuts behavioral issues
The new data comes from a survey by researchers at UNC Chapel Hill to assess the impact of school-based telehealth programs.
How to protect your property from an uptick in mosquitoes after rain, humidity
Proposed Mills 50 parking garage sparks debate over parking needs and business displacement
A proposed parking garage in Orlando’s Mills 50 district could bring hundreds of new spaces to an area known for crowded streets and limited parking.
Latvia pilots citizen engagement in research grant evaluations
Latvia has introduced an element of citizen engagement to the evaluation of nationally funded research grants. The aim is to both create more connections between science and society, and to improve the quality of its evaluations. The move comes as research funders across Europe are experimenting with ways to improve evaluation processes in the face of a sharpened focus on science’s impact on society. Evaluators of grant applications submitted to Latvia’s Fundamental and Applied Research Programme (FLPP), the country’s main research funder, will this year have the option of consulting citizen feedback on challenges the public thinks science should focus on to inform their decisions. “In recent years, both public discussions and policy-level debates in Latvia have highlighted the importance of demonstrating how publicly funded research contributes to society, the economy and the resolution of real-world challenges,” said a source at the Latvian Council of Science (LCS), which manages the FLPP. “At the same time, research institutions themselves expressed interest in improving the project evaluation framework while continuing to ensure that funding is awarded to the highest-quality projects,” the source added. The citizen input comes from a survey that was conducted between 25 February and 16 March 2025, to which 1,737 people responded. It gathered information on what the public views as problem areas for Latvia, and the role of science and technology in providing solutions to these problems. A summary of these responses has been included as an annex to the FLPP 2026 call for proposals that evaluators can refer to, purely in an advisory manner, when judging proposals. Results from the survey show that the main problem areas identified by the public were in healthcare and public health, followed by the development of new treatment methods and medicines, and then digital technology, data security and cyber security. At the bottom of the list was research aimed at acquiring new knowledge about the universe, matter and the laws of nature. Further analysis looked at the public view of the possible role of science in solving these problems. The survey charted 4,167 individual responses based on open-ended questions that were derived from the participants’ answers. The analysis again found that medical and health sciences topped the scoring, with 788 responses referring to the field. Humanities and the arts were bottom of the list, with 625. Digging further into the details, the survey suggests citizens are aware of and concerned about a number of research areas. This includes technologies and innovation to improve the environment or reduce pollution, the development of modern military technologies and cybersecurity tools, and the development and application of artificial intelligence, among others. “We hope this initiative will help strengthen public trust in science and create a more meaningful dialogue between researchers and society,” the LCS source said, adding that it offers benefits to researchers, evaluators and to the general public. More space for citizen engagement in evaluationsThere is a gradual but increasing use of citizen engagement in research evaluation processes around Europe, especially in healthcare, but it remains relatively rare, said Henry Sauermann, a professor at the European School of Management and Technology in Berlin and an expert in citizen science.“Given that we are at a point where citizen involvement is extremely limited, there is presumably space for more, but it's not that we should do it just because we want to do it,” he told Science|Business. He said some research lends itself better to having citizen input, and this usually tends to be on the applied end of the science spectrum where the public can offer useful feedback based on their experiences. He added that advising scientists on certain topics to study is also a useful approach, in the way that Latvia is doing. “The public does fund a lot of science, there's a lot of tax money going into this. We of course do want to preserve academic freedom, but it's also not unreasonable to incorporate more feedback or input from citizens where possible,” he said. Related articlesCitizen science: where, when, and how to let the public contribute to researchHow can Europe cope with a flood of AI-assisted research grant proposals?Data Corner: Horizon Europe’s AI, digital and data call success rate is 5.2%There are several ways of involving citizens in science funding. The most minimal way is having a few representatives on a panel, such as members of a patient group or union. The most direct way is crowdsourcing funding for specific projects. There is an increasing number of online platforms that allow the public to chip in to support scientific proposals.Sauermann studied this in a recent paper and found that it can have its uses, but it still is not clear if there are benefits to it. There are various assumptions linked to citizen engagement, for example that it increases public trust in science, or that it provides a representative view of what the public thinks about science. These are not necessarily true, Sauermann found. People who participate in engagement activities tend to already be very trusting of science, and, on the whole, it is generally the well-off and well educated who contribute, giving a narrow view of public opinion. On whether citizen input can help manage the increasing number of proposals that are being submitted due to assistance from AI, Sauermann is more sceptical. “The obvious answer to the flood of AI-written proposals is AI-driven evaluation,” he said, adding that it doesn’t mean citizen engagement shouldn’t be a part of evaluations in a well thought-out manner. Southern Denmark’s successful approachOne successful example of citizen engagement in science evaluations was implemented in southern Denmark. Between 2019 and 2025, citizens in the region were invited to vote to fund one of five pre-selected projects in the field of healthcare. The project, called A Healthier Southern Denmark, was a collaboration between regional authorities, the University of Southern Denmark, and two media partners. Over the seven years, there were 75,000 votes and significant public engagement online and on social media. “It was a bit of a wild project, we’d never done something like that before and we were a bit nervous about what would be said in the media about it. But actually, people were very positive,” said Anne Kathrine Overgaard, one of the main organisers of the project from the University of Southern Denmark. The university and its researchers have learned a lot from the experience, particularly about engaging with society and shaping their research to match real-world needs. This is important with Europe’s increasing focus on competitiveness and bringing innovations to market faster, Overgaard said. She hopes to see more citizen engagement in evaluation processes and in science more broadly. “For many years, citizen engagement has been a bit of an add-on to proposals, just to check a box. But I think things are changing,” she said. It’s less about citizens just gathering data and more “about the dialogue between the public and the scientists,” she said. The initiative ended last year as the team wanted to regroup to find fresh momentum. The development of AI and AI-written proposals has made Overgaard reflect on how the project could be reworked to help evaluators. She hopes to bring it back in the future. “It could be a good idea to try this initiative again in a slightly re-worked format,” she said.
Health Outcomes Data For Wearables Key To Medicare Coverage Expansion
Insurance coverage of wearables is spotty. This could soon change as Medicare begins a pilot to facilitate access to wearables while gathering data on health outcomes.
U.S. Ryder Cup Team Making Analytics Hires Before 2027 Event
Jim Furyk hired a new data analytics staff for the U.S. Ryder Cup team headlined by a prominent golf writer.
Got World Cup Fever? Send scientists your smartwatch data.
For fans, stress levels can skyrocket even 14 hours before kickoff.
Nasdaq Data Just Revealed a Surprising Truth Behind the Recent Surge in New Solo Businesses
A wave of AI-powered founders is reshaping what it means to start a company.
Exploring the Current Boundaries of AI for Science at TPC26
Last week’s TPC26 event brought together many of the world’s preeminent experts in using AI for science and engineering. The conference demonstrated that we have come quite far in just […]
How States with Health Care Cost Growth Targets Are Using Their Data to Develop Bold New Policy Approaches to Constrain Spending
News article: In a new Health Affairs Forefront article, Michael Bailit, January Angeles, and Rachel Block show how states with health care cost growth targets have
NASA Uses Machine Learning to Enhance Flash Flood Warnings
The Transient Artifact and Continuous Learning System (TACLS) leverages data from continuously operating satellite networks coupled with machine learning models to help meteorologists at the National Weather Service forecast flash floods more efficiently.
Highest possible ambition: science-aligned fossil fuel phase-out…
This brief presents some timelines on what transitioning away from fossil fuels could look like at both the global and national level, building on the Highest Possible Ambition scenario released last year by Climate Analytics and PIK. Focusing on fossil fuel demand, this brief provides data on the…
How the fight over US datacenters is scrambling this state’s politics: ‘We don’t want it’
Josh Shapiro, Pennsylvania’s governor, squares off with state lawmakers over the facilities powering an AI boom
KERRIGAN IN THE WASHINGTON TIMES: Virginia Should Not Tax Away its Data Center Advantage - Small Business & Entrepreneurship Council
“However it is framed, the practical effect would reach far beyond one industry. A tax on digital infrastructure is a tax on everyone, including working families, local governments and small businesses in every corner of Virginia.” In a June 15 Washington Times Op-ed, SBE Council President & CEO Karen Kerrigan documents the state of Virginia’s tech […]
Gross Medicaid Prescription Drug Spending
State level data on Gross Medicaid Prescription Drug Spending from KFF, the leading health policy organization in the U.S.
Dave & Buster's Entertainment, Inc. Stock 12‑Month Price Target Cut to $19.78, Implies 61% Upside
Explore more price target data and ratings for Dave & Buster's Entertainment, Inc. on the Forecasts tab, and track all previous and future analyst recommendations for Dave & Buster's Entertainment, Inc. in the dedicated News Flow.Select reference data provided by FactSet. Copyright © 2026 FactSet R…
Pathlock Partners with NTT DATA Business Solutions to Deliver Managed SAP Cybersecurity Services Worldwide
/PRNewswire/ -- Pathlock, a leader in Identity and Access Governance and ERP Security, today announced a global strategic partnership with NTT DATA Business...
Michigan mastodon to find new ‘habitat’ at Cranbrook Institute of Science
Elmer the mastodon will migrate from the upper floors of Levinson Hall at OCC’s Highland Lakes campus to Bloomfield Hills.
Hong Kong Science Park, SenseTime partner to build home-grown AI data centre
Project to be built in three stages, targeting 40,000 petaflops of computing power by 2030 to drive sector’s industrialisation.
Oracle champions sustainable and responsible AI at the Global Data Science and AI Summit, iLabAfrica Centre at Strathmore University, Nairobi
Oracle champions sustainable and responsible AI at the Global Data Science and AI Summit, iLabAfrica Centre at Strathmore University, Nairobi
Exclusive | Databricks Releases General AI Agents for Businesses
The data-analytics company is pushing further into AI applications for general work as it aims to carve out a place in the artificial-intelligence world.
Healthcare AI vendor suffers data breach, exposing patient records to hackers
Tennessee-based Xsolis said the incident occurred in January, and the sensitive data was from its clients. The company provides AI-powered case management software to hospitals and health insurers.
New report seeks to shed light on financial and health care needs of people in greater Hartford
Nearly one in four young adults in Hartford experience anxiety and depression, according to the DataHaven study. But they may not be getting the care they need.
Dave & Buster's Entertainment, Inc. Stock 12‑Month Price Target Cut to $20.11, Implies 63% Upside
Explore more price target data and ratings for Dave & Buster's Entertainment, Inc. on the Forecasts tab, and track all previous and future analyst recommendations for Dave & Buster's Entertainment, Inc. in the dedicated News Flow.Select reference data provided by FactSet. Copyright © 2026 FactSet R…
What's the average age of first-time homebuyers across Europe?
Fewer than seven in ten EU households live in owner-occupied homes. Euronews Business takes a closer look at the age at which Europeans buy their first home, which varies widely across the continent, based on exclusive data provided by RE/MAX.
Can $100 million overcome a Trump endorsement? What to watch in Tuesday's elections
An endorsement from President Donald Trump is worth a lot in Republican primaries.
Testing longitudinal gene–environment interactions
Nature Computational Science - A gene–environment interaction test (SAGELD) is developed to speed up large-scale genome-wide analyses using longitudinal data, facilitating novel discoveries...
Rochester Regional Health data breach: Letters sent to 18,600 patients after third-party vendor Xsolis hack
Rochester Regional Health patients received letters about a data breach, but the letters themselves looked like scams. The letters were sent by a third-party vendor and incorrectly identified the hospital system as "Rochester Regional Medical Center," which doesn't exist. Hospital officials confirmed to News10NBC the letters are legitimate despite the error.
Nominate your favorite Services business in San Antonio
Nominations for this year’s SA Picks are open, and we’re looking for the best Services Businesses in the San Antonio area!
NASA Flights Map Tropical Ecosystems, Water, Ice
Data from a NASA campaign in Panama and Peru will help communities prepare for tropical floods in cloud-covered areas, improve scientific understanding of
IBX team wins first place at Google Code for the Cure Hackathon with AI prototype to make prior authorization clearer and fairer
A team of associates from Independence Blue Cross’s (IBX) Advanced Analytics and Data Science department won first place at a recent Google Code for the Cure Hackathon in New York City. The event, run by Google Cloud, brings together teams to build real-world AI solutions to health care challenges. In just four hours, the IBX team designed and built a fully functional prototype that shows how AI can make prior authorization decisions clearer, more consistent, and fair for patients and providers.
What federal cuts to science funding could mean for the Great Lakes
Some groups that do research and collect data on the Great Lakes are facing existential threats as the annual budgeting process for the National Oceanic and Atmospheric Administration gets underway.
Duluth riders invited to ‘Bike for Science’ event collecting safety data for MnDOT
Riders can participate Wednesday at the Rose Garden at Leif Erikson Park.
Health Insurance Coverage of Adults Ages 19 or Older, Multiple Sources of Coverage
State level data on Health Insurance Coverage of Adults Ages 19 or Older, Multiple Sources of Coverage from KFF, the leading health policy organization in the U.S.
Health Insurance Coverage of Adults Ages 19 or Older
State level data on Health Insurance Coverage of Adults Ages 19 or Older from KFF, the leading health policy organization in the U.S.
Otherworldly music albums feature space weather data
A science-art team uses research data to make music featuring sounds of Antarctica and outer space
Booth Insights: Your AI strategy is the next business valuation test
Investors will put a premium on companies that use AI to deepen customer relationships, improve operations and turn data into an asset.
How Driscoll's Is Turning Berries Into A Data-Driven Business
Driscoll's CIO Sankar Chinnathambi explains how AI, real-time data and a company-wide digital overhaul are keeping the world's berries fresh from field to store.
Here Are Monday’s Best Wall Street Analyst Research Calls: Accenture, Caesars Entertainment, Datadog, Dupont, Epam Systems, Ferrari, Paychex, Rocket Lab, TeraWulf, and More
Pre-Market Stock Futures: Futures are exploding higher on news of a peace deal with Iran expected to be signed this Friday. This follows a historic Friday that saw the coming-out party of Space Exploration Technologies (NASDAQ: SPCX), widely known as Elon Musk’s SpaceX. The record-breaking size of the offering, raising $75 billion, the company’s debut ... Here Are Monday’s Best Wall Street Analyst Research Calls: Accenture, Caesars Entertainment, Datadog, Dupont, Epam Systems, Ferrari, Paychex, Rocket Lab, TeraWulf, and More
Here Are Monday’s Best Wall Street Analyst Research Calls: Accenture, Caesars Entertainment, Datadog, Dupont, Epam Systems, Ferrari, Paychex, Rocket Lab, TeraWulf, and More
Pre-Market Stock Futures: Futures are exploding higher on news of a peace deal with Iran expected to be signed this Friday. This follows a historic Friday that saw the coming-out party of Space Exploration Technologies (NASDAQ: SPCX), widely known as Elon Musk’s SpaceX. The record-breaking size of the offering, raising $75 billion, the company’s debut ... Here Are Monday’s Best Wall Street Analyst Research Calls: Accenture, Caesars Entertainment, Datadog, Dupont, Epam Systems, Ferrari, Paychex,
Trump administration's assault on climate science and ocean research
Scientists are sounding the alarm after the Trump administration said it plans to dismantle a deep-sea observation system that provides critical data on ocean health.
Business Associates Face Increased Regulatory Scrutiny as Vendor Breaches Soar
The healthcare industry has the highest rate of third-party data breaches out of any sector, according to the Verizon Data Breach Investigations Report In 2017, 13% of healthcare data breaches involved healthcare vendors. Fast forward to H1 2026, and that percentage has risen to 43%. With data breaches soaring, vendors are facing increased regulatory scrutiny, and new cybersecurity requirements are due for imminent release.
How Ohio State is helping the US men's World Cup players recover
Ohio State researchers are helping U.S. soccer players recover faster using data-driven methods.
After a lifetime in politics, a former Maine congressman finds his biggest fight at home
Mike Michaud avoided scandal for nearly 50 years in state and federal politics. So how did he wind up in one in a small northern Maine town?
After a lifetime in politics, a former Maine congressman finds his biggest fight at home
Mike Michaud avoided scandal for nearly 50 years in state and federal politics. So how did he wind up in one in a small northern Maine town?
Devoted dads and citizen science: The evolution of parental care in harvestmen spiders is uncovered
Citizen science data from the popular platform iNaturalist has helped uncover the evolution of parental guarding behavior in harvestmen spiders, as shown in research published in the Zoological Journal ...
No country should have to build its digital health future alone – now none of them will
WHO/Europe and Healthcare Denmark have signed a memorandum of understanding (MoU) to accelerate cooperation on digital health, health data, artificial intelligence (AI) and health system innovation in the 53 countries of the WHO European Region.
Period pain: Simple shopping swap for better pain relief, study reveals
Many women are buying less effective pain medication for period cramps, supermarket data suggests.
The #1 pop song from the year you graduated high school
Stacker pulled data from Billboard's year-end charts to compile a list of the #1 pop song for each year from 1946 to 2024.
Historic Basila Frocks building transforms into hub for small businesses, art
Users' opinion of T-Mobile reaches a new low after bombshell discovery
T-Mobile users were surprised to learn what the carrier is doing with their data.
Americans are living longer, increasing the need of geriatricians. Does Louisiana have enough?
As the baby boomer generation reaches older adulthood and average lifespans continue to increase, the number of geriatricians needed to meet demand is also rising. Here's where the data currently stands in each state.
Congo says 782 Ebola cases confirmed, two new health zones affected
The number of confirmed Ebola cases in Democratic Republic of Congo has increased to 782 after 72 new cases were documented in 24 hours, one of the biggest single-day jumps during the ongoing outbreak, government data showed on Sunday.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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