SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " Face " 8,047 found 🔀 AI-powered Shuffle
Lee, Niou face off ahead of Senate District 27 Democratic primary
Both Grace Lee and Yuh-Line Niou are progressives who favor taxing the rich, but oppose the city's plan for the district’s planned jail site as a replacement for Rikers Island.
Lee, Niou face off ahead of Senate District 27 Democratic primary
Both Grace Lee and Yuh-Line Niou are progressives who favor taxing the rich, but oppose the city's plan for the district’s planned jail site as a replacement for Rikers Island.
Do Michigan parents have a right to see everything in kids’ medical records?
In Michigan, parents may face limited access to certain medical records, such as substance abuse treatment, as their children get older. State Rep. Joe Aragona, R-Clinton Township, would change that.
Medline recalls nearly 50K procedure kits, including many used by cardiologists
This recall was put in place due to a risk of the included adhesive not working. Nothing needs to be returned, but clinicians should not use the adhesive that comes inside the procedure kits.
June 18 Vallejo/Vacaville Arts-Entertainment Source: Faces and Places
Sem Yeto High School Principal John McMorris announced plans to establish the Jamario Baker Legacy Award Fund to honor Jamario’s memory and support future students who demonstrate resilience, personal growth, perseverance, and…
Medtronic completes $550M acquisition of neurovascular company
Scientia Vascular, a medtech company focused on advanced stroke therapies, is now officially part of Medtronic.
Voters to head to polls in Georgia, Alabama, California and DC on Tuesday
One of the most watched races is the Republican Senate primary in Georgia, the winner of which will face Sen. Jon Ossoff
Left-wing distraction of Trump's UFC event falls flat as bitter celebrities mocked online
Celebrities including Bette Midler and Robert De Niro faced widespread online mockery for their anti-Trump concert meant to counter-program his UFC event.
"Three Women and Me" Launches a Bold New Health Media Platform Designed to Change the Conversation Around Women's Health and the Issues Families Face Every Day
Award-Winning Producer Charles Mattocks and Bionic Bloom's own Dr Angela Fisher- Join Heather Reilly Hiemstra, Dr. Jenny Vaughn-Curtman, and Dr. Cathleen Gerenger, for a Powerful New Television Series and Podcast Featuring World-Renowned Experts, ...
What Brendan Sorsby case reinforces: There are no rules in college sports
The Sorsby case was the NCAA’s Waterloo. If the NCAA was already staggered with the myriad problems it faces via NIL and the portal, the Sorsby case was the kill shot
World Cup 2026 schedule, live updates: Spain opens vs. Cape Verde; Uruguay debuts as Iran arrive in U.S. to face New Zealand
Spain and Uruguay open their tournaments Monday, while Iran's first match arrives amid heightened attention off the field.
Reflecting On Business Services & Supplies Stocks’ Q1 Earnings: Interface (NASDAQ:TILE)
As the craze of earnings season draws to a close, here’s a look back at some of the most exciting (and some less so) results from Q1. Today, we are looking at business services & supplies stocks, starting with Interface (NASDAQ:TILE).
DEPEND® AND DEION "COACH PRIME" SANDERS ENCOURAGE PROACTIVE CARE DURING MEN'S HEALTH MONTH
/PRNewswire/ -- This Men's Health Month, Depend®, the #1 brand of absorbent underwear, and Deion "Coach Prime" Sanders are encouraging men to take a proactive...
SK Life Science, Inc. Announces FDA Acceptance for Review of New Drug Application for Cenobamate Oral Suspension
Key Facts: FDA has accepted for review the New Drug Application (NDA) for an investigational oral suspension formulation of cenobamate for the treatment of...
Supreme Court dumps Trump aide Carter Page’s wiretapping suit against James Comey
The Supreme Court on Monday declined to take up an appeal from former Trump campaign adviser Carter Page who sued former FBI officials over flawed government surveillance he faced during the investigation into Russian interference in the 2016 election.
I Just Realized Why 'Sweet Magnolias' Star Heather Headley Looks Familiar and I Can't Believe It Took Me So Long
Heather Headley is back as Helen in Sweet Magnolias season 5, but there's a good chance you've seen her in another hit Netflix series before. Here's where you recognize the actress from and why her face feels so familiar.
Inside the unique challenges of military spouse entrepreneurs: 'Not everybody is going to understand this life'
Military spouses turn to entrepreneurship amid high rates of unemployment. They face high barriers to success, but a growing coalition is pushing for more help.
'Alf' star Anne Schedeen dies at 77, family highlights her 'burning hatred for Trump'
'Al'f actress Anne Schedeen has died at age 77, the star's family announced in an emotional Facebook post, saying she left behind 'burning hatred for Trump.'
Equip Exposition Dials Up Fun With Three Nights of Epic Entertainment For Attendees
/PRNewswire/ -- Equip Exposition, the award-winning international landscape, outdoor living, and equipment exposition trade show, announced today its 2026...
The $4 Billion Coffee Pod Business Faces Its Biggest Threat Yet
Billions of coffee pods are sold every year. Coffee giant Lavazza is betting that consumers are finally ready for a different approach.
Express Scripts sues Tennessee over PBM law that would close specialty pharmacy
The company called the state’s regulation of pharmacy benefit managers “shortsighted,” as it would force the closure of Accredo, a specialty drug dispensary that supplies drugs it says aren’t available anywhere else in the state.
Business Associates Face Increased Regulatory Scrutiny as Vendor Breaches Soar
The healthcare industry has the highest rate of third-party data breaches out of any sector, according to the Verizon Data Breach Investigations Report In 2017, 13% of healthcare data breaches involved healthcare vendors. Fast forward to H1 2026, and that percentage has risen to 43%. With data breaches soaring, vendors are facing increased regulatory scrutiny, and new cybersecurity requirements are due for imminent release.
An ancient piece of the moon found in Africa hints at a long-ago collision that turned the lunar surface molten
A meteorite shows evidence that an ancient crash on the moon 3.5 billion years ago was so powerful, it turned the surface molten.
Commentary: ‘Scary Movie’ cements Hollywood’s spoof comedy renaissance
When "Scream 7" arrived in theaters in February, the Ghostface turning heads wasn’t from the horror hit itself but from "Scary Movie." The trailer for the long-running parody series’ sixth
The politics behind the White House's UFC event
NPR's Steve Inskeep speaks with investigative sports journalist Karim Zidan about the politics of the UFC fight night at the White House.
'Risk of electrical shock' prompts recall of imaging systems
A handful of fluoroscopy units manufactured by GE HealthCare are the subject of a new recall by the U.S. Food and Drug Administration.
Factors making healthcare AI devices more likely to face recall
Deviations from a device’s intended use most often trigger FDA recalls, “highlighting unique safety challenges” in AI, experts write June 11 in JAMA.
Oprah Winfrey blesses new CT scanner she helped fund in Hawaii
Maui Memorial Medical Center, a 214-bed acute care hospital in Wailuku, celebrated the new computed tomography machine with its imaging team on June 8.
North Canyon Medical Center and All Access Hosted by Andy Garcia Highlight Rural Healthcare Infrastructure and Advanced Robotics
As rural medical facilities face increasing operational challenges, North Canyon Medical Center joins the award-winning series, "All Access Hosted by Andy Garcia," to explore how technical innovation and organizational agility stabilize local economies and healthcare access.
Cape Verde XI vs Spain – Predicted lineup and team news
Cape Verde face Spain in Atlanta on Monday to make absolute World Cup history.This monumental match represents their first-ever appearance at the global finals, completing a remarkable journey. The Bl...
Best photos from UFC 250 spectacular at the White House
President Donald Trump attended UFC 250 on Sunday as the event faced weather delays but delivered fast action.
UFC White House live blog: Ilia Topuria vs. Justin Gaethje
Ilia Topuria and Justin Gaethje face off at UFC White House
Trump admin says Anthropic's 'recklessness' triggered export controls on latest AI models
Anthropic's Fable 5 AI model faced export controls after a senior administration official says the company's "recklessness" in addressing vulnerabilities damaged government trust.
Trump marks 80th birthday with UFC fight at the White House
President Trump is celebrating his 80th birthday with a UFC fight on the White House lawn. A closer look a the political message behind the event and why some Republicans are uneasy.
UNC vs. West Virginia live blog, updates, highlights and more
The Tar Heels face West Virginia in the College World Series winners' bracket. Follow along on our live blog.
World Cup 2026: How Scientists Helped Engineer The Perfect Soccer Field
Ahead of the largest World Cup in history, researchers spent years testing grasses and stadium conditions to create consistent playing surfaces across climate zones.
Marin Voice: Addressing LGBTQ+ mental health needs requires affirming care
LGBTQ+ young people are more than four times as likely to attempt suicide than their peers. Queer individuals face higher rates of anxiety, depression and suicide — not because of who we are, but because of the stigma, discrimination and r…
Menopausal hormone therapy linked to stronger bone health
Women on menopausal hormonal therapy face a decreased risk of low bone mineral density compared to those not using it, according to a study being presented Sunday at ENDO 2026, the Endocrine Society's annual meeting in Chicago, Ill.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
World Cup: Undav adds Germany sixth after early Curacao hope
Listen to BBC Radio 5 Live commentary and follow live text coverage as Germany face Curacao in World Cup Group E.
Emory appoints Saby Mitra to lead Goizueta Business School
Emory appoints Saby Mitra to lead Goizueta Business School
🎥 Nmecha’s fabulous goal gets Germany up and running 🔥
Germany face Curaçao in their opening match of this World Cup.In their first-ever appearance, Curaçao tried to score and make even more history.Unfortunately, the start of the match did not go as pl...
Nigel Farage vows to ban foreign nationals from social housing
The Reform UK leader says tenants would have three months to find a new home or face potential deportation.
Cal Fire expands aerial fleet amid jetfuel concerns
Cal Fire is enhancing its firefighting capabilities with new aircraft and increased staffing as it prepares for another challenging fire season in California, even as the state faces budget issues and uncertainty around fuel this summer.
Trump endorses Rep. Mike Collins ahead of GOP Senate runoff in Georgia
President Donald Trump on Sunday waded into the Georgia Republican primary for Senate, endorsing Rep. Mike Collins just days before the congressman faces off against Derek Dooley in a runoff election.
Italy’s Meloni faces a far-right dilemma as 'Il Generale' Vannacci rises
Roberto Vannacci, a former Italian army general, is shaking up Italy’s political scene with his new party, Futuro Nazionale
A TALE OF TWO DEVILS
AC Milan will face Manchester United in an international friendly on Saturday, August 15. The Rossoneri will be in action at the Tarczyński Arena in Wrocław just before the start of the new Serie A ...
Italy's Meloni faces a challenge from the right for the first time
Roberto Vannacci, a former Italian army general, is shaking up Italy's political scene with his new party, Futuro Nazionale.
Italy’s Meloni faces a far-right dilemma as 'Il Generale' Vannacci rises
Roberto Vannacci, a former Italian army general, is shaking up Italy's political scene with his new party, Futuro Nazionale | KNX News 1070 AM
Politics chat: Trump promises end to Iran war; White House to host UFC fight
President Trump is again promising an end to the war with Iran.
Tuberville faces renewed residency challenge in run for Alabama governor
Alabama Republican Party leaders will hold a hearing Sunday on whether U.S. Sen. Tommy Tuberville meets the residency requirement to run for governor
Tuberville faces renewed residency challenge in run for Alabama governor
Alabama Republican Party leaders will hold a hearing Sunday on whether U.S. Sen. Tommy Tuberville meets the residency requirement to run for governor.
UFC Freedom 250 Final Face-Offs
During Saturday's UFC Freedom 250 Ceremonial Weigh-In at the Lincoln Memorial, the fighters competing on Sunday's historic event at The White House faced off with their opponents a final time. The event takes place on the South Lawn of the White House and is headlined by a lightweight title ...
Dooley campaigns with Kemp in Middle Georgia as lawmakers allege 'pay-to-play politics'
Derek Dooley is making some of his final pitches to voters in Middle Georgia as the U.S. Senate runoff inches closer to Election Day, and his campaign faces...
From the mat to Mount Elbert, Summit County’s female athletes find success in male-dominated sports
Jess Gresho’s nails are usually painted pink. She often has glitter on her face, and her athletic gear — from her ski pants to her running shoes — boasts bright colors and funky patterns. But...
Hundreds help kick off first ever Utica Unity Weekend
Face painting, cotton candy ring toss and more greeted children at Carnival Day the Utica Recreation Center on Saturday — and that was just one of the three days dedicated to Utica Unity Weekend, hosted by the city Youth Bureau and several community organizations.
Phillies Face Outfield Crisis After Adolis Garcia's Season-Ending Injury
The Philadelphia Phillies have a decision to make after Adolis Garcia injury news.
DA District 23: Incumbent Adam Panter, Mayor Daniel McClure clash over politics, experience
In Lincoln and Pottawatomie counties, incumbent DA Adam Panter faces a June 16, 2026, GOP primary challenge by McLoud Mayor Daniel McClure.
Resellers asking high prices for Mamdani's affordable World Cup shirts
The NYC-themed jerseys have popped up on sites like Facebook Marketplace and eBay, where sellers are looking for as much as $999.
‘Legislated out of business’: TN dispensaries face ‘difficult decisions’ ahead of new statewide THCA ban
Some Middle Tennessee hemp retailers may not be able to continue operating after June 30, as a new prohibition on THCA products takes effect.
Steam machine reportedly sent to reviewers as embargo date and package contents leak
According to a new leak, the first Steam Machine review units may already have been shipped to reviewers and content creators. The rumored review embargo date and possible package contents have also surfaced.
Platner's 'deranged' response to Musk becoming a trillionaire sparks online outrage: 'Loserthink'
Maine Democratic Senate candidate Graham Platner faces conservative backlash after posting about Elon Musk becoming the world's first trillionaire.
Sindhu faces Yamaguchi in the Australian Open semis; Archery World Cup continues: Indian Sports LIVE, June 13
Here are all the updates from Indian sports on June 13, 2026.
Divorcees and widows share concerning mental health trait, researchers find
New research from Norway finds divorcees and widows may face higher mortality risk than those who remain coupled, highlighting social disconnection.
It’s my tree. Why can’t I cut it down?
Can the government stop you from cutting down your own tree? In many towns and cities these days, removing a tree now requires a permit. You might have to pay a fee, or promise to plant replacement trees. But sometimes, the city won't let you cut down the tree at all, even a tree in your own backyard.That's because trees are important for air quality, for flood control, and for public health. They help keep neighborhoods cool on hot days. But some think that tree protection laws have gone too far — that they might even be unconstitutional.On today's episode, it's the latest showdown between property rights and local zoning laws. Typically, towns and cities enjoy a lot of power when it comes to zoning and permits. They can ban certain types of buildings. They can make you paint your house a certain color. But can they make it illegal to cut down a tree? And what does it mean to "own" a piece of property anyway?Support:Planet Money+Read: Our book: Planet Money: A Guide to the Economic Forces That Shape Your Life Our weekly longform Planet Money newsletterOur weekly Indicator round-up newsletterFollow: InstagramTikTokYouTubeFacebookThis episode of Planet Money was hosted by Jeff Guo and Amanda Aronczyk. It was produced by James Sneed and Emma Peaslee, edited by Jess Jiang, and fact-checked by Vito Emanuel. It was engineered by Robert Rodriguez and Cena Loffredo. Alex Goldmark is our executive producer.
ACA Enrollment Could Fall By 5 Million As Enhanced Health Insurance Subsidies Expire
Millions of Americans face higher health insurance costs as enhanced ACA subsidies expire. New projections show marketplace enrollment could fall by 5 million people.
New degree focus helps health professionals boost their communication skills
Communication plays a critical role in nearly every aspect of health and wellness. It shapes how patients understand information, how teams collaborate and how health organizations engage the communities they serve. But communication is rarely the primary focus of professional training. As health care and wellness organizations face increasingly complex challenges, professionals need advanced communication skills to navigate change, foster understanding and improve outcomes.
FDA clears new computer-assisted device for removing clots in stroke patients
The Thunderbolt device from California-based Penumbra uses modulated aspiration to detect and remove blood clots. Back in January, Boston Scientific agreed to acquire Penumbra for approximately $14.5 billion.
Nissan's Nostalgic 2027 Z Gets More Than Just A New Face
As the refreshed Z arrives in showrooms, Nissan honors its roots, while packing in a host of modern upgrades, like new colors inside and out.
Redo TAVR with balloon-expandable valves linked to positive outcomes, key improvements
Researchers tracked real-world data from more than 140 patients who originally received a transcatheter heart valve from Edwards Lifesciences, Medtronic or Boston Scientific.
Cuba opens more sectors to private business
Cuban President Miguel Diaz-Canel on Friday announced greater freedoms for small businesses across the country, as the communist government takes steps to liberalize the island's economy in the face o...
Where to watch New York Yankees vs. Toronto Blue Jays: Live stream, start time, TV channel, odds for Friday, June 12
The Yankees and Blue Jays face off in Toronto.
Workplace benefits face cuts as costs rise
Companies are trimming benefits as health costs and AI spending climb.
Notion Is Migrating to SwiftUI, Apple Confirms at WWDC
Apple this week confirmed that Notion is migrating its user interface to SwiftUI, citing the app's desire for greater performance and UI consistency than its existing web-based stack can deliver. Notion is a productivity app that combines notes, documents, databases, and project management tools in one place. Users can create pages containing text, tables, kanban boards, calendars, and more, and organize them in a flexible hierarchy.
Meta's Facebook and Instagram hit by outages
Facebook and Instagram users reported issues with accessing the platforms, according to the third-party outage-tracking website DownDetector.com.
The Feed: From Bryson DeChambeau to Justin Thomas, Bob Does Sports continue to land YouTube golf’s biggest fish
A big week for Bob Does Sports, Brad Dalke faces this alma mater and Luke Kwon heads to ... Ohio? The Feed recaps YouTube golf's best videos of the week.
Zelda: Ocarina Of Time Remake Officially To Be Unplayable For Millions
Millions of Zelda fans face heartbreak as the highly-anticipated Ocarina of Time Remake is set to be unplayable for those who didn't upgrade.
Brendan Sorsby isn’t a victim. He’s the latest face of America’s public health crisis
Texas Tech QB's injunction may allow him to play, but the problem remains: Online betting and a growing gambling addiction among young men.
Nintendo wanted to block Palworld — now it faces a 0% chance and a measly $30K payout
Public record shows the Nintendo v Pocketpair case is practically wrapped up and the best Nintendo can hope for is $30k chump change
International experts issue new MRI-based prostate cancer screening guidance
The exam should be performed on patients with greater than 10 years of life expectancy and between the ages of 50 and 70, with earlier imaging recommended for black men.
House committee votes to halt prior authorization pilot impacting radiology services
Lawmakers have opted against authorizing funding for the Wasteful and Inappropriate Service Reduction Model, citing concerns it will overburden patients and providers.
South African pundits stunned silent after team’s performance against Mexico
The World Cup did not get off to a hot start for South Africa on Thursday. The 2010 World Cup host faced off against one of this year’s host nations, Mexico, to kick off the 2026 World Cup, and it was never a contest. From the jump, the Mexican team looked dominant, scoring in the…
Protecting health after earthquakes: learning from a community-centred approach in Türkiye
In the hours and days after an earthquake, communities face devastating loss, displacement and profound disruption of daily life. In the weeks and months that follow, new health risks can quickly emerge that compound the immediate impacts. These continue to evolve over time.
Constantino leans into Trump support, business record in NY-21 Republican primary
Constantino is touting his endorsement from President Donald Trump in the race to represent NY-21. He will face Robert Smullen in the Republican primary.
iOS 27: All the New Health and Fitness Features
Apple was rumored to be working on an AI health service, but it was scrapped well before the iOS 27 beta came out. It could resurface in the future, but for now, there are a handful of health and fitness changes in the update. Design Apple redesigned the Browse section of the Health app, and it now uses a card-style interface instead of a list. It is more colorful and easier to see the different categories.
Radial Entertainment Names Brendon Thomas As Chief Revenue Officer
/PRNewswire/ -- Radial Entertainment, operator of the largest independent catalog of film and television in the industry, today announced the appointment of...
COVID pandemic’s effect on nurse staffing confounds linear expectations
Many or most who left their jobs in the early 2020s—whether for other nursing jobs or entirely new work—were thinking about doing so prior to the pandemic.
Dodgers vs. Pirates game chat
Justin Wrobleski and the Dodgers face the Pirates before heading off to Chicago for a three-game set with the White Sox. Thursday’s game info
Cleve Moler, Who Unlocked the Power of Computing for Millions, Dies at 86
He built interfaces that allowed engineers, scientists and everyday people to solve difficult problems without having to write the underlying code.
Death after TAVR: New data support use of better patient assessments
A vast majority of patient deaths in the first year after TAVR have nothing to do with heart health. Could care teams be doing more to identify high-risk patients?
A sign of the times? Two more Riverside restaurants closing their doors
Two more Riverside restaurants are closing their doors, sharing the sad news on Facebook.
Douglas County and Children’s Hospital Colorado partner for new youth mental health crisis services
Today’s youth face a fresh set of expectations and societal pressures that can be difficult to manage. That’s why the Douglas County Board of County Commissioners approved an agreement with…
Leadership vacuum plaguing U.S. health agencies
A wave of firings and resignations at the highest levels of the CDC and the FDA suggests the Trump administration may be pivoting away from facets of the "Make America Healthy Again" movement. NBC News' Aria Bendix reports.
Scientists reveal surprising mechanism behind Venus flytrap’s rapid snap
Intricate tests show hair-trigger detection causes cells on outer surface of leaf to soften, prompting closure
SkyBlue Cinematix Enters Türkiye, Bringing Its Global Content, Brand Integration and Entertainment Ecosystem to One of the World’s Leading Production Hubs
As part of its Türkiye launch, SkyBlue Cinematix has appointed two highly experienced media executives to lead its local operations, effective June 1, 2026.ISTANBUL, Türkiye, June 11, 2026 (GLOBE NEWSWIRE) -- SkyBlue Cinematix, the entertainment division of SkyBlue Media Group, today announced its official entry into the Turkish market, marking another major milestone in the company’s global expansion strategy. By establishing its presence in one of the world’s most influential television and fi
Tuffy Latour Elected Vice President of Sport on IBSF Executive Committee
SALZBURG, AUSTRIA (June 11, 2026) – During the ongoing 2026 International Bobsleigh & Skeleton Federation (IBSF) Congress, USA Bobsled/Skeleton (USABS) is proud to celebrate the election of longtime coach and leader Tuffy Latour to the IBSF Executi...
CD&R Engages Former Enovis CEO as Operating Advisor — Clayton Dubilier & Rice, LLC
We are a global private equity manager that invests in and builds valuable businesses.
INTERVENT International and Brand Engagement Network Launch INTERVENT Health AI, Inc., Combining 25+ Years of Clinically Validated Health Coaching with Enterprise-Grade Conversational AI
/PRNewswire/ -- Brand Engagement Network Inc. (NASDAQ: BNAI) ("BEN" or the "Company"), a provider of secure, enterprise-grade artificial intelligence for the...