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High gas prices have voters switching parties and voting for the first time
Gas prices are reshaping voter attitudes in a longtime Republican Georgia county, with some backing Democrats while others remain firmly loyal to Trump.
The Witcher 3 Remastered Crushes GPUs With Path Tracing, but Free Mod Claws Back Up to 30% Performance
Following its surprise announcement during this year's gamescom Opening Night Live, The Witcher 3 Remastered is now available on PC, PlayStation 5, Xbox Series X|S, and Nintendo Switch 2. While the number of improvements to gameplay is staggering and well thought out, what most were looking forward to was the visual uplift, which includes very demanding path tracing support on PC. Thankfully, a mod has already come to the rescue, as it did after the launch of the Next-Gen update, optimizing both ray tracing and path tracing for better performance with minimal loss of quality. "Faster RT/PT in The Witcher […]
County commissioners approve switch to NDPERS for employee health insurance
Some employees were disappointed that employee contributions were not decreased across the board, as the county may have excess health insurance funds budgeted for next year.
Star Fox 1.2.0 update out now, patch notes
Star Fox for Nintendo Switch 2 just received a major version 1.2.0 update, and the full patch notes can be found here.
The Witcher 3 Remastered showed 38 FPS with DLSS 5 versus 68 FPS for the Next-Gen version
Detailed performance and visual quality measurements of the updated version have appeared online. The Witcher 3: Wild Hunt Remastered using...
How to prepare your Samsung Galaxy for the One UI 9 update
With Samsung's One UI 9 rollout chugging along the globe, there's no better time to make a few quick checks before you make the switch.
US drivers are finally getting the adaptive headlights Europe has had for years
Rather than switching between high and low beams, ADBs can dim or shut off only the parts of the beam that would reach another driver's eyes while...
Nintendo shares Zora’s Domain footage from Zelda: Ocarina of Time remake
It’s not too long now until we can all get our hands on the eagerly-anticipated The Legend of Zelda: Ocarina of Time remake for the Nintendo Switch 2 as it launches on 5th November. Today…
My husband and I met at work; then I switched careers
I met my now-husband while we were working together at the same place in similar jobs as teachers. A few years later, I switched careers and fields.
PS5 Jailbreak Exploit For Systems Running July 2026 Firmware
According to those who have installed the new Relapse exploit, it works with everything from Marvel's Wolverine to The Witcher 3: Remastered
GTA 5 Modder Cancels Nintendo Switch Port Just Days Before Launch After Previously Taunting Rockstar: 'I Am Thankful For Take-Two's Mercy'
The creator behind the planned port will not release any code or assets online in order to avoid a possible lawsuit
‘The Witcher 3: Wild Hunt – Remastered’ Hits A Metacritic Review Score Record
‘The Witcher 3: Wild Hunt – Remastered’ has arrived with such good reviews it has actually tied a 2026 record. Here's the score and what critics are saying.
Magic in Store: This month, a witchy business will put you in the right spirit
Abby Minnich is a planetary scientist who puts complex concepts into plain language. “I like to connect with the earth,” she said. “Trying to figure out how things came to be. I would say that is my purpose, almost, trying to figure it out and sharing it.” Which leads her to visit metaphysical shops like […]
Rumor: Nintendo Switch Online app datamine points to potential event gifts system for Switch 2 and Switch
Fans are discussing the possibility of a new event gifts feature for Nintendo Switch 2 and Switch following the latest datamine. X user @idocode01 shared the latest findings from a Nintendo Switch Online app update, pointing to the functionality. What we know so far is that there can be multiple gift events on at the same time. Additionally, each event...
ServiceNow says AI agent kill switches need business context
ServiceNow explains why shutting down rogue AI agents instantly can cause more harm than the agent itself; business context must be the guide.
Google Will Support ChromeOS Until 2034 As It Shifts To Googlebook OS
Some recent Chromebook devices will be able to switch to the new operating system.
Every Upgrade In ‘The Witcher 3: Wild Hunt
'The Witcher 3: Wild Hunt - Remastered' is out Sept. 29, and now we have the full patch notes for everything that has changed in the game.
Staff killed and wounded in Russian strike on Kyiv’s science academy
Moscow’s jet-powered drones pummel Ukraine’s capital in switch to daytime attacks
Mario Nintendo Switch Games Now Available for 85 to 90% Off on eShop
Mario Nintendo Switch games are now available for 85 to 90% off, until October 8, courtesy of the Nintendo eShop.
Famitsu sales (9/14/26 - 9/20/26) - first week sales revealed for Fire Emblem: Fortune's Weave
The latest Japanese hardware sales from Famitsu are as follows: Switch 2 – 34,341 PS5 Digital Edition – 7,441 Switch OLED – 2,634 Switch Lite – 2,248 Switch – 823 PS5 Pro – 219 PS5 – 187 Xbox Series X – 136 Xbox Series X Digital Edition – 116 Xbox Series S – 19 For comparison’s sake, here are the...
Turtle Beach Afterglow review: A Switch 2 controller with the full RGB treatment
This is for the gamer who wants RGB everything.
CD Projekt Releases Official List of All the Improvements in The Witcher 3: Wild Hunt
CD Projekt has released an official list of all the improvements made for The Witcher 3: Wild Hunt — Remastered.
Scientists Test an Unexpected Sleep Aid Made From Tree Roots
A pilot study suggests that oil from underused Hinoki roots could be used in scented products for relaxation. Falling asleep can be compared to easing down a dimmer switch, with brain activity gradually shifting as sleep deepens. Researchers studying Hinoki, or Japanese cypress, are exploring whether its scent could help smooth that transition for women
PSA: The Witcher 3 Remastered File Size And Release Time Confirmed, Separate Purchase Required
No automatic upgrades here
The Witcher 3 Remastered a 45GB PS5 Patch, Release Times Revealed
An update to current PS5 version
Experimental Emulator Brings Nintendo Switch Games to Jailbroken PS5 Consoles
An unofficial port of the Eden Nintendo Switch emulator is now running natively on jailbroken PlayStation 5 consoles. Developer BlackBearReloaded released ProsperoEden, which adapts Eden, itself a fork of the now-defunct Yuzu project, to run directly on Sony's hardware as homebrew rather than...
Witcher Dev Reveals Why CD Projekt Red Doesn't Do Crossovers In Its Own Games
A Geralt-inspired skin is coming to Diablo 4, but don't expect Diablo characters in The Witcher 3 Remastered
Nintendo Switch emulator now runs natively on jailbroken PS5, Cuphead reaches 60 FPS
ProsperoEden is an experimental native PS5 port of the Eden Nintendo Switch emulator, with several games already reaching gameplay on jailbroken consoles.
Nier: Automata director made the game he wanted to make and tried to stay hidden from Square Enix
In a new interview the eccentric Nier: Automata director Yoko Taro has said that the game turned out just how he wanted it, but he was also cautious to stay as far away from Square Enix as possible to…
Terrell Williams making impact with Patriots after beating prostate cancer
Williams, who switched roles after beginning last year as defensive coordinator, would be the favorite for a Comeback Coach of the Year award, if it existed.
Court Orders Reddit Moderator to Pay Nintendo $4.5 Million Over Switch Piracy
A federal court in Washington has ordered Reddit moderator James "Archbox" Williams to pay Nintendo $4.5 million in damages over alleged Nintendo Switch piracy. US District Judge Lauren King granted Nintendo's motion for default judgment in full on September 23, along with a permanent injunction...
The Witcher 3 Remastered Download Size, Global Release Times and Review Embargo Lift Dates Revealed
In case you missed the big announcement at gamescom last month, CD Projekt RED is set to unleash The Witcher 3: Wild Hunt Remastered this coming week, and it'll be…
I wasn't sure about Googlebooks, but after playing with two Snapdragon-powered laptops, I'm actually considering switching
The best of Android and ChromeOS, together.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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US court orders Redditor to pay Nintendo £3.4m over Switch piracy
A US court has ordered Reddit moderator James 'Archbox' Williams to pay Nintendo £3.4 million after he ignored a lawsuit over pirated Switch games.
How a baby business survived China and Canada tariffs
Garett Senez's company Quark Baby is based in Canada and manufactured in China. The tariffs required him to switch up his supply chain to survive.
"And, Now... An Evil Has Appeared" - Nintendo Releases Extended Zelda: Ocarina Of Time Switch 2 Clip
Here's another look at Ganondorf
Video: Digital Foundry Delivers Its Tech Analysis Of Fire Emblem: Fortune's Weave
Fire Emblem dedicated Switch 2 release is here
Next Week on XBOX: New Games for September 28 to October 2
Minecraft Dungeons II, Gears of War: E- Day Premium Edition, Ace Combat 8: Wings of Theve, The Witcher 3: Wild Hunt — Remastered, and more coming soon to XBOX.
Ubisoft Switch eShop Sale Now Live, Up To 90% Off
Assassin's Creed Shadows! Mario & Rabbids! Rayman!
Woot's New 'Fall in Love with Video Games' Sale is Even Better Than Nintendo's Customer Appreciation Sale for Switch 2 Deals — Here's How to Get an Extra 30% Off Everything
Woot's new 'Fall in Love with Video Games' sale includes the best Switch 2 console deal of the year so far, but it expires before the end of the day (September 25, 2026).
Nintendo of America awarded $4.5m in lawsuit from Redditor for pirating Switch hardware and software
James C. Williams, also known as 'Archbox,' ordered to disable access to online shops offering pirated Switch games and social media accounts linked to piracy
Square Enix Shows Off Exclusive Sleeve For Dragon Quest XI S On Switch 2
Available with the "packaged version" in Japan
Falcons – Packers instant recap: Making the Lambeau leap
It started off bad, and after the first two weeks of the season, that led many of us to brace for the worst. Michael Penix Jr. threw an interception, the team allowed a quick scoring drive for the Packers, and trouble seemed to be on the horizon. Then the switch flipped, the Falcons discovered what […]
Unicorn Overlord director Takafumi Noma announces fantasy IP IGNISPHERE and action RPG DAWNGAZER for PS5, Switch 2, and PC
Publisher Good Smile Company and developer Monochrome Corporation have announced new fantasy intellectual property IGNISPHERE, and the first game set in that world, DAWNGAZER, led by Unicorn Overlo…
Ubisoft hosting new Nintendo Switch 2 and Switch sale, lowest prices ever for Assassin's Creed: The Ezio Collection, Rayman: 30th Anniversary Edition, more
Ubisoft is celebrating its 40th anniversary with a brand new sale on the Nintendo eShop, which includes games like Assassin’s Creed: The Ezio Collection, Rayman: 30th Anniversary Edition, and more at new low prices. Other notable releases are included as well. You can save big on the Mario + Rabbids series, The Rogue Prince of Persia, and more. The full...
Entire Prince of Persia: The Lost Crown Game Available to Play for Free in Nintendo Switch Demo, But There’s a Catch
Players who haven’t yet experienced Prince of Persia: The Lost Crown can play the entire game for free right now on Nintendo Switch and the Nintendo Switch 2 until September 30.
Turtle Beach Rematch review: The cutest Switch 2 controller of the bunch
Official Nintendo designs and RGB lighting give the Rematch an adorable edge.
Reddit mod ordered to pay Nintendo $4.5 million in Switch piracy lawsuit
Nintendo’s copyright crusade continues.
‘Happy Valley’ Star Sarah Lancashire Leading Dark Netflix Series About A Modern-Day Witch Hunt
Netflix is teaming with Happy Valley star Sarah Lancashire, Abi Morgan and Sister on a dark thriller about a modern-day witch hunt, while the streamer has secured Bob Mortimer and Ricahrd Ayoade for i...
Nintendo Wins $4.5M In Switch Pirate Lawsuit
The court entered a default judgement in favor of Nintendo
The Witcher 3: Wild Hunt – Remastered Global Release Times Confirmed by CD Projekt
CD Projekt has confirmed the global release times for The Witcher 3: Wild Hunt – Remastered. Here's when you can play in your region.
Review: DRAGON QUEST XI S: Echoes Of An Elusive Age - Definitive Edition (Switch 2) - Square Enix Needs To Get With The Upgrade Path Program
Well, at least it looks a little nicer
Which is the best version of Dragon Quest XI S? Switch 2, PC, PS4, Xbox, PS5, Steam Deck, & AYN Thor compared
We compare Dragon Quest XI S: Echoes of an Elusive Age - Definitive Edition launches for Switch 2 on September 24
Digital Foundry: Fire Emblem Fortune’s Weave is 720p docked, 540p handheld and 30fps, but uses DLSS
The tech-focussed team at Digital Foundry has been busy examining the recently released Fire Emblem Fortune’s Weave on the Nintendo Switch 2. The strategic RPG runs at 720p when played in docked mode…
One Of The Switch's Most Underrated Gems Is Now Free For Switch Online Users
Play it, for goodness' sake
Japan switches on its first full-stack room-temperature quantum computer — and scientists plan to scale it up to 10,000 qubits
Japan's new quantum system, Shunkai, uses "optical tweezers" to trap and rearrange atoms, and will be available to researchers working on quantum error correction.
Virgil van Dijk: Liverpool captain slams Dutch reporter following claims he forced Ronald Koeman to change World Cup tactics
Virgil van Dijk claimed media in the Netherlands had said that he had ruined Dutch football after allegedly telling Ronald Koeman to change formation during the World Cup; Koeman switched to a back five against Morocco, but would be eliminated on penalties
Illinois Offensive Weapon Grows in Confidence After Position Switch
An Illinois football offensive weapon is making strides ahead of the Ohio State game according to a position coach.
SLO County hospital network switches to AI-assisted electronic records system
Here’s what the switch means for patients.
Fans Seem to Think The Witcher 3 Remastered Looks Worse Than the Original
The Witcher 3: Wild Hunt Remastered comes out in about a week, and when CD Projekt Red put out a comparison clip on Twitter, some fans really didn't like what they saw.
Roma Reportedly Eyeing Frosinone Winger Giorgi Kvernadze
Roma’s search for an athletic left winger could lead to Frosinone’s Giorgi Kvernadze, who could make a midseason switch.
AT&T Responds to iOS 27's New iPhone Handoff Feature
Apple added a new iPhone Handoff feature to iOS 27 that allows you to switch between two iPhones while using the same phone number on each device. T-Mobile and Deutsche Telekom are the first carriers to offer iPhone Handoff, and Apple said Verizon and EE will add support later this year, but AT&T is noncommittal about the feature.
Stellar Blade will let players turn off frame generation on Nintendo Switch 2
According to Shift Up, when Stellar Blade launches on Nintendo Switch 2, the full game will include a toggle for frame generation, allowing players to turn it on and off at will. News about the planned functionality was shared on social media. A few days ago, the game received a demo on Nintendo Switch 2. Shift Up has been monitoring...
BizTrip AI Announces Connection With Claude and ChatGPT
Users will be able to manage travel without switching to separate app or website
Review: EA Sports FC 27 (Switch 2) - Still The Best Football Option, Even With Caveats
Zidane and shurrup, EA FC's back
BizTrip AI Brings Business Travel Booking Directly Into Claude and ChatGPT
SAN FRANCISCO, September 23, 2026--BizTrip AI, makers of agentic AI for corporate travel management, today announced that its core trip-planning and booking experience is now available natively inside both Claude and ChatGPT. The integration uses the Model Context Protocol (MCP) — specifically MCP "apps," which support rich, interactive rendering directly in a chat conversation — allowing travelers to search, compare, and book business travel without switching to a separate app or website.
The calendar says it’s 2026, so why does it suddenly feel like 2028?
Summer’s swampy heat released its grip on Washington Tuesday as if someone had flipped a switch.
Zelda: Ocarina of Time Nintendo Switch 2 pre-order bonus guide
New guide covers every pre-order bonus available for The Legend of Zelda: Ocarina of Time remake on Switch 2 worldwide.
How Index Switches Will Impact Tencent Music Stock Investors
Tencent Music Entertainment Group was removed from the FTSE All-World Index on its NYSE listing and added on its SEHK listing in September 2026, while fresh research updates highlighted mixed views on its core music operations and broader platform trajectory. The index switch concentrates liquidity closer to Tencent Music Entertainment Group’s onshore business footprint. This may sharpen investor focus on how its streaming, social entertainment, and offline initiatives line up with...
Sudden Demand for Middle-earth: Shadow of Mordor and War PS5 Ports After Switch 2 Bundle Is Revealed
Nemesis
iPhone Handoff Will Get a Lot of Nerds to Carry Two iPhones
Why choose between an iPhone Duo and another iPhone when you can use one phone number on both and seamlessly switch between the two?
Middle-earth: Shadow Bundle announced for Switch 2
Aspyr has announced Middle-earth: Shadow Bundle for Switch 2, which includes Middle-earth: Shadow of Mordor Game of the Year Edition and Middle-earth: Shadow of War Definitive Edition. It will laun…
Middle-earth: Shadow of War, Shadow of Mordor coming to Nintendo Switch 2
Middle-earth: Shadow of War Definitive Edition and Shadow of Mordor Game of the Year Edition are both coming to Nintendo Switch 2, it’s been revealed. A listing on the Nintendo eShop has them down for September 30, 2026. Middle-earth: Shadow of War Game of the Year Edition features season pass content – specifically the Guardians of the Flaming Eye Warband...
The Legend of Zelda: Ocarina of Time remake’s world map revealed
The Legend of Zelda: Ocarina of Time remake will launch exclusively on Nintendo Switch 2 on November 5th, 2026. You can pre-order your copy on Amazon today.
Rayman Legends Retold Doesn’t Feel Like a Necessary Remake, But It’s Still a Good Time
Rayman Legends Retold isn't breaking any new ground – not visually and not gameplay-wise, not that it should be expected to since it's a remake, after all – but it is a clean remake chock-full of content both new and old at a pretty nice value. It might be of particular interest to the Switch 2 crowd that isn’t getting the GTA 6 meteor landing in their lives this Fall (particularly in light of a new 3D Mario platformer’s continued absence and Super Mario Bros. Wonder being a couple years old now), and/or to the younger crowd that hasn’t played the series before. Here’s hoping it leads to a brand-new Rayman adventure sooner rather than later.
Graham says getting first Scotland call-up was 'surreal'
Luke Graham says getting his first call-up to the Scotland squad was "pretty surreal". The 22-year-old defender has impressed since making the summer switch to Stoke City, playing eight games so far in the Championship. Sebastien Pocognoli included the former Dundee defender in his first Scotland squad - a pleasant surprise for the Graham family.
Pasadena ISD will not switch employee health insurance program after concerns
Pasadena ISD sent out an announcement to staff on Tuesday morning saying they will not switch the employee health insurance program after some raised concerns.
Can AI Be Slowed Down? Stanford HAI Experts Weigh the Risks, Rules and Race Ahead
In a new series called 'Prompt Response,' Stanford’s Surya Ganguli, Diyi Yang and Rob Reich examined emergent agent behavior, recursive self-improvement, independent evaluation and whether a 'kill switch' can make advanced AI safer.
Orioles prospect season review: Aron Estrada
The 21-year-old switch-hitter turned in a fine season at Double-A.
The best and biggest games of September
From Silent Hill: Townfall to Control Resonant to Fire Emblem: Fortune's Weave, we review the best new games to play as autumn begins, ahead of the titanic GTA6 release.
‘Diary of a Black Girl’: the politics of code-switching
As a Black girl growing up in a predominantly white space, it is common to hear phrases such as “Why
watchOS 27.2 beta 2 restores App Switcher with a new gesture
If you’ve been missing the double-click of the Digital Crown that used to bring up the App Switcher on the Apple Watch before watchOS 27, it looks like the feature is making a comeback as of watchOS 27.2 beta 2.
Nintendo Shares First Look At Zelda: Ocarina Of Time Switch 2 World Map
See how it compares to the original game
11 RB Leipzig Players Head Away On International Duty
From Maarten Vandevoordt’s Belgian call-up to Ezechiel Banzuzi’s allegiance switch for DR Congo, stars across Europe and Africa prepare for crucial qualifiers and Nations League clashes this week.
Nintendo Switch ports of Pokémon Ruby and Sapphire look even more likely after official account shares suspiciously HD footage of the GBA games
Pokémon fans are convinced the other third-generation GBA games are headed to Nintendo Switch - and the evidence is certainly convincing.
Does your natural scent repel or attract people? What the science shows. - Futura-Sciences
Despite decades of perfume marketing and pop-science claims, researchers have never confirmed the existence of a human sexual pheromone that triggers attraction. Instead, controlled brain-imaging and behavioral trials reveal a far more subtle reality: human scent acts as a fleeting emotional signal rather than a switch for sexual desire. From...
This weird real-life exploit is discounting Switch game prices and causing... bananas to sell out?
Gaming is not a cheap hobby in 2026. Needless to say, most gamers are generally happy when they're able to stumble on discounts.Users on Reddit have apparently discovered a bizarre real-life hack that can potentially cut the price ...
HD Pokémon Ruby/Sapphire Video Sparks Switch Port Speculation
The suspiciously HD Pokémon Ruby And Sapphire clip has fans convinced that Nintendo Switch ports of the games might be dropping sooner than expected
Three City games switched for TV coverage in November
Three of our November matches have switched for TV coverage.The Premier League have confirmed their broadcast selections today, with our games against Nottingham Forest, Fulham and Arsenal seeing chan...
The Elder Scrolls 4: Oblivion Remastered Nintendo Switch 2 patch has broken the game a bit, Bethesda acknowledges issues
The Elder Scrolls 4: Oblivion Remastered Nintendo Switch 2 patch has all sorts of issues as Bethesda issues statement.
Pokemon account posts Pokemon Ruby & Sapphire played on unknown emulator fuelling Switch re-release hopes
The official Pokemon X account has recently posted footage of the much-loved Pokemon Ruby & Sapphire being played on unknown emulator. This has naturally sparked hopes of a re-release of the games on…
Accelerating AI creates need to nurture a constituency for ‘anticipatory democracy’
Recent appeals from a half-dozen chief executives in our artificial intelligence (AI) community asking the federal government to jump in and slow them down should alarm us all. Their warnings imply a fear their rapid progress in achieving “super intelligence” just may get us all killed. Now that Congress is considering mandatory “kill switches” installed […]
This Week’s Japanese Game Releases: Silent Hill: Townfall, GOBBLE, more
Silent Hill: Townfall for PlayStation 5 and PC, and GOBBLE for PlayStation 5, Switch 2, Switch, and PC are the highlights of this week’s Japanese video game releases.
Video: Stellar Blade Nintendo Switch 2 vs. PS5 graphics comparison
A brand-new graphics comparison video has surfaced for the upcoming Nintendo Switch 2 and PS5 versions of Stellar Blade. For those that missed the news, Shift Up just dropped a demo for the Nintendo Switch 2 release on the eShop today. That’s where the latest footage comes in. Note that it’s possible we could see changes / improvements in the...
Neon Abyss 2 launches October 8
Side-scrolling roguelike action game sequel Neon Abyss 2 will leave Early Access and launch for PlayStation 5, Xbox Series, Switch, and PC via Steam on October 8, publisher Kepler Ghost and develop…
Lufia I & II: The Sinistrals Saga announced for PS5, Switch 2, Switch, and PC
TAITO has announced Lufia I & II: The Sinistrals Saga for PlayStation 5, Switch 2, Switch, and PC (Steam). It will launch in 2027. It will be published by Clear River Games in the west.
Eagles make surprising offensive line change ahead of Titans game
The Eagles make switch on o-line.
Multiple Switch Games Receive Switch 2 Compatibility Fixes
Following a major firmware update