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Orlando City's Justin Ellis scores first USMNT goal in debut

By Ari LiljenwallTalk about a dream start.Just four minutes into his US men's national team debut, Orlando City homegrown Justin Ellis opened the scoring against Peru on Saturday at Inter.co Stadium �...

Sep 26 • 8:00 PM EDT • Sports • sports.yahoo.com

Hurricanes Rally Past Predators In Historic Preseason Comeback

Carolina overcame a 5-1 deficit to beat Nashville 6-5. See the key plays, roster cuts, and what this means for the 2026 season opener.

Sep 26 • 3:21 PM EDT • Sports • sports.yahoo.com

Muharemović impresses in Nations League opener

Tarik Muharemović played the full 90 minutes for Bosnia and Herzegovina as they opened their UEFA Nations League campaign with a goalless draw against Poland in Warsaw.The Leeds United defender start...

Sep 26 • 2:13 PM EDT • Sports • sports.yahoo.com

🚨 BREAKING: Czechia & Croatia name XIs for Nations League opener

UEFA Nations League play is underway across Europe during an extended international break, with an intriguing clash between Czechia and Croatia set to unfold in Prague. Czechia comes into tournament p...

Sep 26 • 2:04 PM EDT • Sports • sports.yahoo.com

Their Entrepreneur Mom Inspired These Birmingham Sisters to Go Into Business Together

When sisters Katherine McRee and Susan Ray opened The Lili Pad in 2004, they were two young moms following in their late mother’s entrepreneurial footsteps. Twenty-two years later, their Cahaba Height...

Sep 26 • 1:00 PM EDT • Business • yahoo.com

Oregon’s Dante Moore Opens Up About Mental Health & College Football Journey

Oregon Ducks QB Dante Moore opened up about his mental health and reflected on the challenges that helped shape his college football journey.

Sep 26 • 11:32 AM EDT • Health • foxsports.com

Patriots Week 3 Roster Updates

The NFL season is in its third week. Everyone's favorite teams are playing, and the rosters are changing. For the New England Patriots, there are spots to fill. With all the injuries that have happened so far, someone needs to step up, and someone needs to be a backup for the backup. Who's Filling in […] The post Patriots Week 3 Roster Updates appeared first on Stadium Rant.

Sep 26 • 10:02 AM EDT • Sports • sports.yahoo.com

Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL

Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Des Moines University Medicine and Health Sciences Launches Doctor of

WEST DES MOINES, IOWA (September 24, 2026) — Des Moines University Medicine and Health Sciences has opened applications for its new Doctor of Medical Science program — the first of its kind in

Sep 24 • 10:03 PM EDT • Science • rcreader.com

Open AI attacked Australia’s health system – and then doubled down on its negligence. The time for ‘wait and see’ is over

Human hackers face serious consequences, and so must AI companies. There is no excuse for what happened

Sep 24 • 8:03 PM EDT • Health • theguardian.com

Googlebook laptops are already selling out just days after pre-orders opened

Google's online store has already sold out of Googlebook pre-order stock in the US, but you can still order through Best Buy.

Sep 24 • 3:45 PM EDT • Technology • androidauthority.com

Mesa Market Place home to hundreds of Latino-owned businesses

Maria Borquez was only a young woman when she opened her shop. Twenty years later, her thriving business has grown into four storefronts — one of hundreds of Latino-owned businesses in Mesa.

Sep 24 • 12:14 PM EDT • Business • wfsb.com

Washington Huskies See New Additions to Injury Report

The Huskies saw two players listed as questionable for Saturday's Big Ten opener against the Minnesota Golden Gophers.

Sep 24 • 11:00 AM EDT • Sports • sports.yahoo.com

Packers’ offensive line becomes Thursday night’s crucial matchup against Falcons

Green Bay has some questions heading into their home opener on Thursday.

Sep 24 • 8:59 AM EDT • Sports • sports.yahoo.com

EU science policy wonks debate prospect of stronger ties with Canada

Europe’s research and innovation sector has started asking questions on how European Commission President Ursula von der Leyen’s offer to make Canada “the first associate member of the EU” would actually work in practice, and who will get to shape priorities in a transatlantic relationship that is getting stronger. The Commission says it wants “a new model of association” under which the EU and Canada will aim to develop “a shared space” to face ongoing challenges. “Working in close coordination with our member states and the European Parliament, we will aim to create a new form of partnership that has not existed until now, building the closest imaginable form of association with a partner outside Europe,” a spokesperson told Science|Business.Locked in an escalating trade war with US President Donald Trump, who has repeatedly talked of annexing Canada, Prime Minister Mark Carney has been looking east, but full EU membership was never in play. Taking the floor a day after von der Leyen’s proposal, he agreed to strengthen ties under “an alliance of the future” but reined in enthusiasm on the new label. He also suggested expanding Canada’s involvement in the Erasmus+ student mobility scheme, to which it currently has limited access, and the next iteration of Horizon Europe. Canada joined the present Horizon Europe in 2024, but only contributes to collaborative projects.Neither side has detailed the next practical steps in developing this new relationship. “I think nobody at the moment truly knows how this will work,” said Michael Browne, chief executive and founder of Crowdhelix, a global collaborative network that connects players in research and innovation. “It’s more of a statement of intent for closer collaboration, which requires legislative frameworks and approval processes, which have not started.”Kurt Deketelaere, secretary general of the League of European Research Universities, said von der Leyen’s pitch to Canada is “politically significant, but the legal content still has to be negotiated and constructed.”Mattias Björnmalm, secretary general of the Cesaer university group, agreed that she had only opened “a political door” to Canada, as “associate membership does not come with a predefined set of rights in the EU institutions.”Not only does this status not currently exist as a legal category in the two treaties that set up how the EU functions, but the Commission president cannot unilaterally create a new category of EU membership.According to Deketelaere, Article 217 of the Treaty on the Functioning of the EU, which allows the bloc to make association deals with non-EU countries involving reciprocal rights and duties, is “the most obvious existing legal basis for building a much deeper EU-Canada relationship.”Getting universities involvedNo matter how this new cooperation takes shape, Liviu Matei, who heads the School of Education, Communication and Society at King’s College London, hopes to see universities involved in discussions from an early stage.“Its primary motivations, entirely justifiably, are political and geopolitical,” he said. “In the area of higher education, however, restricting the initiative to political and geopolitical considerations would limit the scope of cooperation and lead to distorted frameworks and counterproductive implementation.”It is all the more important since academic interests on the two sides of the Atlantic are “neither identical nor fully aligned,” Matei added. “This is not insurmountable; it simply requires work to articulate the details of this privileged cooperation, including its governance and funding frameworks, as well as its substantive content in education and research.”Related articlesCanada looks to deepen research and education links with the EUZaharieva hopes for a Horizon Europe deal in 2026Canada might participate in European Research Council schemes, for example, which was not on offer in the present Horizon Europe association agreement. But “there would have to be something in it for the EU,” Browne said. “They don’t want to be funding projects outside of the EU where intellectual property is going to sit outside of the EU. There has to be some kind of transfer of knowledge.”But access to funding will not by itself resolve all the practical difficulties of working together, said Björnmalm. “For researchers and students, these include visas and residence arrangements, recognition of qualifications and study periods, and the conditions for pursuing a research career across borders,” he said. “For universities, there is scope for more predictable access to shared laboratories, computing and research data, and stronger support for joint doctoral training and long-term institutional partnerships.”Linda Doyle, provost and president of Trinity College Dublin, said Europe should strive for the “closest possible expression” of this new political alliance. “If Europe is serious about recovering its voice and its place in the world, it needs to be strongly allied with countries who share its values and its vision for a stable, rules-based, peaceful world.”

Sep 24 • 8:00 AM EDT • Science • sciencebusiness.net

FC Dallas planning to billion-dollar entertainment district around Toyota Stadium

| 100.3 Jack FM

Sep 24 • 7:55 AM EDT • Entertainment • audacy.com

CJ Bailey discusses aftermath of Vanderbilt game

CJ Bailey met with the media yesterday, the first time he’d spoken with reporters since The Thing That Happened. There is no way to explain any part of what went down during The Thing That Happened, of course, but he did the best he could. Sometimes the football is snapped and major regret ensues. In […]

Sep 24 • 7:44 AM EDT • Sports • sports.yahoo.com

'What happened on Saturday will not happen to us again'

Rachel: Arsenal seemed to start the season with intent and they delighted us with their slick passing game. Richard: We've handed out and been given one tonking (Coventry and Brighton, respectively). A good start overall but the Brighton game showed what can and will happen if we're not at the races.

Sep 24 • 7:01 AM EDT • Sports • sports.yahoo.com

How Latinos became America’s biggest swing vote

Donald Trump’s 2024 gains are being erased in the midterms. Here’s what happened.

Sep 24 • 6:00 AM EDT • Politics • vox.com

Calling all current and future scientists: Kiel is the place to be this week

This week, Kiel has become a meeting place for science in Europe. Researchers, school pupils, young scientists and members of the public are coming together through a series of major events led or co-organised by Kiel University.At the centre of it all are around 150 of Europe’s most talented young researchers, aged 14 to 20, who have travelled to Kiel from nearly 40 countries for the 37th European Union Contest for Young Scientists (EUCYS). Running from 22 to 27 September, the European Union’s flagship competition for young scientists brings together winners of national science competitions to present around 100 original research projects across fields ranging from engineering and computer science to medicine, environmental research and the social sciences. The winners will be announced at the Award Ceremony on Saturday.For Kiel University, hosting EUCYS is both an honour and a natural extension of a much longer story. Germany’s northernmost comprehensive university has invested for many years in supporting young scientific talent and bringing research into dialogue with society. The Kiel Science Factory gives school pupils opportunities to experience research first-hand, while programmes such as Rent-a-Scientist send researchers directly into local classrooms. Major annual public events including Kiel Week and the European Researchers’ Night take science beyond the campus through talks, exhibitions and hands-on activities.That long-standing commitment has increasingly taken on a European dimension – and this week, many of those efforts are coming together.One of the foundations for this success is the European Researchers’ Night (ERN), which celebrates its tenth edition in the Kiel region this year. The initiative is funded through the Marie Skłodowska-Curie Actions, with Kiel University developing the successful EU proposals and securing the funding, while regional partner KielRegion coordinates the many activities on the ground. Together with research institutions, schools, companies, local authorities and civil society, they have built ERN into a major platform for public engagement.Over the years, Kiel’s ERN programme has grown far beyond a single evening into a whole “Science Summer”, beginning with “Science Shopping” in spring and culminating tomorrow, 25 September, in Science Day.“We have developed a wide range of public engagement formats, often together with the other research institutions in the region, the city and regional authorities, schools, companies and civil society,” says Eckhard Quandt, Kiel University’s vice president for research, academic infrastructure and transfer. “Over the past decade, we have increasingly taken this commitment to the European level.”That combination of European funding expertise and strong regional partnerships also helped Kiel University take the next step. Drawing on its experience with ERN and its European networks, including the SEA-EU University Alliance, the university brought together Brest in France and Split in Croatia for a successful bid to the EU’s new Science Comes to Town initiative. Throughout 2026, the three cities are serving as Europe’s first Science Ambassadors, with more than one thousand activities bringing science into schools, public spaces, cultural venues and everyday life.EUCYS is perhaps the clearest example of how Kiel University is using Science Comes to Town to create new connections between major European initiatives. From the outset, the university deliberately planned the contest for the week of European Researchers’ Night and opened the EUCYS exhibition to the wider Science Day audience. Tomorrow, that means thousands of visitors can encounter the next generation of scientific talent first-hand, while the young researchers themselves gain a much bigger public stage.“Because we opened EUCYS up for European Researchers’ Night, there will be a lot of people actually visiting the exhibition,” says organiser Stefanie Altemark of Kiel University.“We wanted Europe’s most talented young scientists not only to compete with one another, but also to become visible to the wider public. At the same time, people in Kiel will have the opportunity to see what the next generation of scientists are already capable of,” says Quandt.“We’ve shown over the last years that science is a big part of Kiel, and it’s always been the goal to not only show that to people in Germany, but also to show it to people all over Europe. Thanks to Kiel University’s expertise in European funding programmes, we have been able to turn that ambition into reality,” says Sünje Fock, who is coordinating the Science Summer at KielRegion.The model is characteristic of Kiel University’s approach: combining European funding expertise and international networks with strong regional partnerships to give major initiatives greater reach and visibility.This year also marks the 30th anniversary of the Marie Skłodowska-Curie Actions, giving Kiel University the special opportunity to welcome Vanessa Debiais-Sainton, Head of Department for the Marie Skłodowska-Curie Actions at the European Research Executive Agency, to Kiel tomorrow. Her visit brings together two priorities that have shaped Kiel University’s work over the past decade: supporting researchers and bringing science closer to society. Debiais-Sainton emphasises how closely the two are connected: "For thirty years, the Marie Skłodowska-Curie Actions (MSCA) have given more than 150,000 researchers the chance to pursue their dreams and open up new fields. Doctoral Networks and Postdoctoral Fellowships give them the freedom to move, to connect, to train and to follow their curiosity across borders, sectors and disciplines. But excellence cannot live only in laboratories. Researchers’ Night takes science out of the lab and into the city, to the families, the schoolchildren and the curious minds who will become the next generation. Kiel shows what that looks like at its best. That is the MSCA promise: open science, open borders, open doors."For Kiel University, these activities are not separate endeavours. They are part of a broader understanding of academic excellence in which outstanding research, talent development, international cooperation, knowledge transfer and engagement with society strengthen one another.“For me, one of the most important lessons from the past decade is that scientific excellence, knowledge transfer, talent development and engagement with society cannot be treated as separate tasks,” stresses vice president Quandt. “They reinforce one another.”That philosophy is also reflected in Kiel University’s current bid for Germany’s Excellence University status. The designation is part of Germany’s national Excellence Strategy, which provides substantial long-term funding to selected universities to strengthen internationally competitive research and their overall institutional development. A successful outcome would provide new opportunities to build on what has already been created: deepening international cooperation, creating more opportunities for knowledge exchange and public engagement, and extending the university’s reach across the region and beyond. “If we are successful, it would allow us to take what we have built in Kiel considerably further – including expanding our networks and transfer activities beyond the region and increasingly across the Baltic area,” says Quandt.This week’s events offer a glimpse of what that could mean in practice: a university using its research strength, European expertise and regional partnerships to create opportunities for scientists at every stage of their careers while making science more visible, accessible and exciting to the wider public.

Sep 24 • 5:37 AM EDT • Science • sciencebusiness.net

Family-run pharmacy in Melbourne Beach closes retail side. Gallery

Savers Pharmacy, on Ocean Drive in Melbourne Beach, opened in 1983. It's shutting down its retail side but will continue to serve people in long-term care.

Sep 24 • 5:04 AM EDT • Business • floridatoday.com

In rural Pa., doctors confront the hidden health impacts of environmental disasters

This article originally appeared on Inside Climate News, a nonprofit, non-partisan news organization that covers climate, energy and the environment. In February 2023, George Garrow jumped in his car and hurried to help people impacted by a freight train that had derailed in East Palestine, Ohio. The crash happened about a quarter-mile west of the […]

Sep 24 • 3:15 AM EDT • Health • penncapital-star.com

Baylor receives health boost ahead of conference opener against Colorado

Baylor will get a health boost with junior quarterback DJ Lagway returning alongside multiple key pieces ahead of the Bears' conference opener against Colorado.

Sep 24 • 12:50 AM EDT • Health • baylorlariat.com

Three Oklahoma State football players questionable vs West Virginia

Three Oklahoma State players are questionable for Saturday's Big 12 opener against West Virginia in Morgantown.

Sep 23 • 10:44 PM EDT • Sports • sports.yahoo.com

Three takeaways from Nebraska volleyball’s sweep against Missouri

Nebraska volleyball took on Missouri Wednesday night in a makeup game after the Wrigley Field court disaster that happened on Wednesday, Sept. 6. The two teams were set to play in the inaugural Big Ten/SEC Challenge. Unfortunately, the contest was cancelled early in the first set due to moisture on the court. At the time of cancellation, the Huskers led 11-7.

Sep 23 • 9:10 PM EDT • Sports • dailynebraskan.com

Will Simmons, Smothers play for Texas against Volunteers?

AUSTIN (KXAN) – As Texas football gets set for their SEC opener against Tennessee, they hope to head into Knoxville at full health. The Longhorns got a bit of a scare in their final non-conference game against UTSA when defensive standout Colin Simmons exited and was seen in a walking boot. Now, it looks like […]

Sep 23 • 9:04 PM EDT • Sports • sports.yahoo.com

Padres fall flat against rival Dodgers in series opener

FriarWatch: September 23 Edition

Sep 23 • 6:20 PM EDT • Sports • sports.yahoo.com

In Payton vs. MacDonald, Comments Were Sort Of Off-Record

Denver Broncos coach Sean Payton is in a news story about something that happened in 2024.

Sep 23 • 5:14 PM EDT • Sports • sports.yahoo.com

Mancini’s first Italy side takes shape for Belgium test

Roberto Mancini’s starting XI for Italy’s Nations League opener against Belgium is taking shape, with Francesco Pio Esposito, Nicolò Zaniolo and Daniel Maldini expected upfront.It kicks off at th...

Sep 23 • 3:25 PM EDT • Sports • sports.yahoo.com

UCF Ready To Prove Doubters Wrong in Big 12 Opener

The Knights face a pivotal showdown against TCU’s elite run defense to shed their underdog status.

Sep 23 • 2:15 PM EDT • Sports • sports.yahoo.com

Arteta 'didn't learn' from Brighton's fast start

Arsenal podcaster Alan Alger says Mikel Arteta "didn't learn" from Brighton's fine start in their 3-0 win over the Gunners on Saturday. The Seagulls' high press smothered Arteta's side, who struggled to match the intensity of their opponents, before Pascal Gross opened the scoring after half an hour. My one big criticism of Arteta is that in his quotes he said 'we will learn from this' - but he didn't learn from watching the first 20 minutes happening in front of him.

Sep 23 • 1:14 PM EDT • Sports • sports.yahoo.com

Permanent jewelry business pops-up in Elgin

ELGIN — Permanent jewelry has found a footing in Northeastern Oregon. Shawna Vaughn, with assistance from her mother, Joeli Hansen, opened Løven Permanent Jewelry in April in Elgin. The mobile […]

Sep 23 • 10:49 AM EDT • Business • lagrandeobserver.com

'It has become very dire in a lot of places': New map reveals exactly where humans are adding and removing precious fresh water on Earth

A new high-resolution map of global freshwater trends between 2002 and 2025 has sharpened scientists' understanding of how humans are using and displacing our most precious resource.

Sep 23 • 10:44 AM EDT • Science • livescience.com

Sphere and Disguise partner to advance immersive entertainment

Sphere Entertainment and Disguise have announced a new multi-year partnership to develop advanced technologies custom-made for Sphere’s immersive entertainment venue. Since Sphere opened in 2023, Disguise has served as a key technology partner supporting the delivery of Sphere’s groundbreaking live residency productions and corporate events. For these events, Sphere uses Disguise media servers and software

Sep 23 • 9:46 AM EDT • Entertainment • tpimagazine.com

Cosplay, Gaming And More At CapeCon 2026

Plans are well underway for CapeCon 2026, which will take place Saturday, October 3 from 10 AM to 4:30 PM at the Falmouth Public Library.

Sep 23 • 9:33 AM EDT • Entertainment • capenews.net

The An-124 Charter Business: Antonov, Volga-Dnepr, SALIS

How NATO ended up renting Soviet-designed freighters from a Ukrainian and a Russian airline — and what happened to the An-124 charter market after 2022.

Sep 23 • 9:07 AM EDT • Business • migflug.com

Klopp ready to 'get straight down to business' in Germany debut

Jürgen Klopp said he will get "straight down to business" in his debut as Germany coach in the Nations League opener against the Netherlands on Thursday. "I haven't heard of many friendly matches in Amsterdam so it's straight down to business," the new national team told journalists after the final training session on Wednesday.

Sep 23 • 8:48 AM EDT • Business • sports.yahoo.com

Troy Clarkson To Deliver Falmouth Forum Season Opener

Author and columnist Troy Clarkson will present the first talk of the Marine Biological Laboratory’s 2026-27 Falmouth Forum series.

Sep 23 • 8:38 AM EDT • Entertainment • capenews.net

Ad break during game was unscheduled, says Disney+

Coverage of Arsenal's Women's Champions League opener also featured a dog on set, a vegetable platter and a rotating floor.

Sep 23 • 8:35 AM EDT • Sports • sports.yahoo.com

What happened to ‘The Love Boat’ cast? See the crew of the Pacific Princess 40 years later

That swirling theme music could mean only one thing: The Pacific Princess was pulling in with its appealing crew and oodles of celebrity guests. See the stars of ‘The Love Boat’ more than 40 years after the finale.

Sep 23 • 8:00 AM EDT • Entertainment • ew.com

New skatepark opens in West Des Moines

The city of West Des Moines has opened its new skatepark at Crossroads Park at 5205 Ashworth Road. The park features all new concrete features designed for skateboarders and scooter riders of all levels, the city said in a news release. The new concrete features include a slappy curb, box bollard, radius wedge and quarter…

Sep 23 • 7:00 AM EDT • Business • businessrecord.com

King Pigeon, under new ownership, reopens following seven-month closure

King Pigeon reopened Friday under new owner Jesus Andres after a seven-month closure, offering coffee from La Cabra and pastries in Walnut Hills.

Sep 23 • 6:36 AM EDT • Business • bizjournals.com

Dodgers rout Padres in bulk in opener

Dodgers use 8 pitchers to blank Padres

Sep 23 • 12:50 AM EDT • Sports • sports.yahoo.com

Dave Roberts Reveals Honest Mookie Betts & Shohei Ohtani Conundrum

The Los Angeles Dodgers have been without superstar slugger Shohei Ohtani for the last week+ as he’s been dealing with a biceps issue that led to his IL placement. Manager Dave Roberts indicated on Tuesday, before the Dodgers’ series opener with the San Diego Padres, that Ohtani will be activated from the IL on Wednesday. […] The post Dave Roberts Reveals Honest Mookie Betts & Shohei Ohtani Conundrum appeared first on HEAVY.

Sep 22 • 10:59 PM EDT • Sports • sports.yahoo.com

State, Maui Health and Kaiser Permanente announce restoration and reopening plans for Kula Hospital

The state of Hawaiʻi, Maui Health and Kaiser Permanente today announced that Kula Hospital will be restored and reopened after damage from the March 2026 Kona Low storms forced the temporary closure of the hospital, its Emergency Department and the Hale Makamae care facility.

Sep 22 • 7:00 PM EDT • Health • mauinow.com

Ernst Names Small Business of the Week, North Lumber & Home Center

Read the release on Sen. Ernst's website HERE. Throughout this Congress, Chair Ernst plans to recognize a small business in every one of Iowa’s 99 counties. RED OAK, Iowa – U.S. Senator Joni Ernst (R-Iowa), Chair of the Senate Small Business Committee, today announced her Small Business of the Week: North Lumber & Home Center of Decatur County. Throughout the 119th Congress, Chair Ernst plans to recognize a small business in each of Iowa's 99 counties. “North Lumber & Home Center has truly gotten to the root of what it means to be a hardworking, dedicated small business” said Chair Ernst. “For more than four decades, this family-owned and operated business has continued to branch out by providing quality services and staying actively engaged in its community.” In 1980, current owner Sally Dykes and her family purchased North Lumber. As the family continued to expand their inventory and operations to better serve its customers, they renamed the business to North Lumber & Home Center. In 2002, they opened a second store in Lamoni, Iowa. Today, Sally continues to run the lumberyard and building materials supplier business alongside her son, Tony Dykes. Stay tuned as Chair Ernst continues to recognize outstanding Iowa small businesses with her Small Business of the Week award. ###

Sep 22 • 5:35 PM EDT • Business • sbc.senate.gov

Hotel Vin Rogers opens in Pinnacle Hills

A more than $72 million hotel recently opened in the Pinnacle Hills area of Rogers with three food-and-beverage concepts, an outdoor pool, and more than 10,000 square feet of event...

Sep 22 • 4:00 PM EDT • Politics • talkbusiness.net

Hotel Vin Rogers opens in Pinnacle Hills

A more than $72 million hotel recently opened in the Pinnacle Hills area of Rogers with three food-and-beverage concepts, an outdoor pool, and more than 10,000 square feet of event...

Sep 22 • 4:00 PM EDT • Business • talkbusiness.net

Vandalia Health celebrates grand opening of Mon Harrison Neighborhood Hospital

BRIDGEPORT, W.Va. – A new two-story emergency and inpatient care hospital has officially opened in Harrison County. Vandalia Health announced via press release that the new Vandalia Health Mon Harrison Neighborhood Hospital officially as part of a ribbon cutting hosted on Tuesday. The ceremony to open the new $26 million hospital aimed to expand access…

Sep 22 • 3:22 PM EDT • Health • wajr.com

FCB Women held by Man City in Champions League opener

FC Bayern Women could only begin their UEFA Women’s Champions League campaign with a point after being held to a 2-2 draw by Manchester City on Tuesday evening. The champions of Germany went ahead e...

Sep 22 • 2:47 PM EDT • Sports • sports.yahoo.com

Sabres Drop Preseason Opener In Pittsburgh, Ex-Sabres News

Sep 22 • 1:52 PM EDT • Sports • sports.yahoo.com

The Man Shot by ICE in Austin Speaks

The lawyer of Wilber Rafael Garces Perez, currently being held in an ICE detention center with a bullet in his back, held a press conference yesterday. Perez happened to call in.

Sep 22 • 1:45 PM EDT • Politics • texasmonthly.com

Florida returns to Athlon Sports rankings' top 25 after beating Auburn

Florida football opened its SEC schedule with a big win over the Auburn Tigers on the road, propelling them back into Athlon Sports rankings' top 25.

Sep 22 • 11:49 AM EDT • Sports • sports.yahoo.com

Around 7,000 Years Ago, The Genetic Diversity Of Males Crashed: What The Hell Happened?

Did generations of violent inter-clan warfare nearly decimate the genetic diversity of males?

Sep 22 • 11:11 AM EDT • Science • iflscience.com

CBS Sports ranks Michigan No. 15 ahead of Big Ten opener vs. Iowa

Michigan football faces a critical test against Iowa as Big Ten play begins with the Wolverines ranked 15th.

Sep 22 • 10:29 AM EDT • Sports • sports.yahoo.com

Tigers aim to clinch series vs Nationals on Tuesday night

The Detroit Tigers opened up the penultimate series of the 2026 campaign with a 9-2 victory at Comerica Park — soon to be Fifth Third Park — on Monday night. River Ryan looked good in his debut wearing the Olde English D, while home runs at the bottom of the batting order from Spencer Torkelson […]

Sep 22 • 7:00 AM EDT • Sports • sports.yahoo.com

Arsenal Women’s start raises early title concerns

Another slow start threatens to derail Arsenal’s title challenge before it really gets going.Photo by Sarah Ray-Gain/Getty ImagesBefore this season, the manager and players knew what had happened in...

Sep 22 • 6:20 AM EDT • Sports • sports.yahoo.com

Pens Points: Preseason Positives

Back on PPG Paints Arena ice for the first time since April, the Pittsburgh Penguins opened their preseason slate with a 4-1 victory over the Buffalo Sabres. Sergei Murashov got the nod in goal and pitched a shutout, stopping 13 shots, in his 30 minutes of action before Joel Blomqvist took over. Connor Dewar, Bryan […]

Sep 22 • 6:00 AM EDT • Sports • sports.yahoo.com

Bruins vs. Flyers PRESEASON PREVIEW:

Just the Facts What happened last game? The Bruins played a tight game where Jake Schmaltz and Charlie McAvoy scored, and it went to the shootout with James Hagens once again stepping in to play the hero. Bruins WIN 3-2! Mike DiPietro also had a huge game for your Boston Bruins, as he stopped 30 […]

Sep 22 • 6:00 AM EDT • Sports • sports.yahoo.com

How lip-syncing to AI let Forced Entertainment ‘play the game of theatre’

Today we have a fascinating piece by long-time Forced Entertainment fan Ben Kulvichit, speaking to Tim Etchells about their latest show Cold Sweat, how they are integrating lip-sync and AI voices into their work, the question of ‘authenticity’ on stage, and how lip-sync has even opened the door for them to make “something a little bit like drama”. This piece is a paid partnership with the Southbank Centre, where you can see Cold Sweat next month – we’re very grateful to the Southbank Centre for their ongoing support for Exeunt. Holly Williams ‘It was immediately interesting and uncanny’ **By Ben Kulvichit** “Is the microphone on?” So goes one of the opening lines of Signal to Noise, delivered by a human performer lip-syncing to an AI-generated voice. The voice is American, cheery but sluggish, slowed down into a gelatinous drawl. It repeats ad infinitum in a farce of stuckness; an answer never materialises. I find myself asking the same question as I hop on a Google Meet call with Tim Etchells, the artistic director of Forced Entertainment. We spend five or ten minutes frowning at each other, muting and unmuting, me gesticulating in semaphore into my webcam, checking if I am coming through now, restarting the laptop. To Etchells, I appear exaggeratedly mouthing words, my voice missing. In this gloopy purgatory of broken communication, life imitates art imitates life imitates art. We try a Zoom instead. Forced Entertainment, the pioneering British theatre company who have been at the avant-garde of performance since the 1980s, turned an interesting artistic corner with Signal to Noise, created on the occasion of their 40th anniversary. The whole performance employed this lip-sync technique to AI voices; on the face of it a left-field move from a company whose identity has long been grounded in the earthy, immediate presences of its performers and its unassuming, low-tech approach to theatricality. The technique, however, turned out to provide the company with a “rich new seam” of artistic enquiry, and has now spawned a trilogy of works. The second instalment, Cold Sweat, plays at Sheffield Theatres, Southbank Centre, and Lancaster Arts in October, while the third part, Everything Must Go, has been touring in Europe and is slated to come to the UK in 2027. As is often the case with Forced Entertainment shows, the main conceit for this work didn’t arrive until quite late. They were “four or five weeks into rehearsals for Signal to Noise,” Etchells recalls, and getting nowhere. Away from rehearsals, he had been playing around with feeding “weird texts” to AI voices to see how they would cope with them – “basically for my own amusement” – and was compelled by the uniformly “serviceable, benign, good-natured” tone they would read in, no matter how poetic, fractured or experimental the writing. On a hunch, he brought some examples into rehearsals and the performers gave lip-syncing a go. “It was immediately interesting and uncanny,” he recalls, with the performers having to deal in the moment with the problem of mapping themselves onto another artificial ‘performer,’ which itself was dealing with the problem of a very human text. “Almost all the writing for these projects would be useless to us unless it was done in this way,” says Etchells. “We wouldn’t know what to do with it. It’s too poetic. It’s too fictional. It’s too tangled.” But exploring lip-syncing along to the text has opened “an enormous reservoir of ways of thinking about writing and performing.” Subscribe to Exeunt, and get two in-depth pieces on theatre a week, direct to your inbox Subscribe Forced Entertainment have long been sifting through the detritus of popular culture, from daytime TV to end-of-the-pier vaudeville, magic acts and clown shows, to find frameworks for their own unusual entertainments. Lip-syncing, then, makes sense for them to experiment with. As a mode of performance, it’s wired into popular consciousness through pop stars trying to convince stadium audiences of their liveness, or those same voices as channeled through the made-up lips of contestants on RuPaul’s Drag Race, or movie dialogue spreading virally through the host bodies of TikTok users. For Etchells, lip-syncing is often about “approaching real voices and trying to take on their aura,” subsuming that original human presence into yours. “There’s a very basic, elemental sort of theatre magic to it, produced in this very easy way.” This broad approach resonates with instances of lip-syncing within contemporary performance, too. In works like Re-Member Me and Showmanism, performance artist Dickie Beau acts as a kind of spirit medium for archival recordings (this process of re-membering – as in, giving corporeal form to voices – relies on his masterfully precise actor’s technique), while Frankie Thompson is similarly possessed by a host of characters ranging from a nine-year-old Jacob Rees-Mogg to Cliff Richards, all of whom she finds compellingly nauseating, in the exorcism ritual that is her latest show, Horrible Things. What’s different about Forced Entertainment’s use of lip-syncing is that here, there is no original presence to be channeled. The performers are instead taking on what Etchells describes as “the voices of nobody,” or rather the “phantasmic, aggregated echoes” of the many many voices on whose data the AI has been trained, and which are now conjuring into existence words they never actually said. There is a sort of mournful, empty quality to these voices, having “washed up” far away from the people they originally belonged to, to find themselves in stranger’s mouths listing objects, wondering if anyone can hear them and glitching in interminable loops. There is a cold, sad anonymity to it all. Etchells remarks that occasionally the software company he used has notified him that particular people are withdrawing their voices from the platform, instructing him to cease use of those voices. Using these technologies in performance certainly brings up ethical questions around digital rights, consent, identity and ownership, although in the grand scheme of things, Etchells is fairly blasé about it: of all the purposes someone’s voice might be put to without their knowledge, “an avant-garde performance is probably the least of their worries.” [ ](https://exeuntmagazine.substack.com/p/frankie-thompson-horrible-things-essay-mental-health-compulsive-behaviours-pleasance-courtyard-soho-theatre) [ Frankie Thompson: How I manage my own ‘horrible things’ at the Edinburgh Fringe ](https://exeuntmagazine.substack.com/p/frankie-thompson-horrible-things-essay-mental-health-compulsive-behaviours-pleasance-courtyard-soho-theatre) Exeunt · Aug 25 [ Read full story ](https://exeuntmagazine.substack.com/p/frankie-thompson-horrible-things-essay-mental-health-compulsive-behaviours-pleasance-courtyard-soho-theatre) For the performers, though, lip-syncing to these strange, artificial voices is an odd task, requiring them to bend their live, human presence into the shapes produced by machines. Politically, it mirrors processes that are already at play in the continued computational automation of human life. Etchells brings up James Bridle’s writings on new technologies as a reference point: one example Bridle gives is of “chaotic storage”, a logistics technique employed by Amazon fulfilment centres whereby items are stored not according to traditional methods of categorisation or alphabetisation, but in a way that an algorithm determines to produce the most efficient routes for ‘picking’ based on customer purchase patterns. This appears completely random and incomprehensible to humans, with paddling pools sitting next to USB sticks sitting next to blowtorches, and so for the warehouse workers, the process of picking items becomes completely reliant on technology which tells them where to go. Our world is increasingly being designed not with humans in mind, but rather machines. As Etchells puts it, “technology malforms the space, and then you end up having to live in it.” Initially, Forced Entertainment tried their best to live in the world of machines: “I was in the it’s-got-to-be-perfect school of lip-sync,” says Etchells. But with their aesthetic being so tied to the failing act, the slipping mask, the shoddy costume, “it’s no surprise really that that didn’t last.” Instead, the performers got to enjoy being late for a line, or playing games with each other, “stealing” each other’s voices. Etchells compares it to the principles of ventriloquism, in which a free-floating voice unattached to a body is fundamentally discomforting and “sort of traumatic”. That discomfort is equally as alluring to Forced Entertainment as the satisfaction of precision, the pretence of authenticity only interesting if shown to be a pretence. Lip-sync has also opened up new avenues for the company. Having been allergic all their lives to Plays-with-a-capital-P, with Cold Sweat Forced Entertainment find themselves approaching something a little bit like drama. Rather than the presentational arena of Signal to Noise’s open white stage, Cold Sweat places us more decisively in a “fictional locale”: what appears to be “the aftermath of some disastrous party or backyard drinking binge” where three figures – family members, or neighbours, perhaps – are the last ones standing. “It’s all quite acrimonious and accusatory, everyone’s talking over each other.” For Etchells, this more fictional mode is “a door that we’ve never been able to open. We’ve just never really gone there.” Perhaps it is the technique of lip-syncing, an extra buffer of mediation, that allows them to venture away from the here-and-now without feeling that they have to commit to the “psychological claptrap” that comes along with acting; to be able to “play the game of theatre, without getting one’s hands too dirty.” As I wonder how else the impulses behind Forced Entertainment’s work have changed over time, it occurs to me that over the last ten years of new creations, with the exception of If All Else Fails, the company’s performers haven’t ever spoken on stage: there were two shows without any language at all, Out of Order and Under Bright Light, and then this trilogy of lip-sync works. Etchells agrees it’s a shift away from earlier productions, that were so often about “the actual voices of the performers and their actual presences. We had a lot of money, in some ways, on an authentic approach to what it might mean to speak on the stage.” But this sense of authentic presence itself had a fakeness to it; these days, Etchells can’t stand that mode of being onstage where performers “are here to be cheeky and witty versions of themselves. I don’t want to be charmed.” Pulling back into a more anonymous space has resulted in works that feel slightly sharper-edged, more brutal in a way. “All of these shows are post-Brexit, post-Trump, post-truth, post-everything,” Etchells notes. Speech, charisma, authenticity – these things feel politically loaded, and perhaps warmth and openness just don’t feel like the right tools to reflect the world we’re living in. “It feels like the space is closing down, and we’re trying to deal with the fact that the system, the structure that you’re in, is more oppressive and more powerful. It probably always was, but I think we’re just more tuned to it now.” Yet even without their voices, the performers’ distinctive presences – ones that many audiences have followed around for years, if not decades – still, inevitably, shine through as they physically navigate whatever unending task the system of the piece has set for them. They’re still trying to keep up with the onslaught of text, still running about, changing costumes, moving stuff around. The human is always stuck in the teeth of the machine, jamming the smooth, frictionless cheeriness of the not-real, gesticulating silently, trying desperately to communicate. Cold Sweat is at Sheffield Theatres, 2 to 3 October; Southbank Centre, London, 9 to 10 October; Lancaster Arts, 14 October [ ](https://exeuntmagazine.substack.com/p/exeunt-recommends-the-best-autumn-theatre-2026-lives-of-others-standard-of-living-our-friends-in-the-north-lanny-) [ Exeunt recommends... the best autumn theatre ](https://exeuntmagazine.substack.com/p/exeunt-recommends-the-best-autumn-theatre-2026-lives-of-others-standard-of-living-our-friends-in-the-north-lanny-) Exeunt · Sep 16 [ Read full story ](https://exeuntmagazine.substack.com/p/exeunt-recommends-the-best-autumn-theatre-2026-lives-of-others-standard-of-living-our-friends-in-the-north-lanny-) This piece was paid for by the Southbank Centre. Such support helps Exeunt to keep publishing the most interesting writing, about the most exciting theatre. Interested in partnering with Exeunt? Visit our Advertise with Exeunt page, where you can get more information, download an advertising pack, and find our contact details.

Sep 22 • 5:02 AM EDT • Entertainment • exeuntmagazine.substack.com

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