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The Fourth Expedition
ARC Raiders is a multiplayer extraction adventure, set in a lethal future earth, ravaged by a mysterious mechanized threat known as ARC.
Online violence against women in politics: what shapes political party responses to technology-facilitated gender-based violence?
Political parties have a primary role to play in tackling online violence against women and gender diverse politicians. While the prevalence and impact of TFGBV, such as coordinated disinformation campaigns, deepfake image-based sexual abuse or trolling are well documented, many parties are still building their knowledge on how to respond effectively and have not put in place internal practices and policies that respond to the rapidly evolving, poorly regulated digital ecosystem. About the ReportIn order to promote and protect fair and democratic participation in politics, this ALIGN Report explores what political parties are doing in response to TFGBV and what factors shape their action. The findings, based on existing literature and interviews with gender and politics professionals, indicate there are three sets of factors which donors, civil society and practitioners should consider when designing action to support political parties to respond to TFGBV internally. These are: (1) gender norms; (2) socio-political environment; and (3) internal party factors.Key messagesUnequal gender norms are ubiquitous across politics, shaping expectations of leaders to be strong and assertive, and practices of political parties to uphold masculinist values and sustain cultures of silence. These often lead to weak response to TFGBV against women politicians.The socio-political context can incentivise or disincentivise action, depending on the salience of gender issues, which are increasingly weaponised. Electoral competitiveness, domestic laws (i.e. quota requirements), and even the political system or global normative frameworks influence political will to act.Internal party factors that shape responses will vary across countries and contexts, but include: structures to enforce codes of conduct, policies and reporting mechanisms on (TF)GBV, political ideology, extent of centralisation of leadership, and crucially the meaningful participation of women in decision-making positions, not least through internal women’s wings.Party responses can be seen as a spectrum, with actions falling between active discouragement to address TFGBV to commitment to transform unequal norms and practices within the party.About the ToolkitTogether with the report, this ALIGN toolkit offers gender professionals and others working on democratic strengthening a set of guiding questions and reflection prompts to identify which responses could be most effective and suitable in different contexts. These actions can complement other solutions to TFGBV, such as regulations promoting safety by design. The assessment spans a broad range of factors including: (1) different manifestations of gender norms, (2) the socio-political environment and (3) internal party structures.Key messagesPolitical parties are duty-bound to take action internally to respond to the significant threats posed to women members and candidates, including from their own party colleagues, affiliates and political peers.Existing party approaches to TFGBV can be assessed along a spectrum which ranges from active discouragement and passive acceptance to minimal response and transformative change.To generate effective and context-appropriate solutions to TFGBV, it is important to consider how gender norms shape leadership expectations and internal party practices, while also analysing the impact of the socio-political environment. While actions to support women to stay safe online are very common, codes of conduct and measures to strengthen women’s voice and power in the parties are proposed as most transformative solutions.
Senate President J. Stuart Adams — burdened by data center fallout
After more than 20 years in the Legislature, Senate President J. Stuart Adams lost his bid for reelection Tuesday, conceding defeat to Stephanie Hollist.
MIP participates in online lecture on the ICTY for Munich students of international law and politics
On 22 June, the Mechanism Information Programme for Affected Communities (MIP) participated online in a session titled “The ICTY: Structures, Legal Significance and Political and Societal Perspectives in the Region and Serbia,” organised by Universität der Bundeswehr München as part of its Academic and Research Trip to Belgrade. The event took place at the Goethe‑Institute Belgrade and was attended by 20 master’s students and four faculty members from the graduate specialisation programme International Law and Politics.
Reprimanded after century in vain: Why Afghanistan captain Hashmatullah Shahidi was punished by ICC after the third ODI vs India
Afghanistan captain Hashmatullah Shahidi received an official reprimand and a demerit point from the ICC for damaging the pitch during the third ODI against India. Despite this, Shahidi scored a maiden century, but India secured a dominant nine-wicket victory, completing a 3-0 series sweep. Shahidi acknowledged his team's shortcomings against a strong Indian side.
New ‘Valorant’ Map Summit Features Dropping Walls That Block Routes
The new Valorant map, known as Summit, has been revealed at the Valorant Masters London tournament and it features some unique mechanics.
The Women Running Businesses Under Taliban Rules
With secondary education and most jobs out of reach, thousands of Afghan women have turned to entrepreneurship as the only path to make money and maintain a social life.
Scientists Finally Uncover Why Solid-State Batteries Short-Circuit
Researchers have uncovered a critical mechanism behind battery failure in solid-state batteries, offering new insights that could help unlock safer, longer-lasting energy storage technologies.
Alexis Ohanian’s VC firm acquires college sports trading card company ONIT
Ohanian plans to lean into ONIT's practice of making trading cards for a wide variety of college athletes, even beyond the biggest sports.
This Ghost in the Shell keyboard makes me want to activate the hundred spidery robot fingers inside my regular fingers
Ghost in the Shell: Stand Alone Keyboard
Shubman Gill surpasses MS Dhoni, enters elite India ODI list
Shubman Gill achieved a significant milestone by reaching 1,000 ODI runs in just 954 balls, surpassing MS Dhoni. This feat came during his brilliant 154 against Afghanistan, where he partnered with Ishan Kishan for a massive 224-run stand. Gill's century, his ninth in ODIs, was a masterclass in aggressive batting, further solidifying his status as a top modern-day Indian batter.
How Trump’s immigration crackdown puts Americans’ healthcare at risk
‘Ali’, from Afghanistan, is a ‘stellar’ doctor caring for patients in under-served West Virginia – but like many other foreign medics, his US future is now in peril
United States Announces U.S. Government Members of the U.S.-Uzbekistan Business and Investment Council
United States Announces U.S. Government Members of the U.S.-Uzbekistan Business and Investment Council Press Release June 16, 2026 Today, at the fifth annual Tashkent International Investment Forum (TIIF 2026), the United States announced the following inaugural members of the U.S.-Uzbekistan Business and Investment Council: U.S. International Development Finance Corporation (DFC) Vice President Bethany Aquilina Brez Export-Import Bank of the United States (EXIM) Senior Vice President Sarah Witten Assistant Secretary of Commerce, David Fogel Assistant Secretary of State for Economic, Energy, and Business Affairs, Caleb Orr U.S. Ambassador to Uzbekistan, Jonathan Henick Launched in Washington, D.C., in April 2026, the U.S.-Uzbekistan Business and Investment Council serves as the premier bilateral platform to accelerate trade and catalyze private sector investment between the United States and Uzbekistan. The Council is Co-Chaired by Special Envoy for South and Central Asia, Ambassador Sergio Gor and Saida Mirziyoyeva, Head of the Administration of the President of the Republic of Uzbekistan. The Council gives American businesses direct access to U.S. government financing, trade promotion, and market development tools to execute large-scale projects in Uzbekistan. Uzbekistan holds significant reserves of critical minerals essential to U.S. technology, defense, and energy sectors. The Council provides a direct mechanism to advance U.S. access to these resources through transparent, mutually beneficial partnerships. Through their participation, the American members of the Council will deepen the institutional framework for American commercial engagement in Uzbekistan.
Chargers' Mike McDaniel taking unusual approach to Justin Herbert relationship
Mike McDaniel is starting his tenure as Chargers OC in an unconventional way: by tinkering with QB Justin Herbert's mechanics.
Scientists just found a hidden weakness in forever chemicals
Researchers discovered that hydrogen radicals generated by intense UV light can break down stubborn PFAS “forever chemicals” without added chemicals. The breakthrough reveals a key mechanism that could lead to greener and more effective technologies for permanently destroying these pollutants.
Live Update 1.33.0
ARC Raiders is a multiplayer extraction adventure, set in a lethal future earth, ravaged by a mysterious mechanized threat known as ARC.
Iran agreement: Bad, BATNA or both?
As the debate over a possible Iran agreement shifts from whether there will be a deal to what is in it, commentary is already racing ahead of the facts. We have not yet seen the text. We do not know the precise commitments, timelines or enforcement mechanisms — if any.
Stephanie Ruhle on Money, Power, Politics and New MS NOW Morning Show
"We're living in unprecedented times," Ruhle tells The Hollywood Reporter.
MS NOW’s Stephanie Ruhle Moves From ‘The 11th Hour’ To Mornings With ‘Money, Power, Politics’
Ruhle signed off MS NOW's 'The 11th Hour' on Friday, and she debuts in her new role this morning after 'Morning Joe,' with a focus on how the economy and Washington impact real people.
Study identifies genetic cause for rare skin condition, points to new therapeutic option
The research highlights the value of studying rare genetic diseases to uncover fundamental immunological mechanisms.
Flight Crew Reveals Dangerous Passenger Behaviors
"The reason they tell you to ask the cabin crew for help if you lose your phone is not to be friendly or show how helpful they are. It's because if your phone is in a seat mechanism and that seat gets moved, the phone will be shredded, the battery may explode, and if it does, it will likely kill everyone onboard."
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
Health department recalls all Clover Hill Dairy cheeses over ongoing listeria risk
Maryland health officials are warning consumers not to eat, sell or serve any cheese products made by Clover Hill Dairy in Mechanicsville after expanding a cons
Health department recalls all Clover Hill Dairy cheeses over ongoing listeria risk
Maryland health officials are warning consumers not to eat, sell or serve any cheese products made by Clover Hill Dairy in Mechanicsville after expanding a cons
445 birds euthanized after bird flu found at Providence business
Cases of the H5N1 strain of avian influenza were confirmed in some birds at Antonelli Poultry in Providence, according to the Rhode Island departments of Health and Environment Management.
Fever's Caitlin Clark, Stephanie White called for 'soft' technical vs. Sky
Indiana Fever guard Caitlin Clark was assessed her third technical of the season after arguing a no-call against the Chicago Sky.
Scientists reveal surprising mechanism behind Venus flytrap’s rapid snap
Intricate tests show hair-trigger detection causes cells on outer surface of leaf to soften, prompting closure
Scientists Explored an Island Cave and Found 1 Million-Year-Old Remnants of a Lost World
A New Zealand cave revealed million-year-old fossils of ancient birds and frogs, showing extinctions began long before humans arrived.
Honor Magic V6 review: A mechanical marvel
There's a lot of impressive engineering inside Honor's Magic V6, but it's let down by software that desperately needs polish.
Oops, Scientists May Have Severely Miscalculated How Many Humans Are on Earth
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Business Restructuring Review Vol. 25 No. 3 May-June 2026
In This Issue Texas Bankruptcy Court Adopts Barnet Rule Requiring Foreign Debtor to Have U.S. Assets to Be Eligible for Chapter 15 Relief In In re Siu-Fung Ceramics Holdings Limited, No. 24-33299, 2026 WL 382424 (Bankr. S.D. Tex. Feb. 10, 2026), the court denied petitions for chapter 15 recognition of Hong Kong bankruptcy and liquidation proceedings commenced on behalf of an individual debtor and a group of companies that he owned or controlled. According to the court: (i) the corporate debtors' Hong Kong liquidation proceeding was not eligible for chapter 15 recognition because the attorney retainer upon which such relief was based was not funded until nine months after the chapter 15 petition date; and (ii) the individual debtor's Hong Kong bankruptcy case could not be recognized because the debtor's "center of main interests" on the chapter 15 petition date was not in Hong Kong, and he did not even maintain an "establishment" there. [read more …] Southern District of Texas Clarifies Post-Purdue Course for Consensual Third-Party Releases and Gatekeeping Provisions In In re Container Store Group, Inc., 676 B.R. 356 (S.D. Tex. 2026), appeal filed, No. 26-20166 (5th Cir. Apr. 14, 2026), cross appeal filed, No. 26-20166 (5th Cir. Apr. 24, 2026), the U.S. District Court for the Southern District of Texas addressed consensual third-party releases and gatekeeping provisions in the aftermath of the U.S. Supreme Court's ruling in Harrington v. Purdue Pharma L.P., 603 U.S. 204 (2024). Consistent with existing Fifth Circuit precedent, the court confirmed that, in appropriate circumstances, consent for third-party releases may be obtained through a creditor's failure to opt out of granting that consent. But, the court ruled, consent through an opt-out mechanism essentially can never be inferred for creditor classes that stand to receive no recovery under a chapter 11 plan and that are deemed to reject the plan by operation of applicable bankruptcy law. Instead, those classes must affirmatively opt in to any release. The court also narrowed and remanded the bankruptcy court's acceptance of a broad gatekeeping provision, ruling that such provisions must correspond to the restrictions established by Fifth Circuit precedent. [read more …] Delaware Bankruptcy Court: Initial Transferee Need Not Be Defendant in Fraudulent Transfer Avoidance and Recovery Litigation The Bankruptcy Code gives a bankruptcy trustee the power to avoid asset transfers that are either made with the intent to defraud creditors or that are "constructively" fraudulent because an insolvent debtor did not receive adequate value in exchange. The Bankruptcy Code also permits recovery of an avoided transfer from not only the initial recipient, but also from subsequent transferees. Courts disagree over whether a transfer must actually be avoided before the trustee can seek recovery from a subsequent transferee and whether the initial transferee must also be a defendant in the recovery litigation against a subsequent transferee. The U.S. Bankruptcy Court for the District of Delaware weighed in on this debate in Phillips v. SS Associates LLC (In re ONH AFC CS Investors, LLC), No. 23-10931 (CTG), 2026 WL 312892 (Bankr. D. Del. Feb. 4, 2026). The court adopted the majority view, ruling that the initial transferee need not be a defendant in avoidance and recovery litigation against a subsequent transferee, but that the trustee must establish the elements necessary to avoid the initial transfer as part of the recovery litigation. [read more …] New York Bankruptcy Court Weighs In on Adequate Assurance of Future Performance under Assigned Leases and Chapter 11 Plan Exculpation Provisions In order to assume and assign an executory contract or unexpired lease, a bankruptcy trustee must cure most defaults under the agreement and provide "adequate assurance" of the assignee's future performance. However, the Bankruptcy Code provides no guidance as to the meaning of "adequate assurance" other than with respect to shopping center leases. In In re Broadway Realty I Co. LLC, No. 25-11050, 2026 WL 147505 (Bankr. S.D.N.Y. Jan. 19, 2026), the U.S. Bankruptcy Court for the Southern District of New York examined this issue in connection with a proposed assignment of thousands of residential leases as part of a free-and-clear sale of debtors' properties. The court held that "adequate assurance" does not mean a guarantee of the assignee's future performance, but merely demonstration that the assignee has the ability to satisfy the underlying obligations. The bankruptcy court also ruled that an exculpation provision in the debtors' chapter 11 plan exonerating non-estate fiduciaries from liability for actions taken in connection with the chapter 11 case was unobjectionable, provided it was limited in scope to postpetition conduct and actions taken in connection with implementation of the plan after its effective date. [read more …] Newsworthy Corinne Ball (New York) (Hall of Fame), Bruce Bennett (Los Angeles), Carl E. Black (Cleveland), Jeffrey B. Ellman (Atlanta), Brad B. Erens (Chicago), Gregory M. Gordon (Dallas), Heather Lennox (Cleveland/New York), Joshua M. Mester (Los Angeles), and Kevyn D. Orr (Washington) were included in the 2026 edition of Lawdragon 500 Leading Bankruptcy and Restructuring Lawyers. The Daily Business Review selected Isel M. Perez (Miami) as an "On the Rise" winner for the Florida Legal Awards. The Florida Legal Awards annually recognize those who have made significant contributions to the legal industry in Florida. Dan T. Moss (Washington/New York) was inducted as a Fellow in the 37th Class of the American College of Bankruptcy at its Annual Meeting in March 2026 in San Antonio, Texas. Christine Borries (Munich) was ranked in the practice area Restructuring/Insolvency in the 2026 edition of Chambers Germany. The 2027 edition of The Best Lawyers in Singapore™ recognized Sushma Jobanputra (Singapore) in the practice area Insolvency & Reorganization. The restructuring transaction involving Eissmann Automotive North America, Inc. received the "2025 Turnaround of the Year (Large Company)" at the Turnaround Management Association (Detroit) Annual Awards Reception. T. Daniel Reynolds (Cleveland) and Nick Buchta (Cleveland) represented subsidiaries of Eissmann Group Automotive in connection with the parent company's German insolvency proceedings. Roger Dobson (Sydney) is among 40 Jones Day lawyers recognized by The Best Lawyers in Australia 2027 for his contributions in Banking and Finance Law; Distressed Investing & Debt Trading; Insolvency and Reorganization Law; Litigation. An article written by Corinne Ball (New York) titled "Ard Finance—A Global Enterprise Combining an LME With a Foreign Insolvency Proceeding and Chapter 15" was published in the April 21, 2026, edition of the New York Law Journal. An article written by Alex Sapp (New York) titled "Recent Developments in Section 510—Subordination" was published in the 2025 edition of the Norton Annual Survey on Bankruptcy Law. An article written by Brad B. Erens (Chicago) titled "New York Bankruptcy Court Approves Insider DIP Litigation Financing" was published on April 6, 2026, by Lexis Practical Guidance. An article written by Corinne Ball (New York), Dan T. Moss (Washington/New York), David S. Torborg (Washington), and Isel M. Perez (Miami) titled "New York District Court Affirms Narrow Scope of 'Public Policy Exception' in Chapter 15 Cases" was published on April 6, 2026, by Lexis Practical Guidance. An article written by Jeffrey B. Ellman (Atlanta) titled "Statutory Cap on Lease Rejection Damage Claims in Bankruptcy Applies to Solvent Debtors" was published on April 6, 2026, by Lexis Practical Guidance. An article written by Trisha L. Mowbray (Real Estate; Chicago) and Ryan Sims (Washington) titled "Chapter 11 Plan that Abridged Non-Debtor Lessee's Rights to Remain in Possession After Rejection Unconfirmable as Having Been Proposed in Bad Faith" was published on April 6, 2026, by Lexis Practical Guidance. Lawyer Spotlight: Ben Rosenblum Ben Rosenblum, a partner in the New York Office, represents debtors, creditors, and other parties in out-of-court restructurings and court-supervised proceedings, including chapter 11 cases, municipal bankruptcies, international insolvency matters, and stockbroker liquidations. His experience spans industries such as manufacturing, shipping, mining, aviation, energy, real estate, and telecommunications. Ben's notable debtor representations include Peabody Energy, the City of Detroit, Chrysler LLC, Spansion Japan, and Dana Corporation. Significant creditor representations include General Maritime Corporation, Calpine Corporation, American Home Mortgage, and Murray Energy. He currently represents creditors in Puerto Rico's restructuring. He also has extensive experience advising financial institutions on bankruptcy law as applied to derivatives.
Humans prefer to walk anticlockwise, scientists find
From Spain to Japan, experiments have repeatedly shown a left-turn bias, but exact mechanic ‘is still an open question’
Iran war ripple effects are increasing risks of acute hunger for millions, World Food Program chief says
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From Classroom to Racetrack: How Charlie Baur is Building a Motorsports Career in a Business Discipline
Charlie Baur can trace his racing story back to a Christmas morning in Michigan — the kind that starts with snow on the ground and ends with a throttle in a kid’s hands. “I remember being 3 years old and then for Christmas that year, my parents had gotten me a 120 cc snowmobile,” Baur said. Long before sprint cars, he was a Michigan kid on snowmobiles, dirt bikes, four-wheelers and jet skis — and a regular at car shows and races with his family. Photo courtesy of Charlie Baur That early exposure became a calling. At 12, he sat in a sprint car for the first time and knew he’d found the next chapter. He started in quarter midgets, moved to go-karts, and the day before he turned 16 — one day shy of the minimum age required by track insurance — he made his first sprint car start after convincing officials to let him race. Five years later, Baur is still pushing forward, now racing sprint cars on both pavement and dirt while pursuing an automotive business education at Northwood University — with a clear-eyed understanding that motorsports encompasses more than what happens under the lights on Saturday night. “It’s a business,” said Charlie, a 20-year-old who calls Fenton, Michigan, home when he’s not at a racetrack or at Northwood’s residential campus in Midland, Michigan. Photo courtesy of Charlie Baur Racing is the product — but preparation is the job To the average fan, race day begins around dinner time. For a team, race day can be a 12-hour shift — plus the work that came before it. And Baur’s racing operation is a family affair. “The team is my parents and myself,” he said, explaining they own the cars, maintain equipment and manage the business side — from sponsor relations to budgeting. On race weekends, the core group includes Baur and his parents (Eric and Stefanie), plus a couple of additional hands (Alex Photiou and Robert Flannigan) who help with the intensity and pace of trackside work. That structure has shaped how he thinks about efficiency and professionalism. “We’ve always kind of had the mentality of we’re never working on the car for maintenance at the track,” he said. “Our goal is to do as little work as possible to the car because it should be ready when that car rolls out of the trailer to go racing.” That mindset shows up in routines: bolt checks, tire procedures, safety equipment and a repeatable process designed to limit errors. “Once I fire the car up and put my helmet on, that’s when it’s go time,” he said. “You can plan as much as possible for how the race is going to play out, but until you take the green flag … you don’t know how it’s going to go.” Photo courtesy of Charlie Baur First-generation driver, student of the game In racing, “first-generation” matters — and Baur wears that label with pride. “A lot of the drivers are third or fourth generation,” he said. “My family has never been in motorsports. So for me, we’ve always looked at it as we’re new to it and we want to be as different as possible. From a marketing standpoint, it helps us stand out.” It also pushes him to seek out mentors — especially veteran drivers who have seen every scenario, solved every problem and won in multiple eras. Baur credits accomplished driver Jason Blonde, a 10-time champion, for becoming his driver coach and helping him develop as a competitor. “To me, learning from Jason helps me because he has had lots of success and knows what to do,” Baur said. “You have to humble yourself and say, ‘I don’t know what to do; can you help me out?’” That willingness to learn extends off the track, too. Baur says one of his biggest challenges is not a mechanical limitation, but credibility. “It’s my age,” he said. “Some people won’t take me seriously because I’m so young. Even though … I do know what we’re talking about and have a general idea.” His answer has been to out-prepare, out-communicate and treat the operation like a real enterprise — because it is. Photo courtesy of Charlie Baur Northwood’s role: Turning passion into a plan Baur is majoring in automotive aftermarket management and pursuing an accelerated path that pairs undergraduate study with graduate work. He’s also exploring how to align his studies with motorsports-focused coursework as Northwood advances related programs and pathways. He sees the value clearly: motorsports needs business-literate professionals who understand budgets, sponsorship, marketing, operations and long-term strategy — and who can translate between the language of the shop and the language of the boardroom. That’s why his Northwood experience isn’t limited to the classroom. He has been involved with the Northwood University International Auto Show and serves as motorsports chair — a leadership role that demands outreach, contracts, coordination and a steady professional demeanor. “There’s so much outside work that makes the auto show successful that people don’t realize,” he said. “And it is truly student led.” He’s also participated in industry experiences through Northwood at major events such as AAPEX, SEMA and PRI, along with other automotive networking events — opportunities he describes as a fast track to understanding how business really gets done. “You learn a lot in the classroom,” he said. “But if you learn it and you can’t apply it to the real world, it loses its value. Or if you learn it and can apply it, but you don’t know anyone, it is still of no value.” In his words, Northwood helps him win because it “gives me the tools to succeed” — including flexibility and faculty support as he balances travel and racing commitments with academics. Photo courtesy of Charlie Baur Racing as an ecosystem — and a talent gap waiting to be filled Baur is blunt about what he sees across the motorsports world: a deep bench of experienced professionals, and not enough young talent entering the pipeline. “I go to car shows, I go to these different events, and typically … the average age is between 45 to 55,” he said. “There’s not a lot of young people going into the motorsports world.” That reality reinforces Northwood’s communications focus: positioning motorsports not as a narrow lane, but as a wide ecosystem of business careers — sponsorship, logistics, data, media, leadership, hospitality and innovation — with real demand for prepared graduates. It also shapes how Baur talks to younger students who love racing but aren’t sure what their future looks like. “If you have a passion for motorsports, there’s gonna be a spot for you somewhere,” he said, emphasizing that driving is only one of many career paths — and that local tracks and hands-on experience are often the best first step. But if someone is interested in driving as a career path, it will take a team to make that happen. Baur’s team includes Stahl’s Motors and Music Experience, Rhino Racing, Randy Wise Buick GMC Chevrolet, Western Michigan Fleet Parts, Mother’s Polish, Schaeffer’s Oil, Hepfner Racing Products, Ameriguard Storage Centers, Justice Brothers, Race 1 Wraps, TBM Brakes, Behind Your Design, CharlieBaur.com and Northwood University. “There are so many people who invest not only in myself but in my race team and who believe in us to succeed,” he added. Pictured: Charlie Bauer’s sprint race car. Looking ahead: A headline worth chasing Ask Baur to imagine 2035, and he’ll give you two answers — one dream, one blueprint. “In a perfect world,” he said, “winning the Indy 500.” Realistically, he wants to build a life where business ownership and racing reinforce each other and where he can pay forward the help he has received by mentoring younger drivers, especially those trying to break into motorsports without a family legacy. “When I retire from full-time racing, I want to be able to provide the same opportunities that were presented to myself to the next generation of drivers,” Baur said. “I know how difficult it is to get your foot in the door.” For now, the focus is simple: keep building the operation, keep learning the business, and keep showing up prepared — because in sprint car racing, as in life, process matters. And once the helmet goes on? “It’s go time,” Baur said. Photo courtesy of Charlie Baur Learn more Students interested in motorsports careers — whether in competition, team operations, marketing, finance, sponsorship, data, or management — can explore opportunities through Northwood University’s Center for Automotive and Mobility Studies. For Charlie Baur’s latest motorsports adventures, follow Charlie_Baur and Charlie Baur Racing on social media. To learn more about Northwood’s Bachelor of Business Administration in Automotive and Mobility Studies and motorsports management concentration, visit www.northwood.edu/programs/automotive-mobility-studies/. Photo courtesy of Charlie Baur Pictured: Charlie Baur at Butler Motor Speedway on May 31, 2026. Share this page
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Nothing takes away from the frustration and the deep disappointment so many climate and energy hawks are expressing, the sense of betrayal by the author of Value(s) and the former UN special envoy for climate action and finance. But we knew two things as the week drew to a close. We’re looking at the world as it most definitely is. And we don’t get to give up finding the pathways to confront climate change and deliver faster, deeper carbon cuts that leave no one else behind. So really, the first question we all have to ask ourselves is: What’s next? Subscribe All the Oxygen in the Room The outpouring of anger and grief over the carbon pricing deal between Prime Minister Mark Carney and Alberta Premier Danielle Smith has been absolutely understandable. So much of the climate community poured years, more than a decade, into dragging the current federal pricing regime across the finish line, then defending it from a deluge of three-syllable rhymes after the Trudeau government proved utterly incapable of delivering its own message. The policy foisted on us by neo-classical economists took up all the oxygen in the room, burned through years of climate response time that we won’t get back, while cornering climate hawks into the position that the best response to the crisis of our lifetimes is a new tax…in an era of historic anti-tax sentiment. I mean, really—what could possibly have gone wrong? Against that history, let’s appreciate columnist Max Fawcett’s point that even a modest carbon pricing agreement with a government as off-the-wall libertarian/conspiracist as Danielle Smith’s—those adjectives are mine, not Max’s—is a win worth savouring (as long as Smith keeps her promises for a change). But part of living in the world as it is (no, I’m not letting that go) is to be clear-headed about what we can and can’t control. And one thing we get to decide, after seeing this week’s carbon price festivities take up all the oxygen yet again, is whether we want to keep letting that happen. Particularly when success down that road depends on a factor that no one with a climate agenda can control or influence—a provincial carbon pricing mechanism that has been manipulated and eroded beyond its lowest possible denominator. Thankfully, that’s not the way it has to go. Not when we have so many other powerful, practical tools at our disposal, including the ones still available to us through this abominable Memorandum of Understanding (MOU) between Canada and Alberta. Tools In Our Toolbox When I started roughing out this list, I didn’t expect it to grow to nearly a dozen bullet points. It’s probably still incomplete. Some of the greatest hits in today’s climate solutions toolbox include: • No Carbon Capture, No Pipeline: On Friday, Prime Minister Mark Carney explicitly stated that there’s been no change to the MOU provision that there will be no West Coast pipeline without an industry commitment to build its massive, $16.5-billion carbon capture and storage (CCUS) hub in Northern Alberta, and vice versa. The two megaprojects were joined at the hip when the MOU was signed Nov. 27, and the implementation agreement this week affirmed that they still are. A parade of independent analysts have spent years pointing to the economic and technical flaws in CCUS, while the industry kept postponing its investment decision until it could arm-twist the government for more “clarity” (by which it meant even more lavish taxpayer subsidies) on the project. Now the industry itself is running away from the CCUS hub and insisting the pipeline should proceed without it, but Carney doesn’t seem to be budging from a central tenet of the MOU to which Smith has signed on. • No Subsidies, No Investors: Climate analysts and advocates have quite rightly been hammering away at Carney and his team, insisting that any new capacity the industry wants to build must proceed without new subsidies. The government has responded with a growing collection of funding and financing mechanisms for the very wide menu of industrial development and nation-building projects they say they want to take on, and that menu always includes fossil fuel infrastructure. But it’s hard to see how even the combined fiscal clout of the federal and supportive provincial governments will deliver the financial backing private investors would need when the business case for new fossil fuel development is evaporating before their eyes. Particularly when… • No Market, No Demand, No Investors: As our friend Markham Hislop at Energi Media (our apparently sleepless friend, given the massive volume of great material he’s been churning out) points out this morning, the biggest vulnerability in any pipeline deal is the assumption that Asian buyers will want the oil or liquefied natural ga that our fossil industry is so keen to send them. Hislop writes in part: Ottawa and Alberta are effectively betting that countries like China and India will continue increasing oil imports for decades as their economies grow and energy consumption rises. That assumption underpins the entire economic rationale for expanding oil sands production and building billions of dollars in new export infrastructure. But Asian energy systems are changing rapidly… China, India, South Korea, and other major hydrocarbon importers are now investing hundreds of billions of dollars into electricity systems built around wind, solar, batteries, nuclear, hydro, and expanded transmission infrastructure. Domestic “energy sovereignty” is increasingly replacing the old energy-security model based on stable oil and gas imports. Those investments are expected to sharply slow oil demand growth and eventually reverse it, even as overall energy consumption continues rising. There are also refining constraints. Many Asian refineries and petrochemical complexes are already optimized to process discounted heavy crude from the Middle East and Latin America. That raises serious questions about how much additional Canadian bitumen Asian markets can absorb at profitable prices. Small wonder that there’s still no private sector investor for the project, despite Smith’s government desperately beating the bushes to put together a deal. For now, Alberta is acting as proponent and covering early start-up costs for a pitch to the federal Major Projects Office, which could actually turn into the next tough hurdle for Smith and her pipeline to jump. • Canada Day Looms: How ironic that Canada’s birthday this year could become a major chokepoint for the provincial premier who’s been working so diligently to tear the country apart! The July 1 target date for Alberta’s pipeline proposal is baked into the MOU, was reaffirmed by the implementation plan, but it hadn’t dawned on me that it cuts both ways. As one very smart colleague wrote in an email yesterday, “they’ve thrown the ball into Alberta’s court to get the project proposal on the table really quickly and to have to do a whole pile of work to put together a massive, complicated project that would typically take years to assemble, and they’ve given them weeks to do it.” That makes July 1 a looming deadline that Smith won’t be able to run away from politically, especially with the separatists in her party and her caucus breathing down her neck. (See previous ref to off-the-wall.) But if Alberta comes in with a sloppy, incomplete submission, even after Carney bent over backwards to simplify the application process and the rules that govern it, it may be harder for the province or the industry to blame Ottawa and insist on the faster process they claim their investors are demanding. (Oh, wait—which investors would those be??) • We’ll See You In Court (Then We’ll See You Again): If Carney did cave, that would be just one more reason for Indigenous and other affected communities to take the government and the process to court—Just as Alberta First Nations did, successfully, in response to Smith’s half-baked separation referendum. Veterans of the Harper era have been warning that a shoddy process around fossil fuel infrastructure or other major projects will be a recipe for the very delays that process seeks to avoid. And now more than ever, with renewable energy and energy storage eating fossil fuels’ lunch in import markets around the world, a delayed pipeline or LNG terminal may be as good as a cancelled one. • Charged Up, Ready to Go: With its goal of doubling Canada’s electricity supply to meet a doubling of demand by 2050, the national electricity strategy that Carney unveiled Thursday has a lot to like. With its explicit language about speeding the shift from fuels to more efficient and affordable electricity, global investment and deployment patterns that already favour that shift, an emerging bidirectional power grid, the role of front-line options like rooftop solar and heat pumps, the emergence of electric vehicles as behind-the-meter energy storage, and the domestic jobs and manufacturing to make it all happen, the document doubles down on the essential cornerstone of a faster shift off fossil fuels. The strategy envisions a more prominent role for gas and nuclear power. But some of those provisions were already in the Clean Electricity Regulations that climate hawks are now fighting so hard to defend, inserted as a compromise in a futile attempt to mollify the industry and its political representatives in Alberta and Saskatchewan. But once again, gas will be a tougher sell when it’s more expensive and now so much more unpredictable than the clean alternatives. The new nuclear technologies are still speculative and deeply vulnerable to cost overruns. Increasingly, utilities, developers, and investors know it. Carney declared Thursday that “it doesn’t do us good to be sitting in court all the time with provinces. It doesn’t do us good to be talking past each other. What does do us good is to come together with specific projects.” There are no guarantees, but so much of the language and narrative-building in the electricity strategy suggests the lion’s share of those projects will be renewable. • The Party Has Already Started: The electricity strategy only rarely digs down to specific projects, but provinces representing three-quarters of Canada’s population are already embracing a faster transition. Hydro-Québec is working on a 10-year, $185-billion renewable energy and grid buildout by 2035. Ontario recently brought 10 provinces and territories together in a National Energy Corridor Agreement to boost interprovincial and -territorial transmission infrastructure. And the MOU implementation agreement commits Alberta to facilitate investment in renewable energy projects, a big step back from its continuing, punitive restrictions on renewables development. The electricity strategy envisions much of the financing and infrastructure that will be needed to pull those advances together into an integrated whole. • Delivering on Affordability: The MOU implementation plan has little or nothing to say about affordability (are you surprised?), but the electricity strategy does, with a top-line pledge to reduce home energy costs for seven out of 10 Canadian households by 2050, a total saving of $15 billion across the board. It’s just a start, but it puts affordability on the government’s narrative map. If they’re serious and deliberate about patching together a least-cost energy strategy, it’ll have little if any room for oil, gas, or nuclear—not with powerful evidence, for example, that electricity prices are higher when those prices are set by gas. • Smith Proves that Canada Works: By signing a deal that makes it harder to claim the federal government is blocking a new pipeline, Smith has helped prove Carney’s constant anti-separatist refrain that “Canada works”—incurring the rage, no doubt, of her own political base. Canada also needs to work for anyone who depends on a clean environment, healthy and thriving ecosystems, and safe, stable climate. But with Smith and her separatist constituents setting up as a fifth column for annexation by Donald Trump’s United States, let’s set aside any notion that 51st state status for Canada is a recipe for anything other than climate disaster (and so much else). Resisting and withstanding Trump (just 170 more sleeps until mid-term elections, which is a damn sight better than the 730 we started with) doesn’t mean a free pass for a pipeline, but we can still appreciate it that keeping Canada whole and sovereign is still Carney’s Job One. • The Words Not Spoken: Apart from a commitment to export a million barrels of “low-emission” Alberta bitumen per day (memo to Smith and Carney: You realize that that’s less than the industry is already exporting??), the MOU implementation plan says nothing about the international trade and economic sovereignty deals that Carney has been travelling the world to negotiate. It didn’t have to. Carney doesn’t need permission from Danielle Smith, her American enablers, or her separatist allies to continue building the alliances that will ratchet down our economic dependency on our unstable, unreliable neighbour to the south. But every connection he builds with countries outside North America helps align our economy and our future with a faster shift off fossil fuels. Little if any of this was on our bingo cards a year or two ago. But it’s the pathway that has opened up to us. And if it gives Canada any climate or energy gains at all in an era still dominated by Trump and his increasingly ridiculous tariffs, his loutish trade negotiations and his continuing annexation threats, we have to take the wins. Not least because they’ll be the point of departure for what we can achieve in 2027, 2029, and beyond, as Trump’s grip and this era begin to loosen and then fade. What is Carney Doing? If this line of thought is right—and it’s a possibility, not a prediction—it means that Carney’s actions and decisions are largely about buying time. Time for Trump’s power to wane. Time for Alberta’s separatist/conspiracist virus to spread, mutate, die out, or at least die back, with help from a vaccine of federal steadiness and calm (appropriate enough, for a movement populated largely by vaccine deniers) that no conspiracy theory can dismiss. And time for the government’s trade and investment agenda to deliver results—even knowing that some of those results will bring impacts that front-line communities will not and should not accept. In the immediate moment, none of this changes the way the wider climate community has to respond, from campaigners to investors to front-line practitioners. All of our voices are still essential. But those voices will be stronger and more confident if we have a clearer sense of the brutal game we’ve been pulled into, and a plausible path (or two it three) for playing it to the win we need. This conversation also underscores our biggest task for the remaining years of what was supposed to be the “decisive” decade for climate response: if we can shift the energy narrative in Canada, make it a mainstream view that the country’s preoccupation with oil and gas has us falling farther behind a changing world, we’ll see far better results in the 2030s and beyond. For many veteran climate advocates, taking on that part of the fight will begin with recognizing that most of our friends and family, neighbours and colleagues already understand that climate change is real and right in front of us: they’re looking away and staying silent because they don’t have what climate communicator Katharine Hayhoe calls “efficacy”. As Hayhoe recently pointed out in a feature interview with The Energy Mix, it amounts to science denial to keep hammering away at the dire news about global warming without also helping audiences understand what they can do about it, with multiple studies telling us why that won’t work. Far better to open those conversations with the dominant crises like energy security, food security, emergency preparedness and business continuity, affordability, and financial security that have knocked climate change far lower on the list of public priorities, and will likely keep it there. We Knew This Would Happen Climate hawks have always known this day would come. For decades, we warned that everyone had to pay attention to climate change right now, because it would be much tougher to respond once the crisis itself started affecting our daily lives. We were right, and here we are. But now, thanks to decades of hard work, communities and countries have an alternative to doubling down on fossil fuels. “In 10 years everyone will have ‘always known’ that solar and batteries were going to win,” Morgan Solar Executive Chair Mike Andrade writes on LinkedIn. With the disruption in the Strait of Hormuz roiling energy priorities around the world, Canada and the United States are among the shrinking number of countries that are still very keen on fossil fuel development. Understanding that gap is a first, essential step in spotting the opportunities ahead, and averting the deep economic as well as environmental and social risk we face if we don’t seize them. Thanks for reading The Energy Mix Weekender! Subscribe for free to receive new posts and support our work. Subscribe Mitchell Beer traces his background in renewable energy and energy efficiency back to 1977, in climate change to 1997. Now he and the rest of the Energy Mix team scan 1,200 news headlines a week to pull together The Energy Mix and The Energy Mix Weekender. Chart of the Week BYD Eyes 20 Dealership Locations After Canada Greenlights Chinese EV Imports ‘Sledgehammer’ Carbon Price Deal Boosts Emissions by 230Mt, Aims for Fall 2027 Pipeline Approval ‘Worse Than Harper’: Regulatory Rollback Would Stop Canada from Assessing Project Impacts, Critics Warn Electricity Strategy Aims for Doubling by 2050, Allows ‘Flexibility’ for Gas Power Plants Opposition Mounts as O’Leary’s Data Centre Approved in Drought-Stricken Utah Diluted Carbon Price Misses ‘Reality of the World We’re In’, Could Impede Diversified Trade: Climate Institute $200B in Clean Energy Investment Will Need On-Time Delivery, Reliable Policies, Trade Association Says ‘Sovereign Pipeline’: CEO Pitches to Keep Trans Mountain in Government Hands What a Supercharged El Niño Could Mean for Canada Canada’s future is electric, and here’s how a power grid superhighway would get us there (Toronto Star) The Perilous Waters of Hecate Strait (Globe and Mail) Saudi Aramco profits jump despite conflict in Middle East (The Guardian) Farmers confront rising cost of fertilizer and fuel as spring seeding under way (Canadian Broadcasting Corporation) Clarkson forecasts 24% decline in offshore oil, gas capital expenditures (Oil & Gas Journal) Pipe Dreams: How Oil and Gas Fail to Deliver Economic Development in Africa (Oil Change International) Developing countries must hold the pen to script the fossil fuel transition (Climate Home News) Iran war threatens the dream of a post-oil economy in the Gulf (Washington Post) U.S. Oil, Gas Work Force Hits Lowest Level Since 2022 (Rigzone) Why Polestar Is Doubling Down on Net Zero as Rivals Pull Back on EVs (Bloomberg) Why this Michigan utility plans to sell its hydro dams for $13 (E&E News/Politico) Levees can no longer save New Orleans (Vox)
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