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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?

Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.

Jun 14 • 3:14 PM EDT • Technology • newsletter.semianalysis.com

Samsung Galaxy S27 and Xiaomi 18 spotted: Major Leica camera lineup changes expected

Months before launch, early traces of two of next year's likely most important camera flagship rivals have appeared in databases. Model numbers have been discovered for both the Samsung Galaxy S27 and an initial Xiaomi 18 model, with major changes to the lineup becoming apparent for the latter in particular.

Jun 14 • 12:01 PM EDT • Technology • notebookcheck.net

Eliminating dietary sugar may disrupt gut health and promote inflammation

Eliminating sugar from your diet may be more detrimental than previously thought, according to an animal study being presented Saturday at ENDO 2026, the Endocrine Society's annual meeting in Chicago, Ill.

Jun 14 • 10:48 AM EDT • Health • news-medical.net

Flashpoint June 14, 2026: Cash in politics, Michigan Chronicle's 90th and the Gordie Howe Bridge

Jun 14 • 10:00 AM EDT • Politics • clickondetroit.com

Oregon couple uses social media sketches to advocate for transparency in healthcare

Dr. and Lady Glaucomflecken — otherwise known as Will and Kristin Flanary — are using humor for healthcare advocacy and education.

Jun 14 • 9:00 AM EDT • Health • opb.org

Intel Raptor Lake “Next” Desktop CPUs To Come In Core 7, Core 5, Core 3 Flavors With Up To 20 Cores But Retain 8 P-Cores On LGA 1700 Socket

Intel Raptor Lake Next Desktop CPUs will bring value-oriented options to mainstream and budget gamers on the existing LGA 1700 sockets.

Jun 14 • 7:25 AM EDT • Technology • wccftech.com

Galaxy S27 Ultra Could Finally Address Endless Customer Complaints Of Older Flagships As Samsung Plans Three Upgrades Next Year

The Galaxy S27 Ultra may finally rectify the mistakes of older flagships as Samsung is rumored to introduce three upgrades in 2027

Jun 14 • 7:20 AM EDT • Technology • wccftech.com

Yellowstone wolves may not have reshaped the national park after all

One of the most celebrated claims about Yellowstone’s wolves is facing a major challenge. Scientists say the study behind the famous trophic cascade story relied on flawed methods that overstated the ecological impact of wolf recovery. Their reanalysis found no evidence for a dramatic, park-wide surge in willow growth. Instead, the effects appear smaller and vary from place to place.

Jun 13 • 8:00 PM EDT • Science • sciencedaily.com

Scientists found a surprising problem with sugar-free diets

A surprising new study suggests that completely eliminating sugar may backfire. Mice on a sucrose-free low-fat diet showed worse blood sugar control, increased inflammation, disrupted gut bacteria, and signs of fatty liver compared with mice that consumed some sucrose. Researchers say the results highlight the importance of a balanced diet and a healthy gut microbiome rather than focusing solely on cutting out sugar.

Jun 13 • 8:00 PM EDT • Science • sciencedaily.com

Bran flakes could be classed as junk food under new guidelines to promote healthy eating

UK government wants to update nutrition rules to include naturally occurring ‘free sugars’ when determining what is unhealthy

Jun 13 • 6:55 PM EDT • Health • theguardian.com

Braves add SP Spencer Strider to 15-day IL with right elbow inflammation

Jun 13 • 11:19 AM EDT • Sports • sports.yahoo.com

Ohio State Fair 2026 tickets drop to $6.14 for 614 Day flash sale

The Ohio State Fair is offering a 12-hour flash sale on June 14 with tickets priced at just $6.14 for the 2026 event.

Jun 13 • 11:07 AM EDT • Entertainment • dispatch.com

Critical Splunk Enterprise Flaw Lets Attackers Run Code Without Authentication

Splunk issued security updates for a critical CVSS 9.8 vulnerability in Splunk Enterprise that allows unauthenticated remote code execution.

Jun 13 • 9:23 AM EDT • Technology • thehackernews.com

How parents can talk to their kids about vaping as FDA authorizes some flavored e-cigarettes

Nearly 6% of U.S. middle and high school students vape

Jun 13 • 8:21 AM EDT • Health • washingtonpost.com

Shohei Ohtani sits Friday with left knee inflammation

Shohei Ohtani did not play in Friday’s series opener in Chicago after leaving Thursday’s game in Pittsburgh with left knee inflammation. Ohtani got an MRI on his left knee with showed “normal wear and tear,” manager Dave Roberts told reporters Friday in Chicago. “With the travel, just to give him an extra day. My hope […]

Jun 13 • 8:06 AM EDT • Sports • sports.yahoo.com

Metro Detroit flag businesses prep Old Glory for America's 250th

As July 4 and the nation's 250th draw near, Metro Detroit flag stores are sewing up business to provide American flags made by Americans.

Jun 13 • 12:01 AM EDT • Business • detroitnews.com

Hillsborough's Accidental Baker grows from home kitchen to award-winning cracker company

The Accidental Baker produces artisan flatbread crackers out of Hillsborough.

Jun 12 • 3:32 PM EDT • Business • abc11.com

AMD Stiffs Researcher $10,000 Bug Bounty After Critical Security Flaw, Takes 124 Days to Fix

AMD's auto-updater downloaded software over insecure HTTP, letting attackers inject malware during updates before a 124-day delayed fix.

Jun 12 • 1:17 PM EDT • Technology • gadgetreview.com

Scientists stunned by two-headed worms—now they’re multiplying without limits - Futura-Sciences

The Unusual Reproduction of Stenostomum brevipharyngium Meet Stenostomum brevipharyngium, a microscopic flatworm that has no need for romance or even a partner when it comes to making more of its kind. This species reproduces by paratomy, an asexual process in which a new worm forms from the middle section of...

Jun 12 • 1:00 PM EDT • Science • futura-sciences.com

Study finds 5 daily servings may fall short of key heart-health compounds

Researchers report that many people in the U.S. and U.K. are not consuming levels of flavanol-rich fruits and vegetables associated with better cardiovascular outcomes.

Jun 12 • 12:23 PM EDT • Health • foxnews.com

US consumer sentiment improves in June due to easing gas prices

Consumer sentiment still remains at historically low levels amid Iran war and rising inflation, new survey shows

Jun 12 • 12:23 PM EDT • Business • theguardian.com

Spielberg seeks blockbuster comeback with ‘Disclosure Day’

Steven Spielberg began tackling the story for his latest movie, "Disclosure Day," after a rare sequence of two films that fell flat at the box office. He started writing in

Jun 12 • 11:42 AM EDT • Entertainment • recorderonline.com

Dodgers' Shohei Ohtani exits with knee, hamstring issue vs. Pirates

Los Angeles Dodgers star Shohei Ohtani experienced knee and hamstring inflammation and exited early during a win over the Pittsburgh Pirates.

Jun 12 • 8:31 AM EDT • Sports • sports.yahoo.com

AMD changes rules, denies researcher $10,000 bounty after taking 124 days to patch security flaw

The vulnerability was discovered by security researcher MrBruh after an AMD updater console window kept appearing on his new gaming PC.

Jun 12 • 8:03 AM EDT • Technology • techspot.com

Stanford scientists regrow lost cartilage and reverse arthritis in major breakthrough

A new treatment that blocks an aging-related protein restored lost cartilage in old mice and helped prevent arthritis after knee injuries. Human cartilage samples showed similar signs of regeneration, raising hopes for a future drug that could repair joints instead of replacing them.

Jun 12 • 8:00 AM EDT • Science • sciencedaily.com

Hubble Sees Swarm of Galaxies

NASA's Hubble Space Telescope captured this image of MACS0329-0211 with its Advanced Camera for Surveys and Wide Field Camera 3.

Jun 12 • 7:34 AM EDT • Science • science.nasa.gov

Dolly Parton affiliated entertainment complex proposed in Panama City Beach

PANAMA CITY BEACH, Fla. (WMBB) – A new family entertainment attraction could be coming to the space next to Pirates Voyage Dinner & Show in Panama City Beach. A Dolly Parton affiliated co…

Jun 11 • 11:35 PM EDT • Entertainment • mypanhandle.com

Dolly Parton affiliated entertainment complex proposed in Panama City Beach

PANAMA CITY BEACH, Fla. (WMBB) – A new family entertainment attraction could be coming to the space next to Pirates Voyage Dinner & Show in Panama City Beach. A Dolly Parton affiliated co…

Jun 11 • 11:35 PM EDT • Entertainment • mypanhandle.com

Dodgers hold off Pirates as Ohtani exits with knee inflammation

PITTSBURGH — The Dodgers accomplished their primary goal Thursday afternoon at PNC Park.

Jun 11 • 10:43 PM EDT • Sports • sports.yahoo.com

Shohei Ohtani Leaves Dodgers Game Early With Injury

Los Angeles Dodgers superstar Shohei Ohtani left Thursday's game against the Pirates early due to left knee inflammation. Here is the latest update. The post Shohei Ohtani Leaves Dodgers Game Early With Injury appeared first on LA Sports Report.

Jun 11 • 9:54 PM EDT • Sports • sports.yahoo.com

Health Brief: Watchdog flags Medicare Advantage denials

Plus: New polling shows how health care could shape the midterms

Jun 11 • 4:38 PM EDT • Health • washingtonpost.com

Eating 5 fruits and vegetables a day may not be enough for heart health, study finds

New research suggests that meeting fruit and vegetable guidelines may not provide enough flavanols for heart health benefits without choosing specific foods.

Jun 11 • 3:40 PM EDT • Health • foxnews.com

Hidden Nazi symbols discovered in famous German artist’s painting

The white and blue Bavarian flag in this urban landscape used to be a very different color.

Jun 11 • 2:45 PM EDT • Science • popsci.com

Science flags paper that found AI chatbots help debunk conspiracy theories

Science has issued an expression of concern for a highly publicized study looking into whether conversations with AI chatbots could convince conspiracy theorists to abandon their beliefs. The move …

Jun 11 • 2:00 PM EDT • Science • retractionwatch.com

Galaxy Z Fold 7 gets two more Galaxy S26 features in its latest update

The Galaxy Z Fold 7 may be last year’s foldable flagship, but it’s still getting features from the Galaxy S26...

Jun 11 • 1:55 PM EDT • Technology • 9to5google.com

The 3 sectors where wage growth is still outpacing inflation

New data showed inflation outpaced wage growth for the second consecutive month in May. Three major sectors still have higher wage growth.

Jun 11 • 1:20 PM EDT • Business • businessinsider.com

Health plans say AI is pushing healthcare costs higher

Nearly 70% of surveyed health plans said providers’ use of AI documentation and coding tools was a top three trend inflating commercial healthcare costs next year, according to a new report from PwC.

Jun 11 • 10:54 AM EDT • Health • healthcaredive.com

Is Six Flags Entertainment Corporation (FUN) A Good Stock To Buy Now?

Is FUN a good stock to buy? We came across a bullish thesis on Six Flags Entertainment Corporation on r/investing_discussion by Variant_Invest. In this article, we will summarize the bulls’ thesis on FUN. Six Flags Entertainment Corporation’s share was trading at $23.14 as of June 10th. FUN’s trailing and forward P/E were 17.57 and 1.00k respectively according […]

Jun 11 • 10:00 AM EDT • Entertainment • finance.yahoo.com

The Dish: Tarrant County restaurants serving up some whiskey business

Fans of smoky flavors can find whiskeys all over the county.

Jun 11 • 10:00 AM EDT • Business • fortworthreport.org

US wholesale inflation rose sharply last month as Iran oil shock continues to drive up business costs

US businesses’ input costs are rising rapidly as the Iran war’s oil shock continues to ripple through the economy.

Jun 11 • 8:34 AM EDT • Business • cnn.com

LatAm in Focus: De la Espriella, Cepeda, and Colombia’s Political Divide

Political scientist Dr. Sanda Borda examines the figures and forces shaping the presidential race ahead of the June 21 runoff.

Jun 11 • 8:00 AM EDT • Politics • as-coa.org

Could Pres. Trump saying he loves ‘the inflation’ haunt Republicans in the midterms?

Jun 11 • 6:48 AM EDT • Politics • cnn.com

Albania’s Flamingo Revolution Spreads From Kushner Resort to Political Elite

As protests in Tirana extend into a second week, they have escalated from opposition to two €5 billion ($5.7 billion) planned resorts in ecologically sensitive areas linked to Jared Kushner into demands for the entire Albanian political establishment to step aside.

Jun 11 • 1:15 AM EDT • Politics • bloomberg.com

Why a frustrated Trump is turning again to bombs to force Iran’s hand

The Trump administration is making a new bid to prove a core assumption the Iran war so far suggests is flawed: that punishing strikes from a far superior US military force will force Tehran to capitulate.

Jun 11 • 12:02 AM EDT • Politics • cnn.com

NBA Finals: Victor Wembanyama draws flagrant foul early in Game 4 loss, called for a flagrant after hitting Karl-Anthony Towns

Victor Wembanyama appeared to get the best of Mitchell Robinson early on Wednesday night at Madison Square Garden.

Jun 10 • 11:42 PM EDT • Sports • sports.yahoo.com

Seven GOP US House candidates talk federal spending, energy rules, inflation at Casper’s Politics in the Park

CASPER, Wyo. — Seven Republican candidates vying for Wyoming’s lone U.S. House of Representatives seat faced a blustery Casper wind on Wednesday to debate

Jun 10 • 11:23 PM EDT • Politics • oilcity.news

NBA Finals: Mitchell Robinson called for flagrant after drilling Victor Wembanyama in the neck early in Game 4

Victor Wembanyama appeared to get the best of Mitchell Robinson early on Wednesday night at Madison Square Garden.

Jun 10 • 9:36 PM EDT • Sports • sports.yahoo.com

Local businesses roll out custom merch as World Cup crowds expected to boost economy

With Philadelphia projected to generate roughly $770 million in economic activity from upcoming FIFA World Cup matches, local businesses are preparing for an influx of fans by offering new merchandise infused with Philly flair.

Jun 10 • 6:17 PM EDT • Business • 6abc.com

ENTERTAINMENT: Flag Day concert, ‘Anastasia’ musical on weekend ‘set list’

The Little Rock Winds’ 29th annual Flag Day concert, 7 p.m. Sunday on the old parade ground behind the MacArthur Museum of Arkansas Military History in MacArthur Park continues the band’s America250 celebration with a program of marches, patriotic songs, and pop tunes.

Jun 10 • 5:30 PM EDT • Entertainment • arkansasonline.com

Small business optimism falls to lowest level since October 2024

Market Domination host Josh Lipton welcomes NFIB Research Center Executive Director Holly Wade to discuss the latest NFIB Small Business Optimism Index, which fell to its lowest level since October 2024 as inflation concerns continue to weigh on business owners. The decline effectively erases much of the optimism gained following President Trump's return to office.

Jun 10 • 4:12 PM EDT • Business • finance.yahoo.com

Democrats decry May inflation numbers that Trump says are 'great'

The Labor Department reported Wednesday that consumer prices rose 4.2% in May compared with a year earlier

Jun 10 • 1:09 PM EDT • Politics • spectrumlocalnews.com

Gas prices push inflation to a three-year high, squeezing consumers and businesses

Rising gas prices pushed inflation to its highest level in three years last month, a headache for the Federal Reserve and a potential political challenge for the Trump administration as midterm elections near

Jun 10 • 12:59 PM EDT • Business • latimes.com

Inflation and volatility have business owners feeling more pessimistic

In May, more small businesses said they planned to raise prices in the next three months, the NFIB says.

Jun 10 • 12:10 PM EDT • Business • cfobrew.com

I put the HONOR Magic V6 against the Motorola Razr Fold, and one of them changed how I think about foldables

Two of the most interesting and recent foldable flagship phones are the HONOR Magic V6 and the Motorola Razr Fold. Both of which are technically "Chinese

Jun 10 • 11:24 AM EDT • Technology • androidheadlines.com

I’m relieved Siri AI isn’t trying to be a health coach

I’d rather no announcement than an underbaked Siri-flavored health coach.

Jun 10 • 10:00 AM EDT • Health • theverge.com

Inflation rose again in May as elevated energy prices squeeze consumers

The Bureau of Labor Statistics released the consumer price index (CPI) inflation data for May which showed that inflation rose and remained persistently high last month.

Jun 10 • 8:32 AM EDT • Business • foxbusiness.com

CPI: Inflation rose to 4.2% in May, matching the forecast

The new CPI report showed inflation in May climbed to the highest rate in about three years.

Jun 10 • 8:32 AM EDT • Business • businessinsider.com

Jedify raises $24M to help companies arm AI agents with context on their business

The funding round was led by Norwest, with participation S Capital VC, Cerca Partners, and Oceans Ventures. Snowflake Ventures also participated as a strategic investor.

Jun 10 • 8:30 AM EDT • Business • techcrunch.com

Should We Change How We Talk About Mental Health and Neurodivergence?

Why do we continue to conflate terms describing general mental health and those with clinical needs?

Jun 10 • 8:00 AM EDT • Health • psychologytoday.com

2025-26 Season in Review: Brett Kulak

Vitals Player: Brett KulakBorn: Jan. 6, 1994 (32 years old)Height: 6-foot-1Weight: 192 poundsHometown: Edmonton, Alberta, CanadaShoots: LeftDraft: 2012 NHL Draft, fourth round, 14th pick (105th overall) by Calgary Flames2025-26 Statistics (with Pittsburgh): 25 games played; one goal; six assists; seven pointsContract Status: Entering unrestricted free agency on July 1 after completion of a four-year, $11,000,000 contract […]

Jun 10 • 6:00 AM EDT • Sports • sports.yahoo.com

The surprising science behind the 2026 World Cup grass

How scientists are engineering the perfect World Cup pitch—one so flawless that players never notice it

Jun 10 • 6:00 AM EDT • Science • scientificamerican.com

Microsoft Patches Record 206 Flaws, Including Three Zero-Days and Critical RCE Bugs

Microsoft released fixes for 206 vulnerabilities across its software portfolio, including 39 Critical flaws and three publicly disclosed zero-days.

Jun 10 • 5:38 AM EDT • Technology • thehackernews.com

business owner says sex offenders used store address without permission

A Flagler County business owner says registered sex offenders have been using his general store’s address as their residence without permission, raising concerns about public safety and oversight of offender registration requirements.

Jun 9 • 11:43 PM EDT • Business • fox35orlando.com

Far-from-perfect 10: Dodgers put up double digits in seventh to beat Pirates, spoil Paul Skenes' quality start

In a tie game in the bottom of the sixth, rain poured. Flags flew horizontally. Fans headed for covered sections. Then the rain stopped. A rainbow appeared. But...

Jun 9 • 10:21 PM EDT • Sports • post-gazette.com

NBA Finals: League said it missed foul after Victor Wembanyama shoved Jalen Brunson early in Game 3 win, won't upgrade to flagrant

Jun 9 • 9:44 PM EDT • Sports • sports.yahoo.com

Graham Platner wins Democratic nomination to challenge Susan Collins in November

U.S. Senate candidate Graham Platner on Tuesday secured the Democratic nomination on Tuesday, withstanding a withering blitz of unflattering revelations and ongoing attempts by Republicans and some Democratic operatives to weaken his candidacy.

Jun 9 • 9:25 PM EDT • Politics • mainepublic.org

A classic brain test exposed AI's biggest weakness

Researchers gave top AI models a classic attention test used in psychology and found a major flaw. While the models could correctly name colors in short lists, their performance deteriorated sharply as the task became longer and more complex. Some leading systems fell from over 90% accuracy to nearly complete failure.

Jun 9 • 8:00 PM EDT • Science • sciencedaily.com

Dan Oborn hosts roundtable with Omaha small business owners

The handful of business owners said inflation was the common theme hurting their businesses because of increases input costs.

Jun 9 • 7:54 PM EDT • Business • nebraskaexaminer.com

Cooper Flagg named to inaugural Time list of the 100 most influential people in sports

Cooper Flagg continues to put Maine on the map, as the recently-crowned NBA Rookie of the Year was named to Time Magazine's inaugural list of the 100 most influential people in sports.

Jun 9 • 6:23 PM EDT • Sports • wmtw.com

Flooding in Lanesville, Corydon challenges local businesses, travel

Residents in Lanesville, Ind., are taking shelter on the roofs of their homes Tuesday afternoon because of extreme flash flooding.

Jun 9 • 3:03 PM EDT • Business • wave3.com

More Small Businesses Are Increasing Prices—Here’s How Accounting Software Can Help

Inflation continues to affect prices, with a net 36% of small business owners reporting raising average selling prices in May—the highest reading since March 2023, according to National Federation of Independent Business (NFIB) data published on June 9. If you’re considering raising prices for yo

Jun 9 • 3:02 PM EDT • Business • forbes.com

Microsoft June 2026 Patch Tuesday fixes 3 zero-day, 200 flaws

Today is Microsoft's June 2026 Patch Tuesday, with security updates for 200 flaws and three publicly disclosed zero-day vulnerabilities.

Jun 9 • 1:57 PM EDT • Technology • bleepingcomputer.com

BofA strategists say tech stocks are flashing a bearish warning

The stock market has clawed back some recent losses, but BofA strategists say technical signals are flashing a bearish warning for what's ahead.

Jun 9 • 10:26 AM EDT • Business • businessinsider.com

macOS 27 Golden Gate makes it clear when apps are sneakily running in background

Google Gemini for macOS was recently flagged for not being a very good app citizen on the Mac. Apple’s new...

Jun 9 • 10:09 AM EDT • Technology • 9to5mac.com

NFIB small business optimism index falls in May 2026

Soaring fuel prices are driving inflation fears among small business owners, who are pulling back on hiring and capital spending plans

Jun 9 • 10:05 AM EDT • Business • qz.com

Study links joint pain supplement to accelerating dementia

GAINESVILLE, Fla. — New research has found an association between taking glucosamine, a popular over-the-counter supplement used for joint pain, and a higher…

Jun 9 • 10:00 AM EDT • Health • ufhealth.org

NUTRITION 2026: The Leading Source for the Latest Science

NUTRITION 2026 puts science in the spotlight as thousands of nutrition researchers and health professionals convene for the the annual flagship meeting of the American Society for Nutrition. Qualifying journalists are invited to join the action July 25–28 in National Harbor, Maryland, just outside Washington, D.C.

Jun 9 • 9:00 AM EDT • Science • newswise.com

From Classroom to Racetrack: How Charlie Baur is Building a Motorsports Career in a Business Discipline

Charlie Baur can trace his racing story back to a Christmas morning in Michigan — the kind that starts with snow on the ground and ends with a throttle in a kid’s hands. “I remember being 3 years old and then for Christmas that year, my parents had gotten me a 120 cc snowmobile,” Baur said. Long before sprint cars, he was a Michigan kid on snowmobiles, dirt bikes, four-wheelers and jet skis — and a regular at car shows and races with his family. Photo courtesy of Charlie Baur That early exposure became a calling. At 12, he sat in a sprint car for the first time and knew he’d found the next chapter. He started in quarter midgets, moved to go-karts, and the day before he turned 16 — one day shy of the minimum age required by track insurance — he made his first sprint car start after convincing officials to let him race. Five years later, Baur is still pushing forward, now racing sprint cars on both pavement and dirt while pursuing an automotive business education at Northwood University — with a clear-eyed understanding that motorsports encompasses more than what happens under the lights on Saturday night. “It’s a business,” said Charlie, a 20-year-old who calls Fenton, Michigan, home when he’s not at a racetrack or at Northwood’s residential campus in Midland, Michigan. Photo courtesy of Charlie Baur Racing is the product — but preparation is the job To the average fan, race day begins around dinner time. For a team, race day can be a 12-hour shift — plus the work that came before it. And Baur’s racing operation is a family affair. “The team is my parents and myself,” he said, explaining they own the cars, maintain equipment and manage the business side — from sponsor relations to budgeting. On race weekends, the core group includes Baur and his parents (Eric and Stefanie), plus a couple of additional hands (Alex Photiou and Robert Flannigan) who help with the intensity and pace of trackside work. That structure has shaped how he thinks about efficiency and professionalism. “We’ve always kind of had the mentality of we’re never working on the car for maintenance at the track,” he said. “Our goal is to do as little work as possible to the car because it should be ready when that car rolls out of the trailer to go racing.” That mindset shows up in routines: bolt checks, tire procedures, safety equipment and a repeatable process designed to limit errors. “Once I fire the car up and put my helmet on, that’s when it’s go time,” he said. “You can plan as much as possible for how the race is going to play out, but until you take the green flag … you don’t know how it’s going to go.” Photo courtesy of Charlie Baur First-generation driver, student of the game In racing, “first-generation” matters — and Baur wears that label with pride. “A lot of the drivers are third or fourth generation,” he said. “My family has never been in motorsports. So for me, we’ve always looked at it as we’re new to it and we want to be as different as possible. From a marketing standpoint, it helps us stand out.” It also pushes him to seek out mentors — especially veteran drivers who have seen every scenario, solved every problem and won in multiple eras. Baur credits accomplished driver Jason Blonde, a 10-time champion, for becoming his driver coach and helping him develop as a competitor. “To me, learning from Jason helps me because he has had lots of success and knows what to do,” Baur said. “You have to humble yourself and say, ‘I don’t know what to do; can you help me out?’” That willingness to learn extends off the track, too. Baur says one of his biggest challenges is not a mechanical limitation, but credibility. “It’s my age,” he said. “Some people won’t take me seriously because I’m so young. Even though … I do know what we’re talking about and have a general idea.” His answer has been to out-prepare, out-communicate and treat the operation like a real enterprise — because it is. Photo courtesy of Charlie Baur Northwood’s role: Turning passion into a plan Baur is majoring in automotive aftermarket management and pursuing an accelerated path that pairs undergraduate study with graduate work. He’s also exploring how to align his studies with motorsports-focused coursework as Northwood advances related programs and pathways. He sees the value clearly: motorsports needs business-literate professionals who understand budgets, sponsorship, marketing, operations and long-term strategy — and who can translate between the language of the shop and the language of the boardroom. That’s why his Northwood experience isn’t limited to the classroom. He has been involved with the Northwood University International Auto Show and serves as motorsports chair — a leadership role that demands outreach, contracts, coordination and a steady professional demeanor. “There’s so much outside work that makes the auto show successful that people don’t realize,” he said. “And it is truly student led.” He’s also participated in industry experiences through Northwood at major events such as AAPEX, SEMA and PRI, along with other automotive networking events — opportunities he describes as a fast track to understanding how business really gets done. “You learn a lot in the classroom,” he said. “But if you learn it and you can’t apply it to the real world, it loses its value. Or if you learn it and can apply it, but you don’t know anyone, it is still of no value.” In his words, Northwood helps him win because it “gives me the tools to succeed” — including flexibility and faculty support as he balances travel and racing commitments with academics. Photo courtesy of Charlie Baur Racing as an ecosystem — and a talent gap waiting to be filled Baur is blunt about what he sees across the motorsports world: a deep bench of experienced professionals, and not enough young talent entering the pipeline. “I go to car shows, I go to these different events, and typically … the average age is between 45 to 55,” he said. “There’s not a lot of young people going into the motorsports world.” That reality reinforces Northwood’s communications focus: positioning motorsports not as a narrow lane, but as a wide ecosystem of business careers — sponsorship, logistics, data, media, leadership, hospitality and innovation — with real demand for prepared graduates. It also shapes how Baur talks to younger students who love racing but aren’t sure what their future looks like. “If you have a passion for motorsports, there’s gonna be a spot for you somewhere,” he said, emphasizing that driving is only one of many career paths — and that local tracks and hands-on experience are often the best first step. But if someone is interested in driving as a career path, it will take a team to make that happen. Baur’s team includes Stahl’s Motors and Music Experience, Rhino Racing, Randy Wise Buick GMC Chevrolet, Western Michigan Fleet Parts, Mother’s Polish, Schaeffer’s Oil, Hepfner Racing Products, Ameriguard Storage Centers, Justice Brothers, Race 1 Wraps, TBM Brakes, Behind Your Design, CharlieBaur.com and Northwood University. “There are so many people who invest not only in myself but in my race team and who believe in us to succeed,” he added. Pictured: Charlie Bauer’s sprint race car. Looking ahead: A headline worth chasing Ask Baur to imagine 2035, and he’ll give you two answers — one dream, one blueprint. “In a perfect world,” he said, “winning the Indy 500.” Realistically, he wants to build a life where business ownership and racing reinforce each other and where he can pay forward the help he has received by mentoring younger drivers, especially those trying to break into motorsports without a family legacy. “When I retire from full-time racing, I want to be able to provide the same opportunities that were presented to myself to the next generation of drivers,” Baur said. “I know how difficult it is to get your foot in the door.” For now, the focus is simple: keep building the operation, keep learning the business, and keep showing up prepared — because in sprint car racing, as in life, process matters. And once the helmet goes on? “It’s go time,” Baur said. Photo courtesy of Charlie Baur Learn more Students interested in motorsports careers — whether in competition, team operations, marketing, finance, sponsorship, data, or management — can explore opportunities through Northwood University’s Center for Automotive and Mobility Studies. For Charlie Baur’s latest motorsports adventures, follow Charlie_Baur and Charlie Baur Racing on social media. To learn more about Northwood’s Bachelor of Business Administration in Automotive and Mobility Studies and motorsports management concentration, visit www.northwood.edu/programs/automotive-mobility-studies/. Photo courtesy of Charlie Baur Pictured: Charlie Baur at Butler Motor Speedway on May 31, 2026. Share this page

Jun 9 • 8:30 AM EDT • Business • northwood.edu

Motorola Razr Ultra review: Too much for too little

The Moto Razr Ultra is a top-notch flagship flip phone that’s marred by a $200 price hike that isn’t fully justified.

Jun 9 • 8:00 AM EDT • Technology • engadget.com

Chrome V8 Zero-Day CVE-2026-11645 Exploited in the Wild

Google released security updates for 74 Chrome vulnerabilities, including CVE-2026-11645, a high-severity V8 out-of-bounds memory access flaw.

Jun 9 • 7:58 AM EDT • Technology • thehackernews.com

US small business sentiment falls in May as inflation worries mount

U.S. small-business sentiment fell in May and the share of owners planning to raise prices over the ‌next three months increased to the highest level in nearly four years, suggesting inflation could remain elevated for a while.

Jun 9 • 6:04 AM EDT • Business • reuters.com

Ohio Small Business Job Openings Decline in May

NFIB’s May Jobs Report shows little change in the employment market as the Small Business Employment Index remained essentially flat.

Jun 9 • 4:48 AM EDT • Business • businessjournaldaily.com

Google patches new Chrome zero-day flaw exploited in the wild

Google has released emergency updates to patch another Chrome zero-day vulnerability that has been exploited in the wild, the fifth such flaw patched since the start of the year.

Jun 9 • 2:56 AM EDT • Technology • bleepingcomputer.com

New Jersey Democrats advance bill criminalizing interference with abortion, transgender healthcare

New Jersey Assembly committee advances bill that would criminalize interference with abortion services and transgender healthcare access statewide.

Jun 8 • 8:43 PM EDT • Health • foxnews.com