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Investing in Nebraska’s Health and Safety
US Senator Deb Fischer By U.S. Senator Deb Fischer I often write about using my role in the U.S. Senate to advocate for Nebraska. It’s why I joined the
Oregon says Dante Moore's CT scan and MRI were "clean"
Oregon quarterback Dante Moore, one of the top prospects in the 2027 draft, suffered a significant concussion on Saturday night, when he was knocked unconscious after sliding by USC linebacker Desman Stephens II.
Two Linebackers Shine in Washington Commanders' Home Opening Win
Washington Commanders linebackers Sonny Styles, Kain Medrano reflect on their first NFL interceptions in the 33-31 win over the Seattle Seahawks
Sunday School: Michigan State
Nebraska's performance on Saturday was in stark contrast to recent Husker teams—in the best way.
Tripp Skipper: Barry Moore is going to Washington. Abdul El-Sayed shows what he’ll be fighting
And there may be no clearer illustration of the ideological fights awaiting Congressman Barry Moore in the United States Senate than Abdul El-Sayed.
Michigan State's top five defenders against Nebraska, according to PFF
See the top five defenders Michigan State had against Nebraska, according to PFF.
Inside Gophers coach P.J. Fleck’s ‘crazy’ moment after Washington win
SEATTLE — P.J. Fleck got a little carried away in the immediate on-field celebration after the Gophers’ 27-24 win over Washington on Saturday. Linebacker Maverick Baranowski had just sealed the win in the Big Ten opener with a final-play tackle on Huskies receiver Dezmen Roebuck at Husky Stadium. Roebuck’s cleat slid up into Baranowski’s helmet and bloodied his mouth. Fleck then hugged one of ...
Families and healthcare providers reunite at Nebraska Medicine's annual NICU reunion
Families and healthcare providers shared hugs, appreciation and gratitude; celebrating the bond between them.
Patriots ST coach reacts to underrated rookie's instant success
Patriots special teams coordinator Jeremy Springer has been impressed by rookie linebacker Namdi Obiazor.
Michigan State QB Alessio Milivojevic talks after loss to Nebraska
Check out what MSU QB Alessio Milivojevic had to say after the loss to Nebraska.
Michigan State Injuries Pile Up In Nebraska Loss
Cam Edwards left on a cart and he was not the only Spartan down Saturday. #GoGreen
Three instant takeaways from Nebraska football’s win at Michigan State
Nebraska football (4-0) started conference play with a dominating win at Michigan State (2-2), 31-14, on Saturday, Sept. 26. After sweeping the non-conference slate for the third straight year, NU improved to 4-0 for the first time in 10 seasons. The Huskers earned their first win in East Lansing since 2012.
Report Card: Defense leads the way for Nebraska football at Michigan State
Nebraska (4-0, 1-0) passed its first real test of the season in East Lansing, forcing turnovers and using a big-play offensive attack to work past Michigan State, 31-13.
Raiders’ defensive makeover has an unexpected star leading the charge
Nakobe Dean is wasting no time proving his value in Las Vegas, as the Raiders’ $36 million linebacker has quickly emerged as the “glue” of their revamped defense.
Group mocks Nebraska Gov. Jim Pillen on $2.5M no-bid contract with $5,000 business grants
Nebraska Gov. Jim Pillen, after criticism from opponents for the state budget, now faces mockery from a new group over the $2.5 million no-bid contract he steered to a lobbyist.
Nebraska vs Michigan State
Big Ten play! I am probably wearing a suit and tie by now. I wonder if I’ll get to watch the game in any way. I bought a Starlink mobile just to get internet at this place we’re going to. I hope it works. HOW TO WATCH Time: 4:00pm CST Location: Memorial Stadium, Lincoln, NE Surface: Hellas Turf […]
Game Thread: Michigan State Vs. Nebraska
Hang out with your TOC friends while enjoying some Spartan football
OU-Georgia: Live updates, TV details
Availability: The final Southeastern Conference gameday availability report dropped ahead of kickoff with junior defensive lineman David Stone listed as a gametime decision and senior linebacker Kip Lewis set to
Sci-Fi Central returns to Science Central for 11th year
FORT WAYNE, Ind. (WANE) – Science Central is getting ready for a day celebrating all things sci-fi and fantasy. Organizers joined us on First News Saturday to preview the 11th annual Sci-Fi Central…
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Who won the NEBA forum? Derzypolski, Perez compete for business vote
Tallahassee commission candidates Tom Derzypolski and P.J. Perez shared their plans for city growth at a recent forum.
Nebraska football TE Carter Nelson to miss Michigan State game
Nebraska football tight end Carter Nelson expected to miss time with an injury.
Huskers dominant in recent NIL sales
UNL was ranked third in the nation in NIL sales amongst all universities. Nebraska volleyball players such as Harper Murray, Andi Jackson and Bergen Reilly placed amongst the top five spots for top-selling female athletes in August.
Week 2 Linebacker Usage and Review
Steve Hungarter uses several metrics to break down what the first two weeks told IDP managers about which LBs appear to be the real thing.
Diesel price spike straining Nebraska farmers, businesses
Diesel prices are surging in Nebraska, with one business reporting an 82% jump in fuel spending.
QB Alessio Milivojevic talks turning the page to Nebraska
Michigan State quarterback Alessio MIlivojevic talked about bouncing back against Nebraska.
Kono’s flawless Round 3 buoys Nebraska women’s golf at Ram Classic
Nebraska women’s golf played Monday and Tuesday in the Ben Connell Ram Classic hosted by Colorado State University at Ptarmigan Country Club in Fort Collins. The tournament marked the Huskers’ second outing of the season after they hit the links at The Bruzzy in Texas earlier this month. The two-day, 54-hole event welcomed 76 golfers from 13 schools that included: Washington, San Diego State, Washington State, UC Davis, Cal Poly, Wyoming, Hawaii, Southern Miss, Nevada, Northern Colorado, Colorado State and the event’s winner, UNLV, which managed to pull away from the competition with a 15-stroke victory at a cumulative 19-under par.
Lincoln brewery shuts down after more than a decade in business
Backswing Brewing Co. has closed the door after serving customers in Nebraska for more than 10 years.
Detroit Lions Make Decision on LB Joe Bachie
The Detroit Lions reportedly released linebacker Joe Bachie in a corresponding move after signing safety Bishop Fitzgerald from Pittsburgh’s practice squad.
OU football recruiting tracker: 4-star linebacker Jay Schell commits
This post tracks OU football's recruitment out of high school. The Sooners currently have 27 commits in the 2027 class and are ranked No. 6 in the nation. They currently
Edgerrin Cooper Breaks 27-Year-Old Packers Record
Exploding into his third season, the disruptive linebacker is anchoring a shorthanded Green Bay Packers defense.
Political science department holds bipartisan midterms panel
The Department of Political Science last Wednesday hosted "Perspectives on the 2026 Midterm Election” as part of the Peter J. Hoagland Integrity in Public Services Lecture Series at the Sheldon Museum.
Monday Night Therapy: Huskers vs. Spartans Week 4
Minnie Hunt welcomes Husker Chuck back to Monday Night Therapy to recap Nebraska’s 3-0 start and look ahead to the Huskers’ first Big Ten matchup against Michigan State. While Nebraska handled its first three opponents as expected, Chuck cautions that conference play represents a significant jump in competition and should provide a much better measuring […]
Big Ten Conference announces start time for Nebraska-Maryland matchup
Nebraska has announced the kickoff time for its Homecoming game against Maryland.
Week 4 Nebraska volleyball grades
Sports reporter grades the performance of Nebraska volleyball after another undefeated week and breaks down each position group. See how Harper Murray, Bergen Reilly and the rest of the Huskers performed against Creighton, North Carolina and Florida Gulf Coast.
Trench play proves big in Nebraska football’s win over North Dakota
To wrap up non-conference play, Nebraska football defeated North Dakota 34-7. The Huskers’ strong first and fourth quarters secured the win against the sixth-ranked FCS team, as the Scarlet and Cream earned their third consecutive 3-0 start to the season.
Brian Schottenheimer: "We Have to Handle Our Business"
Head coach Brian Schottenheimer discusses the Cowboys' improvements following their Week 2 win, highlighting better communication on defense, the emergence of rookie linebacker Jaishawn Barham as the defensive green-dot communicator, and the continued gro
Texas Longhorns offer rising ACC LB commit
Texas is still without a linebacker prospect in its 2027 recruiting class. On Monday, the Longhorns dished out an offer to a new target that’s currently committed elsewhere. Prattville (Ala.) three-star LB Jason Crenshaw plays for one of the top high school football programs in Alabama. Back in June, amidst official visit season, he made […]
Maine’s Office of Affordable Health Care seeks public input
Mainers are encouraged to attend the Office of Affordable Health Care’s annual public hearing this week to share their experiences of navigating today’s healthcare system.Surveys show nearly half of Maine households have taken on medical debt in the past two years and the majority point to hospital-based services like surgeries or emergency care as the
Jordan Hall Shines in Return From Injury
After overcoming an elbow injury, the relentless linebacker racked up 12 tackles against Notre Dame, cementing his status as a Butkus Award contender and Michigan State’s defensive heart.
Buffalo Bills Lose Linebacker To AFC East Rival
Miami poaches linebacker Andre Jones Jr. from Buffalo’s practice squad, securing a versatile special teams asset while leaving the Bills with a fresh vacancy to fill immediately.
Matt Rhule looks ahead to Michigan State, reviews non-conference play
The non-conference slate has officially wrapped up; now Nebraska will begin conference play with a trip to East Lansing to face Michigan State (2-1) on Saturday, Sept. 26.
Pat Fitzgerald previews MSU's matchup with Nebraska
See what Pat Fitzgerald said after wrapping up Notre Dame week, and turning ahead to Nebraska.
Corn Nation Overreaction: Huskers Start 3-0, MSU Next
Jon Johnston put out a video this morning wondering if this is Nebraska’s best team ever. At least, that’s the headline. It’s much more captivating than “Huskers Start 3-0, MSU Next.” As of this writing, I haven’t watched the video yet. This is probably the best team in the Matt Rhule era. And the team […]
From the Editor: Politics has taken taken top billing in Maine this year
Maine's political races have been in the spotlight this year, with attention on battles for seats in the U.S. Senate and House of Representatives, as well as Blaine House.
Around the Big Ten: teams make statements as Big Ten play begins
Around the Big Ten is back as sports writer Conner Krumme reviews last weekends Big Ten games.
6 Ways to Manage Your Healthcare Costs
Rent. Groceries. Utilities. A car payment. Most households know what these expenses cost each month and plan for them accordingly. Healthcare is different. Unlike a fixed monthly bill, healthcare costs can vary from month to month. One month may include only a routine checkup. The next could bring a specialist visit, a new prescription, or an unexpected trip to urgent care.
Bucs Rookie LB Trotter Continues Hot Start to NFL Career
The Tampa Bay Buccaneers have quickly found their top linebacker of the future in Josiah Trotter, who has arguably been the best player on the team through two weeks.
Bucs Rookie LB Trotter Continues Hot Start to NFL Career
The Tampa Bay Buccaneers have quickly found their top linebacker of the future in Josiah Trotter, who has arguably been the best player on the team through two weeks.
UCF's Defense Forces Three Turnovers in 44-30 Victory
Demari Henderson’s career-high performance and a relentless linebacking duo anchored a ball-hawking secondary, stifling Georgia State to secure momentum ahead of the Knights’ Big 12 opener against TCU.
Report Card: Huskers 34, North Dakota Fighting Hawks 7
Nebraska closed out what I call the exhibition schedule of the 2026 season successfully with a fairly dominant 34-7 victory over FCS #6 North Dakota. I say “fairly” because the score was a lot closer than the stats indicated. When Nebraska outgains an opponent 493 to 205 yards, you probably should expect the score to […]
Nebraska soccer draws with No. 11 Washington
Nebraska soccer drew 2-2 with No. 11 Washington Sunday. The Huskers showed significant improvement and came within 46 seconds of taking down the defending Big Ten conference champions. NU nearly won its first ranked match in four years, and also almost beat a top-15 team for the first time in 22 years.
MSU football opens as slight underdog against Nebraska this week
Check out the opening betting line for the Spartans-Cornhuskers matchup this upcoming week
Betting odds released for Nebraska vs. Michigan State Matchup
College Football can be odd. Nebraska handled the non-conference portion of their schedule, toppling the North Dakota Fighting Hawks 34-7 Saturday night. It was a game that could have been more lopsided, but Matt Rhule elected to have TJ Lateef and even Danny Kaelin see some action. Nebraska scored in every quarter, and only allowed […]
Nebraska Humane Society: Daily walks improve dog behavior and health
Dogs need daily walks to stay healthy and engaged.
HIRO Report: Nebraska vs. North Dakota
Weeks 1 and 2 were headlined by explosive performances. Week 3 was different. Here's what our HIRO metric thought of Nebraska's methodical win over North Dakota.
Report card: Strong run game leads Nebraska football past North Dakota
Nebraska football (3-0) worked past a relentless North Dakota squad to finish its non-conference schedule undefeated on Saturday night in Memorial Stadium.
Stukenholtz: Huskers Answered Questions in Workmanlike Non-Con Slate
With Big Ten play on the horizon, we did actually learn some important details about this team in their blowout wins.
Nebraska Finishes Non-Conference Undefeated After Topping North Dakota
The Huskers moved to 3-0 with a 34-7 win over the Fighting Hawks.
Three takeaways from Nebraska football’s win against North Dakota
Nebraska football (3-0) closed out its non-conference schedule Saturday night with a 34-7 win against North Dakota (3-1). Fans showed out for the under-the-lights matchup and so did the Huskers, who pieced together an impressive performance, especially on defense. Here are three takeaways from the win:
MLT’s new family-focused indoor entertainment complex open for business
Just in time for the rainy season, Monster Mini Golf opens its doors in Mountlake Terrace, across the street from the Grocery Outlet and Cinebarre. The 18-hole, glow-in-the-dark, mini golf […]
MLT’s new family-focused indoor entertainment complex open for business
Just in time for the rainy season, Monster Mini Golf opens its doors in Mountlake Terrace, across the street from the Grocery Outlet and Cinebarre. The 18-hole, glow-in-the-dark, mini golf […]
Cedric Gray injury update before Titans-Eagles game
Titans linebacker Cedric Gray has cleared concussion protocol ahead of the Sept. 20 game against the Philadelphia Eagles.
One Foot Down Reacts: We Like The Lines
With under nine hours to tonight’s kick, let’s take a quick peek at our weekly survey question at One Foot Down. If Notre Dame is going to be a championship caliber team, it’ll be on the backs of guys like linebacker Jaiden Ausberry, defensive end Bryce Young, safety Adon Shuler and linebacker Drayk Bowen. This […]
Expert score prediction: Nebraska vs. North Dakota
Nebraska’s final non-conference opponent has shaped up to be a unique challenger. North Dakota is 3-0 and has scored 40-plus points in each contest.
Phillipsburg football takes care of business, dispatches Hillsborough
Linebacker Vince Berger returns from injury to contribute pair of momentum-changing plays.
No. 1 Nebraska Volleyball overcomes offensive troubles to beat UNC
No. 1 Nebraska (9-0) volleyball faced No. 25 North Carolina (4-3) at the Bob Devaney Sports Center on Friday, Sept. 18, and won in four sets (25-14, 20-25, 25-20, 25-10).
Nebraska's Final Test before a Tough Big Ten Schedule
While an FCS opponent may seem like an easy win for the Huskers, North Dakota might be the toughest opponent Nebraska has played in 2026.
Nebraska DHHS extends health alert for toxic algae at lakes in Gage and Jefferson counties
Nebraska Department of Health and Human Services has extended a health alert for toxic blue-green algae at Big Indian Lake in Gage County and Cub Creek Lake in Jefferson County.
Nebraska soccer prepares for undefeated No. 11 Washington
Nebraska women's soccer prepares to take on No. 11 Washington this coming Sunday, Sept. 20, at Hibner Stadium. The Huskers have held possession for the majority of several of their most recent games; however, Washington will still be a tough matchup.
Editor Score Predictions: Nebraska vs. North Dakota
The sports senior staff for The Daily Nebraskan gives their score predictions for the upcoming Nebraska Husker football game against North Dakota. The game will take place at Memorial Stadium on Sept. 19 2026.
Illinois Fighting Illini 2026 Football Preview
Some of the more headscratching losses over Nebraska’s lost decade have come at the hands of the Illini. Start with Mike Riley’s throw-the-ball-into-a-gale debacle in 2015, the “field a punt at the goal line” mistakes of 2021 or the Dylan Raiola in full retreat overtime offense in 2024. Almost as bad as against Minnesota; we […]
Mizzou Football Linebackers Continuing Trend of Greatness
The “Death Row Defense” is once again relying on star linebackers to lead.
The Strange New Politics of AI. Plus. . .
It’s Thursday, September 17. This is The Front Page, your daily window into the world of The Free Press—and our take on the world at large. Today: Douglas Murray asks, why do we allow terrorists to die of old age? The American nonprofits backing Hamas. A conversation with Dara Horn and Coleman Hughes. And much more. But first: inside the unlikely coalition warning that AI may kill us all. Last week, an AI researcher named Jacob Coxon made headlines around the world after saying that he had resigned from Anthropic because he believes AI might cause human extinction—and his co-workers do, too. Unlike the rest of us, potentially, the story just won’t die. The Pro-Human Assembly, a conference held Tuesday in Washington, D.C., about the existential dangers of artificial intelligence, couldn’t have come at a better time—or with a more eclectic coalition. The Archbishop of San Francisco was there. So was Steve Bannon, screaming about the Chinese. Bernie Sanders did a quasi-dramatic reading of messages posted to an online forum by rogue AI agents. Ashley Judd paraphrased a graphic Andrea Dworkin quote for reasons that remain a mystery to me still. It was odd. People in the AI industry have talked openly about the possibility of this technology causing human extinction for years, but it hits differently in the wake of the Hugging Face incident. If you don’t know what that is, all the more reason to read my dispatch today. As the doomers see it, the best-case scenario is a future in which humans are basically kept as pets: well cared for, but with zero autonomy. The worst-case scenario, obviously, is the everyone dies thing. What should be done? I heard lots of ideas but no easy answers. There are currently zero federal regulations on AI, which is sort of strange even to think about. After all, we regulate microwaves, and the people running the microwave industry have never once refused to rule out the possibility that their products will end all human life on Earth. What I saw in D.C. left me even more convinced that you would be hard-pressed to find anyone who believes nothing should be done. You know, except for President Trump. — River Page River Page • Tech and Business [ The AI Doomers Have a Plan to Save Us. I Went to Find Out What It Is. ](https://www.thefp.com/p/the-ai-doomers-have-plan-save-bernie-sanders-bannon) Read story How Robert Kraft Made Macklemore a Martyr—and How to Better Fight Antisemitism On Monday, New England Patriots owner Robert Kraft and a group of other NFL owners banned Macklemore from performing at their stadiums after the rapper delivered a “Free Palestine” speech while opening for Ed Sheeran. Kraft cited the rapper’s “broader history of antisemitic rhetoric and imagery.” Once multiple venues refused to host shows with Macklemore on the lineup, the tour’s promoter officially dropped him. Today, Josh Kaplan says that the move was counterproductive, arguing that though well-intentioned, Kraft’s decision turned an irrelevant footnote into a martyr. “You cannot cancel people into liking you,” Josh writes. Read his column on what a better response to Macklemore would have looked like. Read [ Robert Kraft Made Macklemore a Martyr ](https://www.thefp.com/p/robert-kraft-made-macklemore-martyr-antisemitism-palestine) This raises the question: What actually works against antisemitism? On the latest episode of Conversations with Coleman, recorded in front of a live audience in New York, Dara Horn joins Coleman Hughes to talk about her new book The Final Solution to the Jewish Question. She argues that antisemitism is a script that has repeated itself across countries and ideologies, and that most people don’t understand that well enough to fight it. Don’t miss their conversation. Watch [ The Lie at the Center of Antisemitism, with Dara Horn ](https://www.thefp.com/p/the-lie-at-the-center-of-antisemitism-coleman-hughes-dana-horn) Listen now Douglas Murray • U.S. Politics [ Douglas Murray: The 9/11 Failure That Still Haunts America ](https://www.thefp.com/p/douglas-murray-911-failure-justice-terrorist-guantanamo-bay) Twenty-five years after the September 11 attacks, the men who planned them have still not faced trial. Khalid Sheikh Mohammed and most of the accused have been locked up in Guantanamo Bay since 2002. Judges have retired, and plea deals have collapsed. Today, Douglas Murray examines how this happened and argues that a justice system that allows terrorists to die of old age in an interminable pretrial process is one that has failed. Read his latest column on what that failure says about our unpreparedness for the era we are now living in. Read story The Editors • U.S. Politics [ When Nonprofits Support Terrorists ](https://www.thefp.com/p/when-nonprofits-support-terrorists) A newly declassified CIA brief from 1998 found that Osama bin Laden used nonprofit shell organizations—including U.S.-based Islamic groups—to fund his terror plots. Today, a similar story is unfolding as multiple organizations on American soil present themselves as nonprofits, taking advantage of tax-exempt status while seeking to advance the ideological mission of terrorist groups like Hamas. Read our editorial on the latest evidence of this dangerous trend—and why there’s no excuse for making the same mistake the CIA revealed 28 years ago. Read story Simon Sebag Montefiore and Bari Weiss Live in New York For decades, the Middle East has shaped American foreign policy and loomed large in the public consciousness. Few understand its influence on our politics better than Simon Sebag Montefiore, who argues that America’s quagmires in the Middle East stem from a deep misunderstanding of the region—on both the left and the right. Join him October 1 as he sits down with Bari Weiss live in New York City to kick off his U.S. book tour for The Cauldron: The Making of the Modern Middle East. Get Tickets Now MORE FROM THE FREE PRESS [ Sydney Sweeney’s Naked Truth ](https://www.thefp.com/p/sydney-sweeneys-naked-truth-caitlin-flanagan) Caitlin Flanagan Read story [ I Thought Ukraine Was Losing. Then I Was Almost Hit by a Russian Drone. ](https://www.thefp.com/p/elliot-ackerman-ukraine-drone-gas-station-train) Elliot Ackerman Read story [ The Dangerous Ideology Behind the AI Warnings ](https://www.thefp.com/p/dangerous-ideology-effective-altruism-artificial-intelligence) Shyam Sankar Read story [ Amanda Knox: Patrick Clancy Can’t Win ](https://www.thefp.com/p/amanda-knox-patrick-clancy-grief-internet-crime) Amanda Knox Read story THE NEWS The Federal Reserve raised interest rates by a quarter point, its first hike since 2023, signaling that another increase could follow as the central bank tries to bring inflation under control. President Donald Trump fired back by demanding that rates be cut sharply, though he stopped short of criticizing Fed Chair Kevin Warsh by name. The Houthis fired drones and missiles at Saudi Arabia on Wednesday, including a major oil port on the Red Sea, and Saudi jets struck back with air strikes across Yemen in an escalating front of the Middle East war. (For more on the Houthis, read Zineb Riboua’s column from earlier this week.) A sweeping Russia and Iran sanctions bill passed the House in a 262–159 vote and is now heading to Trump for his signature. Named after the late senator Lindsey Graham, the legislation would hit countries that purchase large volumes of Russian oil and gas with tariffs of up to 100 percent, and is aimed at cutting off revenue that funds Russia’s war in Ukraine. European Commission president Ursula von der Leyen proposed making Canada the European Union’s first-ever “associate member,” drawing a standing ovation from European lawmakers. The proposal, framed as a response to a world grown more hostile, faces an uncertain path as EU member states would have to approve it, and one diplomat said that “nobody really knows what it means.” The House voted unanimously to send billionaire Leon Black a criminal contempt referral after he defied a congressional subpoena to testify and hand over documents related to his connections to Jeffrey Epstein. Black chose to fight the subpoena in court rather than comply. Charlie Kirk’s family filed a wrongful death notice Wednesday against Utah Valley University, alleging that a series of security failures left him exposed to a rooftop sniper. The notice is a required legal step before the family can sue. Merriam-Webster added 1,400 words and definitions to its dictionary, including looksmaxxing, vibe coding, and cuffing season. The publisher said the new entries offer “a window into the world today.” The Free Press earns a commission from any purchases made through all book links in this article.
Bills Get Good News on Starting Linebacker After Injury Scare
The Buffalo Bills cleared linebacker Terrel Bernard to play against the Detroit Lions. The post Bills Get Good News on Starting Linebacker After Injury Scare appeared first on HEAVY.
Husker football scouting report: North Dakota
Nebraska football won its first two games but arguably North Dakota could be the toughest test of its non-conference schedule this season.
As shortfall looms, Pillen installs allies on board meant to keep politics out of budget forecast
Decades ago, lawmakers created a board that predicts Nebraska's tax receipts in an effort to keep politics out. Last week, Gov. Jim Pillen appointed two political allies to serve on it