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Tuesday ‘Dawg Bites Knows Effort Counts Twice
Welcome to Tuesday, Bulldog Fans! Your Bulldogs are 4-0, and undefeated in conference play. 40+ points in each win, each by 4 touchdowns, ranked #2 in the land, and yet (we know, we know). These are the first world problems UGA fans face in this golden era of Georgia football. A wise man once told […]
Alajbegovic on right Juventus decision, Spalletti help and Scudetto ambition
Kerim Alajbegovic insists he ‘didn’t think twice’ about joining Juventus, despite an offer from Chelsea, thanks Luciano Spalletti for advice, and wants to ‘compete for the title.’The Bosnia ...
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Haaland scores twice as Norway beat Denmark
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Trump SBA to Extend Comment Period After Ranking Member Markey Leads Effort to Rescind SBA Policy that Reclassifies Billion-Dollar Businesses as “Small Businesses”
Trump admin policy would reclassify 114,000 larger businesses as “small” to access small business resources and win federal contracts meant for small businesses Letter (PDF) (Washington, September 23) – This week, the Small Business Administration (SBA) announced its plans to extend the deadline to submit comments on its controversial proposed rule regarding small business size standards until November 20. The Trump SBA’s announcement came shortly after Ranking Member Edward J. Markey (D-Mass.), alongside 12 of his Senate colleagues, sent a letter to Administrator Kelly Loeffler demanding that the Trump SBA rescind a harmful policy that would dramatically redefine what a small business is. The Administration’s proposed policy would change the small business size standard to designate 114,000 larger companies some with annual revenue above $1 billion—as small businesses, giving these businesses access to small business resources and federal contracts typically set aside for actual small businesses. In the letter, Ranking Member Markey and the lawmakers emphasized that small businesses will be shut out of the federal contracting space as government agencies award contracts to larger businesses, causing small businesses to lose revenue, lay off workers, or close their businesses entirely. “For more than 70 years, SBA’s mission has been clear: promote and protect the interests and viability of small businesses. By proceeding with this proposed methodology and rule, SBA moves further away from its mission of facilitating healthy small business participation in the U.S. economy. We urge SBA to rescind these proposals, meet in earnest with small businesses across the country, and discuss the proposal and methodology with congressional committees of jurisdiction. SBA must be committed to developing measured increases to the size standards that do not reward large, billion-dollar companies but instead helps our small businesses survive, grow, and thrive.” The lawmakers highlighted the following points in their letter: Under the Trump SBA’s new size standards, the highest receipts-based standard would exceed $1 billion in annual revenue—more than 20 times the current $47 million maximum—and the highest employee-based standard would reach 3,600 employees—more than twice the current 1,500 employee maximum. Specific increases include an increase in size of nearly 492% for banks, 1,500% for law firms, and more than 2,051% for private equity firms. Of the 114,000 businesses that would be newly classified as small, more than 37,000 of these businesses have collectively won more than 100,000 federal contracts worth approximately $71 billion in Fiscal Year 2025 alone without a small business designation. If SBA included the awards won by these 37,000 businesses in its Fiscal Year 2025 analysis, small business contracts would have accounted for 38% of all federal contracts, instead of the 27% that SBA announced this summer. The letter was co-signed by Senators Mazie Hirono (D-Hawaii), Angela Alsobrooks (D-Md.), Richard Blumenthal (D-Conn.), Christopher Coons (D-Dela.), Elissa Slotkin (D-Mich.), Chris Van Hollen (D-Md.), Jacky Rosen (D-Nev.), Elizabeth Warren (D-Mass.), Tim Kaine (D-Va.), Brian Schatz (D-Hawaii), Mark Warner (D-Va.), and Ruben Gallego (D-Ariz.). Ranking Member Markey is fighting to protect small businesses in Massachusetts and across the country from the Trump SBA’s harmful policies that put big businesses and billionaires over American small businesses, workers, and families. In August, Ranking Member Markey slammed the Trump SBA’s proposal to overhaul its small business size standards to benefit big businesses over small businesses. In July, Ranking Member Markey and House Small Business Committee Ranking Member Nydia M. Velázquez (D-NY-7) introduced a Congressional Review Act (CRA) resolution to rescind the Trump administration’s policy that bans green card holders from accessing essential Small Business Administration (SBA) loans to start and grow their businesses. Also in July, Ranking Member Markey and Senator Hirono submitted a comment letter to the Small Business Administration (SBA) opposing a proposed rule change by Trump’s SBA to the 8(a) Business Development Program that would harm underserved small business owners and entrepreneurs. In June, Ranking Member Markey released a new report highlighting Trump’s drastic reduction in federal contracting dollars awarded to American small businesses. ###
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Boss Rob Page hailed the "character and resilience" of his Liverpool U21's side as they drew 3-3 against Rochdale in the Jersey Mike's Trophy while down to 10-men. Mor Talla Ndiaye was sent off in the first half for Liverpool before Devante Rodney broke the deadlock for Rochdale. Liverpool equalised before the break with a great solo goal from Will Wright, but Rochdale scored twice in quick succession in the second half through 41-year-old Ian Henderson.
Marlon James and Douglas Stuart have chance to become 5th multiple winner of Booker Prize book award
Marlon James and Douglas Stuart can become the fifth author to win the Booker Prize twice after both were shortlisted for arguably the U.K.’s most prestigious fiction accolade | WBBM Newsradio 780 AM & 105.9 FM
Marlon James and Douglas Stuart have chance to become 5th multiple winner of Booker Prize book award
Marlon James and Douglas Stuart can become the fifth author to win the Booker Prize twice after both were shortlisted for arguably the U.K.’s most prestigious fiction accolade | WBBM Newsradio 780 AM & 105.9 FM
Apple Watch Series 10 vs. Series 12 Buyer's Guide: Should You Upgrade?
The Apple Watch Series 12 is now available, two years after the Series 10 introduced the current thinner design. But is it worth upgrading? While last year's Series 11 brought just four changes, the Series 12 is a much more substantial update, with a new chip, twice as much RAM, redesigned health sensors, exclusive health and audio features, tougher cover glass, 5G connectivity, and new case materials. The Series 12 starts at the same $399 price as the Series 10 did in 2024.
35 Random Thoughts On Buffalo
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Steur has 'huge future in the game'
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Jiang Feng: The Unravelling of German & European Politics
A state election in eastern Germany has become a revealing test of the changing political landscapes of Germany and Europe, writes Jiang Feng, Professor and Chairman of the Council of the Shanghai Academy of Global Governance and Area Studies (SAGGAS) at Shanghai International Studies University. His analysis follows the decisive victory of the Alternative for Germany (AfD) (which has been classified as right-wing extremist by German authorities)in the state of Saxony-Anhalt on 6 September, in which it finished far ahead of its mainstream rivals. Jiang previously served as Minister-Counsellor at the Chinese Embassy in Berlin. The following article was published on 8 September 2026 on huanqiu.com, the online platform of the Global Times. On 6 September, the results of the state election in Saxony-Anhalt, Germany, were announced. The Alternative for Germany (AfD), classified as far-right by German authorities, made history by becoming the largest party in the state parliament, winning 43.8 per cent of the vote — twice its share in the previous election. The Christian Democratic Union (CDU), which had governed the state continuously for 24 years, won just 17.2 per cent, its worst result ever in Saxony-Anhalt. On the night the results were announced, the atmosphere at the CDU gathering was unusually calm. There was neither shock nor argument, as if the defeat had long been expected. Several veteran party members who had spent years working in the state government said: “Defeat is not a bad thing. It is time to make changes.” This state election has not only upended Saxony-Anhalt’s political landscape, but also laid bare the deep tensions between Germany’s traditional party structure and model of governance, on the one hand, and an increasingly polarised society on the other. Its repercussions are already being felt at the federal level, making Saxony-Anhalt a useful case study of the broader trend towards political polarisation and realignment in Europe. Governing Difficulties after Electoral Victory The most immediate consequence of the election is a historic setback for the mainstream party order that took shape in post-war Germany. In Saxony-Anhalt, the AfD has leapt from a peripheral party to the largest political force in the state. Its electoral base has expanded beyond the traditional category of “marginal protest voters” to take on the characteristics of a cross-class coalition. The party has not only consolidated its support in rural areas, but also attracted many middle-class voters and even members of the social elite with stable jobs, their own homes, and substantial incomes. It has thus evolved from a “protest party” into one with the potential to govern. Despite its commanding lead in the vote, however, the AfD faces an institutional obstacle to governing the state: the mainstream parties’ long-standing “firewall” against it. Neither of the two potential routes to forming a government appears likely to break the current political deadlock. The first would be a coalition of establishment parties, led by the CDU and bringing together the Social Democratic Party (SPD), the Greens, the Left Party (Die Linke) and the Sahra Wagenknecht Alliance (BSW) in a cross-camp government. In terms of parliamentary arithmetic, such a coalition could prevent the AfD from forming a government and preserve the outward stability of the traditional political order. Yet these parties are fundamentally divided over key issues including immigration, the energy transition, economic management, and cultural and education policy. Coalition negotiations would therefore be extremely difficult, and even if a government could be formed, it would most likely prove short-lived. More importantly, an alliance of establishment parties aimed at keeping the largest party out of government would play directly into the AfD’s narrative that “political elites are suppressing public opinion”. It could deepen perceptions of political unfairness, further strengthening the AfD’s political capital, and creating a dynamic in which “the more it is suppressed, the more people vote for it”. Ulrich Siegmund, the AfD’s candidate for state premier, has said that if efforts to form a government fail because other parties refuse to cooperate, the AfD will push for a fresh election, which he believes could deliver the party an absolute majority of seats. This points to more intense political battles ahead. The second option would be a coalition between the AfD and the BSW. Together, the two parties would command a simple majority in parliament, making this, on paper, the quickest route to forming a government. The BSW is the only elected party that has not ruled out cooperation with the AfD, and the two parties share some common ground, including on policy towards Russia. There is therefore a degree of political basis for cooperation. Were such a coalition to materialise, Germany would see its first state government jointly formed by a party defined as far-right and one with a far-left background, creating what might be called a “bipolar anti-establishment alliance”. Such an outcome would fundamentally break with the ideological boundaries of post-war German party politics. It is worth noting that even if the AfD ultimately fails to enter the state government, its roughly 47 per cent share of parliamentary seats would give it a powerful blocking minority. Without its consent, major decisions requiring a two-thirds majority — including constitutional amendments, significant budgetary adjustments, and state-level institutional reforms — would be extremely difficult to pass. Therefore, whoever ultimately forms the government, the AfD will be an unavoidable force in Saxony-Anhalt politics, with a direct influence on the state’s legislative process. Systemic Failures in Germany’s Governance Model The Saxony-Anhalt election result reflects a systemic failure of Germany’s post-war mainstream-party model of governance to adapt to rapidly changing socioeconomic conditions. It stems from multiple, mutually reinforcing structural tensions and highlights the existing political system’s difficulty in adapting to “an increasingly polarised society First, collective anxiety has replaced individual material hardship as a central driver of political mobilisation. The rise of the AfD can no longer be explained simply by poverty or social marginalisation. Its increasingly cross-class electoral base suggests that what is driving voters towards the party is, above all, concern about the broader direction of society. This anxiety about the future of the political community goes beyond individual gains and losses. In political discourse, economic anxiety has become closely intertwined with immigration, while immigration and refugee issues are, in essence, questions of social fairness. This perception turns conflicts over the distribution of social resources into negative assessments of governing parties, providing a broad social basis for far-right political narratives. Second, regional disparities and East German identity have undermined the strategy of addressing eastern Germany’s structural challenges at the regional level. More than three decades after German reunification, eastern states such as Saxony-Anhalt have experienced periods of economic growth, but their underlying economic structures remain weak, and household incomes and wealth remain significantly below those in western Germany. At the same time, they continue to face population outflow, an ageing population, labour shortages, and other structural challenges. At a deeper level, historical experiences — including the collapse of the former East German economic system, mass unemployment during the transition, and the westward shift of decision-making power over major issues — have left some residents with a sense of being “second-class citizens” and of being excluded. For years, the German government treated the “syndrome” of reunification as a regional problem to be gradually addressed at the local level. That approach is becoming increasingly unsustainable, as regional development disparities emerge as a core structural factor shaping national politics. Third, the erosion of institutional trust is perhaps the most decisive factor. AfD supporters tend to distrust establishment institutions, including parliament, government, and the mainstream media. Their concerns about economic security, pensions, and social fairness are significantly greater than the social average. Increasingly, their support for the AfD reflects not an expectation that the existing system can be improved, but a search for an alternative to the current political order. Such a systemic deficit of trust will be extremely difficult for the traditional parties to repair in the short term. Fourth, a generational shift in political mobilisation has amplified political polarisation. Unlike traditional parties, which rely heavily on offline rallies and mainstream media coverage, the AfD has developed a social-media mobilisation strategy built around “raising an issue — identifying who is responsible — offering a simplified solution — building a shared identity”. It turns complex social tensions into concise political narratives, rapidly channelling public sentiment into political support. The contrast on the eve of the election was particularly telling. The establishment parties, together with trade unions and churches, organised an offline march attended by more than 10,000 people, but its reach was largely confined to those present and to traditional media coverage. The AfD held a much smaller indoor event, yet livestreaming on TikTok, YouTube, and other platforms, combined with the involvement of online influencers, gave it a reach and mobilising capacity far beyond that of the march. The contrast illustrates how the traditional parties’ methods of political mobilisation are increasingly struggling to keep pace with a political environment transformed by changes in media technology. A Microcosm of Structural Political Change in Europe The shockwaves from the Saxony-Anhalt election quickly travelled beyond the state to the federal level. Calls for political accountability followed immediately after the results were announced. The governing CDU and SPD are now under enormous pressure, while Chancellor Friedrich Merz and Vice Chancellor Lars Klingbeil face an unprecedented test. Political polarisation in Germany is no longer simply a regional phenomenon. The post-war model of multiparty government by establishment parties is breaking down and being reshaped. Viewed in a broader European context, the Saxony-Anhalt election is part of a continent-wide wave of party polarisation, mainstream-party decline, and rising right-wing forces. Far from an isolated phenomenon, it is a microcosm of the structural political changes unfolding across Europe. Weak economic growth, cultural tensions over immigration, and declining trust in institutions are fuelling the rise of right-wing forces in several countries, challenging the liberal internationalist order established in post-war Europe. As a core member state of the European Union, Germany’s ability to adapt its political system and the direction of its politics will have profound implications for both European integration and the evolution of the international order. Subscribe [ Pekingnology China’s Germany watchers take stock of Berlin’s uneasy turn On 7 December 2025, nearly 50 Chinese scholars and policy researchers gathered in Beijing for the 2025年德国形势年终研讨会 “2025 Year-End Seminar on the Situation in Germany… Read more 9 months ago · 31 likes · 1 comment · YIRUI LI and Yuxuan JIA ](https://www.pekingnology.com/p/chinas-germany-watchers-take-stock?utm_source=substack&utm_campaign=post_embed&utm_medium=web&embedding_publication_id=1151841) [ Jiang Feng on Germany's 2025 and beyond: no easy exit ](https://www.eastisread.com/p/jiang-feng-on-germanys-2025-and-beyond) Yirui LI and Yuxuan JIA · Jan 24 The following is an op-ed by Jiang Feng, published on 29 December 2025 at Shanghai Observer 上观新闻, the digital platform of Jiefang Daily, the official newspaper of the Shanghai Municipal Committee of the Communist Party of China (CPC). [ Read full story ](https://www.eastisread.com/p/jiang-feng-on-germanys-2025-and-beyond)
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Gold Reverses 3.8% Slide as Central Bank Politics Hit the Headlines
The PRICE of GOLD extended an overnight rally on Thursday, reversing this week's previous 3.8% slide in London's spot market as doubts grew whether the US Fed will raise Dollar interest rates once or twice before the end of the year, and the politics of central bank gold reserves hit the headlines.
Sony and Microsoft say they’re not obligated to pass U.S. tariff refunds to consumers, echoing Nintendo
Back in July, Sony executives told investors that the company expected to receive $508 million in refunds from the U.S. government, after tariffs that the PlayStation-maker paid were ruled mostly in 2025 were found to be illegal. “Most” of the refund would by recouped by Sony’s gaming division, its chief financial officer said. This week, Sony’s lawyers are arguing that the company is not legally obligated to pass those proceeds on to consumers who paid for recently price-hiked PlayStation consoles. That’s in the face of a lawsuit from gamers calling on them to do exactly that. “Paying fair market price for voluntarily purchased consumer goods is not a legally cognizable injury in fact,” the lawyers wrote in a legal motion filed on Monday, as they asked a judge in California’s Northern District to dismiss a potential class action lawsuit over the tariff refunds. Microsoft made a similar argument two weeks ahead of Sony’s lawyers, in a similar lawsuit brought by a gamer in federal court in Washington State. As Microsoft’s legal team put it on August 21, in their request for a dismissal of that lawsuit: “There is nothing unjust about Plaintiff purchasing an Xbox at an advertised price and getting exactly what he paid for—regardless of whatever theory he devised months later about Microsoft’s cost structure.” Both legal fights are set to go on for some time. How things got to this point U.S. tariffs impacting a wide range of imported goods, including game consoles, had kicked off in early 2025. In May 2025, Microsoft raised the price of its Xbox consoles, citing “market conditions and the rising cost of development.” They raised them again that September. In August of that year, Sony raised the price of PlayStation 5 consoles, citing “a challenging economic environment.” Sony later told investors that its tariff fees for the fall quarter were nearly $200 million. in February of this year, the U.S. Supreme Court ruled the 2025 tariffs illegal, prompting impacted companies to begin to request refunds. In turn, consumers began suing the likes of Sony and Microsoft to get what they said was their share. The gamers in the Microsoft and Sony lawsuits argue that the 2025 price hikes of PlayStation and Xbox consoles, which added $50 or more to their sticker price, were due to illegal tariffs and should now be returned to consumers. The Sony suit started in May, when a group of gamers sued in federal court in California, saying Sony Interactive Entertainment (PlayStation) would be unjustly enriching itself if it did not pass tariff refunds to its PS5 buyers. “Sony is poised to be paid twice for the same unlawful tariff burden: once by its customers (through elevated prices) and once by the U.S. government (through tariff refunds),” the gamers’ lawyers wrote at the time. They called for Sony to partially reimburse anyone who bought a PlayStation in the U.S. since August 1, 2025. The Microsoft suit, filed by gamer Trevor Hastings against the Xbox giant in July, made similar claims. The console makers push back In late July, Nintendo’s lawyers, facing a similar suit accusing them of double-dipping on tariffs and refunds, replied with arguments that previewed Microsoft’s and Sony’s: “Nintendo or one of its retailers set a price for each product, and consumers decided whether that price was worth paying,” they wrote. Sony has buttressed that Nintendo-style argument this week by saying that the gamers have failed to prove that tariffs were the reason for its August 2025 PS5 price hike. They call thatclaim “speculative and illogical.” Other factors, including “inflation, currency fluctuations, component costs, logistics, competitive dynamics, or demand,” could have played a role. (No, the Sony lawyers do not break down the costs and factors that officially triggered the price increases). Microsoft has also argued that there’s no proof in these lawsuits that tariffs drove all or some of the price increase, as it seeks to dismiss the tariff refund suit it’s facing: “Plaintiff provides no specific allegations that would establish any pricing differential attributable to tariffs or suggest any possibility that Microsoft applied then or could recreate now any dollar-for-dollar calculation of tariff-related pricing—any more than it could any other market factor that affects pricing.” To further skewer the gamer side’s argument in its case, Sony’s lawyers have pointed to what might be a surprising defense: yet another PlayStation 5 price hike from this past spring, after the tariffs were ruled illegal. “If the original price increase were attributable to tariffs, SIE [Sony Interactive Entertainment, aka PlayStation] would have had no reason to raise prices again after the Supreme Court invalidated the IEEPA tariffs.” … “If tariffs were the cause of the price increases, one would expect SIE to lower prices once the tariffs were eliminated—not raise them again. Instead, the timeline confirms that the pricing of PlayStation consoles includes a diverse and dynamic set of input costs.” Judges have not yet ruled on the arguments made by Sony, Microsoft or Nintendo. Last week, Panic, the company behind the small, yellow Playdate handheld said it would be passing its tariff refunds on to consumers. It is the only gaming hardware maker to have made such a pledge. Game File is a reader-supported publication. To receive new posts and support my reporting, please consider becoming a free or paid subscriber. Subscribe Item 2: A reporter’s second Second Life Wagner James Au, who from 2003-2006 was paid by San Francisco-based tech company Linden Lab to be a full-time journalist embedded in their virtual world Second Life, is returning to the company. This time, he’ll be an editorial advisor and business development specialist, he tells Game File. The new role will involve trying to share the stories of people inhabiting Second Life’s ongoing online world with reporters and by extension the public. Au plans to continue to also chronicle some of that through his long-running blog New World Notes. I’ve known Au since the mid-2000s and featured him in a 2007 article for the Columbia Journalism Review about reporters like him opening up virtual news outlets within Second Life. As I wrote at the time: On April 22, 2003, writing as Hamlet Linden for the New World Notes blog on Second Life’s Web site, Au introduced himself. “For the next few months, Linden Lab has invited me to set aside my journalist cap, and instead, don the digital beanie of their in-house virtual correspondent.” He wasn’t paid to keep it positive. He wrote about builders and eccentrics, but then in August of that year, he reported on a tax revolt against Linden Lab (a complaint about the fees it charges users who build stuff) led by a resident whose avatar was a big cat. Second Life has always been less of a video game and more of a virtual world where people can live, hang out, make art, sell virtual items and flirt. Back in 2007, Au described touring it as “sort of like underwater lucid dreaming.” For the past two decades, Au has maintained New World Notes as an independent publication. But he said he’s been drawn back to Second Life and Linden Lab as a place to directly work. The virtual world has around 650,000 monthly active users, he said, “which is actually about what it was during the hype wave.” Au says he’s still finding rich stories in Second Life, the kind that keep him interested 20 years into the beat: “Over the last few months for instance, I wrote about an SL creator in Venezuela whose apartment was destroyed by the earthquakes, so the global SL community rallied to get him back on his feet,” he told me. “Then there’s the woman from a Middle Eastern country who explored her lesbian sexuality in SL, then earned enough from her virtual jewelry to escape her abusive family situation and country.” Au wants to beckon more reporters to give Second Life another look. He argues that it is often ahead of internet trends, noting, for example, an early backlash in the community against AI-made art. Now the platform is drawing curiosity from more of the user-generated content community who’ve grown up with the likes of Roblox, according to Au. “Second Life was too early during its hype wave in 2005-2010, but it now feels right for a new wave of interest,” he told me.
gamescom 2026’s Steam wishlist winners
gamescom wrapped up last weekend, and it was bloody fantastic. It really felt like the industry had a spring in its step again. The show itself was BUZZING, with 368K attendees (+3% over last year), maxed-out exhibit space, and Opening Night Live pulling over 78M online views (+7.5%). Let’s have a look at the games at the event that brought in the most new Steam wishlists between August 23 and 30. One quick thing before we start, and stop me if you’ve heard this one before, but wishlists are NOT a barometer for launch sales (they’re bookmarks, not baskets is what we always say over here at Alinea). With that aside, wishlists are a nice gauge of hype, so let’s dive in. Witche(r)s and Warlocks take the top two spots The biggest game of the event (by new wishlists, anyways) wasn’t a game at all. It was an expansion. The Witcher 3: Wild Hunt’s upcoming expansion, Songs of the Past, nabbed 451K Steam wishlists by the end of the weekend. It’s a big example of something we bang on about constantly: proven IP with built-in fandom is the most powerful force in this market. But said IP can also ripple into other external success stories (more on that later!). Anyway, Songs of the Past debuted at Opening Night Live, and it’s the first Witcher 3 expansion in over a decade, landing next year after a full Witcher 3 remaster (free for existing owners!) arrives next month. The Witcher 3 has sold around 66M copies, and I’ll be one of those owners jumping back in to refresh myself on the core game (like there isn’t enough to play!), then play the expansion next year. This is all part of CDPR’s plan. The studio is clearly whetting everyone’s appetite for The Witcher 4 in 2028 via a classic bridge strategy. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Releasing a free 4K remaster next month – followed by a proper expansion in 2027 – keeps IP top-of-mind across a huge gap between content (games-wise, anyway). It kind of echoes Capcom’s evergreen catalogue strategy. And outsourcing co-development to Fool’s Theory (a studio led by trusted Witcher 3 veterans) keeps CDPR’s internal headcount focused on The Witcher 4. #2 by wishlists between Aug 23 and 30 went to another giant IP: Warlock: Dungeons & Dragons, published by Wizards of the Coast and developed by Invoke Studios (a team of ex-Far Cry, Watch Dogs, and Splinter Cell devs). It’s due to launch in 2027, and it looks brilliant so far. It’s a dark-fantasy open world with third-person spell-slinging. It’s a very Witcher-ish aesthetic. As you might expect, 48% of Warlock’s Steam wishlisters have played Baldur’s Gate 3, and 46% have played The Witcher 3. One to watch. For sure! Mash-ups: Anime GTA (!?) and a city-builder for kids (and adults) Ananta took #3 with 302K new wishlists. It’s an open-world game that looks like GTA and Persona had a baby. It was published by NetEase, developed by Naked Rain, and got a trailer at Opening Night Live. I got hands-on at the show, and it wears its influences openly; there’s literal web-slinging (very Spider-Man) and a LOAD of mini-games (Like a Dragon). It’s free-to-play and out in January. For Ananta, Naked Rain is taking the free-to-play, cosmetics-only route. That’s certainly a choice for a single-player open-world game. Without gacha mechanics driving high ARPU, Ananta is betting purely on top-of-funnel reach and long-term retention. This puts pressure on skin appeal when there’s no multiplayer lobby to flex in (although, co-op is reportedly coming later). Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Then there’s Lego Skylines (273K wishlists between Aug 23 and 30), which does exactly what it says on the tin. It’s a cosy Lego twist on the city-builder genre, as shallow or as deep as you fancy (five min quick sesh or ten-hour no-lifer session; latter for me). There’s some family-friendly stuff in there like couch co-op, which is only really viable on console. Iceflake Studios, which Paradox acquired back in 2020 is developing this one. So Paradox is probably looking for a family-friendly onramp to its rad Cities: Skylines games. The overlap there is plain, with 33% of Lego Skylines wishlisters having played Cities: Skylines and 16% Skylines II. There’s no doubt plenty of parents here (and uncles, ahem) planning to indoctrinate the next gen of city-builders. I’ll definitely be playing with my youngest nephew. This one could be big and educational. I’m very curious to see more. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Mature IP, new and old, rounds out the list As for the rest of the list of gamescom games by new wishlists between Aug 23 and 30: Heroes of Might & Magic III Remake got 189K new wishlists. It remakes the iconic 1999 turn-based-strategy classic in full 3D and 4K. It follows this year’s Heroes of Might & Magic: Olden Era (~1.8M copies sold, as per our estimates), and around a quarter of the III Remake wishlisters have played Olden Era, including 7% of them this month. Wardogs – a $40 PvP shooter – added another 146K to an already massive pile (nearly 1.6M total). It’s published by Team17 and made by Bulkhead. It plays somewhere between the tactical squad stuff of … Squad and the all-out-chaos battlefield of … Battlefield. It’s up to 100 players, and it’s out in about 10 days. It’s already pre-sold over 500K copies on Steam ($16.6M), boosted by a pre-order-only beta. It sold another 70K copies during gamescom, too. Afterworld managed 121K new wishlists. It’s a Paradox-made post-apocalyptic grand-strategy game, and it was announced at the show. It’s a departure from Paradox’s usual historical stuff, and the studio’s first new setting in over a decade. The Paradox purists are into it, with over half its wishlisters having played Hearts of Iron IV (19% this month) and 41% Crusader Kings III (17% this month). Metro 2039 got 110K during the show, tunnelling its total past 1.3M. Nearly 40% of wishlisters have played 2020’s Metro Exodus, the previous mainline title in the series. The Metro novels are Russian, dev 4A Games is Ukrainian, and it’s set in Moscow, so it’s unsurprising that – after the US (17.3% of wishlisters) – the next two countries are Russia (12.7%) and Ukraine (10.0%). The Blood of the Dawnwalker drew in (the blood of) 108K new wishlisters, now totalling an impressive 1.7M (at a $70 price point, though). It’s an open-world dark-fantasy action-RPG set in 14th-century Europe (with vampires!), made by some former Witcher devs at Rebel Wolves. Again, it shows. Over half of Blood of the Dawnwalker’s wishlisters have played The Witcher 3, and its #2 market is Poland, home of Rebel Wolves. That’s that hometown-hero effect we keep banging on about again! And Blood of the Dawnwalker plays very well, by the way. While it looks like a Witcher clone on the surface, it actually brings a lot to the table mechanics-wise. I love the whole time-as-a-currency spin on RPG gameplay. It gives the game a different, refreshing pace. Essentially, you start Blood of the Dawnwalker with a pool of 480 action points spread across 30 days and 30 nights. As for how the game performs, we’ll be posting some numbers next week, so hit subscribe below to get that in your inbox when it’s ready. Subscribe The Witcher’s legacy ripples Make no mistake: on a high level, this was The Witcher‘s gamescom. The #1 game by wishlisters was a Witcher 3 DLC. Warlock is clearly Witcher-inspired – as is Blood of the Dawnwalker, which was made by ex-Witcher devs. There was a lot of other cool stuff on the floor that we’ll no doubt be covering in subsequent newsletters, though! As always, wishlists went through the roof for sequels, remakes, DLC, and licensed IP. As always, though, these wishlists will likely convert to about 5% to 10% of launch-day buyers, with the probable exception of The Witcher DLC – the exception that proves the rule. Either way, we’ve got a nice, diverse list here – one that is very Witcher-y, Paradox-y, and – if you’re a fan of great games on Steam – a bloody good list. We even got a bunch of new IP to get excited for. Great gamescom! Even if we are still processing that unfathomable number of mini Kölsch beers! One more thing: GTA 6 broke the internet (again) Move aside, Spider-Man and The Odyssey (I love you both, really). But the decade’s defining entertainment zeitgeist is round the corner. Unless you’ve been living under a rock, you’ll know that Rockstar dropped an extended look at GTA 6 last week. It was INSANE, the most impressed I’ve ever been by a showcase like this. You can see the budget seeping through every second of the extended look, and this level of game is unobtainable for any other publisher. Everyone’s going nuts, and rightly so. GTA 6 is out in holiday 2026, and it’ll be the biggest entertainment release ever, full stop. For those without a PS5 or Xbox Series console, a $500-$900 console is a big ask in this economy, but GTA will pull a lot of last-generation-console fence sitters over the current-gen fence either way: The autumn timing puts GTA 6 on (digital) shelves for the holidays, meaning a PS5 or Xbox (let’s be honest, mostly the former) will be on many a Christmas and Hanukkah list. Demand will outweigh the struggling supply, though, and PS5 Pros are already sold out and being sold at a markup via scalpers. Every console that isn’t on a shelf is a sale deferred or lost, and worse, it hands scalpers the margin. GTA has cultural clout that reaches everyone. It’s been a mainstream fixture since 2001’s GTA III and its clout has only grown exponentially since then. There’s a touchpoint for every generation alive. The FOMO-word-of-mouth double punch does the rest. Loading... It’ll reactivate the lockdown cohort, the millions who picked up gaming in 2020-21 and churned. GTA 6 will bring them back. Remember when College Football 25 brought a bunch of US gamers to current-gen consoles? GTA will do that globally. Once they’re back (or upgraded), and all GTA’d out, the fresh current-gen-console folks will check out the rest of the current-gen catalogue they missed. GTA Online, if not free to play, will also lead to a boost for PS+ and Xbox Game Pass, another boost for the ecosystem players. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Even some of the smug PCMR 60FPS crew won’t be able to resist their FOMO and will bite the bullet on a console to play this one early (then double dip). The consoles cost the same as a decent stick of RAM these days anyway lmao… Don’t get me wrong, though. GTA 6 is no silver bullet for the mature console market, but it does prime the current gen for a couple of strong swan-song years. And it’ll also give the consoles more users from which to maximise ARPU. ‘’We are in the latter half of the lifetime cycle of [the PS5],’’ said Sony President and CEO Hiroki Totoki in a Wall Street Journal interview. ‘’That means we do not need to aggressively sell the console today; rather than that, we are focusing on the current revenue from the current user base.’’ The biggest, best premium games always arrive late in a console cycle, so getting more players aboard now, ahead of that content storm (the new current-gen-only Call of Duty included), is a clear win for the platforms. On the Netflix thing, though: let’s all chill out a bit, like. Half my LinkedIn feed was going bonkers treating the reveal debuting on Netflix like it’s the future of entertainment. It wasn’t. It was a six-hour head start, and Netflix left that detail out of the “first-of-its-kind partnership” press release. The extended look hit Netflix at 3pm ET on 27 August, then went up on YouTube and Rockstar’s site for everyone six hours later. And it was all over social immediately, anyways. This reveal was going to reach an untold number of people whether it debuted on Netflix, YouTube, a Times Square screen, or a group chat. The last trailer did nearly half a billion views in a day with no gatekeeper at all. Netflix just stood next to that audience for six hours, borrowing it. It’s was a tidy deal for Netflix, sure. But every outlet on earth was breaking the thing down frame by frame by the evening anyway. Anyway. I’m hype. And we’ll be covering some GTA numbers on the newsletter soon. So hit subscribe below to get that in your inbox when it’s ready! Subscribe The last word Reply to this email – or reach out here – if you have any feedback for the newsletter – or want to request a game for us to cover. [Alinea Analytics boasts the most accurate PC and console estimates in the business. Game makers use our platform to understand their audience, keep an eye on the competition, monitor sales trends, and spot new opportunities. We equip game studios and financial institutions with accurate data and the confidence to make smarter, data-driven decisions. Want to talk about all things games market data? We’d love to chat!]
A course correction Canada would concur with
I’ve always harbored a soft spot for Canada. My father was stationed there twice, once in the 1960s as the Atomic Energy Commission’s American liaison with the Canadian nuclear reactor program in Chalk River, Ontario and again in the 1970s as the State Department’s scientific attache at the U.S. Embassy in Ottawa. I had the […]
Chinese map of South China Sea floor has ‘twice the resolution’ of Western ones
Intel Sold Its NAND Memory Business for About $9 Billion. Micron Is Now Worth More Than Twice What Intel Is.
The chipmaker exited NAND memory in one of the semiconductor industry's biggest asset sales. Nearly six years later, the market has put a price on what it walked away from.
These 5 Everyday Foods Can Slash Your Fracture Risk by Up to 46%, According to Science
You probably don’t think twice about what your bones are doing right now. They feel solid, reliable, invisible – until they’re not. Most of us grew up hearing that milk builds strong bones, and then we moved on, assuming the job was done somewhere around adolescence. But bone density doesn’t stay constant. It quietly declines...
The Intersection Debuts with Get TO The Point, New Sports Culture Podcast Hosted By Terrell Owens and Chris Spencer
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Nvidia’s Hidden $40 Billion Business Beyond Big Tech Is Growing Twice as Fast
Nvidia's data center customer list is changing fast, and the new buyers look nothing like the hyperscalers who built the company's dominance. Whether that signals genuine strength or a subtler kind of risk depends on who is actually paying the bills.
60 years ago, the Beatles played twice at Seattle Coliseum
Fans of the Beatles didn't know it at the time, but a 1966 tour stop would be the group's last in Seattle. Here's what the shows were like, and how
49ers' 53-man roster prediction for 2026 NFL season
The San Francisco 49ers are one of the most consistent teams in the NFL. They have registered double-digit victories in four of the last five years, but that’s simply not good enough when at team competes in the NFC West. The 49ers have to face the defending Super Bowl champion Seattle Seahawks twice a year and they also have to do the same with […] The post 49ers' 53-man roster prediction for 2026 NFL season appeared first on ClutchPoints.
Why politicians are punchlines at the Edinburgh Fringe
There was a time when satire had an easier gig. Politicians said something ridiculous, comedians made fun of them, audiences laughed, and everyone went home. Subscribe Now the joke is often the headline. In a world where the unbelievable regularly makes the news, where politics can veer into parody before the comedians have had time to write the punchline, you might reasonably wonder: is satire running out of material? Not in Edinburgh. At the Fringe, I can confirm satire has a pulse, even in a relentless and rapid news cycle. Politicians as punchlines Take NewsRevue, the world’s longest-running live sketch show, where politicians are turned into punchlines at industrial speed. Its latest target? Andy Burnham - or, more accurately, his doppelganger, pictured below in the middle. The joke, he tells us, is that there have been so many politicians coming and going that even satire risks suffering from political fatigue. But perhaps that revolving door is precisely why comedy matters. When the news cycle moves faster than our ability to process it, comedians can hold up a mirror - and make us think twice. Small talk Take Ayoade Bamgboye, the Saturday Night Live UK star who won the Best Newcomer prize at last year’s Edinburgh Comedy Awards. Her Fringe debut was critically acclaimed; this year she is turning her attention to one of Britain’s most baffling social rituals: small talk. Share It’s a reminder that satire doesn’t always need a politician in its sights. Sometimes the target is simply us civilians - the strange little rules and rituals we have collectively agreed to pretend are normal. Politics and Palestinian identity For British-Palestinian comedian Sami Abu Wardeh, pictured below, comedy has a more urgent job. His new show, Sami Abu Wardeh Hates You, asks who gets to hate, and whether anger belongs to everyone, not just the far right. His comedy confronts politics and Palestinian identity while refusing to surrender the simple business of making people laugh. Shakespeare meets climate crisis And then there is HAM: an “eco-hijacking” of Hamlet, which its creators describe as “a sordid wrestle between a vegan and a sausage-lover”. Shakespeare meets the climate crisis. Meat meets moral panic. The end result? You’ll leave promising to become vegan and swiftly bulk buying Linda McCartney sausages. HAM was created by theatre company Hotter Project, aka Ell Potter and Mary Higgins, pictured below. They say comedy helped them avoid the preachiness sometimes associated with climate activism - using Shakespeare as a vessel for uncomfortable questions about the planet, politics and the way we live. Perhaps that is satire’s secret weapon. It doesn’t necessarily make the world less absurd. It makes the absurdity crystal clear. And at a moment when reality increasingly feels like it has been written by a sketch writer, the Fringe is proving there is still plenty to laugh and cry at. Satire isn’t dead. It’s alive, subletting and having the time of its life at the Fringe. Subscribe Share Channel 4 News Leave a comment
Losing A Parent Doubles Rates Of Mental Health Problems Among Children
By Dennis Thompson HealthDay ReporterMONDAY, Aug. 21, 2026 (HealthDay News) — Children who lose a parent develop mental health problems at twice the rate of kids with an intact family, a new study reports. Losing a parent to death, imprisonment or separation all dramatically increase risk of mental ...