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Siesta Entertainment picks up sales rights to Puerto Rican preschool show
Barcelona-based animation distribution and brand development company Siesta Entertainment has acquired the worldwide sales rights to Puerto Rican musical preschool series Rockolandia Las Cabritas.
Hispanic Heritage Festival returns with more food and entertainment
A couple dances in the street during last year’s Hispanic Heritage Festival in downtown Delphi. Comet file photo As evening settles over the courthouse square Saturday, Oct. 3, downtown Delphi will take on the sounds and colors of a celebration that has quickly become an annual tradition. Latin music will fill the square as colorful
Hayden Panettiere's ex Wladimir Klitschko petitions to protect their daughter's inheritance
LOS ANGELES — Actor Hayden Panettiere’s ex-fiancé, Wladimir Klitschko, has filed an urgent petition asking that he be allowed to act as their 11-year-old daughter’s temporary representative in California court
September Mental Health Column by Candyce Scott
By Ald Candyce Scott September 2026: Mental Health Awareness Year 2026 & Suicide Prevention Month September is more than a change of seasons. It’s time for us to pause, check in on one another, and recognize Suicide Prevention Month. I believe that talking openly about mental health saves lives. Recognizing the warning signs and encouraging […]
Britain Politics Labour
Britain's Prime Minister Andy Burnham delivers his Leader's Speech during the Labour Party Conference in Liverpool, England, Tuesday, Sept. 29, 2026. (AP Photo/Jon Super)
Expert urges Hispanic families to break mental health stigma during Heritage Month
Gambit's Best of New Orleans 2026: Entertainment
Design by Dora Sison / Gambit Best Bounce Artist googletag.cmd.push(function() { googletag.display('ad-1492300'); }); 1. Big Freedia (Instagram: @bigfreedia)2. Ha Sizzle (Instagram: @hasizzlethevoice)3. Subtweet Shawn (Instagram: @subtweetshawn1) Trixie Minx Photo by Sophia Germer / The Times-Picayune Best Burlesque Performer1. Trixie Minx (Instagram: @trixienola)2. Bella Blue (Instagram: @bellablueforever)3. Miss Angie Z (Instagram: @missangiez) Best Casino1. Caesars New Orleans (8 Canal St., 800-427-7247; caesars.com/caesars-new-orleans)2. Treasure Chest Casino (4550 Williams Blvd., Kenner, 504-443-8000; treasurechest.com)3. Boomtown Casino (4132 Peters Road., Harvey, 504-366-7711; boomtownneworleans.com) Best Drag Performer1. Debbie with a D (Instagram: @debbiewithad)2. Katrina Waters (Instagram: @katrinawaters504)3. Laveau Contraire (Instagram: @laveaucontraire) Best Festival (that's still around)1. New Orleans Jazz & Heritage Festival (nojazzfest.com)2. French Quarter Festival (frenchquarterfest.org)3. Hogs For The Cause (hogsfest.org) Best Food Festival1. New Orleans Fried Chicken Festival (friedchickenfestival.com)2. Oak Street Po-Boy Festival (poboyfest.com)3. New Orleans Jazz & Heritage Festival (nojazzfest.com) Tipitina's Photo by Sophia Germer / The Times-Picayune Best Live Music Venue1. Tipitina’s (501 Napoleon Ave., 504-895-8477; tipitinas.com)2. The Broadside (600 N Broad St., 504-766-0871; broadsidenola.com)3. The Fillmore (6 Canal St., 504-881-1555; thefillmorenola.com) Best Live Music Club1. Maple Leaf Bar (8316 Oak St., 504-866-9359; mapleleafbar.com)2. Snug Harbor Jazz Bistro (626 Frenchmen St., 504-949-0696; snugjazz.com)3. Chickie Wah Wah (2828 Canal St., 504-541-2050; chickiewahwah.com)3. Blue Nile (532 Frenchmen St., 504-766-6193; bluenilelive.com) Best Local Blues Artist/Band1. Little Freddie King (littlefreddieking.com)2. Samantha Fish (samanthafish.com)3. Tab Benoit (tabbenoit.com) Best Local Brass Band1. Rebirth Brass Band (rebirthbrassband.com)2. Hot 8 Brass Band (hot8brassband.com)3. The Soul Rebels (thesoulrebels.com) Best Local DJ1. Paul Lakeway (Instagram: @paul_lakeway)2. DJ Soul Sister (Instagram: @djsoulsister)3. ANTWIGADEE! (Instagram: @antwigadee) Best Local Funk Band1. Dumpstaphunk (dumpstaphunk.com)2. Galactic (galacticfunk.com)3. Big Sam's Funky Nation (bigsamsfunkynation.com) Kaye the Beast Provided Photo by Catherine Debuys Best Local Hip-Hop Group/Artist1. Kaye the Beast (Instagram: @kayethebeast)2. La Reezy (Instagram: @lareezymusic)3. Pell (Instagram: @pellyeah) Best Local Movie Theater1. The Broad Theater (636 N. Broad St., 504-218-1008; thebroadtheater.com)2. The Prytania (5339 Prytania St., 504-891-2787; theprytania.com) googletag.cmd.push(function() { googletag.display('ad-1492297'); }); 3. The Prytania Theatre at Canal Place (333 Canal St., 3rd floor, 504-290-2658; theprytania.com) Best Local Music Artist/Band1. Robin Barnes & The Fiya Birds (robinbarnesmusic.com)2. Trombone Shorty (tromboneshorty.com)3. Sweet Crude (sweetcrudeband.com) Best Local Rock Band1. The Revivalists (therevivalists.com)2. Better Than Ezra (betterthanezra.com)3. Cowboy Mouth (cowboymouth.com) Best Wedding Band/ DJ1. The Mixed Nuts (themixednuts.com)2. Bucktown All-Stars (bucktownallstars.com)3. Warm Advice (warmadvice.com) Doreen Ketchens Provided photo Best Local Street Performer1. Doreen Ketchens (doreensjazz.org)2. Jourdan Blue (Instagram: @jourblue)3. Sariyah Idan (ariyahidan.com) Best Local Theater Company1. The Tennessee Williams Theatre Company of New Orleans (504-264-2580; twtheatrenola.com)2. Le Petit Theatre (616 St. Peter St., 504-522-2081; lepetittheatre.com)3. The NOLA Project (504-302-9117; nolaproject.com) Best Local Traditional Jazz Group/Artist1. Preservation Hall Jazz Band (preservationhalljazzband.com)2. Kermit Ruffins (@ruffinsbbq)3. Trombone Shorty (tromboneshorty.com) Best Marching Band1. St. Augustine High School Marching 100 (Instagram: @staugmarching100)2. Edna Karr High School Marching Band (Instagram: @theofficialkarrband)3. The Roots of Music Marching Crusaders (therootsofmusic.org) Best Mardi Gras Parade1. Muses (kreweofmuses.org)2. Iris (kreweofiris.org)3. Endymion (endymion.org) 610 Stompers Photo by Chris Granger / The Times-Picayune Best Mardi Gras Dance Krewe1. 610 Stompers (610stompers.com)2. Amelia EarHawts (aecabinkrewe.com)3. The Jamettes (Instagram: @thejametteskrewe) Best Place to See Burlesque/Drag1. The AllWays Lounge & Cabaret (2240 St. Claude Ave., 504-218-5778; theallwayslounge.net)2. The Original Nite Cap (1300 St. Bernard Ave., 2nd floor, 504-224-2854; Instagram: @originalnitecap)3. The Country Club (634 Louisa St., 504-945-0742; thecountryclubneworleans.com) Best Place to See Comedy1. Sports Drink (1042 Toledano St.; sportsdrink.org)2. The Howlin' Wolf (907 S. Peters St., 504-529-5844; thehowlinwolf.com)3. Big Couch New Orleans (1045 Desire St.; bigcouchnola.com) Best Local Comedian1. Ryan Rogers (ryanrogerscomedy.com)2. Mark Normand (marknormandcomedy.com)3. Cyrus Cooper (Instagram: @cyrusjcooper) Best Strip Club1. The Penthouse Club (727 Iberville St., 504-524-4354; penthouseclubneworleans.com)2. Rick’s Cabaret (315 Bourbon St., 504-524-4222; rickscabaretneworleans.com)3. Larry Flynt's Hustler Club (225 Bourbon St., 504-524-0010; neworleanshustlerclub.com) Best Performing Arts Center1. Jefferson Performing Arts Center (6400 Airline Dr., 504-731-4700; jeffersonpac.com)2. Saenger Theatre (1111 Canal St., 504-525-1052; saengertheatreneworleans.com)3. Mahalia Jackson Theater for the Performing Arts (1419 Basin St., 504-525-1052; mahaliajacksontheater.com) .donate-gambit-article-module-container { text-align: center; padding: 10px; /* background-color: #24da6d; */ background-color: rgb(153, 0, 0); margin-bottom: 20px; } .donate-gambit-article-module-title { font-weight: bold; color: #fff; } .donate-gambit-article-module-copy { color: #fff !important; font-size: 16px; } .donate-gambit-article-module-button { background-color: black; width: 50%; border-color: black; font-size: 16px; } .donate-gambit-article-module-button:hover { background-color: black; } @media only screen and (max-width: 600px) { .donate-gambit-article-module-button { font-size: 14px; width: 100%; } .donate-gambit-article-module-copy { font-size: 14px; } } BECOME A GAMBIT MEMBER AND JOIN OUR KREWE TODAY For more than 40 years, Gambit has covered New Orleans, for New Orleans. We’ve stood up to city hall with you, cheered the Saints with you, danced in the streets with you and cried over our collective loss with you. And we’re plannin’ on being here for 40 more. To do that, we need your help. Become a Gambit member today and help us continue our mission SUPPORT GAMBIT
Andy Burnham pledges a radical shake-up for Britain in a high-risk political speech
Prime Minister Andy Burnham has vowed to give Britain “a new social contract for the 21st century.”
PM Burnham vows big shake-up for UK in high-risk political speech
The prime minister promised a rethink of ties with the EU, a reform of Britain’s electoral system and a new social care service.
The Family Business Advantage: Third Quarterly Power Breakfast of 2026 explores how family businesses balance legacy and innovation
Photo by GFBJAnother successful Power Breakfast is in the books. The Greater Fayetteville Business Journal hosted its third quarterly Power Breakfast of 2026 on Tuesday, Sept. 29. Local leaders and decision-makers gathered to network and learn from the panel about how established principles drive long-term stability while allowing for operational evolution. The panel featured Managing Partner of Luigi’s Italian Chophouse & Bar, Nate Ernst; Inside Sales at Hubbard Supplyhouse, Mary Grace Hurley; Chief Operations Officer for Copiers Plus, Drew Smith; and CEO of Holmes Security Systems, Stephen Wheeler. The panel was moderated by Lauren Willets, director of the Family Enterprise Center at UNC’s Kenan-Flagler Business School. Throughout the discussion, the panelists returned to a common idea: family businesses thrive when they preserve the relationships and values at their core while remaining open to change.Each panelist shared personal stories that carried practical lessons. Stephen Wheeler emphasized the role of relationships with customers and employees, saying, “What makes a family business successful today is relationships.” Mary Grace Hurley echoed Wheeler’s sentiment, describing relationships as a lasting inheritance, including a customer connection that began when she was young and continued into her working life. “If something’s given to you, that’s going to cost you too,” added Nate Ernst. He explained this philosophy by sharing that, in his view, earning responsibility builds credibility and confidence.Another hot topic was the idea of tradition versus change. For these businesses that have been around for a century or even more, it can be difficult to escape the “we’ve always done it this way” caveat, but these speakers emphasized how change has been an integral part of their growth and longevity. A family business can honor its history without being bound by it.“Innovation and tradition–they don’t have to be competing with one another,” shared Hurley. She pointed to changes in how businesses operate, including the adoption of computers and new management practices. Ernst stressed that adaptation is essential, while Wheeler described how his family’s electrical contracting business had evolved into a security-focused company. The details of the work may change, but identifying and upholding core values is key to embracing change while maintaining the character of a business. “I think it’s just important to remember why you started in the first place. What was your mission? What are your core values? And to reevaluate those,” shared Drew Smith.In addition to the first-hand accounts and wisdom shared by panelists, Moderator Lauren Willets recommended two novels during the panel for those seeking additional educational resources. Those two novels are “Hug of War: How to Lead a Family Business with both Love and Logic”by Cathy Carroll and “In the Company of Family: How to Thrive When Business Is Personal” by Melissa Mitchell-Blitch. Preparing the next generation requires more than handing over a title or company. Wheeler argued that future leaders need genuine passion and a vested interest in the business. The panelists were in agreement that succession is a process, and there is not one clear answer for how to perfectly prepare for it. Leaders must cultivate readiness, keep communication open and make room for the next generation to earn responsibility while being sure not to neglect the business in the here and now. “Today’s Power Breakfast was one of our best events yet! Between the passion and in-depth knowledge of the panelists, the great audience questions and the guidance and expertise of Mrs. Willets, the conversation was both engaging and informative,” shared GFBJ Publisher Faith Hatton. “A lot of small businesses in Fayetteville are family-owned and grown, and it’s great to be able to spotlight some of the businesses that have stood the test of time by strengthening the next generation of leadership and preparing them for ownership. I hope everyone received some inspiration and ideas that they can bring back to their own businesses and organizations!”We thank everyone who attended this Power Breakfast and hope you’ll all join us for the next Power Breakfast on Dec. 8. Details about the event will be shared on our social media and in future email updates. To learn about becoming a Power Breakfast sponsor, contact the Greater Fayetteville Business Journal at 910.240.9697 or marketing@bizfayetteville.com.
Hayden Panettiere's ex petitions to protect daughter's inheritance
Hayden Panettiere's ex-fiancé Wladimir Klitschko has filed an urgent petition to act as their 11-year-old daughter's temporary representative in California court.
Andy Burnham pledges a big shakeup for Britain in a high-risk political speech
Prime Minister Andy Burnham has vowed to give Britain “a new social contract for the 21st century.”
Andy Burnham pledges a big shakeup for Britain in a high-risk political speech
LONDON (AP) — Prime Minister Andy Burnham pledged Tuesday to give Britain “a new social contract for the 21st century," reform the country's electoral system and reset its relationship with its European neighbors. But he acknowledged that economic constraints make delivering his sweeping plans a ...
Britain Politics Labour
Britain's Prime Minister Andy Burnham delivers his Leader's Speech during the Labour Party Conference in Liverpool, England, Tuesday, Sept. 29, 2026. (AP Photo/Jon Super)
Victoria Coates discusses US foreign policy on Iran, Taiwan
Heritage Foundation VP of National Security Victoria Coates and panelist Mike Lee discuss the latest U.S. foreign policy updates, focusing on indirect peace talks with Iran, military funding for Taiwan and ongoing economic pressure on Cuba.
"Contempt for Science and Truth": Macron Condemns Russian Strike on Ukraine’s Science Academy
The attack on the National Academy of Sciences follows drone hits on a Kyiv university where 160 sheltered, and damage to a UNESCO World Heritage site.
Britain Politics Labour
Politician Charles Clarke attends the Labour Party Conference in Liverpool, England, Tuesday, Sept. 29, 2026. (AP Photo/Jon Super)
Oktoberfest returns for 61st year in Amana Colonies
One of the longest-running Oktoberfest celebrations in the country returns this week for its 61st year, bringing four days of German heritage, music, food, drinks, dancing and more to the
Hayden Panettiere's ex Wladimir Klitschko petitions to protect their daughter's inheritance
LOS ANGELES (AP) — Actor Hayden Panettiere's ex-fiancé Wladimir Klitschko has filed an urgent petition asking that he be allowed to act as their 11-year-old daughter's temporary representative in California
October 1 Vallejo/Vacaville Arts-Entertainment Source: Activities
Vallejo Hike Club’s Morning Hike is set for Friday at 7 a.m., at Mare Island Shoreline Heritage Preserve, 167 O’Hara Court, Vallejo.
‘Santa Clarita Karen’ forced to apologize as her business implodes after vicious street vendor war
Greenville Country Music Fest back at CCNB Amphitheatre
The Greenville Country Music Fest is set to return to CCNB Amphitheatre at Heritage Park in Simpsonville on April 30 and May 1, 2027.
Rod Stewart announces his 'last tour ever, ever, ever'
Rod Stewart, 81, has announced that his Final Encore tour in 2027 will be his last rock 'n' roll tour 'ever, ever, ever.'
Mayor Sarno joins Health Commissioner Caulton Harris to bring greetings at Department of Elder Affairs Hispanic Heritage Month Luncheon at the Ray Jordan Senior Center
Mayor Domenic J. Sarno was honored to join Health & Human Services Commissioner Helen Caulton Harris and the Springfield Department of Elder Affairs team on Friday to bring greetings at a special Hispanic Heritage Month Luncheon celebration with our seniors at the Raymond A. Jordan Senior Center. This special luncheon is a collaboration between the Raymond A. Jordan Senior Center and the North End Senior Center and celebrated Hispanic heritage and the valued contributions of our senior community. Members of the senior centers were invited for a vibrant day of music, dance, food, and culture. El Morro bakery provided lunch to members by our kind and dedicated Elder Affairs staff. Grupo Erupxion performed live music. Special thanks to host/emcee Joanna, the Springfield Department of Elder Affairs and the Council on Aging team for bringing us together to celebrate the beautiful mosaic of our Springfield. Mayor Sarno states, “We are always proud to celebrate the vibrancy and beautiful mosaic that is our Springfield community. On behalf of the City of Springfield, we celebrate and welcome the continued contributions of Hispanic Americans toward our community, including their cultural heritage, public service, and entrepreneurial spirit. I commend and appreciate this collaboration between the North End Senior Center and the Ray Jordan Senior Center to host this special luncheon in celebration of Hispanic Heritage Month for all our seniors to enjoy. ‘Que tenga buena salud y Dios te bendiga’ – Good health and God Bless.”
Massimo Iorizzo Named Director of NC State’s Plants for Human Health Institute
Horticultural Science Professor Massimo Iorizzo, whose research has delved into the genetics of a veritable rainbow of small fruit and vegetable crops, will lead NC State University's Plants for Human Health Institute.
Massimo Iorizzo Named Director of NC State’s Plants for Human Health Institute
Horticultural Science Professor Massimo Iorizzo, whose research has delved into the genetics of a veritable rainbow of small fruit and vegetable crops, will lead NC State University's Plants for Human Health Institute.
A trailblazer in science and teaching - College of Arts and Sciences
Chemistry Professor Emerita Linda Spremulli will be honored for her lasting impact on generations of scientists ahead of the Linda L. Spremulli Trailblazer Chemistry Symposium on Oct. 2.
Meritage to close 38 restaurants as Wendy’s fight unfolds
Meritage Hospitality Group plans to close 38 restaurants as the Wendy’s franchisee fights to retain control of 314 locations in Chapter 11.
Progressive politics the only credible path to revive Democratic Party
The center has fallen. As Republican Party has veered toward authoritarianism under Donald Trump, Democrats need to head in a new direction.
Think Beyond Brita — These Advanced Water Filter Pitchers From $15 Help Remove Microplastics From Your Glass
More microplastics and forever chemicals are popping up in our drinking water. As a public health expert, I rounded up seven water filter pitchers to help reduce your microplastic exposure in your drinking water. Picks include pitchers from Culligan, Aquagear, LifeStraw, Aarke, and more.
Gándara Center works to improve Latino mental health care
During Hispanic Heritage Month, the Gándara Center is highlighting the importance of cultural representation and language access in addressing mental health needs within Latino communities across w…
Andy Burnham brings good vibes to Labour’s annual conference but tough choices are coming
British Prime Minister Andy Burnham has been in office for two months, and his party seems content for now | KNSS Radio
HCA Florida hospitals celebrate Hispanic Heritage with family health event
HCA Florida Healthcare hospitals are celebrating Hispanic Heritage. Hospitals in Ocala and West Marion hosted a family health and wellness event at the Silver Springs Shore Community Center.
Trump posts series of attacks on GOP congresswoman who criticized him on immigration
President Donald Trump appeared to intensify his irritation with GOP Rep. Maria Elvira Salazar on Saturday evening after reposting a series of social media attacks on the congresswoman who made waves last week for breaking with him on his immigration tactics.
45th annual Catface Turpentine Festival is set for Saturday, October 3
From a parade and rosin potatoes to Turpentine soap and a street dance, the Catface Turpentine Festival promises a day of entertainment for the whole family. This year marks the 45th anniversary of the event, hosted by the Portal Heritage Society.
Jennifer Lopez brings diva wattage as Dolce & Gabbana refreshes its Sicilian inheritance
Jennifer Lopez has brought her diva wattage to Dolce & Gabbana’s Spring Summer 2027 runway show | Newsradio 1140 WRVA
Jennifer Lopez brings diva wattage as Dolce & Gabbana refreshes its Sicilian inheritance
Jennifer Lopez has brought her diva wattage to Dolce & Gabbana’s Spring Summer 2027 runway show | Talk 1370
Jennifer Lopez brings diva wattage as Dolce & Gabbana refreshes its Sicilian inheritance
Jennifer Lopez has brought her diva wattage to Dolce & Gabbana’s Spring Summer 2027 runway show | WWJ Newsradio 950
Sold-out Charity Regatta Raises Record $334,690 for VNA Health
For 22 years, the Santa Barbara Yacht Club (SBYC) has raced boats to raise funds and friends to benefit the Community Care Programs and charitable mission
Opinion: Liberal Democrats reflect profound political change in Britain
British politics today is fracturing into multiple parties, no longer 2 or even 3
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Second-line season kicks into high gear this weekend in New Orleans. Here’s the schedule.
With the exception of Sundays during Christmas, Carnival and the New Orleans Jazz & Heritage Festival, some 40 second-lines roll each week until around mid-June.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Family business blends Cajun, Caribbean flavors at Continental Kitchen
Family-run catering business -- Grub 2 Go -- is combining Cajun and Caribbean flavors while working out of a shared commercial kitchen during Hispanic Heritage.
Virginia City businesses adapt after Montana Heritage Commission lease controversy
Virginia City businesses are closing out a tough season after steep lease hikes from the Montana Heritage Commission displaced several longtime operators.
New book, class aim to help ranching families pass businesses to future generations
Rawls and Davis college collaborate on a book with the Ranching Heritage Center.
New book, class aim to help ranching families pass businesses to future generations
Rawls and Davis college collaborate on a book with the Ranching Heritage Center.
On This Mexican Island, Raccoons Make and Play With Toys (and Also Sip Margaritas)
Scientists observed a family of pygmy raccoons near a Cozumel beach club learning from one another how to craft balls from paper, an indication that the animals have a culture.
'Santa Clarita Karen' gets ultimate revenge on tormentor after her business implodes following vicious taco shop war
City Arts and Sciences Academy partners with UMass Lowell
LYNN — As Lynn Public Schools’ City Arts and Sciences Academy enters its second year, the district is developing a partnership with UMass Lowell that will expand college and career… Related posts: City Arts and Sciences Academy receives $250,000 grant Lynn school celebrates AAPI Heritage Month ‘The American Dream’ explores the pursuit of justice with […]
Dove Family Dentistry Highlights Dental Health During Hispanic Heritage Month
News Channel 3 - Memphis, TN News, Sports and Weather
Charlotte nonprofit works to close mental health gap for Hispanic girls, women
September is Suicide Prevention Month and also marks Hispanic Heritage Month.
Charlotte nonprofit works to close mental health gap for Hispanic girls, women
September is Suicide Prevention Month and also marks Hispanic Heritage Month.
Charlotte nonprofit works to close mental health gap for Hispanic girls, women
September is Suicide Prevention Month and also marks Hispanic Heritage Month.
Charlotte nonprofit works to close mental health gap for Hispanic girls, women
September is Suicide Prevention Month and also marks Hispanic Heritage Month.
Charlotte nonprofit works to close mental health gap for Hispanic girls, women
September is Suicide Prevention Month and also marks Hispanic Heritage Month.
Charlotte nonprofit works to close mental health gap for Hispanic girls, women
September is Suicide Prevention Month and also marks Hispanic Heritage Month.
Charlotte nonprofit works to close mental health gap for Hispanic girls, women
September is Suicide Prevention Month and also marks Hispanic Heritage Month.
Charlotte nonprofit works to close mental health gap for Hispanic girls, women
September is Suicide Prevention Month and also marks Hispanic Heritage Month.
Charlotte nonprofit works to close mental health gap for Hispanic girls, women
September is Suicide Prevention Month and also marks Hispanic Heritage Month.
Charlotte nonprofit works to close mental health gap for Hispanic girls, women
September is Suicide Prevention Month and also marks Hispanic Heritage Month.
East Tennessee sports announcer dies in head-on crash
Longtime East Tennessee sports broadcaster and youth coach Aaron Harvey has died following a two-vehicle head-on crash on Ruritan Road in Roane County.
Greek PM urges 'courage' in talks with UK over Parthenon Marbles
Greece's Prime Minister Kyriakos Mitsotakis on Thursday called for "political will and courage" to resolve the country's protracted battle with Britain over returning the prized Parthenon Marbles to A...
Hispanic Heritage Festival offers full day of celebration in Elkhart
The Hispanic Heritage Festival brings music, food vendors, family activities and fireworks to downtown Elkhart on Sept. 26.
11-12 IN SPAIN | OPEN THREAD
Welcome to The Daily Merengue! THESE ARE YOUR MODS: Ezek XI, Valyrian Steel, KungFuZizou, NeRObutBlanco, Felipejack, and Juninho ENOUGH OF “MR NICE GUY” Over the past 2+ years, we’ve lost to much on the pitch that now, when i see our players looking as nonchalant as possible. It irritates me more than their inability to […]
Press Release: The Molina Healthcare Charitable Foundation Awards $15,000 Grant to Ozark Center for Behavioral Health Training in Southwest Missouri Schools
The Molina Healthcare Charitable Foundation (“MolinaCares”), in collaboration with Molina Healthcare of Missouri (“Molina”), awarded a $15,000 grant to the Ozark Center
Britain to join the EU’s new global ocean monitoring system
Cooperation on OceanEye, which will help to predict extreme weather and climate events, comes amid government attempts to move closer to Brussels
Barbara Finlay, psychology professor emerita, dies at age 75
Barbara Finlay, the W.R. Kenan, Jr. Professor of Psychology Emerita and an award-winning scholar who challenged traditional thinking regarding psychology and brain function, died Sept. 12.
Reform and the UAE – a threat to British politics
By Alex Carlen The United Arab Emirates likes to present itself as part of the solution to the climate crisis. The oil-rich Gulf state has committed to Net Zero by 2050, hosted COP 28, and even declared “championing climate action” as one of three strategic objectives for this week’s session of the United Nations General Assembly. But behind the scenes the UAE has quietly built one of its closest political relationships in Europe with the party most hostile to climate action in Britain: Nigel Farage’s Reform UK. There is no evidence that the UAE is funding Reform. But a new FairSquare report, Petro-populism: the UAE–Reform threat, published today, documents a growing political relationship that should concern anyone interested in the integrity of British democracy. Reform’s leaders have embraced the UAE’s political model and promoted positions that align closely with the Emirati government’s priorities, while the UAE has given Farage and his party unusually warm access and public backing. What is emerging is not simply a relationship between British politicians and a wealthy Gulf state, but a channel through which an authoritarian government can cultivate political influence here, and abroad. Democracy for Sale relies on its readers. If you already support us, thanks so much. If you don’t, sign up to support fearless independent investigative journalism. Subscribe Back in January, Nigel Farage appeared at a GB News event in Dubai. On the 50th floor of a tower overlooking the luxury resorts and upscale residences of Palm Jumeirah, the Reform leader declared: “I want Clacton to look like this.” At the event – which Farage never declared on his official register of interests – senior Emirati officials mixed with British expats. Farage was keen to flatter. “We recognise you are our friends”, he said, assuring them that “a Brexit London, a Reform London, will remember you.” Controversy surrounding Reform’s finances and its susceptibility to foreign influence have centred around high-profile donations from billionaire crypto donors, and the jailing of Nathan Gill, Reform’s former leader in Wales, for accepting bribes to give pro-Russia speeches. Far less attention has been paid to Reform’s blossoming new alliance with the UAE, an oil-rich authoritarian state with a track record of ruinous anti-democratic interventions. Farage wasn’t always so fond of the UAE. Back in 2023 he called it an “absolute monarchy with an abysmal human rights record.” Now Reform’s hierarchy calls the UAE home. Deputy leader Richard Tice splits his time between his constituency and Dubai and has called on the UK to learn from the UAE. The party’s treasurer Nick Candy runs a firm which has been in partnership with a UAE-state linked firm since 2024. Nadhim Zahawi sits on the board of an Abu Dhabi think tank alongside an array of the most senior UAE officials and is reportedly close to three brothers of the country’s despotic ruler Mohammed Bin Zayed. Reform’s leading lights have effusively praised the UAE’s governance model, defended it from criticism, and advanced its political agenda in the UK. GB News, whose two major shareholders – the Legatum Foundation and Paul Marshall – have strong links to the UAE, has been more than happy to broadcast UAE propaganda and was forced to pay damages in 2025 after airing a false claim about a UK charity by the UAE “disinfluencer” Amjad Taha. The UAE has responded in kind. When the UAE Minister for Foreign Affairs conducted an official visit to the UK in May, Farage was the only non-government figure granted an audience. UAE state media publicised the meeting, and said that they discussed “the strategic relations between the two countries and ways to enhance them in a manner that serves mutual interests.” For the UAE these ‘mutual interests’ largely concern its paranoia over political Islam, and in this regard the UAE-Reform alliance is part of a broad and troubling pattern. Following a crackdown on dissent at home in the aftermath of the Arab Spring, the UAE has offered material and political support to a range of violent and authoritarian actors willing to oppose the Muslim Brotherhood with no regard for the consequences. Its meddling in Egypt, Tunisia, Yemen, and most notably Sudan, have been devastating. The UAE’s strategy of seeking out partners on the political fringes who it believes will advance its interests is not unique to Britain – it extends beyond the Middle East to Europe and the US. In France, it has offered clandestine support to Marine Le Pen through secret meetings, as well allegedly funding trips to the region after which Le Pen returned with a renewed focus on the UAE’s perceived enemies – Qatar and the Muslim Brotherhood. Left-wing opposition leader Jean-Luc Mélenchon has accused the UAE of smearing him and of “encouraging discrimination, hatred or violence”. In the US, the UAE actively supported the rise of Donald Trump, establishing itself as a key ally during both his first and second terms. Around these relationships sits a wider ecosystem of figures willing to amplify UAE narratives, that even extends to Andrew Tate and Tommy Robinson. Subscribe In Britain, the UAE has used a combination of aggressive diplomacy and illicit, disruptive tactics to achieve its policy goal of eliminating any perceived threat from political Islam. In 2012, for instance, it threatened to block billion-pound arms deals with the UK and stop inward investment if David Cameron did not act against the Muslim Brotherhood and rein in the BBC’s coverage of the group – going so far as to suggest, with no supporting evidence, that the group had infiltrated the BBC. It has financed smear campaigns against a high-profile UK charity and funded a mercenary to secretly surveil, and possibly assassinate, a British national on British soil. In Reform UK, the UAE has finally found an ally willing to not only ban the Muslim Brotherhood, but to publicly vilify the group and repeat the UAE’s claims that dangerous Muslims are a fifth column in British society, a narrative that aligns with the Islamophobia and anti-immigration sentiments that underpin Reform’s populist politics. The Rycroft review into foreign interference concluded that “hostile states and non-state actors have a clear incentive to attempt to undermine UK democracy.” The UAE’s network and alliance with Reform must be understood within that framework. It is a powerful, disruptive and deeply authoritarian actor with the resources and networks to intervene in our politics, and a track-record of doing so in a multitude of other countries. The evidence of the threat the UAE poses is overwhelming. The question is whether parliamentarians are willing to call the UAE out and demand action using the tools that the government has to respond. Placing the UAE on the “Enhanced Tier” of the Foreign Registration scheme alongside Russia and Iran would send a powerful signal to the UAE that its meddling will no longer be tolerated, and would place Farage’s next trips to the UAE under the scrutiny they deserve. Alex Carlen is research and advocacy manager at London based human rights organisation FairSquare and author of its new report Petro-populism: the UAE–Reform threat. Subscribe
Britain's JD Sports says Nike turnaround is only a matter of time
Nike is taking the right steps to revive its business and a turnaround is only a matter of time, said the finance chief of British sports and fashion retailer JD Sports , one of the U.S. group's largest customers.
Britain's JD Sports says Nike turnaround is only a matter of time
Nike is taking the right steps to revive its business and a turnaround is only a matter of time, said the finance chief of British sports and fashion retailer JD Sports , one of the U.S. group's largest customers.
Marlon James and Douglas Stuart have chance to become 5th multiple winner of Booker Prize book award
Marlon James and Douglas Stuart can become the fifth author to win the Booker Prize twice after both were shortlisted for arguably the U.K.’s most prestigious fiction accolade | WBBM Newsradio 780 AM & 105.9 FM
Fall has officially arrived. Here's what to know about the autumnal equinox
At 8:05 p.m. Eastern time Tuesday, the sun will be directly overhead at the equator.
Beshear praises Kentucky's 'Good Samaritans,' rebukes Trump in new book
Gov. Andy Beshear has published a new book detailing his time in office during the pandemic, multiple natural disasters and a deadly mass shooting.
First-ever literary festival planned for Orange County
What happens when you bring together four Orange County writers with a goal to recognize its proud literary heritage and honor the poets, novelists, memoirists and others who have shaped
Green policies just good politics, says UK minister
Transitioning to a low-carbon economy isn't just vital for the planet's future -- it's also good politics, according to Britain's climate minister, who argues the country's record-hot summer has galvanized public opinion like never before. Katie White, a member of the ruling Labour government, said the UK's right-wing parties had…
'You should not be here.' Trump taunts CNN at U.N. in credential fight
Trump taunted news outlets for continuing to cover him after he revoked the White House credentials of CNN, MS NOW and Politico.
Marlon James and Douglas Stuart have chance to become 5th multiple winner of Booker Prize book award
Marlon James and Douglas Stuart can become the fifth author to win the Booker Prize twice after both were shortlisted for arguably the U.K.’s most prestigious fiction accolade | WBBM Newsradio 780 AM & 105.9 FM
Jewel on Emotional Inheritance, Mental Health, Motherhood, More
Singer-songwriter Jewel sits down with TODAY’s Jenna Bush Hager and Sheinelle Jones to talk about her nonprofit, Inspiring Children Foundation, and the #NotAloneChallenge. She opens up about growing up in Alaska and overcoming challenges from her childhood. Jewel also talks about motherhood: “I really love being a mom. I wanted to be a mom, and I was in a really privileged position that I could change a lot of my life to make sure my son was the center,” she shares.
NOAA Selects Superintendent for Lake Ontario National Marine Sanctuary
The city of Oswego is pleased to announce that the National Oceanic and Atmospheric Administration has selected Stephanie Gandulla to serve as the first Superintendent of the Lake Ontario National Marine Sanctuary. Gandulla, who currently serves as Research Protection Coordinator at Thunder Bay National Marine Sanctuary, brings extensive experience in marine resource protection, maritime heritage preservation, research, education, outreach and community engagement. Throughout her career with NOAA’s Office of National Marine Sanctuaries, Gandulla has worked closely with communities, Tribal Nations, government agencies, local organizations and other partners to advance marine conservation and connect the public with the Great Lakes’ natural and cultural resources. She holds a master’s degree in Maritime Studies from East Carolina University and has extensive technical experience in scientific diving, marine operations, research and monitoring, interpretation and resource protection. As superintendent, Gandulla will provide leadership for the Lake Ontario National Marine Sanctuary and work with regional partners and stakeholders to advance its mission of protecting and conserving Lake Ontario’s significant marine resources and maritime heritage. “This is another exciting and important step forward in the process of establishing the Lake Ontario National Marine Sanctuary,” said Oswego Mayor Robert A. Corradino. “Stephanie Gandulla brings tremendous experience and a proven commitment to protecting our Great Lakes resources while building strong partnerships with communities. We are excited to welcome her to this role and look forward to working with NOAA, Stephanie and our many partners as we continue moving this initiative forward.” Gandulla’s extensive experience throughout the Great Lakes region positions her to build upon the strong foundation established for the sanctuary and foster continued collaboration among communities, agencies, organizations and stakeholders. Gandulla’s first official day as superintendent is Sept. 21. The city of Oswego looks forward to welcoming Gandulla to her new position and continuing to support the collaborative efforts surrounding the Lake Ontario National Marine Sanctuary.
'A really positive start for Barry'
Thierno Barry has been the surprise hit of Everton's season so far, with the 23-year-old striker the match-winner against Ipswich to take his tally to five goals this season. It is a marked improvement in scoring ratio from his eight goals in 41 games last season - and BBC Sport Merseyside commenter Chris Coughlin believes Barry is becoming a favourite with fans. It is Everton heritage and an honour to wear the number nine.