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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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In Retrospect: Poland, Russia, Europe
In April I spent a few days with Zryw, a Polish non-profit organization that recruits young people to enter politics and public life. Their aim is to build a new generation of civic leaders in Poland. I’ve followed their evolution from the beginning; my son is one of the founders. (“Zryw” means “impulse” or “burst of speed” in Polish). Julie Chmielewska, one of Zryw’s leaders, interviewed me at the event. Here is the conversation, lightly edited for grammar and context: Julia Chmielewska: Assuming that culture shapes institutions, could we conclude that some cultures are more prone to authoritarianism? Anne Applebaum: I don’t think so. Every culture, every nation, and every country has the potential for change. When we look at history, we can see that nations do change. Poland has changed, for example, from the 1980s to today. There’s a completely different mentality here than the one I encountered when I first visited, in 1988. The current generation sees the world through a different frame. So no, I don’t believe that certain nations are doomed to authoritarianism, or to anything. Of course, there are political and cultural traditions, but they can always be challenged. JC: So do you think there’s something intrinsic in human nature that pushes people to democracy, freedom? AA: I think there is something in human nature, a deep instinct, that pushes people towards freedom, yes. People who live in authoritarian countries – and I’ve heard this from them over and over again – sooner or later find themselves angered by a feeling of helplessness. They can see the unfairness of crooked courts, irrational political decisions. They naturally dislike the fact that somebody has all the power while they have none. In those circumstances, people who have no political background at all sometimes are politicized just by that frustration. I’m thinking of Svetlana Tikhanovskaya, for example, who was a Belarusian housewife, until the circumstances of her husband’s arrest forced her to become a politician. I met a woman who is a Uyghur from China, and who had come to live in Turkey. After several of her family members were arrested, she too was propelled into a political role. These kinds of experiences make people interested in democracy or political reform, even if they thought they didn’t care. I also think that the opposite is true: some people instinctively prefer homogeneity, order, hierarchy. They don’t like the confrontation of opinions or the noise of debate, and they lean towards a single leader or a unified regime. I think that most of modern history is shaped by the clash between those two different sides of human nature. JC: Which force do you find more powerful today? AA: I think they both have a lot of power and there’s no way of predicting who wins. Even in countries that seem very shut off or stuck in an authoritarian system can change. We’ve seen that happen. And vice versa, I think democracies can also begin to fail and slide into authoritarianism. So it’s very important not to be complacent in either direction. JC: I want to go into your history and your experiences. You’ve lived in Russia during a time of incredible change in the late 80s, and then you came back to do research in post-Soviet Russia. AA: I was a student in Russia just before the collapse of the Soviet Union. I then traveled and worked there extensively in the 1990s, and I met people who really were full of hope. They hoped that Russia could become a democracy, or at least a place that guaranteed freedom of speech, freedom of the press. These weren’t ideas that came from Washington. Although now the narrative in the Kremlin is different, I met many people who were working towards exactly that kind of transformation. A friend of mine ran a series of seminars – once a year, and then later several times a year, in cities all over Russia – designed to get people to discuss politics in new ways. She invited young politicians and journalists, as well as foreigners. I went to many of them, in Moscow as well as Volgograd and Novosibirsk. Over two decades, hundreds of people came to these seminars, and all of them wanted Russia to be different. I remain convinced that many Russians still want Russia to be different. It’s just that the old system, in the form of Putin, a representative of that system, returned. The KGB reimposed their power. And this wasn’t because of something to do with culture, this was to do with money and politics, and who was in charge. JC: You’ve partially answered my question... I wanted to ask whether that excitement of the 1990s was an exception from the Russian historical norm which has been rather authoritarian? AA: Of course, if you look at the history of Russia since the 18th century, there have always been liberal groups, reformers and revolutionaries. There were the Decembrists, in the early 19th century, and the rural populists later on, who tried to organize the peasantry. A significant group of liberal Russians appeared at the turn of the 20th century, people like the father of the writer Vladimir Nabokov, who was a Russian politician before the revolution. These groups were small in number, but sometimes had a broader significance. The Russian dissident movement in the 1950s and 1960s actually invented the modern human rights movement. It was their idea to hold the leaders of the Soviet Union accountable for the language they used, to remind them of the treaties they had signed and the promised they had made. They created the Helsinki group, for example, that held Soviet leadership to the language of the Helsinki Treaty, which formally ended the Second World War and which contained guarantees of human rights, at least on paper. That idea spread to Eastern Europe, and similar tactics were used here in Poland. (Benjamin Nathans recently wrote a great book about the Soviet dissidents, To the Success of Our Hopeless Cause) JC: But seemingly, even if they do ever get power, they could never hold on to it. AA: We don’t know, because they have never really had power. But in any case, we also don’t know what will happen in the future. There is no reason to assume that Russia will forever be condemned to totalitarianism. Even during the first fifteen years of Putin’s regime there was some form of democratic politics. Only when the full-scale war began did he bring everything to an end: he shut down all remaining independent organizations and killed his most important opponent, Alexi Navalny. But does that mean he is popular, that he enjoys legitimacy? Even now, we don’t really know what Russians think about him, or about the war. There is no way of doing real polling in Russia because nobody will answer an independent pollster over the phone. JC: Do you think that the flock of young people, especially young men, who fled Russia after the start of the war represent a continuation of liberal movements that refuse to partake in the authoritarian state, or do you think they are moving for the sake of self-preservation – “I don’t want to go to the army, so I leave”? AA: I’m sure it’s both. I actually know many people who left Russia for political reasons either in the very last years before the war, or else just after the war began. JC: And do you see a change in the young generation versus the old one that have fled? AA: It’s hard for me to say because the people who I know were mostly already politicized. I do know some younger people who left, but most of them were already either active in the opposition, or working as journalists. Many of them very self-consciously think of themselves as maintaining Russian culture abroad, just as in the 20th century the Soviet dissidents or the anti-communist White Russians once thought of themselves as people who maintained the true Russian culture, outside of Bolshevik Russia. JC: Let’s move on to Poland. One of your first experiences with Poland was reporting on Margaret Thatcher’s first state visit, in the autumn of 1988. You followed her around the farmers’ market. AA: She was making a symbolic gesture. She wanted to welcome free markets, but the only one she could really visit was the farmers’ market at Hala Mirowska. JC: And I want to talk about this area because today you can look out of any window in that district, Mirów, and see rows and rows of skyscrapers. How does it feel to see a country built from the ground in such a short time, both politically and economically? AA: You know, when you’re living in a period of dramatic change, it’s always hard to know whether the change is positive or negative. The transformation in Poland created winners and losers, as well as new classes of people, new political movements of different kinds. At the time, it sometimes just felt like turbulence. Now, we can look back at the 1990s and early 2000s in Poland and see in retrospect that the country was headed in towards prosperity and European integration. In around 2009 or 2010, I remember speaking to a woman who worked cleaning government offices, and who asked me if her daughter should study in Amsterdam or in London. This seemed to me to be a real transformation, and it happened very fast: within a few years, Poles stopped feeling like second-class Europeans, and a generation of younger Poles appeared who had no qualms about crossing borders. JC: We again live in turbulent times. Do you think we’re heading towards positive outcomes? AA: I can’t make predictions, because everything that happens tomorrow depends on what people do today. Also, history doesn’t have a trajectory. It doesn’t move in a particular direction. You only think it does afterwards. As I said, you can look afterwards at Poland in the 1990s and you could say this was a period of great progress. But not everybody at the time saw that. Sometimes people are very wrong about a given country’s trajectory. I remember people writing about Ukraine in the 1990s, about how dangerous it was that Ukraine was independent, that this was going to be an anti-semitic state, that Ukrainian nationalism was going to come back... and although you can say many bad things about Ukraine, the country made many bad choices, actually it became a pretty tolerant state which now has a Jewish president and until recently a Muslim defense minister. JC: In the 1990s Poland’s and Ukraine’s GDP were roughly similar. Ukraine was even a bit richer. So the starting point was similar for both of these countries, but they’ve turned out very, very differently. Even if we stop in 2014. Why do you think Ukraine “chose East”? Was it external influence? AA: No, I think Ukraine was in a different position. First of all, central and eastern Ukraine had been part of the Soviet Union since the 1920s, and had therefore experienced a longer period of occupation, repression, Sovietization and even Russification. Ukraine did not have, as Poland did, an alternative elite: a large cadre of economists and politicians, who already had some experience in opposition politics and in independent thinking. In Poland, the transformative finance minister, Leszek Balcerowicz, had already thought about how an economy might be decentralized before he took office. We can argue about how successful he was, but at least he was prepared to try something new. In Ukraine, people weren’t prepared. For one, there hadn’t been much space even for an illegal opposition in the previous couple of decades. Ukraine was also in many ways still emerging from colonial occupation. For the previous couple of centuries, many of the most capable Ukrainians had moved to Russia, and the first generation of leaders in independent Ukraine tended to be former Soviet apparatchiks. They didn’t immediately seek to become closer to western Europe. Instead, they looked for some kind of economic and political “third way” and an accomodation with Russia. Ukraine became stuck in this position, half-in, half-out and became pretty profoundly corrupt. JC: The Polish alternative elite had a vision of where they wanted the country to go. I think the general perception now is that this vision ends with the next election, right? Is this a natural process of gaining power? AA: Their vision, and it was shared by the time by politicians who now call themselves both left and right, was that Poland should join the EU and NATO, as fast as possible. My husband (Radek Sikorski) was in the very first government that said it wanted to join NATO. At the time this was taken very badly in Washington: the demand for NATO membership absolutely came from Poland, not from the US. But even then, in the early 1990s, many Poles already understood that the Russian sphere of influence would grow once again, that it was important to become part of the transatlantic alliance and an integrated Europe as fast as possible: NATO, the EU, the Council of Europe, all of the trading and security alliances. That consensus lasted through several different governments and over many years, even governments containing former communists. For twenty years, right, left and center disagreed about many things, but they all agreed on the direction that the country should go. In retrospect, that consensus created the basis for prosperity in Poland. JC: And regarding the Polish-Ukrainian relations. We know that antagonisms, e.g. the myth of Wołyń [a massacre of Poles that took place in what is now Western Ukraine, in 1943] are increasingly used in Polish political discourse today. In Ukraine, nationalist historians make heroes out of UPA, the Ukrainian revolutionary army, which is held responsible for this tragedy. Where do you see a start for burying the hatchet? Is the reconciliation of our nations possible? AA: So here’s a strange thing: For more than a decade after they both gained independence, Poland and Ukraine participated in a number of projects that were designed to solve exactly these kinds of Polish-Ukrainian differences. Books were published that were jointly written by Polish and Ukrainian historians, monuments were built. These projects were successful: If you’d asked me this question in 2010, I would have said that there are no real historical issues between Poland and Ukraine, that the two countries had mostly reconciled. For a number of reasons, this began to shift. In Poland, children and grandchildren of victims of the Wołyń massacre felt their tragedy hadn’t been fully recognized. In Ukraine, nationalist groups wanted the UPA partisans who had fought against the Soviet Union recognized for their heroism, despite the fact that some in this broad and not well-defined group were also linked to Wołyń. In both eastern Poland and western Ukraine, the memory of the ethnic cleansing that took place there in the late 1940s - Poles were moved West, Ukrainians East - to accomodate new borders has left feelings of displacement and bitterness. The wave of Ukrainian immigration, which started before the war, may have provoked some of this. But don’t underestimate the role played by Russia, which has always wanted to create discord between Poland and Ukraine, and pumps out propaganda to that effect in both countries. Vandalism on both sides of the border, damage done to cemeteries and monuments, is sometimes carried out by provacateurs working for Russia, just to create bad feelings. The Polish-Ukrainian conflict also hides a different reality: although there are real grievances and bad memories, the truth is that the biggest tragedies both nations experienced in the twentieth century were inflicted by the Soviet Union and Nazi Germany. That should unite these two countries, not divide them. JC: This week (19.04.2026 – Ed.) in Hungary we saw that using historical narratives to create grievance has no longer worked. Are you optimistic about the direction after Orban’s loss? AA: The Hungarian election was really important because it shows that people can actually resist powerful, dominant propaganda. The ruling party Fidesz controlled all of the TV, 90% of the newspapers, the constitutional court, the bureaucracy... and yet people had the nerve to vote against it and resist it. It’s also an important election because Hungary created a huge network of well-funded think tanks and foundations that were funding other far right groups and projects. So that loss is going to have a knock-on effect in other places too, maybe even in Poland. JC: What you’ve said about resisting propaganda reminds me of one of the interviews you did about talking to Russians in the post-Soviet era who claimed that people knew that the system was lying. Why do people choose to believe in these regimes anyway? AA: Because it’s useful. Stephen Kotkin, an American historian, once described how people would learn how to “speak Bolshevik”: It was just a language that you needed to use in order to get by in society. If you didn’t talk the way the regime wanted you to talk, then you might have problems, or lose your job, or your kids would not get into university. It was a way of getting along. Communist Poland was similar, at least in the early years. When I was writing a book about the Sovietization of Eastern Europe after World War II, I met a lot of people who wanted to talk a lot about the war, when many of them had done really heroic things. But almost nobody wanted to talk about the decade afterwards, between 1945 and 1956. This was when you had the short period of terror, violence and Polish Stalinism. To stay safe, people felt the need to just go along with what others were saying, or stay out of politics, or use communist jargon without necessarily believing it. I don’t judge them for it, and I wouldn’t describe all of those people as collaborators. It’s easy to feel moral certainty in retrospect, because we know that communism ended. But if you were living in 1949, it might not have been clear to you that communism was going to end. In very repressive societies, maybe about 10% of people who are really evil – collaborators, torturers. Maybe 10% of people are really brave and who find ways to resist. And then around 80% of people have kids, they have parents, they have to have jobs and they’ve had to get through it somehow. Strange though it may sound, I’ve found that the work I did on that book is now very useful in explaining some of what’s going on in the United States today. There are plenty of members of the Republican Party in Congress who know perfectly well that Donald Trump says many things that aren’t true. But they avoid criticizing him because it’s inconvenient, because they would get in trouble, because someone would attack them on the internet. So actually you don’t even need mass terror to get people to conform. JC: Is Gen Z reinventing agency? AA: We’ll see. In any generation you can find groups of people who want agency. If you live in a society that’s unfair, for example where a tiny number of people have captured most of the wealth, then at a certain point people rebel. This is always easier for younger people, who have you have less to lose. The question now is how the internet will affect the relationships between citizens and the state, and how it will change organizations. The “Twitter revolutions” people spoke about as early as 2008-9, mass protests organized online, have often proved to be very superficial. Although you can easily join something just by clicking, the work of creating a real movement requires physical participation. Successful mass movements of the past, for example the Civil Rights movement in the United States, were built by people who had spent many years together. They had participated in non-violent workshops together. They practiced and prepared. Just using the you can get everybody to show up at a certain moment, but then when the protest is broken up, nothing happens. It’s also true that the repressive regimes have more recently learned how to use the internet to undermine leaders and movements. Most of all, they now understand how to make people cynical. The form of propaganda that most modern authoritarians use - and I think the Russians really pioneered this - deploys sneering cynicism. Instead of praising the rulers, the regime propagandists mock the opposition movement leadership for being supposedly corrupt or sexually degenerate, with the goal of undermining any kind of idealism. JC: MAGA grew on the internet? AA: MAGA is a real grassroots movement. They had symbols, red hats, they showed up at rallies. But you’re right that the cynicism, the sarcasm and the distrust that the movement embodies came originally from the internet, and this is different. Fifty years ago, most European political parties had a social base in real organizations, in trade unions for Social Democrats, in church groups for Christian Democrats. As people stopped going to church and as the trade unions became smaller, the social base of these parties disappeared. Now people who wouldn’t have known one another in the past meet on the internet and create new movements, many of which don’t last. JC: Is history ending? Going in stale circles? AA: History never ends. In truth, human beings want contradictory things at the same time: order and freedom, stability and change. These things are never resolved, and when a society swings too far in one direction, people always push it the other way. But each time that happens, the result is different. Certainly it is true that we are now in a period when old philosophers and ideas from the 1930s are undergoing a revival. Carl Schmitt, who was a philosopher who was very influential on the Nazis, is back as an influence on both the far left and the far right, once again inspiring people to think that all politics has to be existential, that all politics is about defining and defeating enemies. In the US, some are also bringing back dominionism, the idea that we need a Christian and not a secular state. It’s also true that we are living through a more fundamental shift. The old left-right divide, which was mostly about the size of the state, is much less important now. Instead, we are arguing about more fundamental things: what are our rights, what protects our freedom. Or how much power do we want to give small elites, versus how much power to give ordinary people. In America a small group of very wealthy people now control information, because they control the social media platforms and AI, which means they determine what people will read and learn. Finding a way to preserve preserve zones of autonomy and independent thinking, this is going to be the main task for the next generation. JC: What is the one book that a person interested in Central Europe should read? AA: You could read my book “Iron Curtain: the Crushing of Eastern Europe” which tells the story of how the Soviet Union imposed its culture on the region. Or read Tim Snyder’s history of the region, “The Reconstruction of Nations: Poland, Ukraine, Lithuania, Belarus 1569-1999.” And everyone should read “The Captive Mind” by Czesław Miłosz, which describes exactly the phenomenon we were talking about: why do people collaborate? I joined Scott Galloway and the brilliant Fiona Hill in a discussion about the wars in Ukraine and Iran, the future of global power, and what these conflicts reveal about America's role in the world. Scott told us that this was the 400th edition of his podcast, which is quite a number: My friend Francesco Chiamulera runs a brilliant series of literary events, Una Colline di Libri, A Hill of Books, in the Prosecco Hills, a region of vineyards and elegant hill towns in the Veneto, north of Venice. We did an event in Vittorio Veneto and also drove and biked around the countryside. Buy Autocracy Inc Buy Iron Curtain Open Letters, from Anne Applebaum is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
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