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Former OpenAI science lead launches Warp Science to automate wet labs with robots
The new startup raised a $215 million round led by Lightspeed.
Rangers Defender Olwethu Makhanya Backed to Reach the Highest Level
Former Philadelphia Union coach Bradley Carnell has backed Rangers defender Olwethu Makhanya to continue progressing after his Ibrox move.
Critical GitLab Flaw (CVSS 10.0) Could Allow Unauthenticated RCE Across 12 Years of Releases
GitLab fixes CVE-2026-110264, a critical flaw that could allow unauthenticated code execution on self-managed versions dating back to 7.0.
Heineken taps into home entertainment
The Dutch lager brand has partnered with Brand Innovation Lab, the creative arm of Amazon Ads, to make going out as easy as streaming your favourite show.
Scientists Use Ancient Rains to Map the Possible Origin Life on Mars
Billions of years ago, rain may have helped shape where the chemistry of life could begin on Mars. A new study maps how formaldehyde, an important prebiotic molecule, may have reached the surface. This map could help guide future missions searching for signs of past life on Mars.
Panama City Beach Senior Center Announces Upcoming Craft Fair and Community Health Fair
Senior crafters are getting a head start on the holidays, with tables full of handmade Christmas gifts, decor, and more up for grabs.
A blue-collar bellwether weighs ousting longtime GOP Sen. Susan Collins in Maine
Voters in Lewiston helped propel Collins to victory in her last election. Some are ready for a change, but others are wary of losing Collins’ sway in the Senate.
Trump will sign an order aimed at boosting women's health research, a plan backed by the first lady
President Donald Trump is set to sign an executive order aimed at bolstering federal research on women's health, a move pushed by first lady Melania Trump.
Building Business: Reveler, Avesta top off 201-unit affordable apartment complex in Portland
The ceremony marked the installation of the final structural component of the six-story, 166,000-square-foot building and the end of the first phase of construction.
Ironworker challenges Rep. Max Miller as the Ohio congressman fights to hold seat amid abuse claims
Ohio Republican congressman Max Miller faces a tough reelection challenge from Democratic union ironworker Brian Poindexter.
Player availability report, presented by Orlando Health Jewett Orthopedic Institute: Orlando Pride at Houston Dash
Here is this week's player availability report, presented by Orlando Health Jewett Orthopedic Institute, for Sunday's away match at Houston Dash
Mother of abducted boy to speak at 'A Night of Hope'
Patty Wetterling, whose son Jacob was abducted in 1989, will share a message of hope and child safety at an Oct. 23 benefit in New York Mills.
The WET Science Center’s fall lineup brings the outdoors inside
With rain in the forecast and cooler temperatures, it’s time to find affordable ways to have fun inside. The WET Science Center is ready to help! Most middle schoolers in …
Orlando Health expands orthopedic care in West Orange County
A new Orlando Health Jewett Orthopedic Institute has opened inside Orlando Health — Health Central Hospital in Ocoee.
Lincoln Science Focus students study rare saline wetlands with local agency partners
KHGI Nebraska TV is the ABC affiliate station for Central and South-western Nebraska, providing news, weather, sports and local event coverage to residents throughout the area including: Kearney, Grand Island, Hastings, North Platte, Lexington, Holdrege, McCook, York, Alda, Aurora and Broken Bow.
N. Syracuse Manufacturer Marks Milestone, Plans for the Future
Air Innovations has grown from a small local manufacturer into a global business, selling its products in 74 countries organizations. Some of its clients include NASA, Blue Origin and SpaceX. By Stefan Yablonski [caption id=attachment_11117 align=alignright width=450] Michael Wetzel, president and CEO, and his father, Larry, who currently is an adviser to the board of directors. Larry served as the chairman of the board until 2024, when the company was acquired by Altus Capital Partners, a private equity firm.[/caption] Air Innovations in North Syracuse hopes to add more employees and possibly even expand its facility in the near future. The company is a global leader in designing and building environmental process control systems for applications that can’t be addressed with standard HVAC equipment, according to Michael Wetzel, president and CEO. “We customize solutions for temperature, humidity, filtration and pressurization, with additional capabilities in direct-expansion, chilled-water and thermoelectric technologies. Our business now is entirely focused on specialty or niche markets.” Air Innovations celebrated its 40th anniversary on Sept. 18, marking four decades of doing business, manufacturing products and growing in Central New York. In the beginning [caption id=attachment_11138 align=alignright width=451] A worker, Ezzy Salehi, tests a Wine Guardian condenser unit at Air Innovations.[/caption] “A guy by the name of Jim Kelley started the business [known as Floratech] in 1986. It was focused on refrigerated display cases for supermarket fresh flowers,” Wetzel said. “My father [Larry] started Clean Room Technology in the early 1980s, then sold that to a French company called Clestra Cleanroom. “My father and I bought Floratech in 1996 — 30 years ago, 10 years after it was started. Then in 1999, Floratech bought a portion of Clestra and their building. At that point everything was still called Floratech. But, as that was not reflective of the diversity of the business, we rebranded as Air Innovations in 2001.” The company rebranded to pursue a strategy of diversification in specialty HVAC systems. Wetzel explained that since then, it has become a trusted global partner, earning the President’s “E” Award for Exports and securing contracts in the most demanding fields, including aerospace, defense and semiconductor manufacturing. Air Innovations has grown from a small local manufacturer into a global business, selling nearly 70,000 units in 74 countries and territories and developing custom environmental control systems for companies and organizations including NASA, Blue Origin and SpaceX. “We work with all the big names you ever heard of and some you never heard of,” Wetzel added. The Wetzels sold the business two years ago to Altus Capital Partners, a private equity firm focused on control investments in lower middle-market, niche manufacturing companies in North America. Founded in 2003, Altus Capital Partners’ headquarters is in Wilton, Connecticut, with an additional office in Lincolnshire, Illinois. “They are an equity firm. Both my father and I both maintain a small minority share. I am going to continue to be involved. I call myself a part-time CEO. I will continue that role for the foreseeable future; I don’t see any change there.” Building to the future “We are at 58 employees right now, which is a little bit down. We had a high of 70. That moves along with the activity we have,” Wetzel said. “We’ll start ramping up here in the fourth quarter into next year. More than 20% of our employees have been with the company for more than a decade. “I am fairly certain that sometime in the next several years we are going to have to enlarge the footprint of our facility and for sure we are going to have to add employees. We already are. We are probably going to have to add five or six people next year. We are always in the market for HVAC technicians; we always need those.” Air Innovations will remain in Central New York, with its current workforce staying in place, he added. “I believe the primary driver of our success over time is the diversity of our business which is a direct result of our willingness to tackle new challenges,” Wetzel said.
Mom-and-Pop Business Owners Grapple with Harsh Times
Report shows small business owners in NYS less optimistic about the economy. Taxes, inflation, labor costs and competition from larger businesses are major concerns right now, they say By Aaron Gifford [caption id=attachment_11067 align=alignright width=300] Ashley Ranslow is director for New York state at The National Federation of Independent Business (NFIB).[/caption] Owners of mom-and-pop businesses in New York state have been less optimistic lately than their peers in other parts of the country, a recent report indicates. The National Federation of Independent Business (NFIB), based on a survey of 11,000 of its members in the Empire State, reported that taxes, inflation, labor costs and competition from larger businesses are major concerns right now. “Indeed, while taxes are a major problem in New York and the United States overall, New York small businesses notably are struggling more with the state’s onerous, multi-level tax burden,” Ashley Ranslow, NFIB’s director for New York state, said in the July report. Compared with surveys of business owners in other states, far fewer New York respondents rated their businesses as in excellent or good health. The report also said labor costs here are about 25% higher than the national average and are the “single most important problem” facing businesses. One respondent to the New York-specific survey complained that too much red tape, taxes and laws that restrict high-yielding companies have stifled their operation’s growth. Others said high disability and workers’ compensation insurance costs, alarming increases in utility rates and excessive building regulations are discouraging. Statewide, New York has a gross domestic product of $2.53 trillion (third in the nation, followed by Texas, $2.90 trillion; and California, $4.25 trillion), a per capita income of $90,500 (sixth) and an unemployment rate of 4.6% (34th). There are 2.4 million small businesses that employ 3.9 million people. [caption id=attachment_11112 align=alignright width=451] Member of the Greater Liverpool Chamber of Commerce gather at one of the several functions the chamber organizes monthly. “Everyone in this business community encourages each other to shop local. Everyone just wants to see each other succeed,” says Megan Wilmot, the chamber director[/caption] “New York state boasts one of the largest, wealthiest and most diverse cities in the world — and that’s still only about half the state’s population,” the report said. “In other words, the state is both its iconic city and so much more — geographically, demographically, economically. But New York is not without its challenges, challenges that include notably high taxes and other weaknesses that impact the small business environment,” it said. The report includes an optimism index that compares responses from New York (NFIB) members with those of their peers in other states across several categories. This ranges from plans to increase employment to expectations for higher sales, to plans to increase inventory or expand. The scores for Empire State business owners were lower in most categories, but they did score higher than the national average in noting that they have current employment openings, and that they are hopeful that the economy will improve. “The metrics so far paint a picture of a state with a series of challenges for small businesses, from a slightly below national average Optimism Index to a more seriously below national business health to very substantially below national Employment Index. What is going on with businesses that are creating these differences?” the report stated. In Central New York, the regional labor force comprises nearly 398,000 workers. The median household income here is $71,463, and the gross domestic product for the region last year totaled $61.3 billion, according to the CenterState CEO economic development and research organization. About half of the region’s labor force works for small and mid-sized businesses, although the number of people employed in that sector has decreased by 7% since 2010, according to CenterState’s 2026 economic forecast report. “While record-high employment in large-scale enterprises provides a strong foundation for Central New York,” the report says, “the long-term health of communities depends on a thriving small business sector to serve as a stabilizer.” Area employers identify several barriers to Central New York’s anticipated growth, including lack of specialized or skilled workers, government regulations, unaffordable housing options and long-term construction disruptions. In the city of Syracuse, the number of jobs in retail trade decreased by 1,500 or 4.7% between July 2025 and this past July. By contrast, the number of jobs in the leisure and hospitality sector increased by 2.5% or 700 jobs, in the same annual period, according to the New York State Department of Labor. Still, there’s plenty of interest for new businesses across Central New York. U.S. Census figures show that the number of applications for new businesses in all four counties increased significantly in the past 20 years. In Cayuga County, there were 324 applications in 2005 compared to 470 last year. In Madison County, the number increased from 385 to 480; Onondaga County, from 2411 to 4132; and Oswego County, from 553 to 836. Downtown Cazenovia is exemplary of Madison County’s trend: In the past year, the village welcomed a bait shop, a thrift store, a vitamin infusion center, a pizzeria, a Pilates studio and an Italian restaurant. A candy store is scheduled to open on the main drag in the months ahead. Oswego’s list of interesting new businesses in the past year includes a bubble tea shop, a hot dog eatery in Fulton, a specialty grocery store that features New York state products in Mexico, a beauty and esthetics studio in Hannibal and a hardware and farm supply store in Sandy Creek. In Onondaga County, the Liverpool area has also enjoyed a steady stream of new shops and eateries in recent years. That suburban community is unique in that, unlike neighboring communities, most of the restaurants are family-owned and not part of a national chain. [caption id=attachment_11116 align=alignright width=300] Megan Wilmot is the executive director of the Greater Liverpool’s Chamber of Commerce.[/caption] Megan Wilmot, executive director of the Greater Liverpool Chamber of Commerce, said independent business owners in her community maintain a strong sense of pride in holding their own against national companies. The chamber helps boost morale with red carpet events, ribbon cuttings, coffee hours and five-year anniversary celebrations for participating businesses. “We have built such a strong community,” Wilmot said. “Everyone in this business community encourages each other to shop local. Everyone just wants to see each other succeed.” In Syracuse, the downtown retail occupancy rate last year was about 82%, a slight improvement from 2024, according to the Downtown Syracuse Committee’s most recent annual report. Buildings with the largest amount of vacant space included The Galleries, One Park Place, and Equitable Towers, though not all of those spaces are designated for retail use. New businesses that opened in downtown Syracuse last year: Better with Time Clothing, Dakshin Curry & Biriyani, Havana Tattoo Society, Milano Bean Café, Miss Daisy, Pausa Coffee, Sweets for Babe, The Society CNY and Yafah Beauty Studio. The Destiny USA mall’s occupancy rate decreased from 80% in 2023 to 72% by the end of 2024, according to Integra Realty Resources. That leaves more than a quarter of the mall’s retail space vacant. “Looking ahead, the retail market is expected to see minimal rent growth, with vacancy rates likely remaining stable in community and neighborhood centers but continuing to rise in enclosed malls,” Integra’s report said. “New construction activity is low and redevelopment plans for former malls like Shoppingtown and Great Northern are still in the planning stages. The proposed Micron chip plant may spur development, but challenges remain in finding co-developers for large-scale projects.” Nationally, the U.S. Chamber of Commerce expects that small businesses will remain resilient and see their sales and revenues eventually improve. That organization, in a recent national survey, found that 25% of small business owners expect the economy to improve in 2027, while 45% indicated that they plan to increase employment in the next 12 months. And 69% said they believe their small business is in good shape and 70% said they are comfortable with their current cash flow. Thirty-one percent of small businesses reported raising their prices in July and 28% are planning to raise their prices within the next three to four months, the report said. Twelve percent indicated that this is a good time to expand their business. “Small business owners voice optimism for future revenues and hiring,” the report said. “High costs continue to be a wet blanket on reinvestment.” The NFIB reported in July that Main Street, despite gas price hikes, “is OK … for now.” Its small business economics trend report said sales across the country have been strong compared to last year, but continued inflation and higher prices from mom-and-pop establishments are causing some “cracks” to show. “If costs stay this high for much longer, reduced investment will have a tangible economic impact,” the report said. “The status quo is OK, but the outlook? The outlook is uncertain.”
LPS Science Focus students explore unique ecosystem at Lincoln salt marsh wetland
There is also an effort underway to reintroduce Salt Creek tiger beetle larvae to the area, with hopes they will survive and thrive in the salt marsh where they once lived.
Analysts eye RevMed’s pancreatic cancer launch, Merck’s data blitz for Q3 earnings
Bellwether Johnson & Johnson will kick off the third quarter earnings reporting period on Tuesday, with analysts searching for news on business development, launch execution and more.
Working Moms: Maternal mental health
Rain from Hurricane Isais slowed business traffic in downtown Asheville
Analysis | The bellwether races to watch in November’s midterm elections
Will Democrats’ blue wave materialize? Watch these races.
Can macular degeneration signal increased cancer risk?
Researchers found people with wet age-related macular degeneration had a slightly higher risk of certain cancers.
Iowa auditor candidates differ but agree office should be nonpartisan
Republican Lt. Gov. Chris Cournoyer and Democratic lawyer Taylor Wettach are vying to fill Iowa's open state auditor seat. Here's how they compare.
Where do Cournoyer, Wettach stand on key Iowa state auditor issues
Republican Chris Cournoyer and Democrat Taylor Wettach are running for Iowa state auditor. Here's where they fall on key issues.
New York Jets vs Cleveland Browns Game Day Forecast
Wet weather is in store when the Jets host the Browns on Sunday
EPA Grant Supports Nature-Based Solutions & Sediment Science for North Bay Marsh
The U.S. Environmental Protection Agency last month announced that it selected the San Francisco Estuary Partnership and the Association of Bay Area Governments as awardees of a $13.9 million grant to restore and enhance some 1,500 acres of tidal wetland habitat known as Strip Marsh East along the State Route 37 corridor in Solano County.... Read More
Caesars casino visitor center opens in Danville with goal to increase local business customers
Guests can create custom digital itineraries there and send them to their phones, said Lisa Meriwether, Danville’s tourism director.
Lewis Hamilton: Ferrari driver says team held 'huge discussions' over strategy following Bahrain GP tyre-choice blunder
Lewis Hamilton plummeted from second on the grid after starting last weekends Bahrain GP on slick dry tyres in wet conditions; watch Practice at 9.30am followed by Sprint Qualifying at 1.30pm on Friday live on Sky Sports F1 as the Singapore Grand Prix weekend begins
EPA grant supports nature-based solutions and sediment science for North Bay marsh
The U.S. Environmental Protection Agency last month announced that it selected the San Francisco Estuary Partnership and the Association of Bay Area Governments as awardees of a $13.9 million grant to restore and enhance some 1,500 acres of tidal wetland habitat known as Strip Marsh East along the State Route 37 corridor in Solano County.
Patient Dies By Suicide After 'Insurance Issue' Delayed Medicine For Lung Disease Flare-Ups
By Lauren Sausser and KFF Health News HealthDay ReportersTUESDAY, Oct. 6, 2026 (HealthDay News) — Kenney Blewett was diagnosed with lung disease more than a decade ago but started experiencing flare-ups this year that made him feel like he couldn’t breathe. Blewett, of Kyle, Texas, described those ...
“We’re in the entertainment business. If someone uses Suno to write a lyric, it’s not a high crime or misdemeanour”: Joe Bonamassa has sympathy for up-and-coming artists using AI to get an edge
But AI ‘artists’ shouldn’t be in the same chart as humans, he says
Rahm Emmanuel says Democrats should focus on ethics reforms rather than impeaching Trump
Democrats have publicly weighed wether they should pursue impeaching Trump for a third time.
CEO SUNDAY: Tropical Smoothie Cafe CEO says 'listening and learning' are keys to success
Max Wetzel said that staying close to franchisees, employees and customers has helped guide decisions as Tropical Smoothie Cafe has grown to nearly 1,800 locations.
How Democrats hope to reverse Trump’s changes to the presidency
As the midterms approach, some of the president’s foes are working to ensure his aggressive approach to executive power doesn’t outlast him.
Who will be Brazil’s next president?
The election could also serve as a bellwether of Donald Trump's influence in Latin America
How to watch Benjamin Russell vs Wetumpka high school football
You can watch Benjamin Russell football all season long with NFHS Network, including this week’s game against Wetumpka.
Patient Dies by Suicide After ‘Insurance Issue’ Delayed Medicine for Lung Disease Flare-Ups
Hours after experiencing a flare-up related to chronic obstructive pulmonary disease, Kenney Blewett of Kyle, Texas, died by suicide in June. A medication his doctor prescribed days earlier to ease his breathing problems hadn’t been filled due to an “insurance issue,” his pharmacy explained via email.
18 Sports earns Sportscast of The Year at NYSBA Awards
BINGHAMTON, N.Y. (WETM) – 18 Sports is proud to share and showcase a special honor for the year. Thursday, at the 2026 New York State Broadcasters Association Awards (NYSBA) in Binghamton, 18 Sports was awarded Sportscast of The Year for our region of the state. WETM-TV Sports Director Andy Malnoske, along with Sports Reporter Nick […]
Science on Repeat, Peat, Peat
Scientists and Knowledge Keepers, industries, and communities are all seeking answers—and finding even more questions—buried in carbon-rich wetlands.
An Agricultural “Island” in the Saskatchewan River Delta
Surrounded by wetlands, Manitoba's northernmost farmland near The Pas turns from green to brown over the 2026 growing season.
Local football teams climb NYS rankings
ELMIRA, N.Y. (WETM) – Several local football teams are starting off strong in 2026. And, they’re getting some well-deserved spots in the latest New York State Sportswriters Association (NYSSWA) Rankings. Waverly, Horseheads, Edison and the Schuyler Storm all come in ranked inside the top 20 in their respective classes. Plus, plenty more have earned honorable […]
SoMAS Students Reflect on Their Summer Science Fellowships with Sea Grant
This past summer, New York Sea Grant (NYSG) provided two Stony Brook University students with hands-on experience alongside scientists, community groups and government agencies through the 2026 Community Engaged Internship (CEI). Fellows worked on projects with mentors while engaging directly with the public and NYSG partners. As a wetlands field data Collection CEI fellow, Rhianna
Pumpkins, Wetlands And A Little Halloween Science
This weekend visitors to the annual FallTastic Trail Walk can participate in a science experiment that combines festive fun with environmental learning.
Woolly Bear says mild? The science behind our winter watch
A woolly bear brings fall folklore, while a strong El Niño puts D.C. on watch for a potentially warmer, wetter season ahead.
Sorcerers of the Imperium coming to Invasive Weed Gallery
BELLOWS FALLS — Invasive Weed Gallery will present a special exhibition of Tom Swetland's Sorcerers of the Imperium – from Himmler to Hegseth, from Oct. 3 to Nov. 7. There
Stockton Interns Help The Wetlands Institute Study Marsh-Nesting Shorebirds
Fieldwork opportunities take students to the beach and bay
What Does Anthropic’s Wet Lab Mean for Pharma?
Anthropic has established a wet lab in the San Francisco East Bay. In this article, experts explore what this means for scientific oversight, data ownership, and AI’s potential to transform drug discovery and rare disease research.
Newly discovered iron minerals might hold primordial water from when Earth formed
Researchers may have found a missing link in how Earth's mantle gets wet: newly discovered iron minerals that can store water at the extremely high temperatures and pressures present near our planet's core.
Bobby Kotick’s lawyers sent me a bad email (and later apologized)
The message I had received was unsettling—for a moment. Then it was just really confusing. Back on January 20 of this year, at 5:15pm ET, I received an email with the subject line “Legal Correspondence re Bobby Kotick.” It was from the law firm Clare Locke, a firm I’d heard had been emailing reporters in recent years about their coverage of Kotick, the former, longtime CEO of Activision Blizzard. The letter was threatening. A lawyer from the firm introduced themselves as “defamation counsel to Bobby Kotick.” They issued a “demand” that I “correct” a Game File article I’d published a week prior. The article that had irked them had been a scoop of sorts. I’d written about a a 2022 lawsuit brought by a Swedish pension fund, AP7, over Microsoft’s purchase of Activision Blizzard. The suit wasn’t news, but I was first to review and report about Kotick’s extensive pushback to the fund’s claims. The pension fund’s core contention was that the sale had been rushed by Kotick to avoid the consequences of sexual misconduct scandals swirling around the company in 2021. (He’d not been accused of misconduct himself in those suits, to be clear.) As I wrote at the time, Kotick had denied the allegations of the rushed sale. Beyond that, Kotick used a December 2025 reply to the Swedish fund’s lawsuit to assign blame for those workplace scandals, the bad press and even for the AP7 lawsuit. I’d found Kotick’s arguments novel and newsworthy. Across nearly 3,000 words, I explained Kotick’s take: that a Swedish gaming company was behind the Swedish fund’s lawsuit (the Embracer group; they denied it); that the Microsoft-Activision deal was not rushed and was secured at what Kotick felt history had proven to be an optimal price for shareholders; that he believed a conspiracy of people at unions government agencies, PR firms and the media had spun up claims of widespread workplace misconduct at Activision Blizzard in 2021. The article gave context for all of this, letting readers assess the claims and weigh their credibility. As I’d later write to Kotick’s lawyers: I would be surprised if you could point to any news article about Bobby Kotick in the last five years that has spent more of its wordcount articulating his point of view. He is welcome to do an interview with Game File any time. Nonetheless, there they were in my inbox that Tuesday evening: Clare Locke, the law firm that secured a $787.5 million settlement from Fox News over false statements about voting machines. They were emailing me, threatening that failure to comply with their demand could support a claim of “actual malice,” a legal standard for libel. Unless… Unless, they said, I added a key paragraph to my article. This was a paragraph that I already knew Kotick’s lawyers had been emailing reporters about for at least a year, and it was a paragraph that was already in my article. The paragraph they wanted is from a 2023 settlement that California’s Civil Rights Department struck with Activision Blizzard. The settlement had closed a two-year-old lawsuit over alleged sexual discrimination at the game maker. The paragraph basically said that claims of systemic or widespread sexual harassment—or of execs like Kotick tolerating such behavior—had never been proven. I’d already seen proof that Kotick’s lawyers had pushed for the settlement’s language to be added to reports about 2021 sexual discrimination and misconduct lawsuits brought against Activision Blizzard by California and, separately, by the U.S. federal government (both suits were since settled). I knew that Kotick and his lawyers felt that the California settlement language should be mentioned in the same breath as references to an article he hated and denied, a November 2021 Wall Street Journal article claiming Kotick knew “for years” of sexual misconduct at Activision Blizzard. So, in the Game File article that Clare Locke emailed me about, in the interest of ensuring I was being fair and balanced regarding the person I was covering, I had already included the following excerpt from the California settlement [emphasis added in bold]: (Kotick has repeatedly pushed back against that November article in the Wall Street Journal, citing among other things, language from a court-approved consent decree as part of Activision’s 2023 $54 million settlement over the California suit. It states: “no court or any independent investigation has substantiated any allegations that: there has been systemic or widespread sexual harassment at Activision Blizzard [or] that Activision Blizzard senior executives ignored, condoned, or tolerated a culture of systemic harassment, retaliation, or discrimination.”) On the evening of January 20, I was incredulous. How do you write a four page legal threat about a week-old article and miss this? While scrambling to also make my kids dinner, I wrote a lengthy reply to Clare Locke’s lawyers, basically asking them to cool it with the threats and to start making sense. In part, I wrote: I hope you can understand why I am having trouble understanding what you’re asking for, when the statement you’re demanding to see in Game File’s article already appears in Game File’s article. Actual malice, as you know, refers to a reckless disregard for the truth. I’m not sure what your argument is when my article already states your client’s position. Here is where I should remind you, the reader, that I am an independent journalist. I publish on Substack, and have availed myself of the Substack Defender program that provides writers on the platform with legal support. But I’m no Wall Street Journal or New York Times, nor even IGN or GameSpot when it comes to such things as, well, having a legal department. There are more fun things for me to do as an independent journalist than writing back to a powerful law firm representing a very rich person. On the evening of January 20th, I was just trying to cook some pasta, broccoli and chicken nuggets for hungry twins. Nevertheless, I wrote back to them. Two hours later, I got a reply. Summarizing: A lawyer for Clare Locke said they’d “reviewed an incomplete version” of my article and they “apologize for the confusion.” (My guess: Someone didn’t read past the piece’s paywall, even though they’d had a full week to scrounge up the funds to do so. What I’d published above the paywall was balanced, as was what came after.)1 That was almost that, but something about the situation bothered me. The letter had been marked “confidential.” I hadn’t agreed to that, and I disliked the idea that powerful people on the beat that I cover would act like they could unilaterally control what I might tell my readers about. On the morning of the 21st, having already gotten the powerful law firm to back off, I oh-so-wisely re-approached them with just one more thing. I thanked them for clearing things up the night before but noted that I’d never agreed to keep their letter confidential. I’m all for agreeing with a source to keep things off the record, but that’s the thing. We have to agree. You can’t just declare it. I’m not bound by that. I wrote to Clare Locke’s lawyer and said, in part: I trust the matter is resolved. It was disappointing to have to spend less time with my kids last night in order to address your legal letter. Family time’s precious. I will add, for clarity’s sake, that, while your letter stipulated that it was confidential, I did not agree to those terms. In the future, should you wish to communicate with me confidentially, I am happy to agree to classifying our communication as “off the record” prior to the actual communication—as is standard with any professional journalist. The firm’s lawyer replied, not directly addressing the confidentiality issue but asserting that the matter was resolved. Why I didn’t write about this until now In May, I told this story on an episode of Simon Parkin’s podcast My Perfect Console, but I held off on sharing it directly with Game File readers. I held off to avoid stepping on the toes of another reporter, the journalist Mikhail Klimentov. He’d interviewed me in the spring of 2025 about an investigation he was working on regarding Bobby Kotick lawyers pressing the media to add the California settlement language to stories referencing the 2021 lawsuits. And about how some outlets had changed their stories and how some simply deleted them. Initially, I was a third-party source for Klimentov’s reporting, providing on-the-record context about the state of the games media. I’d heard about the letters but hadn’t put the time into pursuing the story. I thought it was interesting, and I was glad he was covering it. When the outlet that Klimentov was going to run his reporting in dropped the story, I began talking to him about potentially publishing his reporting on Game File. This was tentative. Then, in January, when I got my own Clare Locke letter, I told Klimentov that I didn’t think it would make sense for me to publish him, not with me now being part of the story. I had my own version of this situation to tell. But I wished him well and said I’d refrain from telling my tale until he could get his reporting out there. Last Friday, Klimentov finally ran his investigation, in a nearly 48-minute video report for People Make Games. It covers various Clare Locke letters, how media outlets reacted to them and what to make of all this. His video weighs the merits of Kotick’s request and looks at some of the articles that were changed (one of which had a glaring error). I highly recommend watching it: (Note, I did some editorial consulting for a People Make Games video last year but nothing to do with this report.) While many outlets haven’t left any public evidence that they updated their Kotick coverage at Kotick’s counsel’s request, at least one has. Back in October 2025, the mainstream outlet Reuters applied the most transparent article update I’ve seen. On the 3rd of the month, they published an article about the state of the Swedish pension fund’s lawsuit. Days later, they added this: In an October 7 letter sent after publication of this article, Kotick’s defamation counsel disputed claims of widespread harassment at Activision. “Not a single investigation, court finding, verdict, or ruling ever concluded that there was any merit” to the allegations of widespread harassment at Activision, Tom Clare and Nick Brechbill of Clare Locke wrote. I’ve never added a statement to my article on Game File, because none was needed. Not for fairness’ sake, nor to meet any demands of Kotick’s lawyers. I’ve nevertheless wanted to be transparent with Game File readers. If someone powerful is questioning my reporting, is threatening a lawsuit over it… if that threat is part of a pattern involving other games media outlets and if, in my case, the whole thing ran into a ridiculous ditch, I want you to know about it. I also share this as a real example of how I handle threats to Game File. I stand up for my own reporting, even when it’s not comfortable to do so. (In that same category of standing up for the work I do, I’ll point to an incident in late August. Asocial media post I published to X/Twitter regarding reporting I did about Take Two and GTA VI was hit by bogus copyright claim by a firm working for the publisher. I pushed back and got it reversed; even while a bigger games media outlet let themselves be censored. This is the other reason I’m sharing this story: To emphasize that dealing with threats from powerful people is one of the costs of covering the video game industry independently and as fearlessly as possible. This is where you come in. Your support, through free and paid subscriptions (sign up here!), can help me keep doing that. It can ensure that I’ve got the back-up I need. And it can help make fiascoes like this even less of a worry, so I can spend my evenings dealing with more important things, such as making sure I steam the kids’ broccoli just right. 1 That pension fund lawsuit I wrote about in January has all but gone away. In May, the fund and Activision Blizzard owner Microsoft agreed to settle. Lawyers for the fund brokered a $250 million settlement for former Activision Blizzard shareholders. In the settlement, the fund’s lawyers changed their rhetoric. Where once they’d questioned the meaning of the California settlement language, they adopted a version of it for themselves. Several weeks ago, while seeking to get a court to sign off on the terms of the settlement, they proposed their fee for their work in the case: $60 million.
Kodiak Sciences Stock Surges 125% After Late-Stage Drug Trial Success
The trial tested two experimental eye drugs, Zenkuda and tabirafusp-ted, for treating wet age-related macular degeneration.
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A 9-Million-Year-Old Tooth Just Challenged What Scientists Thought They Knew About the Atacama Desert
Scientists were surprised to discover a fossilized tooth from a capybara that lived almost 9 million years ago in what is now northern Chile’s Atacama Desert. Chile’s Atacama Desert is an unlikely place to find traces of capybaras, the world’s largest living rodents, whose lives revolve around water and wetland plants. Yet a fossilized tooth
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
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Health experts warn of seasonal illness increase as fall begins
Local health experts are warning residents to prepare for an increase in seasonal illnesses as the first day of fall brings a drastic shift from humid heat to cool, wet conditions.
Health experts warn of seasonal illness increase as fall begins
Local health experts are warning residents to prepare for an increase in seasonal illnesses as the first day of fall brings a drastic shift from humid heat to cool, wet conditions.
Health experts warn of seasonal illness increase as fall begins
Local health experts are warning residents to prepare for an increase in seasonal illnesses as the first day of fall brings a drastic shift from humid heat to cool, wet conditions.
Health experts warn of seasonal illness increase as fall begins
Local health experts are warning residents to prepare for an increase in seasonal illnesses as the first day of fall brings a drastic shift from humid heat to cool, wet conditions.
Health experts warn of seasonal illness increase as fall begins
Local health experts are warning residents to prepare for an increase in seasonal illnesses as the first day of fall brings a drastic shift from humid heat to cool, wet conditions.
Health experts warn of seasonal illness increase as fall begins
Local health experts are warning residents to prepare for an increase in seasonal illnesses as the first day of fall brings a drastic shift from humid heat to cool, wet conditions.
Health experts warn of seasonal illness increase as fall begins
Local health experts are warning residents to prepare for an increase in seasonal illnesses as the first day of fall brings a drastic shift from humid heat to cool, wet conditions.
Health experts warn of seasonal illness increase as fall begins
Local health experts are warning residents to prepare for an increase in seasonal illnesses as the first day of fall brings a drastic shift from humid heat to cool, wet conditions.
Health experts warn of seasonal illness increase as fall begins
Local health experts are warning residents to prepare for an increase in seasonal illnesses as the first day of fall brings a drastic shift from humid heat to cool, wet conditions.
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It could be a wet afternoon when the Patriots and Steelers collide in Sunday's Week 2 NFL matchup.
For many Pittsburgh residents, wet basements pose health risks » Yale Climate Connections
Chronic moisture can create ideal conditions for mold that can trigger asthma attacks, allergies, and rashes.
Anthropic quietly sets up biology lab as it ramps AI drug program
At a time when fears of AI are gripping the public, the startup has built a wet lab — or place for physical experiments — in the San Francisco Bay Area, two people familiar with the matter said.
Ohio voters are mad as hell, but will they actually hold any politicians accountable in November?
Before it turned reliably red, Ohio was considered a bellwether for national politics. In every presidential election since 1964, the candidate who won Ohio, went on to win the White House. “As Ohio goes, so goes the nation,” was the old saying. We were the quintessential battleground state until we weren’t. That streak ended in […]
How Independent Fashion Designers Can Close the Gap Between Visibility and Viability
During New York Fashion Week, RaiseFashion’s Felita Harris, Afterpay’s Rachel Helfman and designer Hiywet ‘Mimi’ Girma joined BoF’s Yasmine Dahlberg at The Standard, East Village to discuss how independent designers can turn attention into a lasting business.
NASCAR Implements New Wet-Weather Policy For Bristol
NASCAR implements new wet-weather policy for Bristol.
Cardinals activate rookie second baseman JJ Wetherholt from injured list
St. Louis activated rookie second baseman JJ Wetherholt from the 10-day injured list Wednesday morning before the Cardinals met the San Francisco Giants.
Greening in China and India reshapes climate both locally and far away
A new study published in Advances in Atmospheric Sciences shows that greening in China generally cools the local climate with more rainfall over southern and northeastern China, while greening in India tends to produce warming and less rainfall. The Co-occurring greening in China and India yields uniform climate feedbacks across over half global lands, producing cooler and wetter southern China, cooler western Eurasia, and warmer northern North America.
Cardinals get promising JJ Wetherholt injury news before Giants series
The Cardinals could get their second baseman back this season.
Science and Sense: Eating local makes sense
This column has covered home gardens before – the process to get proper soil, things we can and can’t grow, the challenges of dry and wet periods (mostly dry), and
GB's Hewett beats Oda to win fifth US Open title
Great Britain's Alfie Hewett beats Japanese top seed Tokito Oda to win a fifth US Open title and his 11th Grand Slam singles crown overall.
El Niño Raises Risk of Wetter, Stormier Autumn across Globe
TEHRAN (Tasnim) – A strengthening El Niño is increasing the likelihood of wetter, stormier conditions in some parts of the world while raising drought and heat risks elsewhere.
Player availability report, presented by Orlando Health Jewett Orthopedic Institute: Orlando Pride at the Kansas City Current
Here is this week's player availability report, presented by Orlando Health Jewett Orthopedic Institute, for Friday's away match at the Kansas City Current
For these Midwest farmers, regenerative agriculture is about more than soil health. It's spiritual
A farmer in Minnesota has transformed a conventional farm using both formal agricultural education and the Indigenous wisdom he learned as a youth growing up in the Guatemalan rainforest.
18 Sports Commentary – the first day of the school year
ELMIRA, N.Y. (WETM) – It’s time for another special 18 Sport Commentary. On this edition, we discuss the very first day of school in the New York region of The Southern Tier. The first day of school symbolizes much more than just being the first day to go back to the classroom. It’s symbolic of […]
18 Sports Plays of the Week
ELMIRA, N.Y. (WETM) – It’s time for the next edition of the 18 Sports Plays of the Week. (Video Courtesy: Rochester Aquinas and Wellsboro Hornets Hudl, Chris Wilcox) The 18 Sports team showcases the top plays from the past week in the Twin Tiers. Top honors this week include 5 major moments on the high school […]
“Furious” creator breaks down season 1 finale and teases what’s next for Alice
“I’m definitely not using the show as a platform to advocate murdering people,” Meriwether tells EW.
‘Furious’ creator breaks down season 1 finale and teases what’s next for Alice
‘Furious’ creator Liz Meriwether breaks down the shocking finale and what’s next for the crime drama: ‘I’m definitely not using the show as a platform to advocate murdering people.’
1st Annual Veterans Mobility Health Expo
Discover leading mobility solutions, veteran support programs, and community resources designed to help people live more independently.
One arrested after vehicle crashes into Watsonville business, yields 3 injuries
Watsonville police arrested Edwin Wetterstrom, 73, on suspicion of driving under the influence after his SUV crashed into the 98 Cents Store on Freedom Boulevard, injuring two others.
Riverhead closer to taking over Long Island Science Center property
The vacant department store, officials said, threatens Riverhead's town square project.
Political cartoons for September 5
Saturday's political cartoons include eating votes, data center jobs, and more
'Pericles' review: Shakespeare playfully reworked at Boston Court
Ellen McLaughlin's modern verse translation of Shakespeare's 'Pericles' has its West Coast premiere at Boston Court Pasadena.
Water wars back in Punxsy for Labor Day
ELK RUN — Have you ever been told that you’re all wet? Well, that could be true on Monday, Labor Day, as the Elk Run Volunteer Fire Company is holding
Pest control business battles roach infestation near Wetlands Park
Residents near Wetlands Park continue to deal with a cockroach infestation that began a couple of weeks ago