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How the Grand Canyon could have lost 1 billion years of geologic history
The rise and fall of a continent-spanning cliff may help explain a mysterious 1-billion-year gap in Earth’s geologic history, a new study suggests.
People on weight-loss drugs report fingernails falling off as researchers uncover surprising link
Nail discoloration was reported by 46% of GLP-1 users versus 17% of non-users, while scalp inflammation accompanied hair loss in most medication users studied.
Citywide Mental Health Emergency Service Continues Expansion With Longer Hours
The city's Crisis Assistance Response and Engagement program (CARE) is moving its previous 10 a.m.-4:30 p.m. hours to a new 8 a.m.-10 p.m. weekday schedule.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
OnePlus 16 officially revealed with up to 1TB storage and three colorways
The OnePlus 16 is set to launch in China, succeeding last year's OnePlus 15. The company has now revealed the phone’s design, color options, and memory configurations.
I was fine with the OnePlus 16 pulling out of the US and the EU, but I wasn't prepared for this low blow
What OnePlus is rumored to be doing is felt way below the belt.
Here’s Why Sotera Health Company (SHC) Surges 25% in Q2
Broyhill Asset Management, a Charlotte-based firm, issued its second-quarter 2026 investor letter, which is available for download here. The Broyhill Equity Composite gained 8.8% in Q2, trailing the MSCI All Country World Index’s 15.1% and the MSCI ACWI Value Index’s 10.8%. For the first half, the Composite returned 2.3%, versus 11.5% for the Index. The […]
NationWide Self Storage Expands Business Storage Advantage Program Across More Unit Sizes and Locations
Businesses can receive their first 4 weeks FREE plus 10% off ongoing rent, with select units also offering a $100 in-store credit on moving suppliesVANCOUVER, BC / ACCESS Newswire / September 11, 2026 / is expanding its Business Storage Advantage program, making its business-focused storage benefits available across a broader selection of unit sizes, including more large storage units, at NationWide locations in Vancouver, Burnaby/East Vancouver, South Surrey and Kamloops.At the core of Business
Scientists find a huge 10-sided pattern in the clouds over Saturn's south pole
Scientists have discovered an enormous 10-sided wave pattern in the icy ammonia clouds over Saturn's south pole
Scientists find a huge 10-sided wave pattern swirling in the clouds over Saturn’s south pole
This photo provided by NASA/ESA/A. Sánchez-Lavega (Basque Country University) shows a pattern of clouds around the Saturn’s south pole on Saturday, Aug. 29, 2026. (NASA/ESA/A. Sánchez-Lavega, Basque Country University, EHU, via AP)By MARCIA DUNN CAPE CANAVERAL, Fla. (AP) — Scientists have discovered an enormous 10-sided wave pattern in the icy ammonia clouds over Saturn’s south pole. The spinning, meandering decagon appears to...
Scientists find a huge 10-sided wave pattern swirling in the clouds over Saturn’s south pole
CAPE CANAVERAL, Fla. -- Scientists have discovered an enormous 10-sided wave pattern in the icy ammonia clouds over Saturn's south pole.
Hubble spots a mysterious 10-sided 'decagon' growing around Saturn's south pole
The Hubble Space Telescope spied a large atmospheric phenomenon on Saturn: a decagon surrounding the south pole.
Scientists find 10-sided wave pattern swirling in the clouds over Saturn's south pole
Scientists have discovered an enormous 10-sided wave pattern in the icy ammonia clouds over Saturn's south pole
Scientists find a churning decagon over Saturn's south pole
Scientists have discovered an enormous 10-sided wave pattern in the icy ammonia clouds over Saturn's south pole.
ATLAS publishes first paper on Public Engagement with Science
You can’t exactly take the ATLAS experiment on tour. At 7,000 tonnes and buried 100 metres underground at CERN, it’s not easy to move. So, for more than a decade, the ATLAS Collaboration has found another way to bring the experiment to people around the world: live, interactive virtual visits with the scientists who work on it. In a recent paper published in the European Physical Journal Plus, the ATLAS Collaboration documents the evolution and impact of its flagship Virtual Visits programme. The paper is the Collaboration’s first publication focused specifically on science education, communication and outreach. It traces the programme from its beginnings as an experimental outreach effort in 2010 through its growth into a global programme – connecting classrooms in the Amazon, schools in the Himalayas and even a research station in Antarctica. Drawing on data collected between 2019 and 2025, the paper examines the programme’s reach and impact. Global reach, local connection Figure 1: World map showing the number of virtual visits across participating countries from 2019 to 2025. Cooler colours (purple and blue) are used for countries with fewer visits, and warmer colours (red and orange) for countries with more visits. (Image: ATLAS Collaboration/CERN) The core mission of the ATLAS Virtual Visit programme is to connect audiences worldwide with particle physicists and engage them in accessible discussions about cutting-edge research. While visiting CERN in person is an unforgettable experience, financial and logistical barriers can make such a trip difficult for many students and public groups. Video conferencing has allowed the Collaboration to break down these barriers: between 2019 and 2025, the Collaboration hosted 698 virtual visits, engaging tens of thousands of participants across nearly 70 countries (see Figure 1). Interactivity is central to the programme. Far from simple one-way broadcasts, Virtual Visit audience members are encouraged to engage in conversation with the scientist(s) hosting the visit. Most hosts are volunteers from the ATLAS Collaboration, who bring their diverse scientific expertise, language skills and cultural backgrounds to each visit. Where possible, audiences are paired with volunteer scientists who share their native language and cultural background, making it easier to engage, ask questions and connect with the hosts. Between 2019 and 2025, Virtual Visits were held in 19 different languages. The core mission of the ATLAS Virtual Visit programme is to connect audiences worldwide with particle physicists and engage them in accessible discussions about cutting-edge research. Constant evolution Figure 2: The number of ATLAS Virtual Visits organised annually since 2019. (Image: ATLAS Collaboration/CERN) The ATLAS Virtual Visit programme has continuously evolved to enhance the visitor experience. Early sessions were hosted directly from the ATLAS Control Room before transitioning in 2014 to a dedicated space in the ATLAS Visitor Centre, equipped with modern videoconferencing technology. In 2019, the ATLAS Collaboration expanded the programme’s reach, introducing live Virtual Visits from the experimental cavern during year-end maintenance stops and long LHC shutdowns. These exclusive sessions take participants beyond the ATLAS visitor platform, offering real-time, up-close views of the towering detector. When the COVID-19 pandemic disrupted in-person gatherings worldwide, demand for virtual engagement surged. The ATLAS Collaboration adapted rapidly by introducing Open Virtual Visits streamed via Zoom and YouTube, allowing individual science enthusiasts and families to join live guided tours. Figure 2 shows that the programme reached a peak of 155 visits in 2021 and has since maintained around 100 visits per year, demonstrating sustained engagement beyond the pandemic-driven increase. More than just a tour Beyond participation numbers, the paper highlights the positive impact on participants and educators. Teachers report successfully integrating Virtual Visits into their physics curricula, sparking sustained curiosity and in many cases inspiring students to pursue STEM studies and careers. Feedback received also highlighted how the direct dialogue with ATLAS scientists has given students an authentic and personal perspective on particle physics, helping them connect what they learn in the classroom with the people behind ATLAS research. Looking ahead, the programme will continue to evolve with new technologies and communication platforms. The goal is simple: to give even more audiences the opportunity to engage directly with particle physics and make fundamental science open to all. Learn more Breaking barriers: the impact of ATLAS Virtual Visits in science communication (Eur. Phys. J. Plus 141, 874 (2026), arXiv:2601.22457, see figures) ATLAS Virtual Visit Dashboard Register for an ATLAS Virtual Visit
New OnePlus 16 leak once again points to major camera upgrade
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Merchants of Doubt and the attacks on Extreme Event Attribution science
Last week, I attended a meeting at Columbia University on attribution science and climate law, hosted by the Sabin Center. It was a fantastic event, bringing together scientists and legal experts working at the intersection of extreme event attribution and climate law. Subscribe For those unfamiliar with it, extreme event attribution attempts to quantify the contribution of climate change to an extreme event. For example, several groups analyzed the impact of climate change on Hurricane Harvey’s enormous rainfall totals over Houston, Texas and they found that climate change increased rainfall by 15 to 38%. One thing that came up again and again was how terrified fossil-fuel interests are of extreme event attribution science. They are acutely aware that this research could land them in court. And losing those cases would leave them legally liable for billions of dollars in climate damages. Because the legal stakes are so high, the blowback has turned ugly. I spoke with several scientists at the meeting who are facing ongoing harassment over their work. This blowback is a coordinated campaign to make the entire field look suspect. The goal is to create the impression that attribution science is too uncertain, too political, or too conflicted to be useful in court or in public policy. The strategy is not based on actual science or evidence of misconduct, but on the generation of doubt. The new Merchants of Doubt We’ve seen this before. In fact, not that long ago: We only have to go back a year to the Department of Energy (DOE) Climate Working Group (CWG) report to see an example of using doubt as the tool to push back against well-established science. This strategy is laid out in an email from a member of the CWG, Dr. Roy Spencer, that was released during litigation over the Climate Working Group process. The key quote is: About all I can hope is that what we write will provide sufficient “reasonable scientific doubt” regarding the science claims in the 2009 TSD [technical support document], based upon almost 2 decades of new science, to call into question the original reasoning for the EPA Administrator’s decision that CO2 presents a threat to human health and welfare. This statement is strong evidence that at least some members of the committee were working to support a particular policy outcome: revoking the Endangerment Finding. The email also explains how they planned to do it: by attempting to generate “reasonable doubt”. This is going to be hard, Spencer implies. Despite falsely claiming that “2 decades of new science” weakens the case, Spencer explicitly acknowledges that the actual peer-reviewed science of climate change overwhelmingly rejects his position: But if the science argument is decided upon by a vote, or by the number of published citations, we lose the science argument. We can go back even further: This CWG email shares unmistakable DNA with the infamous 1969 tobacco memo that declared: “Doubt is our product, since it is the best means of competing with the ‘body of fact’ that exists in the mind of the general public. It is also the means of establishing a controversy.” The tobacco memo also acknowledges the limit of this strategy: Like the CWG, they knew the science was not on their side. Share The new new Merchants of Doubt The people attacking the IPCC chapter on extreme event attribution are the newest iteration of the Merchants of Doubt. Their goal, like all Merchants before them, is to introduce doubt into the process. Because the report is not even out yet, they cannot attack its conclusions. So they are attacking the authors instead. Here is a press release from the House Science, Space, and Technology Committee: In the letter, the Chairmen express concerns about potential conflicts of interest involving members of the Attribution Committee, stating that “publicly available information suggests a troubling pattern” in which committee members are affiliated with nonprofits that support climate accountability lawsuits, “raising the appearance of impropriety and member bias.” To be clear, this is just innuendo. There is no actual evidence of bias. And given the robust process that these reports go through, including multiple lines of peer review, it seems very unlikely that significant bias can survive into the report. When the report comes out, critics will have the opportunity to make legitimate criticisms of the report — if any exist. If none do, however, they’ll still make criticisms, but they’ll be bogus, simply designed to generate doubt. We’ll see. A note to the press: Fix your frame To any journalists reading this: The public debate over extreme event attribution science is not going away. The science is simply too dangerous to fossil-fuel interests for them to stop fighting it. You very well might be assigned to write an article about this area of research in the future. When you do, do not automatically adopt the framing that climate misinformers want you to use. They want you to frame the story around questions like: Are climate scientists trying to put their thumb on the scale to achieve a predetermined, politically motivated result? Are climate scientists improperly letting their politics invade the science of the IPCC? That frame is a trap. Instead, you need to view this through the historical lens of the Merchants of Doubt. How does the ecosystem of doubt operate? Who funds it? What methods do they use to misrepresent science and slime researchers? What scientific results are they trying to keep people from understanding are legitimate? Ultimately, you instead need to focus your article on the generation of doubt as a way to maintain the fossil fuel industry’s social and legal license to keep burning oil, gas, and coal. If you treat the misinformers’ frame as a legitimate, good-faith scientific critique, you are helping them produce doubt. Don’t do it. Don’t be a Merchant of Doubt. Thanks for reading The Climate Brink! Subscribe for free to receive new posts and support our work. Subscribe other stuff The Staying Curious Substack has an interesting post about the different flavors of climate sensitivity. This is crucial information if you want to understand how scientists think about how much warming the Earth will experience. I’d be grateful if you could hit the like button ❤️ below! It helps more people discover these ideas and lets me know what’s connecting with readers.
In Retrospect: Poland, Russia, Europe
In April I spent a few days with Zryw, a Polish non-profit organization that recruits young people to enter politics and public life. Their aim is to build a new generation of civic leaders in Poland. I’ve followed their evolution from the beginning; my son is one of the founders. (“Zryw” means “impulse” or “burst of speed” in Polish). Julie Chmielewska, one of Zryw’s leaders, interviewed me at the event. Here is the conversation, lightly edited for grammar and context: Julia Chmielewska: Assuming that culture shapes institutions, could we conclude that some cultures are more prone to authoritarianism? Anne Applebaum: I don’t think so. Every culture, every nation, and every country has the potential for change. When we look at history, we can see that nations do change. Poland has changed, for example, from the 1980s to today. There’s a completely different mentality here than the one I encountered when I first visited, in 1988. The current generation sees the world through a different frame. So no, I don’t believe that certain nations are doomed to authoritarianism, or to anything. Of course, there are political and cultural traditions, but they can always be challenged. JC: So do you think there’s something intrinsic in human nature that pushes people to democracy, freedom? AA: I think there is something in human nature, a deep instinct, that pushes people towards freedom, yes. People who live in authoritarian countries – and I’ve heard this from them over and over again – sooner or later find themselves angered by a feeling of helplessness. They can see the unfairness of crooked courts, irrational political decisions. They naturally dislike the fact that somebody has all the power while they have none. In those circumstances, people who have no political background at all sometimes are politicized just by that frustration. I’m thinking of Svetlana Tikhanovskaya, for example, who was a Belarusian housewife, until the circumstances of her husband’s arrest forced her to become a politician. I met a woman who is a Uyghur from China, and who had come to live in Turkey. After several of her family members were arrested, she too was propelled into a political role. These kinds of experiences make people interested in democracy or political reform, even if they thought they didn’t care. I also think that the opposite is true: some people instinctively prefer homogeneity, order, hierarchy. They don’t like the confrontation of opinions or the noise of debate, and they lean towards a single leader or a unified regime. I think that most of modern history is shaped by the clash between those two different sides of human nature. JC: Which force do you find more powerful today? AA: I think they both have a lot of power and there’s no way of predicting who wins. Even in countries that seem very shut off or stuck in an authoritarian system can change. We’ve seen that happen. And vice versa, I think democracies can also begin to fail and slide into authoritarianism. So it’s very important not to be complacent in either direction. JC: I want to go into your history and your experiences. You’ve lived in Russia during a time of incredible change in the late 80s, and then you came back to do research in post-Soviet Russia. AA: I was a student in Russia just before the collapse of the Soviet Union. I then traveled and worked there extensively in the 1990s, and I met people who really were full of hope. They hoped that Russia could become a democracy, or at least a place that guaranteed freedom of speech, freedom of the press. These weren’t ideas that came from Washington. Although now the narrative in the Kremlin is different, I met many people who were working towards exactly that kind of transformation. A friend of mine ran a series of seminars – once a year, and then later several times a year, in cities all over Russia – designed to get people to discuss politics in new ways. She invited young politicians and journalists, as well as foreigners. I went to many of them, in Moscow as well as Volgograd and Novosibirsk. Over two decades, hundreds of people came to these seminars, and all of them wanted Russia to be different. I remain convinced that many Russians still want Russia to be different. It’s just that the old system, in the form of Putin, a representative of that system, returned. The KGB reimposed their power. And this wasn’t because of something to do with culture, this was to do with money and politics, and who was in charge. JC: You’ve partially answered my question... I wanted to ask whether that excitement of the 1990s was an exception from the Russian historical norm which has been rather authoritarian? AA: Of course, if you look at the history of Russia since the 18th century, there have always been liberal groups, reformers and revolutionaries. There were the Decembrists, in the early 19th century, and the rural populists later on, who tried to organize the peasantry. A significant group of liberal Russians appeared at the turn of the 20th century, people like the father of the writer Vladimir Nabokov, who was a Russian politician before the revolution. These groups were small in number, but sometimes had a broader significance. The Russian dissident movement in the 1950s and 1960s actually invented the modern human rights movement. It was their idea to hold the leaders of the Soviet Union accountable for the language they used, to remind them of the treaties they had signed and the promised they had made. They created the Helsinki group, for example, that held Soviet leadership to the language of the Helsinki Treaty, which formally ended the Second World War and which contained guarantees of human rights, at least on paper. That idea spread to Eastern Europe, and similar tactics were used here in Poland. (Benjamin Nathans recently wrote a great book about the Soviet dissidents, To the Success of Our Hopeless Cause) JC: But seemingly, even if they do ever get power, they could never hold on to it. AA: We don’t know, because they have never really had power. But in any case, we also don’t know what will happen in the future. There is no reason to assume that Russia will forever be condemned to totalitarianism. Even during the first fifteen years of Putin’s regime there was some form of democratic politics. Only when the full-scale war began did he bring everything to an end: he shut down all remaining independent organizations and killed his most important opponent, Alexi Navalny. But does that mean he is popular, that he enjoys legitimacy? Even now, we don’t really know what Russians think about him, or about the war. There is no way of doing real polling in Russia because nobody will answer an independent pollster over the phone. JC: Do you think that the flock of young people, especially young men, who fled Russia after the start of the war represent a continuation of liberal movements that refuse to partake in the authoritarian state, or do you think they are moving for the sake of self-preservation – “I don’t want to go to the army, so I leave”? AA: I’m sure it’s both. I actually know many people who left Russia for political reasons either in the very last years before the war, or else just after the war began. JC: And do you see a change in the young generation versus the old one that have fled? AA: It’s hard for me to say because the people who I know were mostly already politicized. I do know some younger people who left, but most of them were already either active in the opposition, or working as journalists. Many of them very self-consciously think of themselves as maintaining Russian culture abroad, just as in the 20th century the Soviet dissidents or the anti-communist White Russians once thought of themselves as people who maintained the true Russian culture, outside of Bolshevik Russia. JC: Let’s move on to Poland. One of your first experiences with Poland was reporting on Margaret Thatcher’s first state visit, in the autumn of 1988. You followed her around the farmers’ market. AA: She was making a symbolic gesture. She wanted to welcome free markets, but the only one she could really visit was the farmers’ market at Hala Mirowska. JC: And I want to talk about this area because today you can look out of any window in that district, Mirów, and see rows and rows of skyscrapers. How does it feel to see a country built from the ground in such a short time, both politically and economically? AA: You know, when you’re living in a period of dramatic change, it’s always hard to know whether the change is positive or negative. The transformation in Poland created winners and losers, as well as new classes of people, new political movements of different kinds. At the time, it sometimes just felt like turbulence. Now, we can look back at the 1990s and early 2000s in Poland and see in retrospect that the country was headed in towards prosperity and European integration. In around 2009 or 2010, I remember speaking to a woman who worked cleaning government offices, and who asked me if her daughter should study in Amsterdam or in London. This seemed to me to be a real transformation, and it happened very fast: within a few years, Poles stopped feeling like second-class Europeans, and a generation of younger Poles appeared who had no qualms about crossing borders. JC: We again live in turbulent times. Do you think we’re heading towards positive outcomes? AA: I can’t make predictions, because everything that happens tomorrow depends on what people do today. Also, history doesn’t have a trajectory. It doesn’t move in a particular direction. You only think it does afterwards. As I said, you can look afterwards at Poland in the 1990s and you could say this was a period of great progress. But not everybody at the time saw that. Sometimes people are very wrong about a given country’s trajectory. I remember people writing about Ukraine in the 1990s, about how dangerous it was that Ukraine was independent, that this was going to be an anti-semitic state, that Ukrainian nationalism was going to come back... and although you can say many bad things about Ukraine, the country made many bad choices, actually it became a pretty tolerant state which now has a Jewish president and until recently a Muslim defense minister. JC: In the 1990s Poland’s and Ukraine’s GDP were roughly similar. Ukraine was even a bit richer. So the starting point was similar for both of these countries, but they’ve turned out very, very differently. Even if we stop in 2014. Why do you think Ukraine “chose East”? Was it external influence? AA: No, I think Ukraine was in a different position. First of all, central and eastern Ukraine had been part of the Soviet Union since the 1920s, and had therefore experienced a longer period of occupation, repression, Sovietization and even Russification. Ukraine did not have, as Poland did, an alternative elite: a large cadre of economists and politicians, who already had some experience in opposition politics and in independent thinking. In Poland, the transformative finance minister, Leszek Balcerowicz, had already thought about how an economy might be decentralized before he took office. We can argue about how successful he was, but at least he was prepared to try something new. In Ukraine, people weren’t prepared. For one, there hadn’t been much space even for an illegal opposition in the previous couple of decades. Ukraine was also in many ways still emerging from colonial occupation. For the previous couple of centuries, many of the most capable Ukrainians had moved to Russia, and the first generation of leaders in independent Ukraine tended to be former Soviet apparatchiks. They didn’t immediately seek to become closer to western Europe. Instead, they looked for some kind of economic and political “third way” and an accomodation with Russia. Ukraine became stuck in this position, half-in, half-out and became pretty profoundly corrupt. JC: The Polish alternative elite had a vision of where they wanted the country to go. I think the general perception now is that this vision ends with the next election, right? Is this a natural process of gaining power? AA: Their vision, and it was shared by the time by politicians who now call themselves both left and right, was that Poland should join the EU and NATO, as fast as possible. My husband (Radek Sikorski) was in the very first government that said it wanted to join NATO. At the time this was taken very badly in Washington: the demand for NATO membership absolutely came from Poland, not from the US. But even then, in the early 1990s, many Poles already understood that the Russian sphere of influence would grow once again, that it was important to become part of the transatlantic alliance and an integrated Europe as fast as possible: NATO, the EU, the Council of Europe, all of the trading and security alliances. That consensus lasted through several different governments and over many years, even governments containing former communists. For twenty years, right, left and center disagreed about many things, but they all agreed on the direction that the country should go. In retrospect, that consensus created the basis for prosperity in Poland. JC: And regarding the Polish-Ukrainian relations. We know that antagonisms, e.g. the myth of Wołyń [a massacre of Poles that took place in what is now Western Ukraine, in 1943] are increasingly used in Polish political discourse today. In Ukraine, nationalist historians make heroes out of UPA, the Ukrainian revolutionary army, which is held responsible for this tragedy. Where do you see a start for burying the hatchet? Is the reconciliation of our nations possible? AA: So here’s a strange thing: For more than a decade after they both gained independence, Poland and Ukraine participated in a number of projects that were designed to solve exactly these kinds of Polish-Ukrainian differences. Books were published that were jointly written by Polish and Ukrainian historians, monuments were built. These projects were successful: If you’d asked me this question in 2010, I would have said that there are no real historical issues between Poland and Ukraine, that the two countries had mostly reconciled. For a number of reasons, this began to shift. In Poland, children and grandchildren of victims of the Wołyń massacre felt their tragedy hadn’t been fully recognized. In Ukraine, nationalist groups wanted the UPA partisans who had fought against the Soviet Union recognized for their heroism, despite the fact that some in this broad and not well-defined group were also linked to Wołyń. In both eastern Poland and western Ukraine, the memory of the ethnic cleansing that took place there in the late 1940s - Poles were moved West, Ukrainians East - to accomodate new borders has left feelings of displacement and bitterness. The wave of Ukrainian immigration, which started before the war, may have provoked some of this. But don’t underestimate the role played by Russia, which has always wanted to create discord between Poland and Ukraine, and pumps out propaganda to that effect in both countries. Vandalism on both sides of the border, damage done to cemeteries and monuments, is sometimes carried out by provacateurs working for Russia, just to create bad feelings. The Polish-Ukrainian conflict also hides a different reality: although there are real grievances and bad memories, the truth is that the biggest tragedies both nations experienced in the twentieth century were inflicted by the Soviet Union and Nazi Germany. That should unite these two countries, not divide them. JC: This week (19.04.2026 – Ed.) in Hungary we saw that using historical narratives to create grievance has no longer worked. Are you optimistic about the direction after Orban’s loss? AA: The Hungarian election was really important because it shows that people can actually resist powerful, dominant propaganda. The ruling party Fidesz controlled all of the TV, 90% of the newspapers, the constitutional court, the bureaucracy... and yet people had the nerve to vote against it and resist it. It’s also an important election because Hungary created a huge network of well-funded think tanks and foundations that were funding other far right groups and projects. So that loss is going to have a knock-on effect in other places too, maybe even in Poland. JC: What you’ve said about resisting propaganda reminds me of one of the interviews you did about talking to Russians in the post-Soviet era who claimed that people knew that the system was lying. Why do people choose to believe in these regimes anyway? AA: Because it’s useful. Stephen Kotkin, an American historian, once described how people would learn how to “speak Bolshevik”: It was just a language that you needed to use in order to get by in society. If you didn’t talk the way the regime wanted you to talk, then you might have problems, or lose your job, or your kids would not get into university. It was a way of getting along. Communist Poland was similar, at least in the early years. When I was writing a book about the Sovietization of Eastern Europe after World War II, I met a lot of people who wanted to talk a lot about the war, when many of them had done really heroic things. But almost nobody wanted to talk about the decade afterwards, between 1945 and 1956. This was when you had the short period of terror, violence and Polish Stalinism. To stay safe, people felt the need to just go along with what others were saying, or stay out of politics, or use communist jargon without necessarily believing it. I don’t judge them for it, and I wouldn’t describe all of those people as collaborators. It’s easy to feel moral certainty in retrospect, because we know that communism ended. But if you were living in 1949, it might not have been clear to you that communism was going to end. In very repressive societies, maybe about 10% of people who are really evil – collaborators, torturers. Maybe 10% of people are really brave and who find ways to resist. And then around 80% of people have kids, they have parents, they have to have jobs and they’ve had to get through it somehow. Strange though it may sound, I’ve found that the work I did on that book is now very useful in explaining some of what’s going on in the United States today. There are plenty of members of the Republican Party in Congress who know perfectly well that Donald Trump says many things that aren’t true. But they avoid criticizing him because it’s inconvenient, because they would get in trouble, because someone would attack them on the internet. So actually you don’t even need mass terror to get people to conform. JC: Is Gen Z reinventing agency? AA: We’ll see. In any generation you can find groups of people who want agency. If you live in a society that’s unfair, for example where a tiny number of people have captured most of the wealth, then at a certain point people rebel. This is always easier for younger people, who have you have less to lose. The question now is how the internet will affect the relationships between citizens and the state, and how it will change organizations. The “Twitter revolutions” people spoke about as early as 2008-9, mass protests organized online, have often proved to be very superficial. Although you can easily join something just by clicking, the work of creating a real movement requires physical participation. Successful mass movements of the past, for example the Civil Rights movement in the United States, were built by people who had spent many years together. They had participated in non-violent workshops together. They practiced and prepared. Just using the you can get everybody to show up at a certain moment, but then when the protest is broken up, nothing happens. It’s also true that the repressive regimes have more recently learned how to use the internet to undermine leaders and movements. Most of all, they now understand how to make people cynical. The form of propaganda that most modern authoritarians use - and I think the Russians really pioneered this - deploys sneering cynicism. Instead of praising the rulers, the regime propagandists mock the opposition movement leadership for being supposedly corrupt or sexually degenerate, with the goal of undermining any kind of idealism. JC: MAGA grew on the internet? AA: MAGA is a real grassroots movement. They had symbols, red hats, they showed up at rallies. But you’re right that the cynicism, the sarcasm and the distrust that the movement embodies came originally from the internet, and this is different. Fifty years ago, most European political parties had a social base in real organizations, in trade unions for Social Democrats, in church groups for Christian Democrats. As people stopped going to church and as the trade unions became smaller, the social base of these parties disappeared. Now people who wouldn’t have known one another in the past meet on the internet and create new movements, many of which don’t last. JC: Is history ending? Going in stale circles? AA: History never ends. In truth, human beings want contradictory things at the same time: order and freedom, stability and change. These things are never resolved, and when a society swings too far in one direction, people always push it the other way. But each time that happens, the result is different. Certainly it is true that we are now in a period when old philosophers and ideas from the 1930s are undergoing a revival. Carl Schmitt, who was a philosopher who was very influential on the Nazis, is back as an influence on both the far left and the far right, once again inspiring people to think that all politics has to be existential, that all politics is about defining and defeating enemies. In the US, some are also bringing back dominionism, the idea that we need a Christian and not a secular state. It’s also true that we are living through a more fundamental shift. The old left-right divide, which was mostly about the size of the state, is much less important now. Instead, we are arguing about more fundamental things: what are our rights, what protects our freedom. Or how much power do we want to give small elites, versus how much power to give ordinary people. In America a small group of very wealthy people now control information, because they control the social media platforms and AI, which means they determine what people will read and learn. Finding a way to preserve preserve zones of autonomy and independent thinking, this is going to be the main task for the next generation. JC: What is the one book that a person interested in Central Europe should read? AA: You could read my book “Iron Curtain: the Crushing of Eastern Europe” which tells the story of how the Soviet Union imposed its culture on the region. Or read Tim Snyder’s history of the region, “The Reconstruction of Nations: Poland, Ukraine, Lithuania, Belarus 1569-1999.” And everyone should read “The Captive Mind” by Czesław Miłosz, which describes exactly the phenomenon we were talking about: why do people collaborate? I joined Scott Galloway and the brilliant Fiona Hill in a discussion about the wars in Ukraine and Iran, the future of global power, and what these conflicts reveal about America's role in the world. Scott told us that this was the 400th edition of his podcast, which is quite a number: My friend Francesco Chiamulera runs a brilliant series of literary events, Una Colline di Libri, A Hill of Books, in the Prosecco Hills, a region of vineyards and elegant hill towns in the Veneto, north of Venice. We did an event in Vittorio Veneto and also drove and biked around the countryside. Buy Autocracy Inc Buy Iron Curtain Open Letters, from Anne Applebaum is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
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OnePlus 15T officially gets a 7,500mAh ‘Glacier’ battery
OnePlus’ upcoming compact Android phone is getting some extra power, with the company confirming the OnePlus 15T will house a...
OnePlus 15T: New compact flagship surpasses Xiaomi 17 Pro and Vivo X300 with larger battery
The OnePlus 15T is set to launch as the successor to the OnePlus 13T, which featured a 6,260mAh battery with 80W wired charging but lacked wireless charging support. Now, the company has officially confirmed that the 15T will pack a 20% larger battery than its predecessor.
OnePlus 15T Confirmed to Launch with Periscope Camera
OnePlus 15T is confirmed to launch with a periscope camera. The OnePlus 15T will launch in China first.
OnePlus 16 leak reveals sub-1 mm display bezels
The next-generation OnePlus flagship, expected to be called the OnePlus 16, has appeared in a fresh leak. It suggests the device could feature even thinner bezels than the OnePlus 15.
Record-Breaking One-Off Bugatti Brouillard Could Become the Most Expensive Bugatti Ever
A one-off aimed at a historic record Bugatti’s latest one-off, the Brouillard, steps onto the hypercar stage with the quiet confidence of a record-breaker. The brand’s tradition of bespoke excellence meets a bold new aesthetic, positioning this unique commission to potentially become the marque’s most expensive creation. Built on the proven underpinnings of the Chiron/Mistral architecture, yet transformed by distinctive craft, the Brouillard is both homage and innovation. A name born from equestrian legend More than a century ago, a striking white horse captivated Ettore Bugatti in Molsheim. That equine myth now informs the car’s name and its sensory identity. The result is an automotive portrait of athletic grace—surfaces that read like muscle, curves that suggest motion, and details that quietly speak of discipline and heritage. Embroidered horse motifs on door panels and seat backs echo the story, while a miniature glass sculpture of the steed crowns the shifter. Sculptural design with purpose The Brouillard’s silhouette favors sinuous surfaces over hard creases, allowing light to glide over its form like a tendon under skin. Aerodynamics inform elegance: an integrated ducktail replaces a deployable wing, cleansing the airflow and boosting stability at speed. Its stance is athletic, its volumes taut, and its visual language unmistakably Bugatti. “Sculptural, organic forms—like a tendon beneath the skin—hide immense power behind noble simplicity,” said design chief Frank Heyl, capturing the car’s philosophy in a single stroke. Craft elevated to an art The cabin embraces craftsmanship at an uncommon level. Custom-woven textiles from Paris introduce a discreet tartan pattern, while green-tinted carbon fiber nods to the exterior’s hue. A glazed roof creates a cathedral atmosphere, bathing the cockpit in natural light. A central spine appears to flow from exterior to interior, emphasizing continuity and structure. Highlights include: Custom textiles with subtle tartan motifs Green-tinted carbon fiber matched to the exterior finish A “cathedral” glass roof that elevates cabin ambience A sculptural centerline linking outside to inside Bespoke embroidery and glass equine detail W16 power at its absolute apex Under the sculpted skin, the final evolution of Bugatti’s 8.0‑liter, quad‑turbo W16 delivers a thunderous 1,600 hp at 7,050 rpm and 1,600 Nm of torque. This represents the pinnacle of nearly two decades of Bugatti engineering, honed to an ultimate state. The lightweight monocoque blends carbon fiber with aluminum, holding mass to around 1,900 kg for poise and control. Experts suggest the Brouillard could surpass the 282 mph (454 km/h) achieved by the Mistral, aided by more aerodynamic bodywork and the fixed ducktail. Whether or not it sets a new benchmark, its intent is clear: relentless speed paired with refinement. Exclusivity with an exacting timeline The commissioning process is intensive, with roughly 18 months of development leading to a 2027 delivery. Bugatti’s program limits itself to no more than two creations per year, ensuring focus and rarity. Each example leaves the atelier as a singular vision, shaped to the client’s collection and the brand’s ethos. An unveiling is planned for Monterey Car Week 2025, placing the Brouillard amid the world’s most discerning enthusiasts. Its patron is a European collector deeply invested in the Bugatti universe, from historic and modern cars to Carlo Bugatti furniture and Rembrandt Bugatti bronzes. A valuation poised to make history While Bugatti has not disclosed an official price, informed estimates place the Brouillard between €10 million and €30 million. Context matters: a series Mistral begins near €5 million, while the Brouillard adds profound personalization, sculptural changes, and a pace of production that keeps scarcity front and center. In an arena where uniqueness drives value, the path to a brand record is unmistakably open. What it signals for the marque The Brouillard crystallizes Bugatti’s dual identity: traditional savoir‑faire intertwined with boundary-pushing performance. It exhibits a narrative soul—the white horse of Molsheim—woven into modern materials and world-class aerodynamics. As a rolling statement, it reaffirms that the Bugatti idea is larger than speed alone; it is about story, craft, and the courage to pursue an ideal to its logical limit.
Unvaccinated baby dies of measles in 15th case since outbreak began, Health Ministry says
Out of the previous 13 deaths, the majority were otherwise healthy babies with no underlying conditions who had not been vaccinated.
12 Data Science Skills (+10 Hard-Won Career Lessons)
Master the data science skills employers are looking for. Our guide covers 12 key technical and soft skills, plus 10 real-world expert lessons.
Samsung Galaxy S26: Leaked Exynos 2600 GPU benchmark compared with OnePlus 15
Leaked Exynos 2600 benchmarks of an actual Galaxy S26 offer an early look at the performance of the world’s first 2nm chipset. This includes the Xclipse 960 GPU benchmark, which can be compared to the Adreno 840 that is part of the Snapdragon 8 Elite Gen 5 found inside the OnePlus 15.
Welsh rugby crisis: Game in Wales 'on a precipice' after another shocking year
BBC Sport looks at another tumultuous 12 months for the men's game in Wales with Welsh rugby close to rock bottom.
I love the OnePlus 15, but here are 5 reasons I'd recommend the OnePlus 15R instead
OnePlus 15R offers 90% of the flagship experience, including great performance and display, for $200 less than the OnePlus 15.
OnePlus 15R Hands-on: If only battery and refresh rate were the name of the game
If you stuff a bigger battery and faster display into a device that copies its more expensive counterpart, does that...
OnePlus 15R review: unbeatable battery life, beatable value
Charging every night is extremely optional.
OnePlus Turbo may have a battery so big that even the OnePlus 15 will seem underpowered
OnePlus started teasing a new smartphone series that may feature truly giant batteries.
The OnePlus 15R is about to get a version we didn’t expect
The Electric Purple 15R Ace Edition, previously China-only, could reach global buyers.
It's official: The OnePlus 15R will pack a crazy big battery (just not as crazy as you expected)
The brand's next affordable flagship will put a lot of its rivals to shame with a 7,400mAh cell.
OnePlus 15R pops up on Geekbench – and now the full spec picture is basically complete
A new Geekbench listing shows its scores, RAM, and software right before launch day.
OnePlus 15 is finally up for pre-order in the US, here's when it ships
You need to act fast if you want the free perks. The OnePlus 15 is finally up for pre-order in the US today, following a rather lengthy launch delay caused...
OnePlus 15 finally gets FCC clearance after government shutdown delay—preorders live
The device starts at $900 and comes with a free gift for a limited time.
OnePlus 15 launches US preorders after delayed FCC clearance
The battery behemoth is here.