SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " throwing " 168 found 🔀 AI-powered Shuffle
Hot 97 DJ Funkmaster Flex gets into fight at Knicks game
NEW YORK — Funkmaster “Funk” Flex was caught throwing down during the Knicks’ season-opening game at Madison Square Garden Tuesday night. Flex, a rapper and the long-running radio host of
Does opting out of smart TV tracking work? Research finds “suspicious” traffic.
OS operators throwing out that data is "unlikely," research author tells Ars.
CT axe throwing business closes up shop. One customer: ‘we had some amazing date nights here!’
A Connecticut axe throwing business has permanently closed its doors, according to a post on their Facebook page.
'SNL UK' slams Shane Gillis, James Austin Johnson's Trump cameos
"SNL UK" is throwing shade at its American counterpart.
Woman charged with throwing, pushing toddler at Auburn business
Larri Alexis Webb is charged with willful abuse of a child, according to Auburn police.
Science Lab: Mike Pettine hire means what exactly for Christian Parker?
Make no mistake about it, the Dallas Cowboys are throwing as many resources as they can at trying to right the ship in 2026, and Mike Pettine has officially entered the chat.
Guns, F-bombs, fortune cookies. What do wild campaign ads actually say?
A single mom who shot a home intruder. A pet alpaca. Chicago voters throwing around profanities. This cycle's campaign ads are fluffy, funny and profane.
Sean McVay reveals Alaric Jackson’s next move after NFL suspends Rams star for throwing punch
Rams coach Sean McVay confirms Alaric Jackson plans to appeal his two-game NFL suspension for punching Bills linebacker Bradley Chubb after Monday's loss.
Josh Allen reveals throwing mechanics issue he tried ‘ignoring’
The issues didn't seem to slow down the Bills offense on Monday Night Football.
Fourth straight 300-yard game for Matthew Stafford
Matthew Stafford topped 300 yards passing for the fourth straight week, throwing for 383 yards and 3 TDs versus Buffalo on Monday Night Football.
Pumpkin festival is Saturday in Pennville
Annual event brings back skillet-throwing and scarecrow contests
3 Players 76ers Must Hold Onto Going Into Regular Season
The rotation is coming into shape for the Philadelphia 76ers, but there may be some players throwing a wrench in the plan.
Aaron Rodgers Reaches Major Steelers Milestone vs. Colts
Pittsburgh Steelers quarterback Aaron Rodgers has reached another significant milestone. With throwing three touchdown passes against the Indianapolis Colts on […]
Brewers Name Jacob Misiorowski NLCS Game 1 Starter Vs Dodgers
The Milwaukee Brewers have officially named Jacob Misiorowski their starting pitcher for Game 1 of the National League Championship Series (NLCS) against the Los Angeles Dodgers. The hard-throwing right-hander will take the mound Sunday night at American Family Field as Milwaukee looks to get off to a strong start in a rematch of last year’s [...]
Rayo Plastic Balls Protest Forces La Liga Match Suspension
Rayo Vallecano’s long-awaited return to their Vallecas stadium ended in chaos on Saturday. The La Liga match against Athletic Club was suspended after local fans repeatedly interrupted play by throwing hundreds of small plastic balls and paper airplanes onto the pitch, a coordinated protest against club president Raúl Martín Presa, in what should have been […] The post Rayo Plastic Balls Protest Forces La Liga Match Suspension appeared first on HEAVY.
Pieper edges Judson 43-42 behind backup quarterback Lance Reid
Backup quarterback Lance Reid led a 22-point fourth-quarter rally, throwing a late touchdown and winning 2-point pass as Pieper edged Judson 43-42.
Warriors’ Steve Kerr Gives Updated Timeline For Jimmy Butler Return
The Golden State Warriors could be seeing their secondary star outside Stephen Curry return as early as the first two months of next year. According to Warriors head coach Steve Kerr, Jimmy Butler could be returning to action for the team in February, one year after tearing his ACL. “No idea. I’m just throwing February […] The post Warriors’ Steve Kerr Gives Updated Timeline For Jimmy Butler Return appeared first on HEAVY.
‘Hotel Transylvania’ Halloween party headed to Waynesville
This year, the Waynesville Parks & Recreation is throwing it’s biggest Halloween celebration yet. The Hotel Transylvania Halloween Party will be held from 5-8 p.m. Friday, Oct. 16, at the
Ted Cruz Says JD Vance’s ‘Political Bomb-Throwing’ Shows He’s ‘Insecure’ Ahead of 2028 Election
While Vice President JD Vance might have been floated as a potential frontrunner for the Republican presidential nomination in the 2028 election, Senator Ted Cruz is doing his part to keep the party’s...
Ted Cruz Says JD Vance Is ‘Feeling Insecure’ amid ‘Political Bomb-Throwing’ Ahead of 2028 GOP Primary
“In my experience, people engage in political bomb-throwing when they’re feeling insecure,” the Texas Republican said of the vice president over the weekend
Allen laments not throwing ball away after interception seals Bills loss
In hindsight, Josh Allen knows he and the Buffalo Bills would have been better off if he threw the ball away.
How to watch Dodgers vs. Braves NLDS Game 2
LOS ANGELES — The Dodgers will turn to Blake Snell in Game 2 of the National League Division Series, throwing another southpaw starter against the Atlanta Braves on Sunday night at Dodger Stadium. Snell, like Skubal, has won two Cy Young Awards in his career. But for Snell, his two Cy Young years (2018, 2023) […]
Travis Etienne Injury Update is Key News for Saints
Travis Etienne hasn’t gotten his New Orleans Saints career off to a great start. It might be getting worse in Week 3. He appears to have sustained an injury. While the Saints were in the midst of throwing four touchdowns to tight ends (two to Juwan Johnson, two to Noah Fant), Etienne left the field […] The post Travis Etienne Injury Update is Key News for Saints appeared first on HEAVY.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Getting Ready for Jackson Jobe’s Final Start
As the flame-throwing righty finds his groove following surgery, Detroit fans get a final look at the electric arm poised to lead the franchise’s next pitching generation.
Norvell Blinded by QB Loyalty Ahead of Central Arkansas Game
Florida State coach continues to praise his starting quarterback, Ashton Daniels, even after throwing three interceptions in a 50-36 loss to Alabama last Saturday. Norvell praises his confidence and decision-making skills. Daniels has thrown three touchdown passes against ranked teams this season.
New entertainment spot ‘Funder Alley’ opens in Fort Oglethorpe, GA
Discover Funder Alley, a fresh entertainment spot in Fort Oglethorpe, Georgia, offering duckpin bowling, axe throwing, and darts alongside a varied food menu and full bar. Located on Battlefield Parkway, it boasts both indoor and outdoor seating options, perfect for casual fun and group events.
Do the Falcons Have the Worst QB Room?
If Michael Penix doesn’t give Atlanta a spark throwing to small receivers, it’s going to be ugly all year
Bucs' Rookie EDGE Bain Dealing With Groin Injury
Tampa Bay Buccaneers rookie first-rounder Rueben Bain Jr. suffered a groin injury on Sunday, throwing his status for Week 3 in the air.
The Franklin Institute is throwing an adults-only Halloween party after dark
Science After Hours: Fright Nite will feature horror-movie effects, planetarium dancing and rooftop stargazing Oct. 16, with food and drinks available for purchase.
Ravens Insider Delivers Final Verdict on Surprising Lamar Jackson Trend
The Baltimore Ravens are off to a mixed start to the 2026 season, but their starting quarterback, Lamar Jackson, has done plenty of good.Jackson has been throwing the ball more than the Ravens have seen from him in the past, and it seems to be working. When the running game struggled in their Week 2 […] The post Ravens Insider Delivers Final Verdict on Surprising Lamar Jackson Trend appeared first on HEAVY.
Redevelopment of Sleepy Hollow to begin as fundraising campaign nears goal
Construction is expected to begin next month on the redevelopment of Sleepy Hollow Sports Park into a year-round recreation destination with a new lodge, ski lift and snowthrowing equipment. The $18 million project received a funding boost last week when the Iowa Economic Development Authority approved a $4.5 million grant from the Destination Iowa program…
Memphis QB Marcus Stokes named American Conference Honorable Mention
On Monday, Marcus Stokes was named an American Conference Honorable Mention after throwing for four touchdowns against UT Martin.
Kamala Harris launches into the 2026 midterms as her 2028 decision looms
As Kamala Harris mulls whether to run for president again, she’s throwing herself into the midterms by campaigning with fellow Democrats, starting with a Tuesday trip to Michigan on behalf of Senate nominee Abdul El-Sayed. It’s an especially notable destination for the former vice president. Michigan was one of seven battlegrounds she lost to Donald […]
Jalen Hurts credits offseason chemistry for Eagles’ late comeback win
Jalen Hurts credited offseason throwing sessions, film study and chemistry for the Eagles’ game-winning drive against the Titans
Alphabet’s Core Business Is Printing Cash Faster Than Regulators Can Write Fines
Regulators keep throwing billion-dollar fines at Alphabet and the company barely notices, which raises a more interesting question about how you value a business that outgrows its own penalties every few weeks.
Le Fee provides stardust on Sunderland's special night
You have to go back to a second-round exit at the hands of Portuguese side Sporting in the 1973-74 Cup Winners' Cup for the last time Sunderland played in a major European competition. There were no shortage of individual displays to galvanise them from Robin Roefs with his crucial saves, Granit Xhaka pulling the strings from deep to full-back turned winger Trai Hume causing chaos in the opponents' box one moment and throwing in a crunching tackle to end an AZ break the next. The 26-year-old worked tirelessly off the ball, nicking the ball back for his side time and again, but it is in the final third that the Sunderland playmaker really comes to life.
Fantasy Football Start 'Em, Sit 'Em Week 2: QB Edition
After throwing for only 175 yards and a pair of touchdowns, and throwing an interception, he posted just 15.4 points
2026 Emmys winners: 'Hacks,' 'The Pitt' and 'Widow's Bay' win big
The 2026 Emmy Awards are lauding perennial favorites, throwing in some surprises and vindicating Stephen Colbert.
Jalen Hurts carves up Commanders in season debut
Jalen Hurts made the most of limited opportunities, throwing for three TDs in a Week 1 win over Washington.
Prep football: Windsor handles business at Maria Carrillo in 42-14 win
Windsor got out to a hot start Firday night, throwing for three touchdowns in the first quarter.
Falcons QB Tua Tagovailoa leaves practice with an oblique injury
Atlanta Falcons quarterback Tua Tagovailoa left practice Thursday with an oblique injury. Tagovailoa bent over in obvious discomfort after throwing a pass during a portion of practice open to media and grabbed his right side. The Falcons listed him as a limited participant.
Brewers send Brandon Sproat to minors after his ninth-inning struggles
He walked four of the five batters he faced in the ninth and had a throwing error and a wild pitch during that stretch.
Johnsonville Votes For Sausage Over Political Ads - Midland
Johnsonville has jumped back into electoral politics, this time asking people to vote for something sensible: affordable protein for dinner. The humorous campaign targets viewer fatigue, as record spending on political ads threatens to drain the fun out of every last game, sitcom and streaming pleasure. This time, the company is throwing its hat in the ring for Dinner 2026. Backed by research it conducted with Harris Polls, Johnsonville has learned Americans are already overwhelmed by both politics and meal planning. Sausage is running the dinner race on a core promise to simplify dinner decisions, the company says.
In a forest where Jews fought the Nazis, a German military base and Lithuanian politics encroach on memory
Under German occupation, some 400 Jews escaped the Vilnius ghetto to Lithuania’s Rūdninkai Forest, created forts and organized attacks against the Nazis. Now, construction of a new German military base in the area is throwing into question …
Student-loan forgiveness is now pushed back for these PSLF borrowers
The Trump administration removed some student-loan borrowers' payments toward Public Service Loan Forgiveness. It's throwing their futures into limbo.
Jays Crush Royals
Blue Jays 9 Royals 2 Let’s get the bad news out of the way off the start. Jameson Taillon came out of the game after the second inning with right elbow discomfort. Why is it always the throwing arm that gets the discomfort? Oh right, because they are doing something very unnatural with the throwing […]
Brewers Face Misiorowski Warning as October Nears
Fading velocity and mounting fatigue for Milwaukee Brewers’ hard-throwing ace Jacob Misiorowski have sparked urgent calls to rest the young phenom before the postseason.
Garcia Takes Another Step Toward Rangers Return
Robert Garcia moved closer to returning to the Texas Rangers after throwing a live batting-practice session on Wednesday.
Auburn vs. Baylor Preview And Prediction
There might not be another player I’m more interested to watch this weekend than DJ Lagway . We already know about the talent. Now we find out whether a fresh start can finally unlock it. Lagway transferred to Baylor after throwing for 4,179 yards and 28 touchdowns during two seasons at Florida , and he’s…
The Latest: Canadian Prime Minister Carney tells Trump: ‘Stop trying to be tough’
Canadian Prime Minister Mark Carney is pushing back against a fresh wave of hostility from Washington, telling the Trump administration Tuesday to “stop doing memes, stop throwing shade and stop trying to be tough.”.
Florida Politics: Hope Florida, Nixon-Moody debate?
Florida Governor Ron DeSantis is set to host a forum with several huge names in the Florida Republican Party, such as Attorney General James Uthmeier and GOP Gubernatorial Candidate Byron Donalds. Meanwhile, Angie Nixon is throwing her hat into the ring, challenging U.S. Senator Ashley Moody to a public debate ahead of the general election. POLITICO Reporter and Florida Playbook author Kimberly Leonard joined FOX 35's Garrett Wymer live over Zoom to discuss what's new in Florida politics.
Diamondbacks 2, San Francisco 7: Out of Gas
After throwing 196 pitches in the first three games, the bullpen was unable to survive another Mitch Bratt start….
Throwing service members a mental health lifeline
PORTSMOUTH, Va. (WAVY) — A Navy sailor aboard the USS Abraham Lincoln faces potential disciplinary action, including having their salary reduced by half, after surviving a suicide attempt whi…
Ring says its new encryption limits what it can give police
Ring is ‘throwing away the key’ to your footage.
The men claiming to defend women’s sports are throwing sex toys at female athletes
The WNBA has attracted grifters who care little for basketball – and whose latest stunt exposes the hollowness of their supposed concern
10 Shows Like 'The 100' You Should Watch Next
The 100 remains our most thoroughly explored TV dystopia. In its absence, explore these other hellscapes near and distant, particularly when they involve throwing teenagers at apocalyptic problems.
Dodgers Expect Ohtani Back on the Mound in September
Shohei Ohtani enters the final phase of his throwing progression, aiming to bolster the Los Angeles Dodgers rotation before the postseason begins.
Los Angeles Dodgers Announce Shohei Ohtani Update During Brewers Series
The Los Angeles Dodgers have split the first two games of their four-game series against the Milwaukee Brewers. However, the story leading into Friday’s contest centered around superstar Shohei Ohtani throwing a bullpen session. He hasn’t pitched since before the All-Star break while dealing with a knee injury. Dodgers manager Dave Roberts spoke to the […] The post Los Angeles Dodgers Announce Shohei Ohtani Update During Brewers Series appeared first on HEAVY.
Shedeur Sanders throws for 79 yards, an interception vs. Bears
After quarterback Deshaun Watson had a so-so first half against the Bears, throwing for 126 yards, Shedeur Sanders also had a middling performance in the second half of the Browns’ first preseason game.
Shedeur Sanders says blister on hand has healed
In recent days, there's been chatter that Browns quarterback Shedeur Sanders has been dealing with a blister on his hand that's affected his throwing.
Shohei Ohtani takes next step in return to mound
PHOENIX — Shohei Ohtani played catch on Saturday before the Dodgers’ game against the Arizona Diamondbacks, his first time throwing a baseball outdoors in more than two weeks. Ohtani previously...
Jays Survive Near Collapse, Beat Phillies 5-4
That was stressful, especially after yesterday’s nightmare ending. It was close all game, with the Jays just edging out to what seemed like a comfortable lead in the late innings before nearly throwing it all away again in the ninth. In the end they hung on by a fingernail. The deadline additions played a huge […]
Vanderbilt Health physical therapist bound for Nationals after winning four medals at Tennessee Senior Olympics
Vanderbilt Health physical therapist Grant Schlisner, PT, DPT, Cert. MDT, won four medals in the recent Tennessee Senior Olympics, which qualifies him to compete in the national Senior Olympics, set for July 2027 in Tulsa, Oklahoma. Senior Olympians are athletes 50 years or older who compete in regional events for an opportunity to move to state events, and eventually to the Nationals. Schlisner’s medals were in the javelin, discus and softball throw (gold) and shot put (bronze). Schlisner, who is based at Vanderbilt Health One Hundred Oaks, grew up in the Chattanooga area in a family that valued physical fitness and playing sports, and he says, with considerable understatement, “The whole family is quite athletic.” Grant Schlisner (R) with brother Bret and sister Sue, all of whom won medals in the Tennessee State Senior Olympics. (photo courtesy Grant Schlisner) His brother Bret also competed in the Senior Olympics. So did his sister Sue. (His other sister Tammy did not compete, but, Schlisner said, “We’re still going to work on her.”) And their father, who now lives in South Dakota, competed in that state’s Senior Olympics in the category for athletes aged 84 to 89. Schlisner was a high school athlete in several sports, including stints as a baseball pitcher and a football quarterback. Since he was already playing positions in other sports in which he was throwing things, he was also recruited to the school’s track and field team, which is where he gained experience in the events that were his ticket to the 2027 Nationals. The medals are a reward for the hard work of training and preparation, but Schlisner said the real reward is the fitness that the medals represent. Schlisner competes in one of his medal-winning events, the shot put. (photo courtesy Grant Schlisner) “[Preparing for competition] got me working out to train for these events. I added more extensive weight training to promote injury prevention and building flexibility and strength have made me feel better overall.” He also said that, in addition to the physical rewards, he enjoys the camaraderie of the other athletes and a feeling of accomplishment. “It’s great to be able to have a goal,” he said. “If you aim low, you’ll hit it. This is aiming high. I want to bring home a medal in the Nationals.” His physical therapy patients, especially those who may be discouraged or need a little extra motivation, also benefit from his example. “I can connect with patients and say, ‘I’m 57 with previous injuries, and I’ve been doing these events, and you can get back to your ‘sport’ as well, whether that is chasing grandkids or participating in a competitive activity,’” he said. And being around the other Senior Olympians, especially in the older age groups, is motivating for him, as well. “One competitor was 90 years old,” he said. “She’s not just sitting around. That was super motivating and cool to see. I don’t want to be a lump on the couch at 90.”
Detroit Tigers Quietly Announced Justin Verlander Update During Mariners Series
On Wednesday, the Detroit Tigers continued their series with the Seattle Mariners in Washington.They lost by a score of 4-2.Detroit Tigers Quietly Announced Justin Verlander UpdateAlso on Wednesday, the Tigers announced the latest update on Justin Verlander.MLB.com wrote (on August 5): “Did some light throwing off the front of the bullpen mound on Aug. 5 […] The post Detroit Tigers Quietly Announced Justin Verlander Update During Mariners Series appeared first on HEAVY.
Cubs acquire reliever Ryan Zeferjahn from Angels for Moisés Ballesteros
The Cubs made a big move to shore up the back of their bullpen with a hard-throwing right-hander.
Health emergency preparedness nominee advances on party lines - Live Updates
Sean Kaufman had previously made controversial comments about vaccines and disparaged the CDC, throwing his nomination into question.
It's not just triple-digit velocity. Jacob Misiorowski might be throwing the best fastball in baseball history
Inside the Phone-Throwing Drama at the Troubled, Broke Democratic Party
The Democrats should be well positioned to make gains in this year’s midterms. But inside party headquarters, every week brings paranoia, worries about money and, on occasion, emotional eruptions.
Ohtani delays throwing session over knee 'regression'
Japanese batting and pitching star Shohei Ohtani postponed a planned bullpen throwing session on Saturday over what Los Angeles Dodgers manager Dave Roberts called "regression" in his left knee injury.Roberts said the 32-year-old right-handed pitcher felt uncomfortable after tossing a 30-pitch bullpen session in Philadelphia on Wednesday, but he has kept him in the Dodgers' batting lineup because hitting and running have not adversely impacted Ohtani's knee.
Trump adds condition to nuclear deal with Saudi Arabia, throwing pact into doubt
Saudi Arabia would need to normalize relations with Israel as a condition of a nuclear deal with the U.S., President Donald Trump said.
Shark’s versatile ChillPill cooling system is back to its best price
Costco’s throwing in free accessories too.
Newark gets new entertainment venue with bowling, arcades, restaurant
Lefty's Alley and Eats brings bowling, axe throwing, a game show experience and a full restaurant to its new Newark location.
Who is pitching to Bryce Harper in the Home Run Derby? Why Dodgers coach Dino Ebel is paired with Phillies star
Harper is aiming to put on a show for his home fans with a non-Phillies coach throwing pitches.
Reds Draft Seminoles P Brodie Purcell in the 12th Round
Cincinnati continues its Florida State pipeline, snagging the hard-throwing reliever after a dominant season featuring 58 strikeouts and a stingy .207 opponent batting average for the Seminoles.
Science is pushing back on the hype over cold plunges
Can an ice bath really help you lose weight, keep you mentally sharp, and speed up your post-workout recovery? Mounting research is throwing water on those claims.
Seahawks Announce Leadership Structure Changes Under New Owners
The Khosla family already throwing a few curveballs as to how the leadership structure will be in the Seattle Seahawks under their leadership.
Patriots Fans Claim Tom Brady Is Sabotaging Drake Maye
Do Tom Brady and Drake Maye have unresolved beef? New England Patriots fans certainly think so. Brady had an incredible run with the Patriots, throwing for 74,571 yards and 541 touchdowns. He's undoubtedly the best player to ever suit up for the franchise. Maye, on the other hand, was an MVP ...
Taylor Frankie Paul reportedly filming again on ‘The Secret Lives of Mormon Wives’
Embattled reality star Taylor Frankie Paul reportedly back in front of the cameras for ‘The Secret Lives of Mormon Wives,’ four months after video surfaced of her throwing a chair at her boyfriend Dakota Mortensen.
Oregon Health Authority Irks Residential Treatment Centers
In recent years, Oregon health officials, desperate to get people with severe mental illness and addiction into scarce residential treatment, have been throwing their weight around.
NEW Best In Games Warren: Metro Detroit’s Ultimate Indoor Family Entertainment Center
Located at 28300 Dequindre Road, this massive entertainment destination features everything from an enormous indoor playground and laser tag to go-karts, bowling, arcade games, and even axe throwing…
5 takeaways from Colorado’s shocker of a 2026 primary election
Voters in Colorado’s Democratic primary on Tuesday night mostly let their elected officials know that they’re fed up with the party’s Washington politicians and ready to back the most aggressive fighters they can find. At the same time, the voters who cast ballots in the Republican primary mostly embraced the GOP’s establishment, throwing the beleaguered […]
This Birmingham entertainment spot is throwing a three-day 4th of July pregame party
Urban Supply and the Birmingham Barons host family-friendly Fourth of July weekend festivities, with live music, games, food and fireworks.
Brewers Continue Testing Jacob Misiorowski's Limits
After touching triple digits with a record-shattering 105.5 mph heater, the Milwaukee Brewers flamethrowing ace escaped a bases-loaded jam to prove his elite resilience and Cy Young caliber endurance.
Walker Buehler delivers statement win for the Padres over Dodgers
The Sporting Tribune's Fernando Ramirez writes about Walker Buehler throwing a solid game against his former team.
Pirates Pitching Coach Confident Team Will Improve On The Mound
Bill Murphy believes Pittsburgh has been throwing the ball well.
Trump co-endorses Alan Wilson in SC governor’s race, dealing major blow to Pamela Evette
President Donald Trump is throwing his support behind both Alan Wilson and Pamela Evette in the June 23 runoff for governor. The news represents a major blow to Evette, whose campaign was built on her ties to Trump.
NFL sees NIL chaos — and smells a threat to its empire
The NFL’s worst nightmare? Players with power before they arrive. That's why the league is throwing support behind Congressional action.
3 takeaways from our new poll: From the Politics Desk
Plus, Trump keeps throwing wrenches in the GOP’s agenda.
Forty Fort business hits the mark: The Hatchet Factory earns $10,000 award
Denise Ogurkis’ ax-throwing gathering spot earns recognition from Citizens as one of the bank’s 20 recipients, from nine states, of its 2026 Small Business Community Champion Award.
Forty Fort business hits the mark: The Hatchet Factory earns $10,000 award
Denise Ogurkis’ ax-throwing gathering spot earns recognition from Citizens as one of the bank’s 20 recipients, from nine states, of its 2026 Small Business Community Champion Award.
Snake Bytes 6/14
Team News D-backs squander another one of Soroka’s walk-free quality starts “When you feel like the hitter might not know what’s coming, I feel a little bit more comfortable throwing balls completely over the plate,” Soroka said. “Last year, I think I ran into struggles, because I didn’t have those extra pitches. And second, third […]
I spent $2,500 on throwing birthday party at a French castle: 1 regret
A woman who is a fantasy fan threw her 30th birthday at a French chateau, hosting 21 friends and spending around $2,500 on the celebration.
Texas Tech had the chance to become a great success story, but chose to be a victim instead
By throwing all its weight behind Brendan Sorsby, Texas Tech drastically altered its public perception
Thomas Theatre adds entertainment center to Quinnesec location
President and Owner Tom Andes says the new addition, which has a restaurant, bar, digital arcade, axe throwing and a party room, appeals to everybody.
Myles Garrett delivers in his first L.A. appearance
As Dolphins quarterback Malik Willis learned last month, throwing out the first pitch at a Major League Baseball game is usually a no-win proposition.
Need to recharge your brain? Stop swiping and turn a page
People are throwing parties in an effort to read more for fun. The meet-ups are more than a social activity or a way to recharge — they can help improve brain health.