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911: Massive blaze destroys woodworking business in rural Blair County
Firefighters in Blair County are providing new details on Wednesday night's response to the massive commercial building fire in the Roaring Spring area.Emergenc
Before the Roar: Previewing Lions vs Packers
Detroit Lions vs. Green Bay Packers Week 7 preview. Breaking down the matchup and biggest storylines.
Why Katseye's Victoria's Secret Fashion Show performance is causing uproar
Katseye delivered the tunes at the Victoria's Secret Fashion Show, but their performance is striking a sour note off the runway.
Ohio governor’s race in uproar over video featuring Democrat’s estranged mother
Amy Acton was removed from her mother’s home when she was 12 after her stepfather was indicted on a charge of raping her.
One of three Jensen Huang-signed RTX Spark laptops won at NVIDIA launch event is already listed for $17,150
An ASUS ProArt RTX Spark laptop bearing Jensen Huang's signature is reportedly being offered for $17,150. The asking price exceeds regular Turkish retail pricing by more than two times.
Roaring exports lift China’s economic growth; violent French protests put pressure on euro and bonds
World’s second-largest economy on track to meet Beijing’s 2026 growth target, though consumer spending lags behind factory output
BEFORE THE ROAR: LSU returns home to welcome Mississippi State
LSU needs to get back in the win column to hold on to CFP hopes.
ASUS ProArt P16 "RTX Spark" Laptop Review - NVIDIA's First Full PC Platform Brings Powerful AI & Gaming Capabilities
NVIDIA RTX Spark launches with ASUS ProArt P16, featuring N1X SoC, 6144 CUDA cores, & up to 128 GB memory for impressive gaming and AI.
Redditor runs FurMark on NVIDIA RTX Spark laptop at a store, nearly gets kicked out
A Redditor installed FurMark on an ASUS ProArt P16 RTX Spark display laptop in France. The 1080p benchmark ran before the user was nearly kicked out of the store.
L.A.’s dynasty is (probably) done, plus the NFL’s uncomfortable moment
The Pulse Newsletter 📣 | This is The Athletic’s daily sports newsletter. Sign up here to receive The Pulse directly in your inbox. Good morning! Work an 11-pitch at-bat today. Coming up: 🍻 Milwaukee roars, again 🖊️ Will anyone sign Hill? 🤒 Warriors star clarifies health Yesterday, we discussed how the Dodgers’ possible demise would impact the sport’s future on a decidedly macro level. Today, after their 6-2 loss in Game 3 of the NLCS last night to the Brewers, I want to get granular: We should start with the winners, who deserve plenty of shine. Milwaukee is...
‘Narnia’ roars to life in rock-infused trailer for Greta Gerwig’s ‘The Magician’s Nephew’
Greta Gerwig brings the origins of ‘Narnia’ to life with a roar from Aslan and a riff from Led Zeppelin in the first trailer for ‘Narnia: The Magician’s Nephew.’
AFTER THE ROAR: LSU drops another road SEC contest
Another late-game heartbreaker full of missed opportunities.
The science, instinct and hard work behind Roosters’ success
Enter your email address to get each Tribune edition sent to your inbox Subscribe There’s a fair bit of unseen work that goes into winning an NRL premiership, dating back many months - just ask Simon Jones. The Sydney Roosters Head of Performance, who hails from Southland, has been in the thick of it. He played a lead role in guiding the 2026 champions through a marathon campaign that ended with a grand final win over the Newcastle Knights. The Roosters had to navigate the lengthy round-robin competition, including the pre-season, before playing through all four weeks of the finals series. It was a demanding stretch that tested the players and the staff responsible for keeping them on the field. “It is a hell of a beast, mate, to be honest,” Jones told The Roar Podcast. “There’s such a great group of staff there that know what they’re doing, and the boys are pretty professional.” Jones believed the Roosters managed the physical demands well, pointing to the health of the squad throughout the campaign and the decision to rest a significant portion of the playing group in the final round of the regular season. That call, made by head coach Trent Robinson and his coaching staff, proved valuable as the Roosters entered the finals with some energy in reserve. “We did finish the season physically where we needed to be, and we’d sort of had a pretty healthy squad all year,” Jones said. “To the team that do that, mate, mission accomplished, really.” It is the sort of work that often goes unnoticed when the spotlight falls on the players scoring tries and making match-winning plays, but Jones knows the cumulative effect of those decisions can be significant over a long season. After a win over Penrith had helped establish them as premiership favourites, losses to the Wests Tigers and Dolphins were followed by a defeat to the Panthers in the opening week of the finals. Rather than panic, the club refocused to position itself to challenge for the title. “The Tigers’ performance was probably the only one where you’re really quite disappointed because it’s hard to get to the top of the competition,” Jones told The Roar Podcast. “We had proof that we could; we knew what we needed to do. We just had to get back to that.” For Jones, the answer was not necessarily a radical change to the programme. It was about executing the basics consistently, both on the field and in preparation. “We just do the basics better than anybody else,” he said. “Whether that is actually the way you play the game or how you’re preparing, it’s just be really consistent, do the basics really, really well.” Like many professional sports teams, the Roosters are entrenched in sports science and performance data. The club has access to a range of information, including players’ sleep, GPS metrics and neuromuscular scores, helping staff assess how individuals are coping with training and competition. “We are very science-backed, and some people would say data-driven, but it’s people first,” he said. “The reason you collect all this data is to try and be the best for that person.” Jones said the club was also prepared to reconsider testing methods if they were not generating useful discussions or helping staff make better decisions. In an environment where technology is continually evolving, he believes experience and gut instinct remain important. “The data is no good unless you have conversations,” he said. “When you strip it right back, mate, trust the gut still and obviously, you know, just doing the basics really, really well.” The return of halfback Sam Walker provided a further example of the importance of individual determination and the work of the club’s medical team. Walker underwent ankle surgery late in the regular season, with his premiership campaign appearing in doubt. However, he was determined to return for the preliminary final. Jones said Walker was back at the training ground three days after surgery, walking freely enough to surprise those around him. While the surgeon’s work was crucial, Jones credited the halfback’s mindset as a major factor in the remarkable turnaround. “He was quite clear with Robbo after he got the surgery that he was going to make it back for the prelim finals,” Jones said. The Roosters’ performance programme also sits within a wider club culture that Jones believes is central to their success. Each season, players develop their own team mantra through a lengthy process facilitated by Robinson. It provides principles that the squad can connect to its actions on the field. Rather than simply carrying over the previous year’s wording after a successful campaign, the club repeats the process because the players’ ownership of it is what gives it meaning. “When it’s led, player-owned and player-led, mate, it’s really powerful,” Jones said. Get more from Logan Savory in the Substack app Available for iOS and Android Get the app Jones joined the Roosters in 2024 and said the environment had evolved as experienced players departed and younger members of the squad took on greater responsibility. Maintaining continuity in the club’s culture and preparation had helped the group navigate those changes. The premiership was a significant achievement for Jones, who acknowledged how difficult it was to win the NRL’s ultimate prize. However, he is already looking at how the performance programme can improve. “There’s still things within my role and things that I’d like to help improve at the club,” he said. For Jones and his team, the challenge now is to review the season, refine their systems and prepare for another campaign. The celebrations may have followed a memorable title win, but the work behind the scenes never really stops. The Southland Tribune is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
ASUS Markets Its RTX Spark-Powered ProArt GR1X Mini-PCs As Efficient Gaming Powerhouses, Can Run 1440p Titles At 100FPS With Just A 140W Power Limit
ASUS markets its RTX Spark-powered ProArt GR1X mini-PCs as efficient gaming powerhouses, capable of running 1440p titles at 100FPS with just a 140W power limit
Arts and Entertainment lineup for Oct. 9-19
Note: for a complete list of calendar events from around Garfield County and the Roaring Fork Valley, go to http://www.postindependent.com/entertainment/community-calendar/. Embervine: A Night of ’70s, ’80s and ’90s Hits What: Bring your friends and your...
Zorua Community Day: Your Go-To PvE Guide
Zorua Community Day features Zoroark with Sucker Punch as its Fast Attack. Learn its PvE outlook and the affect of its new attack.
The science behind the Superdome’s roar during the Domecoming game
Superdome Decibels Debunked: How loud was the Dome when Steve Gleason blocked the punt?
BEFORE THE ROAR: LSU welcomes in-state foe McNeese
LSU opens October with an in-state battle.
'Godzilla Minus Zero' review: The epic monster melodrama fans have been roaring for
Now with R-rated mayhem!
Penguins Re-Assign McGroarty; More News Possible
Perhaps it will be a harbinger of good news for the Pittsburgh Penguins but Thursday, the team re-assigned young forward […]
Lions vs. Panthers: ‘Before the Roar’ preview podcast
Detroit Lions vs. Carolina Panthers Week 4 preview: ‘Before the Roar’ breaks down the matchup and biggest storylines.
Chris Koza album release concert Oct. 24
Lanesboro Arts is thrilled to celebrate the release of Chris Koza’s latest album, “Millsmoke on the Skyline,” with a concert at the St. Mane Theatre at 7 p.m. on October 24. Chris Koza is a composer and performer based in Denver and Minneapolis. In his writing, Koza both honors and builds on the vast genre of Americana music. For every song that sounds like it could be strummed from a boxcar clacking slowly across a grassy midwestern plain, there’s a tune sailing from a city rooftop, echoing across a valley of streets and traffic, or a melody twisting and shimmering like a dim frequency deep into the starry night.Both as a solo artist and with his band Rogue Valley, Koza has supported and shared the stage with artists such as Brandi Carlile, Gordon Lightfoot, Ingrid Michaelson, The Jayhawks, Neko Case, Kathleen Edwards, Dan Wilson, and many more. His music regularly appears on ABC’s “General Hospital,” “60 Minutes,” and “Good Morning America.” Koza’s song, “Be Wild,” was also featured in a state of Minnesota tourism campaign.#placement_932485_0_i{width:100%;max-width:550px;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid932485 = window.pid932485 || rnd;var plc932485 = window.plc932485 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=932485;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid932485+';place='+(plc932485++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');Koza’s latest offering, “Millsmoke on the Skyline,” grants the newfound outsider perspective of the rich life and golden fleeting days throughout the rural Midwest. Weaving melody and lyrics into vignettes and narratives set in places where love is powerful, dreams are vast, and life is beautiful.The St. Mane Theatre box office will open at 6 p.m. on the day of the concert. Tickets will be sold in person at the door or can be purchased online at lanesboroarts.org. Seating at the St. Mane theatre is first come, first served. Tickets are on sale now for $25 for general admission or $22 for Lanesboro Arts members.The 2026 performing arts season at Lanesboro Arts is made possible by our season sponsor, Poet Refinery, as well as our concert level sponsors, High Court Pub, Krage Insurance Agency & Preble Farmers Mutual, Stone Mill Clothing & Gifts, E2 Boutique/Amish Experience, and The Cottage House Inn, and community sponsors, VIS Plumbing, Granny’s Liquor, Kingsley Mercantile, Batstone CPA, Clara’s Eatery, IGA, Niagara Cave, and Huntington Electric. This event is made possible by the voters of Minnesota through a Minnesota State Arts Board grant, thanks to a legislative appropriation from the Arts and Cultural Heritage Fund. #placement_932489_0_i{width:100%;max-width:550px;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid932489 = window.pid932489 || rnd;var plc932489 = window.plc932489 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=932489;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid932489+';place='+(plc932489++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');
Basalt Chamber announces 2026 Roaring Fork Valley Business Summit
The Basalt Chamber of Commerce has announced that the 2026 Roaring Fork Valley Business Summit will take place on Thursday, Oct. 8, from 8 to 11:30 a.m. at the Rocky Mountain Institute Innovation Center. The...
Cats want to talk to us. Scientists are trying to decipher the meow
LOS ANGELES — For decades scientists and researchers have been vexed by a sound emanating from cats. Not a call of the wild, a roar or a hiss. No, multiple
49th Tawes Crab and Clam Bake serves up politics, seafood despite roaring winds
CRISFIELD, Md. — Howling winds and heavy rain could not halt one of Maryland’s most enduring political and culinary traditions on Wednesday.
Pens Points: Penguins drop second preseason game
Here are your Pens Points for this Wednesday morning… The Pittsburgh Penguins fell 7-4 to the Detroit Red Wings in Pittsburgh’s second preseason game on Tuesday at PPG Paints Arena. Nick Robertson scored in his Penguins debut, while Kaeden Korczak and Rutger McGroarty also found the net in the loss. [Recap] Forward Nick Robertson is […]
Over McClure and into the blues
Annual Telluride festival electrifies Roaring Fork Valley music lovers
Whether you like it or not, celebrities have an impact on politics
The global groundswell of support for Macklemore’s pro-Palestinian advocacy serves to remind us that maybe celebrity activism really is that deep after all, writes Cheek’s Varsha Yajman. Subscribe In the last week, publications, podcasts, and influencers that have either rarely or never spoken about Israel’s genocide in Palestine have flooded my social feed. And it was all because singer Ed Sheeran and his team dropped Macklemore as his opener for saying “Free Palestine” on stage. Millions raised, millions speaking up in support of Palestine - all of this confirming my view that, whether I like it or not, celebrities do have an impact on political outcomes. And this is interesting when much of the time celebrity activism can induce an eye roll - I love to see Charli XCX pointing out a Palestinian flag in the crowd, but it’s hardly the bold symbol of allyship that some fans would make it out to be. But there’s a line between healthy scepticism and outright dismissal - and I’d argue that the latter lets the rich and powerful off far too easily. For instance, actress Jennifer Lawrence, once outspoken about her political views, last year told The Times she no longer believes celebrities have a role to play: “Celebrities do not make a difference whatsoever on who people vote for. So then what am I doing? I’m just sharing my opinion on something that’s going to add fuel to a fire that’s ripping the country apart.” While it’s a narrative she might find comfort in, it simply is not true. Grassroots movements often garner worldwide attention when celebrities and other high-profile spokespeople bring a mainstream platform to their causes. And this frustrates me. We have had three years of a live-streamed genocide. Macklemore himself has been calling for a Free Palestine long before he booked the Sheeran concert. Yet it’s the high-profile fallout of the last week that finally seems to have made saying “Free Palestine” socially acceptable in the mainstream. It feels like the collective mood has shifted, where calling out censorship is now the obvious response - not just the business of ‘radical’ activists. To recap, Sheeran’s decision followed an ultimatum from billionaire Robert Kraft, owner of Gillette Stadium, one of the venues Sheeran was scheduled to perform at: either drop Macklemore as your opener after only two of the eight scheduled shows, or you do not play at any stadiums. Sheeran’s disappointing decision to stand on the side of billionaire-led censorship has ultimately seen a surge in support for Free Palestine. It began when all his openers and his backing band pulled out of Sheeran’s tour, in solidarity with Macklemore and with the Palestinian cause. It was met with an uproar of support from those who had never or barely touched politics before: influencers lip-syncing to Macklemore’s music, singers like Jack Antonoff singing “Free Palestine,” and publications and podcasts standing with Macklemore. And finally, we saw material support: Macklemore donated $1 million in profits from his two nights opening for Sheeran’s tour to several Palestinian aid groups and called for Sheeran and Kraft to match it, which they have since promised to do. We’ve also seen children’s entertainer Ms Rachel follow suit with a $1 million donation to Palestinian aid, and publication PopBase has donated $10,000. Anera, a humanitarian aid group working in Palestine, Lebanon, and Jordan, said donations since Macklemore’s announcement were more than triple this month’s daily average. The group’s Instagram page has also gained 8,000 followers. Macklemore far from the first celebrity to speak and participate in politics in the Western World. In 1924, singer Al Jolson supported Republican candidate Warren G. Harding for president, and decades later, celebrities such as Harry Belafonte, Lena Horne, and Aretha Franklin voiced their public support for the Civil Rights movement. More recently, in the lead-up to the 2024 US election, ‘The Daily Show with Trevor Noah partnered with the organisation Power the Polls to recruit poll workers to address shortages- a problem disproportionately affecting voters of colour. The campaign saw 170,000 new sign-ups - 35,000 of which came directly through the TV show’s link - resulting in the recruitment of 713,000 total poll workers that year, an almost three-fold increase on the organisation’s goal. Alongside recruiting workers, celebrities in the US (where voting in elections is not compulsory) have made a huge difference by calling for people to register to vote. Taylor Swift’s endorsement of Kamala Harris in 2024 saw over 400,000 visitors on the voter registration site within 24 hours of her Instagram post. In 2023, Swift had urged her fans to register, resulting in 35,000 new voter registrations. Similarly, Ariana Grande promoted voter registration in 2019 by setting up booths at concerts on the American leg of her tour, resulting in over 33,000 voters registering. And the same thing is happening closer to home. This year, musician Jack River successfully called for government action to ensure creatives in Australia do not have their work scraped by generative AI companies. Celebrity as the mediator between the punter and the politician Celebrity activism isn’t just a feel-good news story - research tells us it actually makes a difference. By directing attention to issues affecting the average person, like voting inaccessibility or a lack of action on a genocide, researchers Alfred Archer and Amanda Cawston state that “celebrities can play a useful bridging role between political elites and the people they represent”. Alternatively, in a world where talking about politics is “not cool,” or where people lack exposure or knowledge to engage with politics, celebrities can act as an educational resource or an entry point into the political world - when they speak up about an issue, their audience gets exposed to it. Olivia Rodrigo’s Daisy Chain Fields festival is a perfect example. Rodrigo partnered with twelve organisations focused on women’s issues, such as reproductive rights. These organisations had stalls at the festival for people to meet them and were also featured heavily on social media, giving their issues global attention and raising $20 million for the organisations. We have also seen celebrities at award shows such as the Emmys wearing F*CK ICE pins, referring to the U.S. Immigration and Customs Enforcement’s treatment and detainment of people - generally people of colour. When celebrities speak up about political issues in public forums, they put the issue at the forefront of mainstream media, rally their supporters, and make it clear that, however much they disagree, the government cannot simply ignore it. Our over-reliance on celebrities versus our politicians As much as I love seeing my favourite celebrity use their platform for a good cause, there is an important question to ask: not whether celebrity activism is good or bad, but whether we should have to rely on celebrities. And the answer would, in an ideal world, be no. In an ideal world, or merely a just world, action on Palestine would’ve happened decades ago, climate change would be taken seriously, and most importantly, people would understand their democratic rights. However, that is not our reality. Only around 28 per cent of Australian Year 10 students reach proficiency in civics and citizenship. In the US, almost two-thirds of people under 30 say high school civics education didn’t prepare them to understand voting deadlines, how to research candidates, or how to vote by mail. When civics education is weak, our trust in these institutions and our understanding of change-making processes also decline. This is where celebrity steps in and becomes our main source of reliance. As Mary R. Connelly notes in _The Tartan, “_Celebrities will always be involved in campaigns in one form or another, but their presence is not what causes people to vote blindly. The lack of political engagement and literacy is what allows celebrities to wield their influence on the political sphere so impactfully.” About the author Varsha Yajman is the Digital Content Producer at Cheek Media. She is a youth advocate and lawyer with a background in climate litigation and is passionate about looking at the intersection between race, climate justice, and mental health. Thanks for reading Cheek Media Co. ! This post is public so feel free to share it. Share
Broncos Rally to Beat Jaguars in Wild Comeback
The Denver Broncos came roaring back Sunday afternoon, overcoming a 13-3 deficit to defeat the Jacksonville Jaguars 20-13 at Empower Field at Mile High. After a disappointing season-opening loss to the Kansas City Chiefs, Denver needed a response. It got exactly that, scoring 17 unanswered points in the second half to hand Jacksonville its first…
Which side Is Ed Sheeran on?
He addressed the Kraft-Macklemore uproar at a show last night—but some topics have no safe middle ground.
A 66-million-year-old tooth reveals T. rex was nearly as warm as a human
Chemical clues preserved inside fossilized T. rex teeth reveal that the dinosaur maintained a body temperature of about 97 degrees Fahrenheit, almost identical to humans. The finding provides direct evidence that the giant predator was warm-blooded, helping explain how it stayed active and survived in chilly environments as far north as Alaska.
Roar & Explore vendor show highlights local businesses at Hovatter’s Wildlife Zoo
Hovatter’s Wildlife Zoo hosted its Roar & Explore vendor show, bringing together local businesses and community members for a day of shopping, family fun and wildlife.
Munich’s Oktoberfest roars to life as the mayor taps the first keg
Munich's Oktoberfest has kicked off with the city's mayor tapping the first beer keg, marking the start of the 191st edition of the festival.
Munich’s Oktoberfest roars to life as the mayor taps the first keg
Munich's Oktoberfest has kicked off with the city's mayor tapping the first beer keg, marking the start of the 191st edition of the festival | KNX News 1070 AM
Munich’s Oktoberfest roars to life as the mayor taps the first keg
Munich's Oktoberfest has kicked off with the city's mayor tapping the first beer keg, marking the start of the 191st edition of the festival | NewsRadio 1080 KRLD
Munich’s Oktoberfest roars to life as the mayor taps the first keg
Munich's Oktoberfest has kicked off with the city's mayor tapping the first beer keg, marking the start of the 191st edition of the festival | WBBM Newsradio 780 AM & 105.9 FM
Encompass Health celebrates Rehab Awareness Week with Roaring 20s party
Patients at Encompass Health in Panama City traded therapy sessions for a Roaring 20s-themed party this week as part of National Rehabilitation Awareness Week.
Lena Dunham welcomes her first baby via surrogacy
(CNN) — Actress and writer Lena Dunham and her husband Luis Felber have welcomed a baby daughter via surrogate.Writing in an op-ed published by Vogue on Wednesday, Dunham, 40, who is best known as the creator of hit TV series “Girls,” revealed that the couple’s first child had arrived 13 days late, before describing the moment of her birth.“I was so focused on our surrogate — in awe at her concentration, her period of quiet followed by what sounded like a roar — I forgot to look down until I heard our baby’s cry,” she wrote.“I saw her face, gasping just as she did. Her eyes, wide and unfocused, taking in the light and shadow, blinking rapidly.”Dunham said she was “bashful and dizzy with joy.”In 2018, Dunham revealed that she’d had a hysterectomy in an attempt to end the pain caused by endometriosis.Endometriosis is a common and often painful condition that happens when tissue similar to the lining of the uterus grows outside the uterus itself. It’s estimated to affect more than 11% of women between the ages of 15 and 44 across the United States.The surgery removed her cervix and uterus, meaning that she was unable to conceive naturally.On meeting her surrogate, Dunham wrote in the Vogue piece: “While I’ve been known to make friends quickly — airport terminals, veterinary offices — this was the quickest leap from first coffee to gynecological procedure I’d ever done.”Dunham said in the months before the embryo transfer date, as she “got to know our surrogate and to trust her,” she thought she would feel “jealousy” towards her, but she did not.“Instead, I felt a different kind of jealousy — toward said baby, for the chance to be tucked into someone who radiated such safety. I could just tell she knew how to steer an SUV in the snow,” Dunham added.The pregnancy came after “12 years circling the fertility drain,” Dunham wrote, and revealed how she dealt with the nerves of the intervening months.“Powerless and unable to feel the physical changes that signal a growing fetus, I horrified friends and family who adhere to the Jewish superstition prohibiting anticipatory purchases, and I started shopping,” said Dunham, before recounting her journey into the world of baby fashion.“I was looking for garments that allowed her personality to develop and express itself rather than announcing an identity she didn’t yet have,” she said.“She would be a person that we helped to dress, who made an impression on the world based on our choices, until she was old enough to do it herself.”The-CNN-Wire™ & © 2026 Cable News Network, Inc., a Warner Bros. Discovery Company. All rights reserved.THE-CNN-WIRE (TM) & © 2026 CABLE NEWS NETWORK, INC., A TIME WARNER COMPANY. ALL RIGHTS RESERVED.
17 Roaring Fork organizations receive more than $50,000 in health grants
The Roaring Fork Community Health Fund (RFVCHF) awarded over $50,000 to 17 organizations in the Roaring Fork Valley, according to a Western Colorado Community Foundation news release. The scope of the organizations covers a wide...
Junior Roary Savagely Trolls Saints Fans at Ford Field
Junior Roary wasted little time developing an attitude, hilariously trolling Saints fans during the Lions’ wild Week 1 victory.
Before the Roar: Previewing Week 2 against Buffalo
Detroit Lions vs. Buffalo Bills Week 2 preview: ‘Before the Roar’ breaks down the matchup and biggest storylines.
Milan Seeking Ways to Properly Ignite Their Attack
Gonçalo Ramos isn’t off to a roaring start in his Serie A career, as he has scored one goal in four games. While he had been wasteful before eventually hitting the net in the previous two rounds, h...
ASU students learn about science, sailing and self-discovery
Keon Davis gripped the side of the 208-foot research vessel as 30-foot waves battered the boat.The roar of the 20 mph winds was so loud that anyone trying to speak to him would be impossible to hear.It was one of those experiences that tethers the mind to the moment — demanding absolute focus on the task at hand.As the ship continued toward the African coast, Davis considered retreating to the cabin.But he had a job to do.
Julianne Moore, Paul Giamatti admit past costars have ‘gone nuts’ and ‘off the deep end’ on movie sets
The pair premiered Jesse Eisenberg’s new movie “The Debut” — about an actor’s wild creative process — to uproarious applause at TIFF.
🏈 Y! Sports AM: Points party
The NFL came roaring back on Sunday, with offenses leading the charge.
😳 Uproar in the Manchester derby! Haaland winner should've been ruled out
Frustration ran deep at Manchester United after the derby defeat. Not only because they had lost the match against Manchester City 0-1, but also because Erling Haaland’s goal (60') should never have...
Colin McMahon: Amid political roar, Army keeps its head down
The Army must work harder than ever at staying out of politics and focusing on the task at hand.
Bone Health Without the Hype
I am at the Australasian Menopause Society meeting and we had a fantastic lecture on Bone Health on Day 2, called, “Everything you need to know about bones - except the boring bits!” Spoiler alert, there were no boring bits. The lecture was given by Dr. Amanda Beech, who is a senior staff specialist in Obstetric Medicine and Endocrinology at the Royal Hospital for Women, where she is director of the Bone Density Unit. I want to summarize my top 10 take-aways for you. Share Osteoporosis is a disease of low bone mass, disruption of bone microarchitecture, and fragility of the skeleton. It is a silent disease…until someone develops a fracture. The diagnosis of osteoporosis is based on either fragility/minimal trauma fractures or a T-score of less than -2.5 on a DXA (Dual-Energy X-ray Absorptiometry) or bone scan. It is important to recognize that about 50% of minimal trauma fractures occur when women have low bone mass (often referred to as osteopenia), but not osteoporosis. This tells us that bone strength is more complicated than a number on a DXA report. I am going to add a little here that wasn’t in the talk (one can only include so much in 25 minutes), as many women might read the above paragraph and think, “Shouldn’t we be treating everyone with low bone mass if this is when 50% of the fractures occur?” Many fractures happen for women with low bone mass because there are so many women with low bone mass –it is a statement about the population on a whole, not about the fracture risk of low bone mass. For you as an individual, bone density is only one component of fracture risk and many women with lower bone mass will not have a significantly elevated fracture risk. This is why individualized risk assessment matters. Subscribe We build bone in our teens and twenties, and by the time we are about thirty we have reached peak bone mass. This is why, when we discuss risk factors for osteoporosis, it is important to consider factors that might have affected us in our teens and twenties when we were actively building bone, such as nutritional restriction/energy imbalance. It is important to ask women about a history of eating disorders, and for those with such a history, getting a bone scan in perimenopause or at age 50 is likely warranted. (This image below isn’t from the talk, but is similar to one that was). Bone mass is relatively stable until about two years before the final menstrual period, and perimenopause marks a time of rapid bone loss for women. Using urinary markers of bone loss we know that the time of significantly accelerated bone loss starts about 1 year before the final period and ends about 2 years after the final period. The Study of Women’s Health Across the Nation (SWAN) shows that over the menopause transition women lose an average of 10.6% of the bone at their lumbar spine and 9.1% at the femoral neck While this wasn’t covered in the lecture, I want to add that the rapid bone loss during perimenopause is clearly related to more than estradiol, because during this time estradiol levels can be erratic and not uniformly low. Bone loss during perimenopause is likely a multi-hormone event. For example, rising FSH (follicle stimulating hormone) tracks with bone loss better than estradiol, and there is evidence that FSH may act directly on bone. While decreased estrogen matters, there is clearly more going on. FSH and bone is an active area of research. Subscribe Screening for osteoporosis was recommended fairly broadly before age 65, and was taken from the “Practitioner’s Toolkit for Managing Menopause,” from Monash University. Here is a screenshot from the toolkit that was used as a slide: I am going to add a little bit more about body weight here for clarification. Low body mass (typically 152.1 lb): 0 points (risk neutral) 60–69 kg (132.3–152.1 lb): 3 points (adds some risk)
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
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We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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