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Victoria Li's senior project: Exploring how AI processes information
Knowing how chatbots turn input into output will help with reliability and trust in AI agents
Watching Ukraine, NATO artillery crews learn to work drones in Arctic
NATO commanders told Business Insider that drones are useful but could never fully replace the reliability of old-fashioned artillery.
Researchers gather at Cornell Tech to explore AI for molecular science
Researchers from around the world gathered at Cornell Tech for a workshop exploring how physics-aware artificial intelligence can accelerate the discovery of molecules and materials while improving the reliability of machine learning models.
I-81 widening aims to improve freight reliability
Virginia has started a $219 million project to widen I-81 through Harrisonburg and Rockingham counties, improving freight reliability and traffic flow.
Sony’s New Blu-ray & DVD Player Upscales DVDs to Near-HD Quality - Bring Your Old DVDs To Life Again
In a time when streaming services continue to raise prices, fragment content libraries, remove content, and push intrusive ads, many households are rediscovering the reliability and ownership of physical DVDs and Blu-rays. Sony has answered this shift with the release of its latest affordable disc player: the Sony BDP-S1700U. Priced at just $114.99, this sleek […]
Redoing Daubert: Are judges letting bad science back into the court room?
Daubert was meant to keep unreliable science out of the courtroom by making judges gatekeepers who ensure the reliability and relevance of expert testimony and the underlying research. A recent Second Circuit decision raises a harder question: how deeply may a judge examine the science when evaluating an expert’s methodology before determining the scientific dispute itself? The answer could reshape how courts translate epidemiological evidence into legal proof.
A commitment to reliability fuels Trash Rangers’ rapid business growth
Trash Rangers began in 2018 when Jake Poche identified a need for more reliable, customer-focused waste services in Ascension Parish, Ascension Business Report reports. Built on the promise of showing up when it says it will, the locally owned company has grown from a residential garbage service into a regional waste provider serving communities throughout […]
Using Claude? Thank Elon Musk
Anthropic now relies on a huge SpaceX data center for AI compute, tying Claude's rapid growth and reliability to Elon Musk.
The 4 PSI Rule For Tires: What Is It, And Is It Reliable?
The 4 PSI rule compares cold and hot tire pressures to estimate proper inflation, but its reliability depends on driving conditions and tire type.
New framework aims to improve reliability of tear-based health sensors
Dr. Yangzhi Zhu of the Terasaki Institute for Biomedical Innovation (TIBI), with collaborators at UC San Diego and USC, published a Nature Sensors perspective on what it will take to turn tear-based wearable sensors into reliable, long-term health-tracking tools.
When junk science decides guilt in the South
States should adopt the federal standard for expert testimony and make reliability a threshold requirement, not a question left for jurors to sort out after unreliable science has been heard.
Seoul National University of Science and Technology Researchers Develop a Reliable AI System for SSD Failure Prediction
/PRNewswire/ -- Solid-state drives (SSDs), which store data in computers and servers, are critical to data center reliability. SSD failures can cause service...
Mercedes faces Ferrari threat amid reliability woes, says David Coulthard
David Coulthard believes Mercedes will be concerned by Ferrari’s recent constructors’ championship gains
New study casts doubt on reliability of mental health diagnosis interviews
Diagnostic interviews seen as ‘gold standard’ vary in reliability from condition to condition, study says
Ohio University Chemistry Professor Eric Masson develops open-source software to advance chemical research
New computational platform, Equilibrist, simplifies complex chemical data analysis and improves the reliability and reproducibility of scientific results.
Series of protests held across New York against Hochul's nuclear agenda
The event comes on the heels of the governor’s kickoff of the Nuclear Reliability Backbone process earlier this month.
New NASA data shows why scientists struggle to model Western rivers
New satellite observations show that some global river models struggle to account for dams, reservoirs and other human influences, raising questions about their reliability for water planning.
Rangers Could Trade Eovaldi to Create Payroll Flexibility
Chris Young must weigh Nathan Eovaldi’s reliability against a looming $25 million salary as the Texas Rangers prioritize financial agility and roster youth after a tough year.
Anthropic’s Claude can now control your Mac, escalating the fight to build AI agents that actually do work
Anthropic has given Claude the ability to control a Mac, marking a major step in the AI agent race and raising new questions about automation, reliability, and security.
OpenAI claims we've entered the AGI era — has GPT-6 Astra really demonstrated general intelligence?
OpenAI says its newly launched GPT-6 Astra model brings humanity to the threshold of AGI, but external evaluators argue that inflated lab metrics and opaque testing obscure its true reliability.
AI science evaluation tools should be scrutinized through ‘critically engaged pragmatism’
Creators of AI tools need to be transparent about how they are designed, trained, and benchmarked to facilitate assessments of their purpose-specific reliability, liability to different kinds of er…
To assess AI in health care, study the human-machine team
AI health care tools appear to have a reliability problem, and experts suggest a new way of evaluating them.
Scientists in Chicago remotely controlled a wireless brain implant in South Korea over the internet
"The biggest challenge is demonstrating long-term safety and reliability in the human brain."
Companies Expand AI Health Offerings, Even as Accuracy Questions Remain — The Monitor
Five technology companies have launched dedicated consumer-facing AI health tools so far in 2026, reflecting though questions about AI’s reliability remain. And a decades-old WHO classification has been misrepresented online to suggest that hormonal birth control pills were recently found to cause cancer.
The T’s unreliability is outrageous. Why do we put up with it?
The quality of MBTA service has real bearing on Massachusetts’ competitiveness and its ability to retain workers.
Vendor Notebook: Health AI bolstered by collective approaches to quality
New collaborations aim to ensure rural healthcare organizations have access to artificial intelligence to address rate-limiting factors in care delivery while vendors seek advancements in reliability and AI controls.
GitHub's AI surge pushes Microsoft into Amazon's arms
Microsoft is adding AWS capacity to GitHub after AI-driven growth strained infrastructure and triggered a series of reliability issues.
“Cognitive Spoofing”: How AI Fakes Expertise, And Why It’s A Huge Problem In Healthcare
AI systems have to be pressure-tested in real-world clinical settings to ensure correct reasoning, accuracy and reliability.
Andrea Stella: F1 2026 reliability fears 'vanished' in Barcelona shakedown
McLaren team principal Andrea Stella says early reliability fears around F1's 2026 regulations quickly eased during the Barcelona shakedown
5 Lexus Models Commonly Said To Be Nearly Indestructible
The Lexus ES 350, RX 350, LS 430, GX 470, and IS 350 stand out for reliability, with reported average lifespans ranging from 142,000 to 228,000 miles.
Only About Half Of Social Science Results Can Be Replicated, Finds New Study
A multi-year study of the reliability of published social & behavioral science research has found that only about half of published results are replicated by new studies.
Chris Young to address Rangers' 'health, reliability' in offseason
The Rangers dealt with a slew of injuries to key players in 2026 and changes are coming in that department for 2027.
How The Story Is Shifting For Alliance Entertainment Holding (AENT) After Analyst Target Cuts
Analysts have trimmed their price targets on Alliance Entertainment Holding by $2, while the stated fair value estimate of $9.0 remains effectively unchanged. This shift is being framed as a recalibration of risk and earnings reliability, with bulls viewing it as fine tuning and bears treating it as a signal to be more cautious. As you read on, you will see how to interpret these updates and track the evolving story around the stock. Stay updated as the Fair Value for Alliance Entertainment...
5 Lexus Engines You Should Steer Clear Of
Discover which 5 Lexus engines you should steer clear of. We detail reliability issues with the 1MZ-FE, 4GR-FSE, 1UR-FSE, and the twin-turbo V35A-FTS.
As diseases loom, CDC's response to measles deaths stirs fears about agency's reliability
The worst U.S. measles outbreak in decades is growing and flu season is imminent. Experts are fretting about federal health data reliability after the CDC questioned two Pennsylvania measles deaths.
Scientists used centuries-old aurora sightings to reconstruct 8 solar cycles from 1560 to 1640; their method placed solar minima within 2 years with more than 90% reliability
Centuries-old reports of strange lights in the night sky have helped scientists reconstruct a missing chapter in the Sun’s history. A study published in Scientific Reports by Kristof Petrovay, Laura G.
New, massive study finds only half of social science findings replicate
The University of Virginia led the work, highlighting the ongoing challenges in the reliability and reproducibility of research.
Opinion | In Science We Trust. Or Do We?
Readers respond to a guest essay about the methods and reliability of science. Also: Opioid addiction; judges and presidents; cursive writing.
Galaxy Buds 4 may not have Galaxy Buds 3 like quality and reliability issues
Samsung has reportedly prioritized quality and reliability in the Galaxy Buds 4 and Galaxy Buds 4 Pro over simply offering more features.
Using multiple AI health tools could pose reliability risks
Hundreds of AI tools for health care tout accuracy rates above 90%, but most are tested only in isolation.
Chargé Arnold Speech - Implementation Plan of Five-Year Health MOU - U.S. Embassy in Madagascar
Chargée d’Affaires Stephanie Arnold's Speech Discussion on the implementation plan for the five-year health Memorandum of Understanding (…) Colleagues, and honored guests, Good morning, and welcome to the United States Embassy. It is a pleasure to host you today for the second day of this important workshop to discuss the implementation of our bilateral health Memorandum of Understanding on U.S. Government health activities in Madagascar, made possible through the Trump Administration’s America First Global Health Strategy. Today’s focus— discussing a shared vision and developing a preliminary draft for the health MOU Implementation Plan and the terms of reference for the two committees that will steer its implementation—is a decisive step in moving from commitments on paper to concrete action over the next five years. On December 22, 2025, the Governments of Madagascar and the United States signed a five-year bilateral health MOU, with a financial intention of approximately 554 billion Ariary from the United States and This jointly decided MOU intends to strengthen Madagascar’s health system, support lifesaving services, and improve disease prevention and response that matter to both our countries’ health security. For the United States, this means detecting and containing infectious disease outbreaks including malaria, polio, and emerging health threats before they can reach American shores through international travel and trade, protecting American families while reducing the need for costly domestic emergency responses Yesterday, technical experts from the Ministry of Public Health and the U.S. Government worked in thematic groups to draft a preliminary Implementation Plan. Today, your task is to review the shared vision and preliminary draft MOU implementation plan, and the proposed terms of reference for the Joint Steering Committee and the Operational Committee that will guide its implementation. These committees are not just administrative structures. They are the mechanisms that will ensure clear roles and responsibilities, regular dialogue between our two governments, consistent monitoring of progress, and real accountability for the results that will directly benefit the lives of Malagasy citizens. They will also track performance against the benchmarks we have jointly established, which will guide the continuation of U.S. support over the five-year period . Continued U.S. support will be contingent on meeting these performance benchmarks. This ensures accountability to both American and Malagasy taxpayers and guarantees that our partnership delivers measurable results. America First Foreign Assistance means that U.S. support must be strategic, results-driven, and accountable to our taxpayers. It also means we aim to support greater self-reliance and reduced long-term dependence on foreign assistance, with systems that are increasingly financed and led by Madagascar itself. This approach benefits both our nations: Madagascar gains sustainable health capacity, while the United States advances our health security interests and creates opportunities for American health innovations and companies to support Madagascar’s development. In that spirit, I want to recognize the presence of the Ministry’s leadership and the technical directors and program heads responsible for surveillance, basic health services, family health, immunization, countering malaria, laboratories, medicines, and health information systems. Your leadership and technical expertise are essential if this bilateral health MOU is to translate into real and lasting improvements for people in need across the country. Let me emphasize how important collaboration is to the United States in this effort. We can bring American resources, technical expertise, and tools. But this bilateral health MOU can only succeed if it reflects Madagascar’s priorities and if Malagasy institutions lead and maintain its implementation. We see this not as a U.S. project, but as a joint framework under Malagasy leadership, with U.S. support. That is why we are genuinely pleased to host this event here at the Embassy. Opening our doors to you today symbolizes our commitment to work side by side and to remain transparent about how we use U.S. resources in support of Madagascar’s health system. In closing, thank you for your time and your partnership. We are very happy to welcome you here and proud to accompany Madagascar in this next step of implementation planning for our bilateral health MOU. I wish you a productive and focused session. The work you do today will shape how our two governments cooperate on health in the years ahead; it will influence the quality and reliability of health services that Malagasy communities receive; and, most importantly, it will help protect both our nations from infectious disease threats while building Madagascar’s capacity for long-term health system sustainability. Thank you.
Gemini for Google Home Keeps Getting Huge Upgrades
We can't seem to go a week at this point without Google pushing out several upgrades and changes to its Google Home products. From Gemini for Home to bug and reliability fixes, we're really...
Argonne develops real-time AI monitoring for an advanced nuclear reactor component
Argonne National Laboratory researchers proposed an AI-powered monitoring system that can spot blockages in the heat exchangers of molten-salt-cooled reactors in real time, helping prevent costly shutdowns and improve reliability for next-generation nuclear energy.
Who slept worst last night: Valtteri Bottas
The Finn had a rough weekend in Austria, battling reliability issues that echoed the fortunes of backmarkers of old
Windows 11 to get a major reliability update in May with faster clipboard, stable taskbar, storage and more
Microsoft is preparing a major Windows 11 reliability update for May 2026 with improvements across File Explorer, explorer.exe, taskbar, Settings, clipboard history, input systems, and Windows Hello. Early Insider builds show faster performance, fewer crashes, and a more stable experience.
Despair-Inducing Analysis Shows AI Eroding the Reliability of Science Publishing
A flood of slop has arrived in science, and everyone has to get less lazy. But does 2026 feel like a time when anyone, anywhere, is getting less lazy?
Amazon Deepens Digital Health Push As Logistics Deal Supports Valuation
Amazon.com (NasdaqGS:AMZN) is rolling out its AI powered healthcare assistant to all customers, expanding access beyond existing One Medical members. Air Transport International's pilot union has reached a tentative labor agreement with management after five years of talks, affecting a key part of Amazon's air cargo network. These developments touch both Amazon's digital health ambitions and the operational reliability of its logistics operations. At a share price of $207.67, Amazon.com...
Philosophy to the Rescue of Science
The pessimistic meta-induction—the argument that since past scientific theories have been shown to be false, we should expect that today’s will turn out false, too—makes the New York Times. . Elay Shech, professor of philosophy at Auburn University, takes up the topic in the context of current political disputes about science and our government’s seemingly increasing disregard of expertise: Robert F. Kennedy Jr., the secretary of health and human services, made a version of this argument in August when defending his decision to halt hundreds of millions of dollars in mRNA vaccine development despite the objections of vaccine scientists. He said that “science is always evolving” and the experts could not always be trusted. Shech accepts that “many widely accepted [scientific] theories have been discarded” but that the question, “why should we trust the ones we have now?” is misleading. Why? It implies that the only possible attitudes toward science are naïve faith and wholesale pessimism. It assumes that science is a single global entity that rises or falls all at once, when in reality, science is an array of local domains of inquiry, each with its own standards of evidence and degrees of reliability. In place of skepticism, Shech recommends “disciplined trust.” The first step in the direction of disciplined trust is recognizing that “there is no single scientific method used in all of science.” Shech writes: Newton’s deduction from observed phenomena is very different from Darwin’s inference to the best explanation, which in turn differs radically from Einstein’s thought experiments with light beams, trains and elevators. What people call “the scientific method” is really many distinct ways of investigating the world—different strategies for representing, experimenting and classifying. Since different areas of science employ different methods and rely on different kinds of evidence, to make a case for skepticism “you need to look at the evidence and methods in a specific area of inquiry.” And that case will not be “a sweeping claim about all of science” but rather about that particular area of inquiry with, for example, what might turn out to be “well-understood methodological problems.” Shech’s piece is “Science Keeps Changing, So Why Should We Trust It?” (NYT gift link). Discussion welcome (readers are advised to keep in..
Apple co-founder Steve Wozniak says he's 'not a fan' of AI
Apple co-founder Steve Wozniak says he is 'not a fan of AI,' warning the technology lacks reliability and the human understanding users expect.
Facing Barbs and Pressure From Trump, Europe's Leaders Close Ranks
ROME (AP) — U.S. President Donald Trump’s attacks on Italy’s premier have had an unintended consequence. After Trump questioned Italy’s reliability as a wartime ally and claimed Giorgia Meloni had groveled for his attention, European leaders rallied to Meloni's side, thawing what had been a frosty ...
PAID POST: How Connecticut Hospitals Are Modernizing Critical Infrastructure for the Future
Connecticut healthcare systems are modernizing critical energy infrastructure to improve reliability, increase efficiency, and support patient care for years to come.
Detroit Tigers Long for Someone Like Todd Jones Again
As Detroit’s bullpen struggles to close the door in 2026, we revisit the dominant, mustachioed reign of franchise saves leader Todd Jones and his unmatched ninth-inning reliability.
Here’s How Trump Is Building a National Citizenship Database to Check Voters
The Supreme Court allowed the Trump administration to deploy a system that merges personal data from across the government. Questions remain about its reliability.
Transmission investment powers Michigan’s economic future
ITC’s Krista Tanner discusses how the state’s electric grid is driving reliability, growth and long-term energy affordability for businesses.
How US-Israeli war on Iran is upending global business
The U.S.-Israeli war with Iran is rattling businesses worldwide, driving up energy prices, squeezing supplies of critical raw materials and raising questions about the reliability of trade routes critical to the flow of goods from food to car parts.
5 reasons patients check with a chatbot before—and often instead of—going to the doctor
Warning healthcare consumers about the unreliability of AI for medical advice is like screaming at tourists for frolicking in a decorative fountain on an oppressively hot and humid day.
Ford takes aim at Tesla with new battery storage business
Ford is positioning the move as a durability and reliability play.
Nvidia and Microsoft Researchers Say AI Agents Don't Care About Safety or Reliability
The researchers compared AI to the near-sighted cartoon character Mr. Magoo, who can’t see he’s stumbling through dangerous situations.
Samara Aerospace tests reliability of attitude control technology with National Science Foundation award
Samara Aerospace tests reliability of attitude control technology with National Science Foundation award
The Latest: Iran deal progress is murky after US military says it carried out ‘self-defense’ strikes
President Donald Trump insists a peace deal is close on this 88th day of the Iran war, but Iran on Tuesday denounced U.S. strikes a day earlier as a sign of “bad faith and unreliability” as negotiations continue.
The disunity of science is a feature, not a bug
Mathematical models wield miraculous power, but mistaking them for reality has trapped science in a destructive quest for a “Theory of Everything.” Physicist and philosopher Ragner Fjelland argues that this leads to bloated, Frankenstein theories kept alive by clumsy, ad-hoc amendments, which reduce rather than boost science’s power. Fjelland calls for a radical shift in our attitude: we must reorientate towards creating entirely new theories, celebrating rather than lamenting disunity and diversity in science. Science, from the scientific revolution in the seventeenth century to the present day, has more or less developed in a “reductionist” way. The fundamental assumption is that all sciences may be ordered in a hierarchy that can be represented as an upside-down pyramid. At the top we find the human sciences, and at the bottom physics. Strong (or “ontological”) reductionism maintains that all theories at one level can be completely reduced to the lower level, all the way down to theories of atoms and elementary particles, or whatever is “at the bottom.” In the end, all diversity in the world can be unified in one fundamental theory. Hence it is called a final theory, or a Theory of Everything.One of the central figures in developing the idea of a Theory of Everything is the Dutch theoretical physicist Gerard 't Hooft, who received a Nobel Prize in physics in 1999 for his work. He emphasizes the non-empirical status of the theory:There exists no closely resembling alternative theory. This means that any slight change brought about in the rules would make the theory unlikely or inelegant. The theory will be a "package deal": take it, or leave it. This should hold both for the local laws and for the boundary conditions.This endeavor is not new. On the contrary, it goes all the way back to the birth of Western philosophy 2,500 years ago. The Babylonians made regular astronomical observations during a period of 600 years, from 747 BCE until 150 ACE. They developed mathematical techniques to predict astronomical phenomena, but they made no attempts at explaining them. However, the Greeks developed models, both material and theoretical, to explain the observed phenomena.The best example is Plato’s late dialogue Timaeus. Here he introduces a divine craftsman, the Demiurge, who has constructed the universe according to an original plan. Plato seems to have thought that the original plan is what is actually real, while the material world is merely an imperfect realization of it. He therefore does not, in the Timaeus, reconstruct the material universe, but the original plan, which can then be used to explain the material universe.Plato’s aim in producing a theoretical model is to reconstruct the original plan. That is what he carries out in Timaeus—and some modern physicists have embarked on the same project. For example, Einstein’s basic attitude is reflected in the title of Abraham Pais’ biography: “Subtle is the Lord...,” echoing Einstein’s comment, “Subtle is the Lord, but malicious He is not.” In an interview Einstein compared our situation to a child who enters a huge library. The child knows that someone has written the books, but he does not know the languages in which they are written. He suspects that there is a mysterious order, but he does not know what it is.___“We have all been working in what Husserl called the Galilean style; that is, we have all been making abstract mathematical models of the universe to which at least the physicists give a higher degree of reality than they accord the ordinary world of sensation.”Steven Weinberg, Nobel Prize in Physics (1979)___This Platonist view is contrary to a widespread impression of science, symbolized by the picture of the “father” of modern science, Galileo Galilei, with his telescope. According to this impression, Galileo liberated himself from the dominating metaphysics of his day—basically Aristotelian philosophy—and constructed a telescope that he directed towards the sky, showing that Jupiter has four moons. He also performed experiments with bronze balls rolling down inclined planes and found the law of freely falling bodies.However, in other cases Galileo emphasized the unreliability of our senses. It is easy to see why. He defended Copernicus’ heliocentric hypothesis. According to this hypothesis, we are not at rest at the center of the universe, but moving at a tremendous speed through space. Why don’t we observe this motion? Galileo praises Copernicus because “with reason as his guide he resolutely continued to affirm what sensible experience seemed to contradict.” In other places he directly refers to Plato. SUGGESTED VIEWING The quest for a final theory With Michio Kaku Galileo’s Platonism goes back to his early writings. In The Assayer, published as early as 1623, Galileo compared the universe to a grand book that is written in the language of mathematics, and “its characters are triangles, circles, and other geometric figures without which it is humanly impossible to understand a single word of it.” Therefore, things that cannot be described by mathematics—for example, colors, smells and odors—are not real. They are merely subjective.This division into subjective and objective, advocated by Galileo and his younger contemporary René Descartes, is normally associated with a mechanistic world view, which is regarded as the opposite of Platonism. When we reduce something to, for example, molecules and atoms, we move “downwards.” In contrast, the Platonist moves “upwards,” to abstract entities. However, it only shows that when we address fundamental questions, we should be careful in applying everyday spatial metaphors like “up” and “down.”___Nature is complex, and we cannot in general construct mathematical models that adequately describe the world.___The endeavor of finding a Theory of Everything has been heavily criticized. In 2006, the theoretical physicist Lee Smolin published “The Crisis in Fundamental Physics.” He argued that one of the most fundamental principles of science is that we should only regard theories as scientific if we have the possibility to show that they are false by experiments. Although he did not refer to Karl Popper, other critics have referred to Popper and argued that a theory is not scientific if it cannot be falsified (see for example Ellis & Silk 2014).These were not the first physicists to be anti-reductionists. In 1972, the journal Science published an article by the physicist Philip Anderson with the title “More Is Different.” This is the kind of article a scientist would normally write only after he has won a Nobel Prize. However, Anderson won the Nobel Prize for physics five years later, in 1977. The article is amazing, not primarily because it argues in favor of anti-reductionism in general, but because it argues for anti-reductionism within physics itself. Anderson’s conclusion was:At each stage entirely new laws, concepts, and generalizations are necessary, requiring inspiration and creativity to just as great a degree as in the previous one. Psychology is not applied biology, nor is biology applied chemistry.We may say that Plato started the “unity of science movement,” based on Euclidean geometry as the model of all knowledge. A distinguishing mark of geometry is that all possible constructions can be reduced to a few fundamental principles. We have to acknowledge that this approach has limitations. In general, we can easily model technological systems. In addition, we may construct simplified and idealized models that capture important aspects of systems, from various perspectives and for various purposes. But nature is complex, and we cannot in general construct mathematical models that adequately describe the world. In a complex system, each level has its distinct, emergent, properties that are characteristic of this level. Therefore, a complex system should be investigated at different levels and from different perspectives. Instead of exclusively pursuing a scientific ideal based on the unity of science, we should acknowledge the diversity—or even the disunity—of science.
WellSpan Health Announces Comprehensive Migration of Technology Portfolio to AWS
Add to FavoritesWellSpan Health, the leading health care system serving Central Pennsylvania and Northern Maryland, today announced plans for a comprehensive cloud migration of its full technology infrastructure. Together with Amazon Web Services (AWS) as its preferred cloud provider, WellSpan will transition its applications, data and environments from traditional data centers to AWS. This migration will establish the foundation for delivering next-generation, AI-enabled health care solutions that reduce administrative burden and improve outcomes for patients across the region and beyond. Supercharging Innovation, Efficiency and Patient Outcomes WellSpan's migration of systems and clinical applications, which serve 1.2 million patients across nine hospitals and 250+ facilities, is expected to be complete by April 2026, one of the fastest full-scale migrations in the health care industry. This transformation enables WellSpan to unify disparate data systems for care teams and patients alike, achieving operational efficiencies and care improvements that fragmented systems are unable to deliver. “Our comprehensive migration to the cloud accelerates our ability to deploy new clinical capabilities that transform patient care while advancing our overall innovation strategy,” said Roxanna Gapstur, Ph.D., R.N., president and CEO, WellSpan Health. “When a physician can access complete patient imaging in seconds instead of hours, we're not just modernizing technology—we're improving patient outcomes. Our new cloud infrastructure also enables us to quickly implement solutions that will free our clinicians from thousands of hours of administrative work annually so they can focus on what they do best: caring for our communities.” The transition allows WellSpan to move away from a data center-based model and enables the rapid deployment and scale of AI technology. WellSpan’s strategic partner, General Catalyst’s Health Assurance Transformation Company (HATCo), facilitated the collaboration with AWS to support the migration. WellSpan’s transformation journey benefits from HATCo’s specialized technology solutions, as well as General Catalyst and AWS’s significant partnership to improve patient outcomes, which was announced in January 2025. “Our decision to go all-in on AWS will enable insights and innovations impossible in traditional siloed environments,” said Kasey Paulus, executive vice president and chief operating officer, WellSpan Health. “This is the largest health care technology transformation in our region's history, and it positions WellSpan to be a premier partner for technology leaders across the country.” “WellSpan is building a foundation with AWS that will improve care and outcomes for patients across their health system by bringing data together into standardized formats that are optimized for AI applications,” said Dan Sheeran, vice president and general manager, Healthcare and Life Science, AWS. “To do this, it is essential to have the most secure and compliant cloud when handling patient data, along with AWS’s built-in AI governance and responsible AI frameworks that follow the industry’s highest standards to protect patient information. We look forward to continuing to work alongside WellSpan as they unlock the cloud and AI’s full potential to deliver exceptional care to their patients.” Key Benefits of the AWS Collaboration Full Portfolio Migration: WellSpan will transition its applications and data from on-premises data centers to AWS, including full IT environments and specialized applications for functions such as nursing, cardiology, pharmacy and the company’s supply chain systems. This represents approximately 7.5 petabytes of clinical and non-clinical data and more than 300 applications—the most comprehensive health system cloud migration in the Mid-Atlantic region. Approved Architectures: AWS will deliver secure, WellSpan-specific architectures tailored to each build, ensuring compliance and reliability across the health system. Unified, AI-Ready Data: Migrating to AWS enables WellSpan to harmonize data across separate systems, transforming unstructured clinical notes and multi-modal datasets into standardized, AI-ready formats. Accelerated Results and Improved Outcomes: Automated data normalization and processing will enable the deployment of applications that reduce turnaround times for items such as analyzing medical imaging or patient records from days to minutes, helping clinicians get patient results faster and improving overall health outcomes. Reduced Administrative Burden: The transition to AWS will enable swift deployment of AI-powered solutions that reclaim thousands of hours for WellSpan’s clinical and corporate teams, allowing them to focus on patient care rather than paperwork. Elastic Infrastructure: Cloud architecture will enable WellSpan to scale computing resources dynamically, supporting seasonal demand fluctuations without infrastructure investments, as well as the rapid deployment of new services across multiple locations simultaneously. Most Secure, Compliant Cloud: AWS offers the highest network availability of any cloud provider, with more than 166 HIPAA-eligible services and certifications for global compliance standards, including HITRUST CSF. Built-in AI governance and responsible AI frameworks ensure that WellSpan’s data is protected under the industry’s most rigorous standards. Tags:News releaseInnovation and partnerships
US-Israel war with Iran sends shockwaves through global business
The U.S.-Israeli war with Iran is rattling businesses worldwide, driving up energy prices, squeezing supplies of critical raw materials and raising questions about the reliability of trade routes critical to the flow of goods from food to car parts.
ModRetro Sells Handheld Made Of The Same Metal As Attack Drones
The Anduril Chromatic device is made for ‘performance and reliability’ in case you’re playing Tetris in a warzone, I guess?
College professors gave ChatGPT a science exam, and its grade was a 'low D'
A new study finds ChatGPT can give different answers to the same question, raising concerns about its accuracy, reliability and consistency.
Energy efficiency that delivers measurable business results
Lower costs, improve reliability and boost productivity with DTE Energy rebates, financing and customized energy efficiency solutions.
Lubrication Engineers Marks 75 Years in Business
Lubrication Engineers marks 75 years, highlighting growth and solutions that help contractors, including roofing professionals, improve equipment reliability and reduce costly downtime.
I read Microsoft's Windows 11 'quality' progress report - and the subtext says it all
Microsoft's latest progress report details much-needed Windows 11 improvements in reliability, performance, stability, and usability. But here's what else I see.
Xbox adds monthly cloud limits to Game Pass as it "continues to invest in its reliability and performance"
Once caps are reached, players can purchase additional cloud playtime hours through the Xbox Store
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
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