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Catapult Books is being sold and its L.A. authors are mourning
Catapult Books has sold its assets to an undisclosed buyer, leaving the future of 16 scheduled titles uncertain as staff negotiate a severance package.
OPD: Package found at business not suspicious
Authorities responded Thursday afternoon to a report of suspicious package at an Omaha business.
SCENE VIDEO: Suspicious package reported at Omaha machine business
Omaha Police and Fire responded Thursday afternoon to the scene at Grede Casting Integrity, on Martha Street, just east of Highway 75.
Suspicious package reported at Omaha machine business
Authorities responded Thursday afternoon to a report of suspicious package at an Omaha business.
Henrico Planning Commission advances proposed marijuana business regulations to board of supervisors
A new package of zoning restrictions on recreational marijuana businesses will advance to the Henrico Board of Supervisors, after the Henrico Planning Commission blessed the proposal Oct. 15. Commissioners voted unanimously for approval after only a few questions and no comments from the public. Supervisors will consider the regulations during
Trump administration announces $8 billion farm relief plan as fuel, fertilizer costs bite
(CNN) — President Donald Trump announced at a Kansas rally on Monday that his administration is introducing an $8 billion aid package for farmers in the face of high diesel
3+ useful features included with Google One that people ignore
Google One plans started off as a way to expand storage limits for files and photos, but they now include AI features, family sharing and YouTube packages.
Uzbekistan's $12bn business drive gathers pace during Rubio visit
The package covers railways, critical minerals, finance and technology, with major US firms involved. Uzbek President Mirziyoyev outlined measures to attract investors, while business executives told Euronews that commercial activity is growing.
Entertainment 360, Griffin Gaming: HITpoint Bridges Gaming, Hollywood
Bridging gaming and Hollywood, the new player will "source, develop, package, and produce adaptations" across genres, including action, horror, high-concept spectacle, comedy and beyond.
A new tool makes mapping the ocean easier
UCSB marine scientists have developed a new, open-source software package that makes it faster and simpler to find, organize and map data about the world’s oceans.
Memorial Health System receives $15,000 grant for Packaged Meal Program
The Food and Nutrition Services department at Memorial Health System has been awarded a $15,000 grant from the Community Foundation of Dickinson County to support the development of a new
Graham breaks with Trump over Russia sanctions law her brother championed
Darline Graham has only been a senator for a few months, but she has cited her role in passing the sanctions package, a major part of her brother’s legacy, as a top achievement.
Intel confirms Razor Lake-AX for 2028 with 700 TOPS AI performance
Intel's Razor Lake-AX will target humanoid robots in 2028. Earlier leaks linked the processor to 16 or 32 Xe3P graphics cores and on-package memory.
Political scientist: 'The darkest moment' in the war in Ukraine
Geopolitical expert Klemens Fischer believes Ukraine finds itself in a desperate situation following President Donald Trump's decision to halt the new US sanctions package intended for Russia. "This i...
Trump signs Executive Order waiving sanctions against Russia
President Donald Trump cited “national interests” for the decision to waive a punishing sanctions package targeting Russian exports and leaders.
Trump puts new Russia sanctions passed by Congress on hold, saying waiver is in U.S. national interest
President Donald Trump has signed an executive order that puts on hold a sweeping new sanctions package targeting the Russian economy, telling Congress the pause was in the national interest.
Trump puts new Russia sanctions passed by Congress on hold, saying waiver is in US national interest
WASHINGTON (AP) — President Donald Trump on Friday signed an executive order that puts on hold a sweeping new sanctions package targeting the Russian economy, telling Congress the pause was in the nat...
Smears, confusion and white powder: a week in the US midterm campaign
This week in US politics, a candidate with the flu fell victim to a false rumor, a campaign ad aired in the wrong city, and packages with suspicious powder were mailed to election officials. Packages ...
Technics EAH-A1000 review: Superior sound and excellent ANC in a premium package
Technics’ flagship over-ear wireless headphones are light on compromises, but enter a competitive market.
National newspaper supplements mark World Mental Health Day 2026 in Bangladesh
To mark World Mental Health Day 2026, special newspaper supplements were published across nine national newspapers in Bangladesh, helping bring mental health messages to readers across the country. The supplements appeared in seven Bangla-language and two English-language newspapers: Bangladesh Pratidin, Bhorer Akash, Jaijaidin, Jugantor, Kalbela, Dainik Amader Shomoy, Prothom Alo, New Age and The Daily Star.
Clinton Policy Institute outlines maternal health solutions for states
Health Care Clinton Policy Institute outlines maternal health solutions for states It’s the first major report from the project, which launched in July to foster nonpartisan policies to improve the wellbeing of children and families. Stephanie Akin 10:00 AM, Oct 15, 2026 Dr. Jacob Lenz performs an ultrasound at the Oklahoma State University obstetrics and gynecology clinic in Tulsa, Okla., on Tuesday, July 16, 2024. (AP Photo/Mary Conlon) The Clinton Policy Institute is calling on states to lead efforts to curb maternal mortality, releasing a 61-page playbook Thursday highlighting successful policies that could be adopted nationwide. The playbook is the first major report from the Clinton Foundation’s project, which launched in July to foster nonpartisan state and local policies to improve the wellbeing of children and families. “Eighty percent of maternal deaths are preventable, and we know what works,” CPI Chair Jennifer Klein said. “The solutions are well established and evidence-based.” CPI’s mission is to convene political leaders from both parties, policy experts, state officials and other stakeholders to explore solutions to longstanding problems. “What we aim to do is bring together people who are deeply engaged, but may not be meeting together in the same room,” Klein said, noting that state policymakers might not always be aware of what their peers are doing in other states. In May, CPI brought together lawmakers from Virginia and Pennsylvania, two of the 14 states that have passed bipartisan maternal health “Momnibus” packages modeled after a comprehensive federal proposal that has repeatedly stalled, called the Black Maternal Health Momnibus Act. Other participants included Dr. Mona Hanna, founder of Rx Kids, a Michigan program that provides direct cash allowances to pregnant women and infants. Pennsylvania Rep. Morgan Cephas, who was part of the group, said she learned about funding opportunities she hadn’t come across during her decade in the Legislature. “As legislators we can issue grants, we can pass legislation, we can move policy, but we want to ensure that funding opportunities and programs that are tackling this issue are sustainable,” Cephas said. The playbook outlines broad areas where state policy can make a difference, such as allowing Medicaid to pay for doulas and remote patient monitoring, and using federal and private grant funding to pay for home visits to pregnant and postpartum women. For each category, it highlights innovative programs that can serve as models, with examples of specific actions state lawmakers and governors’ offices can take. Those include the Rx Kids model, which gets funding from the Michigan state budget; Pennsylvania’s Healthy Moms Vibrant Futures strategic action plan, emphasizing equity-centered maternal care, regional collaboration, Medicaid innovation, and workforce development that was launched this year with more than 160 stakeholders; and Kansas’s Bridging Plan, which reserves three slots and provides at least $26,000 in loan forgiveness for obstetric residents who commit to practicing in rural or underserved communities for 36 months. CPI emphasizes that its work is nonpartisan. Klein, the director of the White House Gender Policy Council under former President Joe Biden, acknowledged that CPI also takes positions on abortion, Medicaid funding, and the need to address the economic and social drivers of poor health, which might rankle some conservatives. “We don’t shy away from talking about those things that we think are part and parcel of the maternal health crisis in this country,” Klein said. “That said, there are so many policies that are both evidence-based and have been tried successfully in both red and blue states, and people can see that they can have real impact.” She pointed to the federal option to extend postpartum Medicaid coverage from 60 days to 12 months that was made available during the Biden administration and has since been adopted by every state but Arkansas. Other initiatives embraced across party lines include Medicaid coverage for midwives and doulas, as well as “bundled” payments for prenatal and postpartum care. That alternative payment model, pioneered in states such as Arkansas, Colorado and Tennessee, incentivizes fixed fees to cover all healthcare services associated with pregnancy and childbirth. Advocates say it promotes more coordination among caregivers, discourages unnecessary interventions, and expands postpartum support. In addition to maternal health, the initiative is also focused on addressing family economic security, children’s well-being, and democracy and civic resilience.
Mercedes F1: The Austin Package Will Define 2027
The German team will equip both W17s with the Sepang updates to expand data with Antonelli and Russell.
SD rules committee advances campaign finance, `Dark Money' reform packages
The two separate proposals, the Ending Perpetual Fundraising Ordinance and Exposing Dark Money and Banning Shadow Campaigns, follow the previously advanced Follow the Money Ordinance, which the Rules Committee advanced in August.
Shipping Data Could Decide the Next Small Business Loan
A small business can have a warehouse full of merchandise, a growing order book and packages moving toward customers, and still struggle to qualify for
Amazon (AMZN) Has a $25B Chip Business. Is the Cash Burn Worth It?
Most people think of Amazon (NASDAQ:AMZN) as the place their packages come from. The part of the company drawing the most attention right now sells something far less visible: custom AI chips. In the second quarter of 2026, Amazon Web Services (AWS) said its chips business and its AI business had each passed a $25 […]
Daldrop Opens for Business in Southern Oswego County
$10 Million Facility in the L. Michael Treadwell Oswego County Industrial Park marks the largest expansion outside of Germany in the company’s 73-year history By Stefan Yablonski [caption id=attachment_11076 align=alignright width=450] Daldrop SBB CEO Jens Daldrop addresses attendees at the 2025 groundbreaking for the project. Daldrop also chairs the advisory board of Germany-based Daldrop Group.[/caption] A new era of cleanroom technology is underway in Central New York. The Daldrop Group’s advanced manufacturing facility and U.S. headquarters is physically built within the L. Michael Treadwell Oswego County Industrial Park. This industrial park is located in the town of Schroeppel. It marks the largest expansion outside of Germany in the company’s 73-year history. Daldrop SBB is based in Neckartailfingen, Germany. It is a global supplier of cleanroom technology, primarily to the pharmaceutical industry. It designs and builds advanced cleanroom environments for the pharmaceutical, biotechnology and medical technology industries. It nvested $10 million in the new project. “We broke ground in 2025; we were under construction all winter. We just opened this spring, early spring,” said Benjamin Morrow, operations manager and control. The company consolidated sites in Salina and DeWitt into the industrial park in Schroeppel, Morrow added. “The next move here is to maximize every square inch of this facility and then we are already looking at the expansion. So, it is more capital investment on equipment — definitely higher-end automation in additional equipment so we can produce more components and then to support the ever-growing base in North America,” Morrow continued. “We are the headquarters for service, maintenance and spare parts. So as Daldrop has more and more installations, they need more and more service, maintenance and spare parts. So that will come out of this facility as well — it already is.” “As a global leader in GMP (global manufacturing support) pharmaceutical cleanrooms for decades, I am very proud to bring manufacturing jobs to Upstate New York,” said Mike Sullivan, president of Daldrop US operations. Key to choosing Southern Oswego County [caption id=attachment_11077 align=alignright width=450] Daldrop SBB at the L. Michael Treadwell Oswego County Industrial Park when the company announced the start of construction.[/caption] Sullivan said that the selection of the Schroeppel industrial park was mainly due to the help of Operation Oswego County and two people in the organization. “Prior to being purchased by Daldrop International from the Stuttgart region of Germany, Vince Bongio was a founding partner in SBB Inc. as well as our head of engineering. We based out of Syracuse due to Vince’s skills in HVAC and the manufacturing capabilities found in Syracuse,” said Sullivan. Bongio moved to Syracuse from California in the 1970s to work in Carrier’s Industrial Division of Large-Scale Petrochemical Refrigeration. Next, he advanced to General Electric’s TV Tube Plant where he got into cleanrooms ,leading to his role of head of engineering for Clestra Cleanrooms where he met Sullivan, their New England distributor. “Vince Bongio is a phenomenal engineer. Formerly of Carrier, he grew up in California and went to Cal Poly,” Sullivan explained. “Carrier hired him right out of college and he moved to Syracuse. He is the reason we are in Syracuse today. He is retiring this year. We are very proud and his legacy is having brought Daldrop to Syracuse.” In 2000, Sullivan, Bazinet, Bongio Inc (SBB) was formed with engineering and manufacturing, based in Syracuse, and sales and construction based in Massachusetts as it is today. “SBB Inc. started in Syracuse. I had a design–build contracting firm out of Massachusetts that was primarily doing all the new technologies coming out of MIT,” Sullivan said. “I started a manufacturing side. A big thing for cleanrooms is the HVAC. Most cleanroom suppliers are architecturally focused people. The strength in Syracuse is HVAC. So, SBB developed with me running sales and construction out of Massachusetts and manufacturing out of Syracuse.” “Daldrop wanted to have a relationship in the States and of those who approached us, they were the only ones who really understood HVAC. So, we were the right fit for them. We did a joint venture focused out of Massachusetts from 2012 to 2018 leveraging their technologies,” Sullivan explained. “The commitment was if we brought their product to the States, we would do that if they built it here. “The pieces that had to be in place to make the investment, they wanted to acquire us, we were great with that. If you looked at business recommendations the general guidance was to build in a low labor area — something like North Carolina — but Syracuse had a strong background in HVAC and we chose Syracuse and Oswego County to be our headquarters in the States. So, it is built off of history, technology and the existing supply chain — bringing jobs back to the area.” During the initial discussions with Daldrop about coming to the U.S., SBB agreed to sell under the conditions Daldrop would manufacture in the U.S. There are many areas that offer incentives and economic packages, but the strength of HVAC expertise and skilled manufacturing was a big part of the discussions for site selection. Coming home [caption id=attachment_11078 align=alignright width=451] Construction moves forward in March at the L. Michael Treadwell Oswego County Industrial Park.[/caption] The second key person to building in Oswego County is Ben Morrow, Sullivan added. “Ben has been working with Daldrop SBB for more than 12 years and has advanced to COO of manufacturing and engineering. Ben grew up in Phoenix, so building a factory for the Germany company in Phoenix is a strong success for both his community and the appreciation of Ben’s skills as a team leader,” Sullivan said. “I went to high school in Phoenix. So, this is like full circle for me. It’s a small world,” Morrow said. “I hadn’t been back to Phoenix since graduation. This is one of the properties that John Trimble of C&S, he is the former president of C&S, he just retired, suggested. He and I were very good personal friends. John was from Mexico and I was from Phoenix. We knew each other from high school. And the architect of this building, Ed Smart of smartDESIGN Architecture in Batavia — I went to high school with him. So, this was a project that’s full circle a coming home kind of thing. The three of us knew each other — kind of like it was meant to be. Very serendipitous.” Schroeppel was one option for Daldrop to consider; the original intent was just to get a warehouse to store some product, he added. The facility is Daldrop’s largest outside of their native country. Total payroll at the facility will be approximately $2.4 million once fully staffed. “Here is 32,000 square feet and we plan to expand and put in an additional 10,000 square feet,” Morrow said. “We have 17.5 acres. We can put at least three more facilities here, just on this property. The master plan submitted for the current building is the first of possible three buildings on the campus.” “If we can find the right people and advance the production according to the plan, we should be able to grow for the next decade. One of the first jobs we filled was our new HR manager, with a primary focus posting and filling new positions,” Sullivan said. Stop the exodus, start hiring [caption id=attachment_11080 align=alignright width=452] Principals at the local Daldrop SBB headquarters, from left: Ben Morrow, Mike Sullivan and Jens Daldrop.[/caption] “I have been coming to Syracuse for 30 years. One of the things I had a hard time watching was the exodus of factories. One of the toughest things is to watch it with my partners’ kids who had to move away for jobs. It is important for us to give opportunity where people’s kids don’t have to leave the area to get work,” Sullivan said. “My responsibility is to find people who have skill sets that want to work and then I have to build opportunity for that work to happen. “After years of watching companies and Vince’s three sons all move out of the areas to get jobs, it is important to us to provide opportunities for the Syracuse region and help grow our company. We have been hiring for our new factory and will continue for the next few years.” “We are hiring and will continue to hire. Currently we have about 19 on staff right now,” Morrow said. “We expect to grow that by about 10 to 15 in the next 12 to 18 months or so. We are at 19 currently — one in the wings. It’s been great being able to hire locally. All these folks that we’ve been hiring, they all live within a few miles from here.” “We hired someone this past week (end of August). She grew up in the area, raised a family and is working down in Florida. She just took a job with us so she can move back and be with her family. We will be moving her back and she should be starting in October. We are very happy to see this happen,” Sullivan said. “I feel strongly about having a spot for the kids to not have to move out of the area. It is better to have people moving into the area.” Currently, Daldrop SBB has openings for finance manager, COO of construction and delivery, as well as mechanical, electrical designers and Revit modelers, construction managers, commissioning agents and many other skills that are needed. Along with Daldrop’s reputation in life science cleanrooms, there is a strong history in semiconductor, electronics, glass, photonics, aerospace and other markets. This may be helpful with any new technologies building in the market such as the Micron expansion and the support network, Sullivan said. “We acquired this property and closed on it two months before any announcement from Micron. It is serendipitous that they’re right down the street from us,” Morrow added. “Everybody started thinking ‘you guys are supporting Micron.’ We were here first. That is not a goal of ours. We may or may not … they are talking to us; it is an opportunity.” The long run [caption id=attachment_11079 align=alignright width=450] Benjamin Morrow, operations manager and control at Daldlrop, speaks during a recent ribbon-cutting event in Schroeppel.[/caption] “Long term, we will expand the Phoenix facility,” Sullivan said. “We built our facility with a campus approach. Sustainability is big. We designed our rooms to be more sustainable. Our building has no gas lines for heat. We put geothermal wells in the ground. We put heat pumps in for heating and cooling out of those wells and we put a large layer of solar panels up on the roof. We worked with National Grid for metering. Our building is a high efficiency model. We upgraded all the instillation and the glass filtering. So, it is a very green building. We will have a very minimal carbon footprint. It also adheres to LEED (Leadership in Energy and Environmental Design) construction standards.” “We are a bunch of HVAC engineers. We did a large scale geothermal and spent the money up front because we knew it made sense in the business sense in the environmental sense and sustainability,” Morrow said. “We have insulated metal panels on walls and roof; we are an envelope from the exterior.” Daldrop, as a global player, has a strong culture of sustainability that is found in all its products including the new facility. The building has been designed with (sixteen) 400-foot deep geothermal wells, high efficiency construction methods, approximately 70 kilowatt solar photovoltaic panels, electric vehicle chargers and 26% recycled content. “Daldrop thinks of long-term investing,” Sullivan said. “On the roof, photovoltaic panels supplement our power. Over half the energy that I use is coming from the sun. We have chargers up front for employee electric vehicles. This place is built to last. This slab that we are walking on, normal buildings are four inches, some go to six inches, we are nine inches all the way through — except where the heavy equipment is — that is 10 to 12 inches thick, solid concrete. It allows us to reconfigure for whatever type of equipment we want to bring in,” Morrow said. “We are authorized by Underwriters Laboratory to self-certify so we don’t need to have an inspector come out and recertify. We get audited often, but we certify our own electronics. The control system in this building is rather high-end. Our thermostat in every room is zoned, independent. We analyze the data; incorporate it with our solar panels.” “There is a lot of competition for people to work. It’s not just about how much salary they are going to make — it’s about the work environment, the ability for stability. We want to make sure our employees have the best environment to work in,” Morrow added. Similarities “One of the reasons I believe why Daldrop chose this area, Phoenix in particular, is because it is a village, a river-based village. Neckartailfingen in Germany where Daldrop is based is also a river-based village, manufacturing community. So, there is a lot of similarities — that smalltown feel,” Morrow said. “We have a lot of connections through multiple employees that lead back to Carrier, also. Everything came together, the timing everything.” “We are thankful for all the economic development support. Everyone has been helping make this happen. So, keep it up, it is working, that is all I got to say, Sullivan said. “If you look at historical industrial manufacturing, this region has skills that have been un-utilized. The northern industrial region has a lot of skills that if we can tap before they go away, we can leverage them. That is what we are trying to do. You’d be surprised at the supply chain left behind from Carrier — that supply chain is still there.” “Operation Oswego County has been fantastic,” Morrow added. “I can’t say enough good things about that group.” What Is Cleanroom Technology Cleanroom technology is a system of specialized engineering, filtration and operational controls used to maintain an extremely low concentration of airborne particles, microbes and chemical vapors. How It Works • Air Filtration: Uses HEPA or ULPA filters to remove 99.97% of tiny particles down to 0.3 microns. • Airflow Control: Directs air in a steady, unidirectional (laminar) or filtered turbulent pattern to push dust away from work areas. • Environmental Regulation: Maintains precise control over temperature, humidity and positive air pressure to block outside air leaks. • Specialized Attire: Requires personnel to wear full-body garments (“bunny suits”), gloves and masks to stop human shedding
AIPOCH Launches Open-Science, Making Research Easier to Follow, Learn From, and Share with .science Packages
/PRNewswire/ -- AIPOCH today announced the formal public release of AIPOCH Open-Science, an open-source AI research workbench designed to help more people...
Timberwolves Offering Insane Deal on NBA Cup Tickets
The Minnesota Timberwolves are the hottest ticket in town, and a new package lets fans chase the NBA Cup on the cheap.
I tried Sonos' sleek new Beam Ultra soundbar, and it packs huge Dolby Atmos sound into a small package
The new Sonos Beam Ultra improves on the standard Beam by adding up-firing audio drivers that bounce Dolby Atmos sound effects off your ceiling.
Lionel Messi is building a business empire that will outlast his football career
From his Inter Miami compensation package to hotel investments, venture capital and football club ownership, Messi is turning his sporting success into a diversified portfolio.
Something Strange Has Appeared On My Lover’s … Package. I Do Not Like Where This Is Going.
He says it's nothing. Yeah, right!
Bowen Byram Sabres-to-Blackhawks Contract Questioned After Aho Embarrassment
Bowen Byram still has a long career ahead of him with the Chicago Blackhawks. He can still turn into the high-end defenseman they believed they were getting when they sent a big package to the Buffalo Sabres for him and then signed him to an expensive contract extension. But the early returns have been less […] The post Bowen Byram Sabres-to-Blackhawks Contract Questioned After Aho Embarrassment appeared first on HEAVY.
Querétaro saw off Atlante and maintained their excellent form
Club Querétaro have gone from being a surprise package to a dominant force in the tournament. Against Atlante, the Gallos Blancos once again demonstrated their tactical solidity, beating the Potros d...
White House Announces $6 Billion Science Initiative Package
The White House says its new science package includes industry computing pledges, a virtual-biology initiative and quantum research competitions, but much of the headline total is not federal cash spending.
Why Congress hasn't passed bills to save Black infants, moms
Wisconsin Democrats in the U.S. House and Senate are pushing a package of bills to improve Black infant and maternal health nationwide. It faces a steep climb.
Amendment 79: New Opportunity: B.8 Heliophysics Spaceflight Science Foundations
The Heliophysics Spaceflight Science Foundations (SSF) program (B.8 of ROSES) solicits investigations that enable the formulation of high-impact spaceflight
The Lateral Is Coming. Is the Business? How Law Firms Can Turn Lateral Hiring into Revenue
A lateral hire represents one of the largest growth investments many law firms make. Yet firms sometimes spend more energy negotiating the lateral’s compensation package than planning how the lawyer will succeed once inside the building.
Healthy Food Bundles Lowered Weight, Blood Pressure Long-Term, Study Shows
By Dennis Thompson HealthDay ReporterWEDNESDAY, Oct. 7, 2026 (HealthDay News) — Sending people bundles of healthy food can help them lose pounds and reduce blood pressure, a new study says. People receiving plant-based grocery packages from a Boston-area food pantry wound up in overall better health ...
Spectrum streaming bundle makes entertainment affordable on Coast Live
With so many plans and packages to choose from, how do you know if you are really getting the most for your money? Experts say there are some simple ways you may be able to save.
Broker facilities expand as technology, alternative capital reshape placements
Broker facilities that automatically or rapidly provide following capacity are expanding as brokers seek to speed placements, use data to package portfolios of risks and tap additional sources of…
Countries race to provide oral health care for all in 100-Day Sprint across Asia
Twenty Asian countries and areas across the WHO Western Pacific and South-East Asia regions vowed to strengthen essential oral health benefits as part of a “100-Day Sprint” initiative, during the 16th Asian Chief Dental Officers Meeting held from 27 to 29 September in Kota Kinabalu, Malaysia. The meeting marked the midpoint of the 100-day sprint bolstering support for countries to develop essential oral health benefit packages that can be integrated into national universal health coverage plans. Convened by the two WHO regional offices and the Malaysian Ministry of Health as the Secretariat, the meeting brought together national oral health leaders from 20 Asian countries, staff from all levels of WHO, WHO collaborating centres and other development partners. Participating countries and areas included: Bangladesh, Bhutan, Brunei Darussalam, Cambodia, China, Hong Kong (SAR) China, India, Indonesia, Japan, Lao People’s Democratic Republic, Malaysia, Maldives, Mongolia, Nepal, the Philippines, Singapore, Sri Lanka, Thailand, Timor-Leste and Viet Nam. Participants reviewed progress and refined proposals using the WHO Service Package Delivery and Implementation (SPDI) Platform. Countries conducted bottleneck analyses across four key areas: service delivery, workforce, access to essential medicines and health products, and health financing. They identified practical actions to address implementation challenges and refined proposed revisions to their national oral health benefit packages. “There is no health without oral health. Through the 100-Day Sprint, countries are advancing the implementation of the Western Pacific regional implementation plan on oral health and strengthening progress towards universal health coverage,” noted WHO Regional Director for the Western Pacific Dr Saia Ma'u Piukala. Participants identified bottlenecks and proposed workable solutions to strengthen access to essential oral health care through primary health care, sharing experiences and discussing how best to translate policy commitments into feasible and sustainable action at the country level. Malaysian Minister of Health Datuk Seri Dr Dzulkefly Ahmad highlighted the importance of prevention and primary health-care approaches to improve oral health: “Oral diseases can have lifelong consequences, yet many are preventable. By integrating essential oral health care into primary health care and promoting prevention in schools and communities, we can improve oral health across the life course.”The WHO team led by Dr Huong Tran, Director of the Division of Health Promotion, Disease Prevention and Control of the WHO Western Pacific Region and national oral health leads from over 20 Asian countries visited the SK Pekan Putatan School, Sabah for school oral health programme including flouride mouth rinsing. © WHO / V. ChaudharyDr Huong Tran, Director of the Division of Health Promotion, Disease Prevention and Control for the WHO Western Pacific Region, emphasized key collaborative roles WHO can play. “Oral diseases are the most common noncommunicable diseases, yet many can be prevented and treated through essential oral health services delivered at the primary health-care level,” she said. “By sharing experiences and using WHO tools such as the SPDI Platform, countries are accelerating progress towards universal health coverage for oral health.” “Integrating oral health into broader health services is essential for reducing inequities, expanding access and recognizing oral health as an integral component of overall health and well-being. The 100-Day Sprint provides an important opportunity to translate this commitment into practical action and ensure that quality oral health services reach all people, especially those most in need,” said Dr Suman Rijal, Director of the WHO South-East Asia regional Department of Healthier Populations and Noncommunicable Diseases. As host of the meeting, Malaysia showcased ongoing efforts to strengthen oral health care through primary health care and prevention-focused approaches, while providing a platform for countries across the two WHO regions to exchange experiences and accelerate progress towards universal health coverage for oral health. “WHO is encouraged by Malaysia's leadership in addressing the burden of oral diseases and advancing universal health coverage for oral health through practical, country-led action,” said Dr Rabi Abeyasinghe, WHO Representative to Malaysia, Brunei Darussalam and Singapore. Countries will continue to refine and figure costs for national oral health benefits during the remaining sessions of the 100 days. These efforts support implementation of the WHO Global strategy and action plan on oral health 2023–2030, while also helping to expand access to essential oral health services through stronger and more equitable health systems across the WHO Western Pacific and South-East Asia regions.______________For more information, or to arrange media interviews, contact: WHO Regional Office for the Western Pacific: wprocom@who.int WHO Regional Office for South-East Asia: SEMediaRelations@who.int
Mail mystery: Astoria businesses, City Hall report spotty delivery, missing packages
Inconsistent mail delivery in Astoria has attracted the attention of Oregon's U.S. senators, especially as midterm elections near.
Davids Fights Washington Healthcare Cuts with Plan to Lower Costs, Protect Kansas Hospitals
WASHINGTON, D.C. — Today, U.S. Representative Sharice Davids (KS-03) introduced a comprehensive package of healthcare legislation that directly counters Washington’s recent healthcare rollbacks, which are increasing monthly costs and closing rural hospitals. Davids’ efforts would protect Kansas families from rising medical costs, block new federal red tape, and keep local hospitals and health clinics open.
Countries race to provide oral health care for all in 100-Day Sprint across Asia
Twenty Asian countries and areas across the WHO Western Pacific and South-East Asia regions vowed to strengthen essential oral health benefits as part of a “100-Day Sprint” initiative, during the 16th Asian Chief Dental Officers Meeting held from 27 to 29 September in Kota Kinabalu, Malaysia. The meeting marked the midpoint of the 100-day sprint bolstering support for countries to develop essential oral health benefit packages that can be integrated into national universal health coverage plans. Convened by the two WHO regional offices and the Malaysian Ministry of Health as the Secretariat, the meeting brought together national oral health leaders from 20 Asian countries, staff from all levels of WHO, WHO collaborating centres and other development partners. Participating countries and areas included: Bangladesh, Bhutan, Brunei Darussalam, Cambodia, China, Hong Kong (SAR) China, India, Indonesia, Japan, Lao People’s Democratic Republic, Malaysia, Maldives, Mongolia, Nepal, the Philippines, Singapore, Sri Lanka, Thailand, Timor-Leste and Viet Nam. Participants reviewed progress and refined proposals using the WHO Service Package Delivery and Implementation (SPDI) Platform. Countries conducted bottleneck analyses across four key areas: service delivery, workforce, access to essential medicines and health products, and health financing. They identified practical actions to address implementation challenges and refined proposed revisions to their national oral health benefit packages. “There is no health without oral health. Through the 100-Day Sprint, countries are advancing the implementation of the Western Pacific regional implementation plan on oral health and strengthening progress towards universal health coverage,” noted WHO Regional Director for the Western Pacific Dr Saia Ma'u Piukala. Participants identified bottlenecks and proposed workable solutions to strengthen access to essential oral health care through primary health care, sharing experiences and discussing how best to translate policy commitments into feasible and sustainable action at the country level. Malaysian Minister of Health Datuk Seri Dr Dzulkefly Ahmad highlighted the importance of prevention and primary health-care approaches to improve oral health: “Oral diseases can have lifelong consequences, yet many are preventable. By integrating essential oral health care into primary health care and promoting prevention in schools and communities, we can improve oral health across the life course.”The WHO team led by Dr Huong Tran, Director of the Division of Health Promotion, Disease Prevention and Control of the WHO Western Pacific Region and national oral health leads from over 20 Asian countries visited the SK Pekan Putatan School, Sabah for school oral health programme including flouride mouth rinsing. © WHO / V. ChaudharyDr Huong Tran, Director of the Division of Health Promotion, Disease Prevention and Control for the WHO Western Pacific Region, emphasized key collaborative roles WHO can play. “Oral diseases are the most common noncommunicable diseases, yet many can be prevented and treated through essential oral health services delivered at the primary health-care level,” she said. “By sharing experiences and using WHO tools such as the SPDI Platform, countries are accelerating progress towards universal health coverage for oral health.” “Integrating oral health into broader health services is essential for reducing inequities, expanding access and recognizing oral health as an integral component of overall health and well-being. The 100-Day Sprint provides an important opportunity to translate this commitment into practical action and ensure that quality oral health services reach all people, especially those most in need,” said Dr Suman Rijal, Director of the WHO South-East Asia regional Department of Healthier Populations and Noncommunicable Diseases. As host of the meeting, Malaysia showcased ongoing efforts to strengthen oral health care through primary health care and prevention-focused approaches, while providing a platform for countries across the two WHO regions to exchange experiences and accelerate progress towards universal health coverage for oral health. “WHO is encouraged by Malaysia's leadership in addressing the burden of oral diseases and advancing universal health coverage for oral health through practical, country-led action,” said Dr Rabi Abeyasinghe, WHO Representative to Malaysia, Brunei Darussalam and Singapore. Countries will continue to refine and figure costs for national oral health benefits during the remaining sessions of the 100 days. These efforts support implementation of the WHO Global strategy and action plan on oral health 2023–2030, while also helping to expand access to essential oral health services through stronger and more equitable health systems across the WHO Western Pacific and South-East Asia regions.______________For more information, or to arrange media interviews, contact: WHO Regional Office for the Western Pacific: wprocom@who.int WHO Regional Office for South-East Asia: SEMediaRelations@who.int
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New evidence in the Secretary-General's report to the 81st UN General Assembly, prepared by the World Health Organization (WHO) in coordination with the UN system, finds more countries acting on healthy ageing than ever before – but longer lives will not become healthy, dignified ones without faster, more sustained investment at country level.(NEW YORK, 28 September 2026) The Secretary-General transmitted to the 81st session of the UN General Assembly the mid-term progress report on the UN Decade of Healthy Ageing (2021–2030), marking the midpoint of the ten-year global effort to improve the lives of older people. The report was prepared by the World Health Organization (WHO) in coordination with the UN Inter-Agency Group on Ageing and with inputs from thirteen UN entities, the World Bank Group and civil society partners. It finds real progress in countries – and persistent gaps that must close before 2030.The number of people aged 60 and over passed 1 billion in 2020 and is projected to reach 2.1 billion by 2050, with the fastest growth in low- and middle-income countries. Longer lives are not automatically healthy ones: globally, the gap between life expectancy and healthy life expectancy at age 60 widened between 2000 and 2023, and an estimated 71% of excess deaths from COVID-19 between 2020 and 2023 were among people aged 60 and over. “Longer lives are one of humanity’s great achievements, but we cannot congratulate ourselves while leaving millions without health and support,” said Dr Pascale Allotey, Director, Department of Sexual, Reproductive, Maternal, Child and Adolescent Health and Ageing, WHO. “The first half of the Decade has shown what is possible. The second half must be about scaling and financing the progress to meet the needs and rights of older persons.”Real progress, unevenly sharedThe report finds that more countries than ever now have legislation against age-based discrimination – up from 44.5% in 2018 to 57.7% today – and over half now have national long-term care policies, up from 49% in 2023 to 56.7%, dedicated programmes to build age-friendly environments (54.6%), and comprehensive health and social assessments of older people (54.6%). New WHO guidance on services for long-term care and for Integrated Care for Older People (ICOPE) delivered in communities is enabling systemic change as an increasing number of countries incorporate these services within national universal health care benefit packages. A host of UN agencies and other partners support training, increasing health workforce competencies and use of digital health tools.“This report shows the Decade of Healthy Ageing is working,” said Dr Ritu Sadana, Head of the WHO Secretariat for the UN Decade of Healthy Ageing. “More countries are legislating against ageism, providing integrated care, strengthening long-term care systems, and creating age-friendly environments than ever before, in all regions and income levels. But progress is uneven and in one area, regressive: fewer countries report active multi-stakeholder forums on ageing, down from 53.1% in 2020 to 43.3% today. The second half of this Decade must turn commitments into results, in every country.”The financing gap: this Decade's binding constraintFinancing remains the binding constraint: more than a third of reporting countries (33.8%) have very little or no dedicated resources to develop long-term care, with similar shortfalls across the Decade’s other priority areas. Less than half of countries (45.4%) have legislation providing access to assistive devices (including hearing aids, spectacles or rollators), which are key to enabling older people to maintain productive, independent and dignified lives. Only 22.7% of countries can track older people’s health over time – the largest gap across the Decade’s core progress indicators. Nationally representative information is needed in each country, as policies and interventions cannot be designed as if all older adults of a given age share similar needs and capacities. The report calls for sustained investment through national budgets, country-owned plans, development cooperation and innovative financing mechanisms to fully close these gaps by 2030.“The Decade was designed as a whole-of-UN effort, and this report shows it in action,” said Amal Abou Rafeh, Chief of the Programme on Ageing Section at the UN Department of Economic and Social Affairs (UN DESA), and Permanent Co-Chair of the UN Inter-Agency Group on Ageing. “Thirteen UN entities, the World Bank group and civil society organizations contributed to this report, with WHO as the lead technical and implementing agency. That is the model of coordination the second half of the Decade will need to scale, with countries leading legislation, funding and implementation, engaging older people.”“Investing in healthy ageing is not simply a cost; it is one of the highest-return investments a government can make,” said Fiona Stewart, Global Lead for Ageing and Pensions at the World Bank Group. “Countries that invest early in integrated and long-term care see savings that outweigh the upfront cost many times over. The evidence in this report makes the economic case; what is now needed is predictable financing at country level to act on it, along with efforts to support older entrepreneurs and the silver economy.”Older people's own voicesThe report also draws on the direct experience of older people themselves, including a multilingual global survey conducted by the International Federation on Ageing that reached more than 1000 older people across 58 countries. WHO and UN partners called on Member States to use the second half of the Decade to accelerate implementation, strengthen data systems, and secure the financing needed so that the gains of longer lives reach older people everywhere. About the UN Decade of Healthy Ageing (2021–2030)Proclaimed by the UN General Assembly in December 2020, the Decade is a global collaboration bringing together governments, UN agencies, civil society, the private sector, academia and older people themselves to improve the lives of older people, their families and communities. It is coordinated by the World Health Organization together with the UN Inter-Agency Group on Ageing. The Decade's mid-term progress report was transmitted to the General Assembly by the Secretary-General, prepared by WHO, and is available in 6 languages.Full Report available: A/81/366 Implementation of the United Nations Decade of Healthy Ageing (2021–2030): Note by Secretary-General [ العربية | 中文 | English | Français | Pусский | Español
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Woman says a political canvasser stole an Amazon package from her porch
A Maine woman said a political canvasser stole an Amazon package containing running shoes from her front porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
Package stolen by political canvasser
Caught on camera: A Maine woman says a political canvasser stole an Amazon package from her porch.
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