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A big step forward for optical core of China’s Taiji gravitational wave project
A detector that will form part of a 3 million km-long triangular ruler has passed ground tests.
Corning Stock Climbs On Multibillion-Dollar Verizon Network Deal
Corning stock rose after the provider of optical communications gear for telecom networks announced a multi-billion agreement with Verizon.
AI can now 'see' optical illusions. What does it tell us about our own brains?
Our eyes can frequently play tricks on us, but scientists have discovered that some artificial intelligence can fall for the same illusions.
The Hasselblad In Your Pocket: Oppo’s Find X9 Ultra Challenges The Galaxy S26 Ultra
The latest phone from Oppo includes dual 200MP Hasselblad cameras and a 10x optical telephoto lens. But it doesn’t come cheap.
Oppo announces the Find X9 Ultra with a 50MP 10x optical zoom telephoto camera
The Find X9 Ultra’s main camera is a 200-megapixel sensor. At 1/1.12 inches, Oppo says it’s the largest 200MP sensor in a phone yet, but the 10x optical zoom telephoto may be the star.
Marvell's AI Business Is Booming. Photonics Could Be Next
Data-center revenue jumped 46% as Marvell positions itself for a shift from copper connections toward faster optical technology.
Scientists create optical skyrmions using a two-century-old light phenomenon
Nanyang Technological University, Singapore (NTU Singapore) scientists have used a classic optical phenomenon known as the Poisson spot to create stable patterns of light called optical skyrmions, which ...
Butterfly wings create dazzling optical illusions
Their many intricate wing patterns baffle predators.
iPhone Duo Has Similar Main Camera to iPhone 17e
Apple's tech specs suggest the iPhone Duo's Main camera sensor is seemingly a match for the iPhone 17e's, not the standard iPhone 17's. According to Apple's tech specs page for the iPhone Duo, the Main camera is a 26mm, ƒ/1.6 sensor with sensor-shift optical image stabilization and Hybrid Focus Pixels, also enabling a 12MP 2x Telephoto crop from the same sensor.
Apple Watch Ultra 4 Could Get Redesign and Blood Pressure Monitoring
The Apple Watch Ultra 4 could feature a complete redesign and blood pressure monitoring, according to DigiTimes. Apple will apparently add a new high blood pressure notification feature to the Apple Watch that uses the optical heart-rate sensor on the back of the device to analyze how blood vessels respond to each heartbeat, sending alerts when an abnormal pattern is detected. The feature is said to be under FDA review.
Oppo Find X9 Ultra debuts with dual 200MP cameras and 10x optical zoom
It is powered by the Snapdragon 8 Elite Gen 5 chipset. After weeks of teasers, the Oppo Find X9 Ultra is now official. Oppo unveiled its latest cameraphone...
Interpretable AI in materials discovery: Uncovering how models make predictions
A method to interpret artificial intelligence (AI) models used in materials discovery by analyzing their learned features has been developed by researchers from Japan. The method extracts key features from an AI model trained on atomic structural data and optical absorption spectra, and then groups materials with similar structural and spectral characteristics. This approach can be extended to reveal how atomic arrangements influence other material properties, paving the way for more efficient materials design.
Optical Vortex Phase Masks for the Detection of Habitable Worlds
A team of NASA researchers is developing new types of optical masks that could help enable the many orders of magnitude of starlight suppression needed for future space observatories to pick out very faint habitable exoplanets from the far brighter glare of their stellar hosts.
This strange crystal acts like metal and glass at the same time
A remarkable crystal called molybdenum oxychloride could help make futuristic technologies like smart contact lenses and ultrathin AR glasses a reality. Scientists have created the first detailed experimental map of its optical properties, revealing the strongest light-bending effect ever measured in a natural material. The crystal can act either like a reflective metal or transparent glass, allowing it to manipulate light with extraordinary efficiency while being thousands of times thinner than a human hair.
Amendment 68: New Opportunity: D.8 Habitable Worlds Observatory Precursor Science Investigations
The Habitable Worlds Observatory (HWO) is a large-aperture ultraviolet/visible/near-infrared observatory concept recommended by the National Academies of
Interferometric scattering for optical tomoslicing of transparent solids
Light: Science & Applications - Interferometric scattering for optical tomoslicing of transparent solids
The shape behind the Einstein problem just revealed strange new physics
A mathematical shape famous for covering a surface without ever repeating has revealed an unexpected ability to twist light into unusual chiral patterns. The discovery could lead to new ways of controlling light, polarization, and advanced optical devices.
Japan switches on its first full-stack room-temperature quantum computer — and scientists plan to scale it up to 10,000 qubits
Japan's new quantum system, Shunkai, uses "optical tweezers" to trap and rearrange atoms, and will be available to researchers working on quantum error correction.
Scientists just sent unhackable quantum keys across 120 kilometers
Scientists have taken a major step toward ultra-secure quantum communication by demonstrating a remarkably stable quantum encryption system that worked across more than 120 kilometers of optical fiber. Using tiny semiconductor quantum dots that emit single particles of light on demand, the team achieved one of the highest secure key rates yet for this type of technology while maintaining continuous operation for over six hours without manual adjustments.
What Is The Black Drop Effect? How An Optical Phenomenon Frustrated Astronomers And May Have Changed Australia’s History
We don’t get to see it very often, but that makes it even more important when it happens.
Here’s the first 4K 120Hz UST projector with optical lens shift
Produces a 120-inch image on a wall from just 7.5 inches away.
Sony Already Invested $34 Million To Repurpose Its EU PlayStation Disc Factory
Sony is converting its PlayStation disc factory into a plant for optical microlenses.
Physicists discover a hidden “curveball” in quantum light
Researchers have experimentally demonstrated the optical Magnus effect for the first time, revealing that a tightly focused laser interacts most strongly with an atom slightly away from the beam’s center. The unexpected shift is similar to the physics that makes a spinning table tennis ball curve through the air. Because lasers are used to control qubits, the effect could create errors in quantum computers, but it might also provide a new way to couple qubits together.
SUNY Optometry’s Inaugural Advancing Vision Summit Explores the Future of Eyecare, AI, and Public Health
NEW YORK—The SUNY College of Optometry Foundation recently brought together leaders from across healthcare for its inaugural Advancing Vision Summit: The Intersection of AI, Eye Care, and Public Health, held September 25, 2026 at CURE in New York City. The day-long event marked the Foundation’s 70th anniversary and explored the growing role eyecare can play in preventive health, an announcement from SUNY said. Sponsors and supporters of the event included EssilorLuxottica, CooperVision, Jobson Optical Group, Alcon, NFP, NYC Health + Hospitals/Gotham Health, Allison & Stephen Flink, Haag-Streit, Marco Lombart, Lavelle Fund for the Blind, Designs for Vision and VSP.
Double-phase metasurface operators for all-optical image processing
Light: Science & Applications - We propose metasurface operators leveraging double-phase encoding and polarization multiplexing enable compact, all-optical analog computing for high-resolution...
Jonty Hurwitz brings mind-bending science, art, and optical illusions to Jerusalem
Jonty Hurwitz’s works are sculptures smaller than atoms and images created by cylindrical mirrors.
Disk Polishing Goes Open Source
Optical media is great — it’s pretty high density, relatively durable, and decently long-lasting if well cared for. If not well cared for, well, it’s only relatively durable, and …
Oh, Thank God: iOS 27 Fixes the Liquid Glass Optical Illusion That Broke My Brain
Sanity prevails.
Explore the science behind optical illusions at Orlando Science Center
Prepare to have your mind blown and your senses boggled with a dazzling new exhibit at Orlando Science Center. In "Phenomena: The Exhibition," visitors will gain a deeper understanding of the science behind illusions and the mechanisms that govern human perception. An interactive journey with over 20 stunning and immersive illusions, "Phenomena: The Exhibition" will
A 200-year-old physics experiment could help build future computers
Scientists at Nanyang Technological University in Singapore have discovered a surprisingly simple way to create exotic light structures called optical skyrmions using a 200-year-old optical effect known as the Poisson spot. Instead of relying on expensive, highly engineered materials, they simply shine a laser at a tiny circular disc, producing stable swirling patterns in light that researchers believe could one day help power advanced data storage, communications, and computing technologies.
You’ve never seen this before: the shocking moment the sound barrier breaks - Futura-Sciences
The XB-1 is a critical stepping stone toward commercial supersonic travel, representing the first civil designed aircraft to break the sound barrier since the Concorde retired. To verify the aircraft’s aerodynamic performance during its supersonic transition, NASA deployed an advanced optical technology called schlieren imaging to make the invisible forces...
Hyperbolic wave attractors could power next-generation optical chips
Scientists found a way to stop light and sound waves from scattering chaotically inside complex, oddly shaped spaces.
Orlando Science Center’s Science Night Live returns with illusions and games
Orlando Science Center's adults-only Science Night Live event returns with optical illusions, board games, trivia, and more. Don't miss out!
Making light spin with a gold nanorod
Controlling photon spin, or the handedness of light, is useful for storing and transmitting information. However, generating circularly polarized light typically requires complex or chiral structures. Researchers from the Tokyo University of Science show that hitting a gold nanorod slightly off-center with an electron beam causes the light around it to rotate. This method offers a simpler way to control photon spin and could accelerate the development of smaller, more efficient optical and quantum devices.
Semtech Enables 50G Optical Transition for AI-Driven 5G-Advanced
CAMARILLO, Calif.--(BUSINESS WIRE)--Sep 21, 2026--
Science Night Live brings adults-only fun to Orlando Science Center
Sip wine, explore optical illusions and try a penguin-inspired board game during this after-hours event.
Scientists sculpt Einstein onto a crystal using only light
A light-sensitive crystal is opening the door to a new era of “light-written” technology. Arsenic trisulfide can be reshaped and permanently altered using simple light, creating ultra-fine optical patterns without expensive manufacturing tools. Scientists even etched a nanoscale portrait of Einstein and high-density patterns that could act as secure optical signatures. This breakthrough could power everything from advanced sensors to next-generation AR devices.
Fluorescent nanosensor enables rapid, first-of-its-kind detection of key gut health biomarker
Researchers developed an optical nanosensor to rapidly detect a key gut biomarker, enabling faster, accessible screening for conditions such as inflammatory bowel disease, Type 2 diabetes, and liver disease.
I won't buy an Android phone in 2026 without this feature
The macro upgrade flagship phones ignore
Corning's deal with Meta should boost optical business: Morgan Stanley
Corning’s $6B Meta deal to supply optical fiber for data centers could lift GLW’s optical revenue and targets.
Vivoo's toilet computer keeps an eye on your hydration
It uses optical sensors to measure the specific gravity of your urine.
Stanford’s new chip boosts light 100x with surprisingly low energy
Researchers at Stanford have developed a compact optical amplifier that dramatically boosts light signals using very little power. By recycling energy inside a looping resonator, the device achieves strong amplification with minimal noise and wide bandwidth. Its efficiency and small size mean it could run on batteries and be integrated into consumer electronics. This breakthrough could enable faster communications and more powerful optical technologies.
UK mathematician debunks myth around Parthenon’s optical illusions
Study challenges belief that temple’s curves were designed to correct optical illusions that would have ruined its clean lines
First Xiaomi 17 Ultra Leica camera reviews, comparisons and hands-on: Tough times for Samsung Galaxy S26 Ultra and others
2026 will not only be a challenge for Samsung. The Vivo X300 Ultra and Oppo Find X9 Ultra will also have to face an extremely dynamic 1-inch sensor and the first optical 200MP zoom camera in a phone, a combination that convinces in early camera tests and comparison shots. Initial hands-on reports also illustrate the advantages of the Leica Leitzphone Special Edition for ambitious photographers.
Mathematician debunks the Parthenon’s famous optical illusions
Some of the 2,500-year-old Greek building's architectural tricks are virtually nonexistent.
NASA Space Telescope Maps Magnetic Fields of ‘Lighthouse’ Pulsar
For the first time, scientists have used NASA’s IXPE (Imaging X-ray Polarimetry Explorer) to directly measure the magnetic fields of PSR J1101−6101, a pulsar
Optical condensation using a fiber-based photothermal module
The system achieves about tenfold higher collection efficiency than conventional approaches, enabling the assembly of approximately 10,000 microparticles or bacteria in just 60 seconds.
Scientists Spin Molecules Inside a Frictionless Superfluid for the First Time
A newly designed optical centrifuge allows scientists to control molecular rotation inside superfluid helium nano-droplets. Physicists have developed a new version of an optical centrifuge that can control how molecules rotate while they are suspended inside liquid helium nano-droplets. The advan
Scientists teleport quantum states across 100 parallel optical channels
Quantum communication networks consist of several connected nodes that exchange information encoded in quantum states. These networks could potentially enable more secure communications between quantum ...
Phonons in Focus
Phonon lasers are used to trap and levitate nanoparticles in the laboratory of Nick Vamivakas, the Marie C. Wilson and Joseph C. Wilson Professor of Optical Physics at the University of Rochester. https://www.doi.org/10.1038/s41467-026-70564-3
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
Sony's PlayStation disc plant is losing 10 percent of its volume in 2028, not 90
Sony’s PlayStation disc plant is losing 10 percent of its volume in 2028, not 90 Sony won’t license disc pressing to anyone else, Microsoft does, and a former PlayStation boss thinks that’s the whole problem. When Sony DADC chief Dietmar Tanzer spoke with an Austrian broadcaster in July about PlayStation disc production at the Thalgau plant, a number of press outlets misunderstood the report, writing that production would fall to a tenth of current levels. It won’t. Sony DADC confirmed to Game this week that the figure is a 10 percent decline, not a decline to 10 percent. “To clarify and avoid any misleading information: in that statement Dietmar anticipated an overall product volume decline by 10 percent, not a decline down to 10 percent,” a spokesperson with Sony DADC told Game. That figure covers 2028. Tanzer didn’t put a number on the years after, and the spokesperson declined to comment further. What we do know is that on July 1, PlayStation announced that physical game disc production for all new games releasing on PlayStation consoles will be discontinued starting January 2028 and that the transition has no impact on games that have already released in disc format or will be releasing in disc format prior to that month. “So, there will be reorders going to the market after January 2028,” the Sony DADC spokesperson said. “For details around that I would ask you to liaise with the PR team from PlayStation, as we can’t speak or comment on their behalf.” PlayStation officials did not respond to questions about reorders or other disc-related matters. But I did recently speak with Shawn Layden, Game Industry Strategic Advisor and former chairman of SIE Worldwide Studios, who called a future without physical PlayStation discs “depressing, but solvable.” then added, “I think.” The chief hurdle to third-party manufacturing of collector’s editions or any other version of a PlayStation game disc is that Sony owns the proprietary process to press those discs, Layden said. “And unless they decide or determine a way to license that to some of these bespoke disc manufacturers, there’s no way to make it happen,” he said. Layden was careful to add that he understands the concept but doesn’t have “line of sight on the particulars.” “Depressing but solvable, I think.” — Shawn Layden Microsoft already licenses replication to outside plants. Xbox discs are pressed by manufacturers Microsoft certifies as Authorized Replicators, a term defined in its publisher agreements, with the approved list set at the company’s sole discretion and Microsoft retaining the right to halt manufacture. The structure is still in place today: publishers select an Authorized Replicator in Partner Center and submit a bill of materials created with a Microsoft representative. Sony, by contrast, presses PlayStation discs through Sony DADC, its own manufacturing subsidiary. No one I spoke with said they were in discussions with Sony about doing that, and PlayStation hasn’t responded to questions about whether it would be open to a licensing deal. There is an obvious reason Sony might not want to. Niko Partners analyst Daniel Ahmad pointed it out on the day of the announcement: it’s a platform-led decision, he wrote, designed to cut costs, eliminate the resale market, and drive all revenue through the PlayStation Store. The math is not subtle. On a $70 third-party game sold through the PlayStation Store, Sony keeps $21. Sold at retail, Ahmad says, it earns about half that. Licensing disc replication to an outside manufacturer might not be worth it. And even if it were, it seems unlikely that such a deal would come from boutique companies like iam8bit, which sells collector’s editions of video games. “We would absolutely love to find a way forward to continue making physical PlayStation games,” said Jon Gibson, co-owner and co-creative director of the company. “We are big believers in giving humans the option to truly own media. If we can play a role in helping make that a reality for the future of PlayStation games, count iam8bit in!” If it were to happen, it would most likely be with a company like Conectiv Supply Chain Solutions, a Memphis-based manufacturer of optical discs and vinyl records that also runs third-party logistics, fulfillment and distribution for packaged media. The company, which was formed in 2025 when Los Angeles private equity firm Variant Equity Advisors purchased Vantiva’s Supply Chain Solutions division, traces its lineage back to Technicolor. When it sold the division, Vantiva described the business as having served video game creators for more than 25 years. Conectiv is also buying, not shrinking. Last month it acquired SDS, the distributor for Universal and Warner Bros. home entertainment, consolidating those studios’ packaged-media pipeline from pressing plant to retail shelf. I reached out to Conectiv and its CEO, but haven’t heard back. Layden pointed to music and books in our discussion about the ongoing value of physical media. “No one ever saw the comeback of cassette tape,” he said. “And vinyl didn’t so much come back. The flame went down, the fire’s dying, but the ember was always there, and it just kind of came back. Much like the book business. We thought we’d all be on Kindles right now. “I believe that physical media is crucial and important. One of the things that makes us gamers, one of the core game mechanics, going back to the beginning of time, is collecting stuff. “Did you get all the diamonds in Crash Bandicoot? Did you get all the stars in Mario? And we like to collect our games. And we have a game shelf. And we put all our boxes up there. And if you’re super hardcore, when you buy a game, you buy two copies, right? One stays in the shrink wrap, and you play the other one. What happens to that important cultural part of the gaming world? You know, we buy the steelbook and the three-disc Final Fantasy set and the figurine and, you know, you can’t download any of that. “What happens to that?” And Layden believes it shouldn’t have been a revenue question for PlayStation. “This was a core thing to the experience of our most devoted fans,” he said. “Yeah, it’s fan service. Why would we take that away? Well, we can’t afford to. It’s already 120 bucks, you know, limited edition special purchase onyx box version of whatever, and those sell at a higher rate than the box selling at $69.99 does. So yeah, the market has said they will continue to buy them. You’re just saying you just don’t want to make them anymore.” Layden said he was recently talking with someone about these sorts of business decisions and how they’re made. Too often, he said, it’s all about the financials and nothing else. “OK, we can do this and save this much money, or we can invest this to look at that outcome, or we can do this and have this happen over there, or move this team to Sri Lanka,” he said. “But each one of those, someone also has to have a ledger there saying, ‘OK, what is the brand impact from that move?’ “Iif you can’t resell it, do you really own it?” — Shawn Layden “If we do that, dollars and cents work out. I get it. That’s just math. But what’s the brand impact? Are people going to say, ‘Good move, you guys?’ Or are they going to say, ‘We hate you guys. Quit doing that.’ And sometimes they say, ‘We hate you.’ Then you take a note and say, OK, how much of that can we live with? How much ‘we hate you’ is OK. And when does it go over the line? “I see a lot of companies making decisions which, objectively speaking, I don’t know what the dollar end of that was for you, Mr. Company, but your brand value just dropped 30 percent. So I hope it was worth it.” Of course, shifting to a digital-only model for games raises other issues beyond simply wanting to collect. The biggest is ownership. Layden pointed out that once you go to a streaming-only or download-only model, it’s just a digital footprint on a hard drive. “What does ownership mean anymore?” he said. “It’s a genuine question. Well, in fact, it’s not even a question anymore. It’s like you are shifting the model from ownership to accessibility. “And what’s always been true, which people forget, is you’ve never been able to sell your iTunes library. And you can’t sell your PlayStation download library. So if you can’t resell it, do you really own it?” The touching tribute found in the credits for Star Wars Zero Company. Resonance: A Plague Tale Legacy Interview and Hands-On with a Minoan Masterpiece Star Wars Zero Company hands-on: Attack Astromechs, permadeath, and delightfully fatal Rube Goldberg tactics Control Resonant opens up as you get stronger — and as characters start trusting you
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The Big Holes in Wearable Heart Rate Variability And Readiness Scores
On September 9th, Apple announced it was revamping its Apple Watch Health Sensing System, rolling out a Readiness score (0 to 10), and increasing the frequency of heart rate variability (HRV) outputs 24-fold. This can be viewed as upping its competition with various other consumer wearable sensors. These “readiness scores” as a composite of multiple metrics, with heart rate variability (HRV) being front and center for most. The majority of Americans are now using wearable sensors, which equates to well over 100 million adults. HRV and Readiness scores are increasingly being marketed as a measurement of autonomic nervous system health, a digital marker for future disease, a clock for biological age, and a holistic metric to promote healthspan and even longevity. (Apple also introduced a new longevity tab and “Health Age”.) None of this has been proven. In this edition of Ground Truths I am going to review what we know about heart rate variability and readiness scores. Heart Rate Variability HRV is the variation in normal heart cycle timing. The variability of the heart rate, the barely perceptible millisecond changes in time between consecutive heart beats (see R-R intervals in the Figure below, left panel), is due to interplay between the sympathetic and parasympathetic (vagal nerve) inputs. Distinct from heart rate, individuals with the same heart rate can have very different HRVs. It is a rough reflection of the autonomic nervous system (ANS) activity, inadequate to say whether a person’s ANS function is abnormal. For more than three decades, heart rate variability (HRV) has been measured and several studies have found an association of low HRV and clinical outcomes, particularly a link with higher all-cause and cardiovascular mortality. There have also been less well established links of low HRV to risk of early cognitive impairment, dementia, mental illness, Type 2 diabetes and substance abuse. An important reminder is that HRV is a surrogate marker without any established cause-and-effect relationship. If you increase your HRV, that doesn’t mean it will improve health outcomes. In fact, there is no hard evidence for that. All that work linking to health outcomes was done with electrocardiogram (ECG) derived HRV. Now, in the era of consumer wearables, this is getting assessed differently, by optical pulse (yes, the lights you see) plethysmography (PPG) or what is called pulse rate variability (PRV). They are not the same, as shown below (right panel) and only concordant when the delay between the ECG and pulse is kept constant, which basically means at rest. I should mention there’s also what I will call MPV, a mattress mechanical movement sensor, a derived heart rate variability, that companies like Eight Sleep use, even further away from directly measuring HRV. HRV has not one uniform measurement but many different types of quantification, such as RMSSD, the magnitude of difference between successive R-R intervals of normal sinus beats (N-N) or SDNN, the standard deviation of NN intervals, both in milliseconds. SDNN is one of the so-called frequency domain HRVs (others are LF, HF, LF/HF). Different wearable sensors use different metics; Apple has relied on SDNN and nearly all of the others use RMSSD, which is generally considered the more accurate metric. There’s also the different length of time measured, such as for a matter of minutes, all day, or an overnight’s sleep. Short measurements are especially problematic since they don’t capture enough of respiratory modulation and other factors that influence HRV. Share Ground Truths How well does HRV correlate with PRV? There are very limited studies, especially independently done. One that is commonly cited was conducted by Air Force researchers in only 13 healthy adults assessing Oura ring 3 and 4, Whoop 4.0, and Garmin Fenix 6 and showed a correlation coefficient of 0.88 to 0.97 and a mean absolute percentage error from 6 to 10%. The correlation is not a perfect 1.0, but there’s at least a fairly high level of correlation. HRV is supposed to increase during the night due to takeover of the parasympathetic nervous system, and higher during deep sleep. A recent example of my 1 week, all day “HRV,” and one during sleep is shown below. As you can see, the N of 1 data are inconsistent for the same days from different sensors (Oura, AppleWatch, Fitbit Air, and Eight Sleep) by patterns, absolute numbers, and comparison with prior days and weeks. The largest study in over 8 million Fitbit users (the old version, not Google Fitbit Air, introduced in May 2026) gives you a sense of the effect of age, sex, and the 2 different main HRV (here PRV) metrics, with RMSSD on the left and SDRR (=SDNN) on the right below. That study, from data collected in 2018, is a major outlier, since all the more recent ones are tiny with respect to sample size. Many of the companies have not had independent evaluation of their HRV, such as Eight Sleep, but have published a low standard error on their website. There are some other published studies on the correlation between HRV and PRV, but they are all small and only in healthy adults. A scoping review emphasized the lack of study in underrepresented individuals, including the aged, people of color (which affects the PPG signal), and individuals who are underweight or obese. Add the typical adult age 60 plus with one or more chronic diseases. For example, one study in over 900 adults found poor correlation of HRV and PRV, non-uniformly underestimated across many chronic diseases (cardiovascular, endocrine, neurological, respiratory, and others), concluding PRV is “an invalid surrogate for HRV.” A recent systematic review of 43 studies comparing HRV and PRV found reasonable pooled absolute standardized error (HRV as gold standard) but only 10 of the studies provided quantitative synthesis in ideal conditions. Their main conclusion was similarly cautious: “PPG-derived HRV [PRV] should not be regarded as universally interchangeable with ECG-derived HRV across all devices, populations, and recording contexts.” Factors Affecting HRV and PRV That gets me to the long list of factors that affect HRV (and PRV) besides the device, the type of measurement (RMSSD, SDNN or others), the person’s signal, the sensor site, the duration of data capture, if weighting by sleep stage is used, how artifact is processed and corrected. And this list is not complete!: Oura puts out data from their community of users (who input data) on what affects their overnight HRV. The factors currently provided are: no alcohol (increase 8%), melatonin (increase 2%, float tank (increase 2%), wine (decrease 4%), and party (decrease 14%) in overnight HRV. Must be some big parties! Subscribe What is a PRV measurement good for? It has been falsely characterized as an index of “autonomic balance” and a specific indicator of stress. A 2018 review of the studies available for HRV and its relationship to stress, not using any of the current wearables, found that stress can lower HRV. But so can many other factors. The non-specificity of the signal, indexed to the table above, is striking. Evidence from a UK Biobank study of over 46,000 participants with actual HRV looked at genetically predicted HRV, a genetic risk score, that failed to show the expected HRV-mortality link, indicating that _HRV is likely not causa_l, but rather a reflection of person’s physiologic state. A review of consumer wearable HRV data from 5 longitudinal studies showed that nighttime PRV was not associated with perceived stress, and surprisingly higher HRV, in the largest cohort (N=717 participants), was correlated with higher stress. An Oura ring cohort of 525 first-year college students found a link between overnight PRV and perceived stress, but that was also seen with resting heart rate, sleep, and respiratory rate. Several very small studies have examined the relationship of HRV and athletic injuries or guiding training with mixed, and predominantly negative results. HRV biofeedback training with paced breathing had no significant effect on reducing stress or raising HRV, as demonstrated with sham controlled trials. When HRV for multiple days showed a decline in conjunction with body temperature, the Oura ring published data for prediction of Covid. The WHOOP company sponsored an observational study, published in 2026, of 30,000 users for 72 weeks, without a control group, that reported reduced alcohol intake (5.8 % points) by self-report. That doesn’t tell us much, and particularly about the merits of HRV for behavioral change. If you use the same device and conditions as longitudinal trends for multiple (at least 2-3) weeks that may be the one way to get something useful from the measurements. Data for overnight sleep with minimal motion and using RMSSD is the best proxy for real HRV. The reason to look at trends rather than any given night is that it more likely represents something, even though you won’t know with certainty what the “it” is. Keep in mind there are no data, no peer-reviewed evidence, to show that HRV fluctuation in-person has any correlation with health outcomes. Share Readiness Scores These are proprietary scores that integrate different metrics for each of the wearables: no algorithms have been disclosed. They are unvalidated against health outcomes. In a review of 14 composite health scores of readiness and recovery, HRV contributed 86% to the scores, followed by reading heart rate (79%), physical activity and sleep duration (both at 71%). That review noted the substantial variability in measurement protools and lack of standardization. Sleep staging is notoriously inconsistent and inaccurate by these sensors, which adds further to the HRV uncertainties for what the scores, which use sleep stage data, mean. Only resting heart rate has been shown consistently across devices to be extremely accurate. I’ve made a Table to summarize what we know about which metrics are included, the scores, any peer-reviewed studies that compared the readiness score with health outcomes, and the corresponding (if any, NA-not available) citation. You will note that some companies do not use the term “readiness," such as WHOOP for recovery, and Garmin, which has 2 different scores, one of which is Body Battery. Eight Sleep uses the term “Fitness Score.” They all include HRV; Apple includes a new metric they call “Recovery HRV” which among other components uses 7-days of sleep, but it is unclear what this means or how it is differentiated from other scores (there are clearly no data for outcomes). We have no knowledge of how the different components are weighted or whether any of these scores are better than resting heart rate, HRV alone, physical activity, or any other single metric. Since none of these are standardized, they are not interchangeable, so if you get a 90 for Oura that has no relationship to a 90 on a Google Fitbit Air. Notably, the company can update its algorithm for readiness score at any point without notification to device users. Without any useful evidence of actionability for these scores or established relationship with health outcomes, it is hard to make a case for their value. At the Apple recent announcement they showed their Readiness score (0-10) on the watch (Figure below) but there are no published data on this score, not even on their website. It’s available only on their new Watch Series 12 or Ultra 4 [of course, ;-)]. That exemplifies the problems with these scores, lack of data and evidence for being meaningful to promote health. Perhaps the best study (which isn’t saying much) is the WHOOP Recovery for golfer performance, because it did correlate with an objective outcome, even though there was no control group and the authors were all from the company. Among the 389 pro golfers, an absolute 10-per cent point increase in Recovery score was associated with about 0.5 fewer strokes per round. But that’s hardly a health outcome! WHOOP is also conducting a study in over 2,700 runners to see if their recovery score will be linked to less injuries and improved performance, but that is not yet published and has no control group or randomization. Putting This in Context For two decades I’ve been enthusiastic about the potential for digital health and particularly wearable biosensors. Over the years, we’ve seen some great progress for their ability to promote physical activity and accurately detect atrial fibrillation (the first FDA cleared deep learning AI for consumers). That work was the subject of rigorous research. But there are holes in the data and evidence for other metrics. One notable one is the “VO2 max” story that I wrote about earlier this year. At that time many subscribers asked me to cover heart rate variability, which I finally got to here. When I dived into the research and publication for HRV and readiness scores, I expected to find at least some that were of high quality and demonstrated their utility by linkage to health outcomes. To my surprise, I found none. The wearable sensor measurements for HRV (PRV) are, for the most part, accurate, but that validation work has only been done in small studies of healthy adults and does not take into account the long list of factors, from the device, software side, and the user side, that affect HRV measurements. Moreover, this metric chiefly relies on optical sensing and, as we have learned for heart rate PPG sensing, may be less accurate in people of color. Keep in mind that all of the health outcome association evidence comes from ECG-derived HRV; none are from wearable sensor data. I will repeat the key point: there's no peer-reviewed evidence to show that in-person HRV fluctuation—or efforts to raise your HRV— has any correlation with health outcomes. For those of you who look at your HRV on awakening, or even 2+ week trends of it being low, I hope this context helps to relieve any anxiety. Yes, low HRV (not PRV) has been shown to increase risk of some diseases as summarized above. But efforts to raise your HRV—a surrogate metric— has not been established for improving any health outcomes. HRV does not have any evidence of causality (the genetic evidence actually goes against this possibility). In this summary, I have not included data for other wearable sensors such as Polar, Samsung, Withings, Suunto, Amazfit, Coros, Ultrahuman, or additional mattress sensors. These are beyond my first-hand experience, and as far as I know from my in-depth review none have any peer-reviewed published data that differ from the 6 sensors I’ve reviewed here. From the points I’ve gone over above, we’re not ready for readiness scores. Besides being proprietary, they are predominantly based on metrics that have their own issues. It’s compounding the problem, like building a house without a solid foundation that has never undergone a rigorous inspection, and then selling it. Like I mentioned for PRV, you can look at trends over weeks rather than any single day, to get a handle, but even that may not be helpful. There’s simply no evidence that these scores meaningfully relate to health outcomes. I’d emphasize they might, but that requires doing prospective or randomized studies to prove it. None exist. There’s great promise for HRV/PRV utility_. For example**,**_ Prof Maiken Nedergaard, who discovered the brain glymphatics that are essential in eliminating metabolic waste products from the brain during sleep, has posited that HRV could be a non-invasive marker for neuromodulator oscillations, brain-body regulatory circuits, and brain clearance. That would be extremely useful, but like everything else on HRV and readiness scores it requires solid research and validation. The lay media isn’t helping much to get the story straight. Earlier this year The Economist published a piece entitled “The most useful indicator of your overall health” which ordained HRV as an “accumulated stress score.” That’s akin to the false assertion about VO2max: “V02 max is the singular most powerful marker for longevity.” As I’ve summarized here, that is not established. The fact is that so many things can lower HRV, including physical exercise (especially an intense workout), reduced sleep quality, stress, the list above, no less the device, signal, and software. Whatever fluctuations observed have not been correlated with any health outcome. Sadly, “datamaxxers” are widely using HRV and readiness scores that have never been validated to mean anything. We already know that for some people using the sensors for sleep metrics, it can induce “orthosomnia,” an obsession to get high sleep quality, with associated high levels of anxiety. In an experiment done by a company to promote sleep quality for its employees, “For those employees who did use the trackers, many reported feeling perfectly rested until their tracker told them they had had a terrible night. Others were told that they had slept like a baby when they had actually been lying awake worrying about the quality of their sleep. “ The same problem can result from preoccupation with HRV or readiness scores, with anxiety that would lead to further reduction in both. It you are using a wearable like >100 million American adults, it’s OK to look at these data, but contextualized with the major caveats reviewed here. If you are one to require evidence that HRV or readiness scores are linked to health outcomes, you may not even want to look. The companies make it hard to turn them off! Let me end with the companies that make and sell wearables. Apple’s doubling down on HRV (24-fold more reporting and heart rate very 5 seconds) and introduction of a Readiness score tells us that consumers have bought into these metrics and they are joining the club. However, all of this is occurring with a backdrop of tens millions of users, claims about the data that are not backed up by adequate evidence, marketing way out in front of whatever limited data exists, and not being transparent about their readiness score algorithms. The companies can well afford to do the research that is needed to connect these metrics with health outcomes show, once and for all, that increasing HRV or using readiness scores promotes our health. If they believed and invested in the products they are selling, we’d not be in this position of not knowing. That’s essentially where we are with HRV and readiness scores. Perhaps someday this will change and we’ll have good reason to embrace them. NB: I wrote this post. No AI. I have no conflicts of interest with any of its content. Loading... Ground Truths has 215,000 subscribers from every US state and 214 countries. There are over 300,000 followers of Ground Truths so more than 90,000 folks who can easily convert to be free subscribers. Your subscription to these free essays and podcasts makes my work in putting them together worthwhile. If you’re not a subscriber, please join! If you found this interesting PLEASE share it! Share Ground Truths The proceeds from all voluntary paid subscriptions go to support our summer internship program. It enabled us to accept and support a record number of 62 summer interns that joined us in 2026! These are high school, college and medical students selected from thousands of applicants. We couldn’t do this expanded program without the funds coming in through Ground Truths. Thank you!
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