SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " matching " 100 found 🔀 AI-powered Shuffle
Sign in to save shuffle history.
Bruce Blakeman sues state board over denying him public campaign matching funds
The state Public Campaign Finance Board recently voted 4-3 on a resolution that disqualifies Blakeman from the program over a technicality.
Raptor discovery in Argentina points to prehistoric links with China
Unearthed on opposite sides of the world, fossils of Kank australis and velociraptors sport matching claws, revealing evolutionary ties.
Hobart and William Smith Colleges gets $3 million for science center
GENEVA — Hobart and William Smith has been awarded a $3 million Higher Education Capital Matching Grant Program grant from New York State to support the next phase of the
How AI can improve patient access – beyond simply filling the next open slot
More precise navigation can improve provider matching, shorten time to intervention and help health systems measure whether digital access actually works.
Bronco Women’s Sports Programs Gifted $30K from Maddyn Homes Matching Gift Initiative
Bronco Women's Sports Gifted $30K from Maddyn Homes Matching Gift Initiative EmpowHER Play fuels the future of female athletes at Boise State and beyond
How small businesses can find qualified employees fast
From targeted job descriptions and proactive recruiting to AI-powered matching, ZipRecruiter can help small businesses find qualified candidates and hire faster.
Brewers' Chourio in Same Conversation as Trout, Rodriguez
By matching the historic early-career power and speed of legendary icons, Milwaukee Brewers' young phenom Jackson Chourio is already cementing his place among baseball’s elite.
Green Bay Packers Quietly Built One of NFL’s Best Advantages
The Green Bay Packers spent much of last season making third down easier than it looked.According to analytics expert Warren Sharp, Green Bay ranked fourth in the NFL with an average of 6.4 yards to go on third down.The Packers finished behind the Los Angeles Rams and Buffalo Bills, while matching the San Francisco 49ers […] The post Green Bay Packers Quietly Built One of NFL’s Best Advantages appeared first on HEAVY.
Gunther Werks Built Its Fastest 911 Yet Without A Single Turbo
Only 15 buyers will get this analog Porsche, and each one comes with a matching carbon racing simulator
Apotex Gets Health Canada Approval for Generic Semaglutide
Apotex receives Health Canada approval for generic semaglutide injection, matching all commercial formats of Novo Nordisk's Ozempic for type 2 diabetes treatmen
The Elite 8 begins, plus Tiger’s arrest
Good morning! Make every 0.4 seconds count today. Inside: 📚 Elite 8 storylines 🔢 Hannah Hidalgo did what? Woods arrested after crash Elite Company: Madness, condensed Today, the men’s Elite Eight begins. We considered assembling a matching number of storylines, but the Elite Eight is all about reaching the Final Four, so let’s go with four instead. That might not make total sense, but March is for Madness. Bracket status: The No. 1 seeds: Arizona is the slight favorite per BetMGM. Duke entered t
Worcester Six business park misses 5,000 new jobs target
Brexit and the pandemic are cited as factors behind the Worcester park not matching expectations.
Intel Core Ultra 7 270K Plus Review - Intel's Fastest Gaming CPU
The Intel Core Ultra 7 270K Plus is a game-changer, featuring more cores and larger cache than the 265K, while cutting the launch price to just $300. In gaming, it outperformed all non-X3D Ryzen CPUs, and application performance is impressive as well, matching the much pricier Ryzen 9 9950X.
Capitol Hill Lutheran Church receives $500,000 grant for historic restoration
Capitol Hill Lutheran Church in Des Moines was given a $500,000 matching grant from the National Fund for Sacred Places to support restoration of its historic tower and steeple. The church, established in 1886, is one of 30 congregations nationwide selected to share more than $9.1 million in funding this year. The National Fund for…
Could Prediction Markets Be a New Hedge Against Business Risk?
Could prediction markets become a new tool for managing business risk? Event-based contracts may help firms hedge revenue uncertainty, but success depends on accurately measuring exposure, matching risks and avoiding conflicts of interest.
Parker Solar Probe Makes 28th Close Pass of Sun
NASA's Parker Solar Probe completed its 28th close approach to the Sun on June 8, again matching its record distance of 3.8 million miles from the solar
Google testing iPhone feature to add to Pixel smartphones
Google might soon expand on a current Pixel capability matching the iOS version of it.
Chinese sodium battery surprised scientists by matching key Tesla benchmarks
Researchers found that a Chinese sodium-ion battery performs far better than expected, with production quality and design features comparable to Tesla’s batteries. If engineers can improve cold-weather charging and energy density, sodium could become a cheaper and more abundant alternative to lithium for EVs and large-scale energy storage.
Hoto’s PixelDrive screwdriver is down to $60, matching its best price
It’s got six adjustable torque settings.
Scientists capture two DNA strands zipping together for the first time
Scientists have directly observed how two negatively charged DNA molecules can pair up despite normally repelling each other. Positively charged metal ions appear to bridge the gap, helping matching DNA helices align groove for groove like a molecular zipper. The discovery confirms a theory proposed two decades ago and could help researchers understand DNA interactions involved in cancer and other cellular processes.
Vikings Offensive Solution Identified for Matching Productive Defense
With the running game sidelined by injuries, quarterback Kyler Murray must lean on red zone threat Jauan Jennings to finally unlock a stagnant offense against Tampa Bay.
UI receives grant for business student wellness
A multimillion-dollar donation to the University of Iowa’s business college, alongside a matching gift challenge to generate even more funds, will help support a student mental health and success initiative
Second season a challenge
John McGlynn believes Falkirk will be given "more respect" in the coming campaign and matching last season will be "a challenge".
Surgery outperforms TAVR in young heart patients, new data confirm
Researchers tracked data from nearly 10,000 patients 60 years old or younger who underwent SAVR or TAVR. Propensity score matching was used to focus on two groups of approximately 1,500 patients.
SBIR Advance: $675,000 in state matching grants advance 7 innovative small businesses
MADISON – Seven small businesses in Wisconsin will receive up to $675,000 to commercialize their innovations, thanks to the SBIR Advance program’s latest round of funding. The state matching grant program provides assistance to companies in the process of completing a project...
Bruce Blakeman's attorneys make case for campaign matching funds in court
Blakeman sued the state Public Campaign Finance Board last month for denying his campaign millions of dollars of public matching funds over a technicality concerning the filing of paperwork.
NASA’s Parker Solar Probe Makes 27th Swing Around the Sun
NASA’s Parker Solar Probe completed its 27th close approach to the Sun on March 11, again matching its record distance of 3.8 million miles (6.2 million kilometers) from the solar surface.
Thunder roll to dominant win over LeBron James, Lakers to grab 1-0 lead
The Thunder have now won six straight postseason games, matching a franchise record.
Patrik Schick’s Hot Streak Interrupted By International Break
The Czech striker has evolved into a vocal leader, matching historic scoring records while spearheading Leverkusen’s resurgence before national duty stalls his clinical momentum in the Bundesliga.
Czinger 21C Spyder Has More Downforce Than Any Other Convertible And The Coolest Brakes You'll See All Week
At 150 mph the 21C Spyder produces 3,307 pounds of downforce with the roof on, matching the coupe, and with it off that figure slightly drops to 3,267 pounds.
Wrexham's Kop: The project matching the club's rise
Wrexham's new Kop stand a signal of their ambition to keep climbing from the Championship to the Premier League.
New iPhone 18 Pro Max battery details leak, and Samsung should be very worried
Apple may finally be matching Android's battery playbook, with the iPhone 18 Pro Max tipped for its biggest battery yet.
Bruce Blakeman denied public campaign matching funds in race for N.Y. governor
The state Public Campaign Finance Board on Tuesday voted 4-3 on a resolution that disqualifies Blakeman from the program over a technicality.
A place for moms: It’s a match
The 27-question survey focused on current experiences with making friends, community connections and loneliness. It also gauged interest and willingness to meet for one-on-one mom matching based on things like logistics, availability,…
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Introducing: Porsche Design Chronograph 1 - 911 GT3 100 Jahre Nürburgring
Celebrating a century of the Nürburgring with an exclusive Chronograph 1 reserved for owners of the matching Porsche 911 GT3 special edition.
David Jolly clears $1M raised in a week with help of matching funds, but can't keep pace with Byron Donalds
It's now or never if national Democrats want to flip the Governor's Mansion.
Microsoft is actively rebuilding Windows 11 Search. What does it mean? Our deep‑dive answers every major question.
Microsoft's new Windows 11 Search promises faster results, better query matching, and useful actions without requiring a Copilot+ PC.
AirPods 5 Review: The Best Noise Cancellation In Affordable Earbuds
Much like Apple's iPhone 17 adopted some of the best Pro features, the AirPods 5 come closer to matching the AirPods Pro than any previous model.
‘Like I Never Left’: Yankees Ace Gerrit Cole Delivers 6 Shutout Innings In Return From Tommy John
NEW YORK — Gerrit Cole walked into the Yankees clubhouse on Friday afternoon wearing a dark brown polo shirt with a matching Tom Ford belt and sharp white dress pants. This was a statement game, and even before suiting up in the Yankees pinstripes, Cole was dressed for the occasion. He was locked in, ready to dominate. The fit was part of the mentality.
Radiology appointment booking platform Scan.com raises $220M
Founded in 2017, the service seeks to connect patients, providers and imaging centers—matching parties based on scanner availability, quality and price.
Top employees for data center company eyeing Yellowstone County made matching political donations before announcing plans
The Quantica employees gave the same amount to the same candidates and on the same days in 2024.
NM spent nearly $844M on behavioral health, but 'investment is not yet matching the outcome'
New Mexico has spent $843.5 million since 2022 to rebuild state’s behavioral health system but still faces problems.
Thunder roll to dominant win over LeBron James, Lakers to grab early 1-0 lead
The Thunder have now won six straight postseason games, matching a franchise record.
Leaked Video Shows iPhone 18 Pro's 3-in-1 Dynamic Island in Action
A leaker has activated Apple's upcoming three-item Dynamic Island mode inside the iOS 27 simulator, offering the first video demonstration of the new iPhone 18 Pro feature. The leaker, known as pdfu, posted a video showing the Dynamic Island toggling between three simultaneous Live Activities, matching what Bloomberg's Mark Gurman described in his report earlier today. "The new Dynamic Island with 3 items is already supported in iOS 27," pdfu wrote.
Zelda-themed Nintendo Switch 2 console and Pro Controller leaked
Nintendo is reportedly planning to launch a new limited-edition Zelda-themed Nintendo Switch 2 console and a matching Pro Controller to celebrate the series' 40th anniversary. And a new leak has now given us our first look at the hardware.
‘Dead’ Destiny 2’s Playercount Now Matches ‘ARC Raiders’
As it stands, Destiny 2’s playercount is matching ARC Raiders, despite being a dead game with no more new content coming.
Steam Machine Companion Cube now up for pre order, arrives next month with matching Steam Controller skin
First teased soon after Valve announced the Steam Machine, dbrand's Companion Cube case is now available to pre-order from $99.95.
The sinister influence of crypto billionaires on our politics
Letters: Readers respond to the news that Christopher Harborne has given £36m to Reform UK, matching a donation from Ben Delo
Dems: Blakeman Should Not Get Matching Funds - Long Island Life & Politics
By Hank Russell The New York State Democratic Committee has accused Nassau County Executive and GOP gubernatorial candidate Bruce Blakeman of illegally trying to obtain matching funds with money he raised outside the state of [...]
Yankees' Cam Schlittler allows 1 run in 4-2 win over Red Sox, outmatching Payton Tolle's 11 strikeouts
Modders are now merging entire games, from Minecraft in Elden Ring to Mario Kart in COD Zombies
Modders are moving beyond model swaps by combining gameplay systems from entirely different titles. AI agents, recompilation and matching decompilation projects are speeding up the work.
Nintendo Switch 2 Docked VRR Leapfrogs PS5, but the Catch Falls Squarely on Game Developers
Nintendo Switch 2 gets docked VRR support, matching Xbox Series X|S and beating PS5 per Digital Foundry analysis
Canada announces retaliatory tariffs on $20 billion worth of US goods, unveils support measures
Canada on Tuesday announced retaliatory tariffs on C$27.6 billion ($19.94 billion) worth of United States goods, matching dollar-for-dollar new duties imposed by Washington, and unveiled financial support for Canadian businesses and workers caught in the escalating trade war.
Stevens Point launches $10K grant program for downtown businesses
The Stevens Point Downtown Business Improvement District is offering matching grants up to $5,000 to help local businesses invest in downtown.
M7 Ultra to potentially feature up to 1.5TB of RAM, finally matching 2019 Mac Pro: report
According to the latest Power On newsletter from Mark Gurman, Apple is preparing to include up to 1.5TB of RAM...
Melinda French Gates, Olivia Rodrigo raise $20M from Daisy Chain Fields
Melinda French Gates is matching a $10 million donation after the success of Daisy Chain Fields, a benefit music festival held in Irvine, Calif., on Saturday.
Paige Bueckers' WNBA debut jersey sells for record $64,720
The jersey Dallas Wings star Paige Bueckers wore throughout her WNBA debut on May 16, 2025 has sold via MeiGray, a photo-matching and authentication company that also has a marketplace, for $64,720, a record paid for a WNBA jersey.
London Business School Lands £25M Gift, Matching Its Largest Since 2013
London Business School has received a £25 million gift from David and Molly Pyott to rename its North Building at Sussex Place and fund MBA scholarships.
Streaming’s Biggest Show Returns…and a Buzzy Genre Struggles
(Welcome to my weekly streaming ratings report, the single best guide to what’s popular in streaming TV and what isn’t. I’m the Entertainment Strategy Guy, a former streaming executive who now analyzes business strategy in the entertainment industry. If you were forwarded this email, please subscribe to get these insights each week.) Obviously, the big news of the week (if not month) is Netflix letting go of executive Bela Bajaria, their chief content officer. I’m going to cover this in my next “Most Important Story of the Week”, but I also have a data angle that I might publish before then. (Too much news this month, am I right?) But first, I have a bonus Streaming Ratings Report issue for you. Today’s article is a bit of a grab bag of topics I’ve wanted to write about, but couldn’t squeeze into the (already very long) Streaming Ratings Report issues. The NFL drives huge viewership numbers, so I’ve got a look at that. A whole bunch of TV shows returned to the traditional broadcast channels, and I have thoughts. And I have a quick look at adult animated shows, since a couple flopped earlier this month. Plus, the Emmys aired earlier this month, and we got some fun data bout how popular those nominated shows are and why I’m not optimistic about the show’s future. That’s a lot, so let’s dive right in. Subscribe Sports - Football Remains the King of Streaming Over the last two Streaming Ratings Reports, I sorta ignored the biggest “show” each week. (I was tempted to say “piece of content” but I know that word bugs folks.) In my database, I call these “specials”, and they sure are special. I speak of the king of American TV: football!!! Streaming football is back and, unlike some other sports, it routinely dominates all viewership. Probably the best way to show this is to update one of my favorite graphics, the “40 Million Hour Club”1 since football games have joined that club each week they’ve premiered: (Yep, that’s the data through 28-Sep, the first four weeks of the season. As a reminder, I take the average minute audience provided by Nielsen, factor out a percentage of linear TV viewers in home markets, and multiply the run time by the three-hour runtime.) Again, the numbers are huge. Let’s start with Netflix. They grabbed the rights to the bonus opening week NFL Kickoff game (which was on YouTube last year) and it put up 18.5 million viewers on average. That nets out to 47.4 million hours of estimated streaming hours. That’s good! Though, notably, it’s well below Christmas Day games from previous years. Compared to other streamers/broadcasters, that’s a bit of a mixed result. On one hand, Netflix’s 18.5 million average is about what YouTube claimed last year, though Nielsen used a bespoke methodology at that time, so I trust this viewership figure more. So that’s good. (The game also shifted from a Friday to a Thursday and that could have helped the viewership as well.) And Netflix continues to best Prime Video in total viewership—as you’ll see next—though Netflix has had much higher-profile (opening week and Christmas Day) games. NBC/Peacock’s opening game the night before averaged 25.1 million average viewers, which is just much bigger than Netflix (or Prime Video). That’s the big caveat to all streaming viewership records: even in success, they can’t compete with traditional linear TV. Previously, I called this my “hierarchy of viewership”, and the data keeps supporting that thesis. The downside for NBC is that this game’s viewership was down compared to previous years, though it may be a counting issue. Here’s a great chart from Sports Media Watch: Indeed, looking at all the opening week games across all windows, Netflix still lags the other primetime windows, but does well compared to the afternoon games: I saw a few folks make the case that streamers still lag traditional broadcasters in reach, and I’d add they really lag compared to “broadcast plus streaming” options like NBC/Peacock, ESPN/Disney+ and CBS/Paramount+. The best data I saw for this came from Samba TV, who charted reach through the 2025 season, and, wow. (Samba TV’s numbers are historically lower than Nielsen’s, so don’t compare their household figures to Nielsen’s hours, but use them as a proxy for the relative reach of the streamers.) The good news is Prime Video is NOT having a down year. Their opening Thursday Night Football game reached 18.6 million viewers (about what Netflix got), but that’s a high for Prime Video on Thursdays and the biggest Thursday night game since 2015. The TNF games the weeks of 21-Sep and 28-Sep continued this streak, getting 43.1 (16.8 million average viewers) and 42.5 total hours (16.6 million average viewers), which were both up from last year. Still, that continues the (typical) season slide: (For those new-to-streaming-football-numbers folks, the viewership declines for Thursday Night Football as the year goes along.) Overall, it appears as if Prime Video is now part of the “football habit”, be it for customers at home or out at places like bars and restaurants. And its viewership is slowly catching up to broadcast. One last chart shows this. Last season, Nielsen started adding out-of-home viewership to the charts, so I try not to do season-to-season comparisons as I did for the first few years. And while Nielsen added Big Data viewing this year, I’m going to compare the last two seasons. Here’s that chart, which shows the season-over-season gains: When it comes to streaming football, we have to keep a few seemingly contradictory thoughts in our head… First, streaming doesn’t come close to matching broadcast’s reach and, thus, viewership. Second, even with that gap, football is still the biggest “thing” on streaming. It’s very, very popular. Third, while some methodology changes have likely helped Prime Video’s numbers, their viewership does appear to be growing. Lastly, yeah, the NFL started the season off poorly, with week one dragging down the numbers in year-over-year comparisons. However—and again, methodology changes may have helped this—the viewership grew compared to previous seasons over the next couple of weeks. So football is still king. On streaming and off. Television - Adult Animation Continues to NOT Make the Streaming Charts In the last two reports, two adult-animated shows whiffed: Netflix’s animated comedy, Dang! Paramount+’s Sega-video-game-inspired fantasy/comedy, Golden Axe. Neither made the charts, but that’s usually the case for animated shows. I mean, here’s literally every animated show that’s made the Nielsen Original charts since the start of 2025: And one of those shows is G_abby’s Dollhouse_! A kids show! The problem with charts like this is that they don’t give you a sense of how many shows miss the charts. Netflix had at least eleven animated flops, including comedies like Big Mouth (a show everyone assumed was popular in the pre-Streaming Ratings Era), Long Story Short, Haunted Hotel, Mating Season, Strip Law, and Alley Cats, and action shows like Blood of Zeus, Castlevania: Nocturne, Devil May Cry, Splinter Cell: Deathwatch, and Tomb Raider: The Legend of Lara Croft. Prime Video had at least six animated misses, two in the same universe (Hazbin Hotel, Helluva Boss), three more comedies (#1 Happy Family USA, The Second Best Hospital in the Galaxy and Kevin) and an action show (The Mighty Nein). Disney+ had MCU and Star Wars animated misses (Eyes of Wakanda, Marvel Zombies, Star Wars: Visions, Star Wars: Maul – Shadow Lord, and Star Wars: Tales of the Underworld) but I can’t tell how many of those shows were geared towards adults. HBO Max had Harley Quinn and Hulu had Solar Opposites. None of these shows made the charts! That’s a lot of misses! If I remade the chart with all those misses, here’s how it would look: Listen, I know the counter arguments. First, it’s cheaper to produce animated shows than live action. Fair enough, but with viewership this low, even that cheaper price point starts to not matter. Second, just look at the acquired charts. Hit animated comedies can generate viewership for years! Shows like The Simpsons, South Park, Family Guy, and Bob’s Burgers do really, really well. Fair enough, but streaming has failed to recreate the dynamic that Fox has mastered so well. That’s a problem for streaming still. Television - Emmys! The annual Emmys broadcast was a few weeks ago, and I’ve got data on how the nominees performed on streaming, plus hot takes on this year’s viewership (and the big news about the broadcast’s, er, streamcast’s future). We’re just getting started with this issue, but the rest is for paid subscribers of the Entertainment Strategy Guy, so if you’d like to find out… The top Emmy-nominated shows… ...why I’m worried about the future of the Emmys telecast... ...the pros of broadcast television ...and the cons... ...please subscribe! We can only keep doing this great work with your support. Coming Soon! Next week, we’ve got a double issue (since the weeks of 21-Sep and 28-Sep were so light), but then I’ll be all caught up after a deluge of streaming ratings data from Nielsen in September. In the meantime, I’m going to try to take a look at Netflix’s stats to explain why Bela Bajaria is out. But even light weeks give me plenty to talk about. The Great British Baking Show returns to Netflix and Apple TV has a buzzy new star-studded comedy. And Netflix has a controversial-but-appears-to-be-popular new game show. Plus big films like Toy Story 5, Backrooms and The Breadwinner head to streaming. And is East of Eden a hit? After that, The Kardashians return to Hulu, Prime Video has a reboot of Carrie, and Netflix has a horror show, Below. Disclosure Day heads to Peacock, The Housemaid heads to HBO Max_,_ a new Ben Affleck film, Animals, lands on Netflix, and Apple TV has a new John Cena action film based on, checks notes, Hasbro’s Matchbox toys. Okay. Longterm, some interesting TV production news. HBO Max ordered How to Survive Without Me, starring Kaley Cuoco, Joshua Jackson, Ray Romano and Rita Wilson, for fifteen episodes! I love that some streamers (or, at least, HBO Max) are finally ordering TV shows with more than eight episodes. In less wise production news, Landman does not appear to be coming back this year, since it just started production. Frankly, I don’t love this (get your shows out on time) but Landman is so popular, I doubt it matters.
TAHOE FUND AND BARTON HEALTH LAUNCH $25,000 MATCH FOR THE MARSH CAMPAIGN
250 donors can help unlock a $25,000 matching gift from Barton Health for the Upper Truckee Marsh The Tahoe Fund and Barton Health have launched an exciting new fundraising campaign to help restore the Upper Truckee Marsh South in South Lake Tahoe—the former site of the Motel 6 property. If 250 community members donate $50 […]
Estée Lauder Companies (EL) Expands Color Science Research For Shade Matching
Estée Lauder Companies (NYSE: EL) announced a research collaboration with the University of Leeds and Dr. Kaida Xiao focused on advanced color science for complexion products. The partnership aims to improve shade matching accuracy in luxury foundations and related complexion lines using visual perception science. The work is expected to inform future formula development and product testing in the prestige cosmetics segment. For investors tracking how advanced data and perception science...
'Heated Rivalry' stars Hudson Williams and Francois Arnaud call out hateful comments
Hudson Williams and Francois Arnaud have shared matching statements condemning racist, homophobic, and other bigoted contingents of the expanding 'Heated Rivalry' fandom: 'If you can't accept that GTFOH.'
Fox News Poll: Voters doubt new agreement will stop Iran from developing nukes
Fox News poll finds 64% of voters doubt a peace deal will keep Iran from developing nuclear weapons, matching skepticism levels from the 2015 deal.
Who should be the Cardinals’ next Kyle Leahy?
After matching his shortest start of the season, Kyle Leahy is nearing the end of his first season as a starter for the St. Louis Cardinals. Despite early struggles that caused some fans to laughably demand his removal from the rotation, Leahy had the lowest ERA among starters since the All-Star Break with the lightened […]
LinkDaddy LLC Announces AI Verified Gold Business Passport
LinkDaddy LLC announced AI Verified Gold, a $297-a-year public identity record at aiverified.io. Each file includes a hashed web page and a matching JSON copy for companies that lack encyclopedia notability. Owners prove website control and may attach filings from live official registry pages.Clearwater, Florida--(Newsfile Corp. - September 11, 2026) - LinkDaddy LLC today announced AI Verified Gold, a $297-a-year public identity record now available at aiverified.io. The Florida company said the
47 revelatory hours with Assassin’s Creed Black Flag Resynced
To review this month’s supposed remake of 2013’s Assassin’s Creed IV: Black Flag, I must first correct the record. Assassin’s Creed Black Flag Resynced isn’t a game about pirates (and assassins) in the 18th century Caribbean. Sure, sure, that’s what the trailers would have you believe. They’ve go their clips of Edward Kenway swinging his swords and steering his pirate ship into cannon-blasting combat against British frigates. Is Resynced truly a pirate game? Of the 47 hours I spent playing Resynced over the past few weeks, I will admit I spent maybe 44 (?) of them collecting plunder with Blackbeard, drinking rum with Anne Bonny and debating the pros and cons of the lawless pirate-run settlement Nassau with Benjamin Hornigold. I may in fact have spent dozens of hours sailing to remote islands, reading treasure maps, opening messages left in bottles, sinking the odd Man o’ War with a well-timed broadside, collecting sea shanties for my crew, befriending a pet monkey, and hunting whales. I am nevertheless neither so Gullible nor so Narrow-Minded as to call the magnificent Resynced a “pirate remake.” Oh no. Forget any reviews of Assassin’s Creed Black Flag Resynced you may have read. Forget what you yourself may have played, if you’ve spent any time with the game since its launch. What Assassin’s Creed Black Flag Resynced is really about I’m here to give you the scoop (spoilers for Resynced’s Animus menu lore, which many players are probably not going to see): Assassin’s Creed Black Flag Resynced, the new game whose development was led by Ubisoft Singapore, is set in the year 2096. It’s about a societal split, about revolution, about an old Assassin’s Creed adventure repurposed in the series’ distant future as propaganda or samizdat. It’s about the overheated future of 2096, essentially conquered by the series’ well-established nefarious Templar-run company Abstergo. (In this future, Abstergo is, among other things, remaking a 2013 pirate movie called Devils of the Caribbean, but this time in VR. The VR version will be backed by a marketing plan that involves AI influencers, a 10,000-avatar “metaverse premiere event” and that manufacturing of memes aimed at “50 million VR nodes.” See what I mean about Abstergo being evil?) Resynced is about a late 21st-century population mollified by the widespread use of Abstergo’s Animus devices which let people experience the lives of historical figures culled from “genetic memories.” It’s about an insurgent faction of Assassins. And it’s about a plan to wake the population into revolutionary fervor by showing them the memories of 18th century pirate Edward Kenway, who—as depicted in the original Black Flag and again in Resynced—gradually comes to an understanding about the Assassins of his day and their centuries old fight for freedom. Resynced is also about an AI developed within the late 21st-century Animus, called Ego. It has found a way to alter genetic memories, to create and show Animus users false ones. The game is about Ego’s efforts to tell the people experiencing Edward Kenway’s memories that Kenway was wrong, that fighting against order is folly, that we should crave a world where “compliance is rewarded with power.” Who are we in this game? We’re an unnamed Animus user in 2096 who experiences Kenway’s journey virtually. At four moments during Kenway’s exploits in the Caribbean our virtual jaunt can be interrupted for 10-15 minutes, as we explore Animus “rifts” where Ego explicitly tries to tell us how wrong Kenway was. None of this is what 2013’s Assassin’s Creed IV: Black Flag was about, of course. That was a different game, even if you also spent dozens of hours pirating as Kenway in that game, across missions and a map that’s been faithfully reintroduced and rebuilt for Resynced. The 2013 Black Flag was about you playing as an unnamed researcher newly hired in 2013 by Abstergo Entertainment, the video game development wing of the Templars’ evil-corp. In that game, you were assigned to use the Animus to dive into the genetic memories of Desmond Miles, a man who died in Assassin’s Creed III and who was descended from a long line of Assassins (and at least one Templar) whose adventures were featured across the prior AC games. In 2013’s Black Flag, your mission was to plumb the Edward Kenway experience for material that Abstergo could use in productions such as the motion picture Devils of the Caribbean, though the Templars had some ulterior motives for the assignment. Resynced is therefore not a remake of 2013’s Black Flag. It’s a sequel. It is a new game about a new exploration of Edward Kenway’s pirate/assassin journey, set 83 years after the framing sequences of the original game. Resynced provides a new narrative framework that, thanks to the concept of an AI that wants to alter historical memories, arrives with creative justification to tweak a now-classic 13-year old game. That makes Resynced, already a hot seller, a tantalizing hint of where Ubisoft could go with a line of Assassin’s Creed remakes. They could remake the first game, the Ezio games, even the recent ones set in ancient Egypt and Greece. And for each, they could not just modernize the graphics and controls but expand and alter their sequences of events to use them as reference points for a conflict set in the late 21st century, as rival factions try to weaponize historical memories. Game File is a reader-supported publication. To receive new posts and support my work, even when that work consists of ravings about Assassin’s Creed’s modern day plot, please consider becoming a free or paid subscriber. Subscribe A story most players will probably miss If you didn’t know any of this, I’m not surprised. If you played the game and still didn’t catch it, I’m not a bit shocked. If Ubisoft has no plans to do more of this, I won’t fall down. Almost all of what I’ve described is optional and missable in Black Flag Resynced. I nearly missed it myself, as I planned for a breezy playthrough of an old Assassin’s Creed favorite. Instead, I found myself in a 40+ hour hunt for the “real” story, buried deeper in Resynced than any gold-filled chest. The story of 2096 is Resynced’s meta-story, told in two remote pockets of the game: 1) four optional playable “rifts” that players may find as they proceed through Resynced’s pirate fantasy , 2) in dozens of text files tucked three menus deep in the game’s barely-interactive Animus hub. Assassin’s Creed games have almost always had a meta-story about people in the 21st century (usually matching the game’s release year) and their connections to the main history portions you play. Those meta-stories have always been squeezed into the margins, though seldom as severely and as, uh, graphiaclly simple, as in recent games. Back in 2013, the modern-day exploits of you as an Abstergo Entertainment employee were prominent. They were portrayed via first-person portions that occasionally interrupted the third-person Kenway experience and could be explored for hours, complete with their own missions, side quests and puzzles. Resynced’s 2096 story—of Assassin “Watchers” vs. Abstergo/Tempar goons, of rogue AIs, of panicking scientists, of a woman wondering why her Animus-addicted husband is muttering about Mary Read (“What does he mean by Assassins?”), of a fight for the population’s hearts and minds via varying interpretations of Edward Kenway’s life choices—is mostly told through unlockable text files. The files are interesting. Offered via diary entries, intercepted chats and news reports, they present varied perspectives of a world in crisis. One set works as a narrative puzzle as it reveals the Rashomonic interpretations of a massacre, or was that a successful Assassin hit? Another favorite reveals the rising bitterness of a person who, through Edward Kenway’s journey, now shakes at the ignored evil around him. One surmises that Ubisoft is averse to putting the Assassin’s Creed’s meta-story in the way of more marketable pirate playgrounds and ninja/samurai epics. Instead, we get a better-than-nothing text-in-menus approach introduced in 2025’s Assassin’s Creed Shadows. In Shadows, players unlocked the meta-story text files largely via time-gated missions that called on the user to kill X number of enemy type Y, clear three enemy castles, re-win a three-phase fighting tournament, and other grinds. Time restrictions on accessing these missions and unlocking the files meant it could take players months to access the full story in-game. But even in the most hardcore Assassin’s Creed hangouts, the fanbase instead seemed to throw up their hands rather than grind to keep up. In Resynced, Ubisoft has shown some mercy, diminishing the amount of new text files that are tied to timed grinds. Now, most of the text-based 2096 lore are associated with “data file” collectibles that players can find in the world. That includes a batch of written entries that explain a historical link between the feudal Japan era in Shadows and the piracy adventures in Black Flag. Players who explore a lot will find dozens of data files, though the game does not appear to offer any in-game tracker for finding each one. You just need to keep looking for them. As of this writing, I have most of them, but not all. I can’t find any full guide for them online. And even Ubisoft’s optional $5 microtransaction that reveals lots of items in-game does not appear to reveal the locations of the text files (at least the official description omits them from its collectibles list). That’s not a huge bother, because tracking the data files down compelled me to re-explore the waves and islands of Black Flag. That was a thoroughly pleasant task to do for the first time in a dozen years. I expect many players, though, will be content to wait for the files to be reproduced in an online AC wiki somewhere, the easier to read on a web page. It may not seem enticing to play a video game in order to gradually unlock pages of text to read. Why not, you may ask, just read a book, where they put the pages in order? For one, they’ve not tucked this latest installment of Assassin’s Creed’s meta saga in a book. I also enjoy the unordered delivery, the dawning comprehension of a story about 2096’s desperate people and questionable tech, which I glimpsed first at its middle, then the end, then the front, then other moments in between1. I am also enamored with the idea of the Assassin’s Creed games I’ve previously played, including Black Flag, being repurposed for an information war. The ideas in Resynced’s meta-story, which builds off characters and ideas in Shadows’ chunks of text, are strong. The potential of where they could go with it is exciting. As for the pirate stuff? Looks great, controls pretty well, is fun to play and oh so speedy in terms of how much of a good time you can have with each sit-down. It never gets old to chase a new shanty page across a rooftop, bombard a fort with upgraded mortars or use a diving bell to explore sunken wrecks (hats off to the team at Ubisoft Barcelona that worked on the underwater portions in Resynced; that team is now facing layoffs, such is the misery of modern gaming and oft-troubled Ubisoft). New pirate missions in Resynced involving new ally characters are brief, dramatic and add more to Edward’s story, even if the gameplay perks they provide barely enhance the gameplay. A new denouement for high-class pirate Stede Bonnet is affecting; a new hunt for Blackbeard’s treasure is a welcome extra moment. A new epilogue to hunt down a pirate killer, on the other hand, over-complicates Kenway’s character. The ending credits remain my favorite of any game I’ve ever played. Black Flag provides great source material. The revisit is well-made and a great sign of what could be. It is offered in a different wrapper that hints at an opportunity for more interesting remakes to come, should Ubisoft choose to pursue such treasures—and as we brace to resist or comply with an Abstergo future. 1 The messages that Edward Kenway finds in bottles tell another out-of-order story, one about a man reckoning with the strange memories and voices he’s heard in his head since he was a boy. That tale was also in the 2013 game and develops into one of Black Flag’s most compelling character arcs. In Resynced, it has lost its climax, because the bottle story previously paid off in the halls of the first-person Abstergo Entertainment, which is exclusive to the older game. An altered resolution, written by the 2013 game’s lead writer is fine, doesn’t invalidate the 2013 version, but makes for an inferior final note.
War, sports collide as Iran's World Cup kicks off in Los Angeles
CBC News reported on the unchartered territory FIFA World Cup 2026 is finding itself in as members of Team Iran arrive in Los Angeles, inviting a divisive collision of geopolitics and sports in an area with a large Iranian diaspora. "You've never had two countries engaged in active military conflict matching up against each other, competing in the same tournament," said Salma Mousa, an assistant professor of political science and affiliated faculty with the Bedari Kindness Institute. Mousa, who studies the intersection of sports and conflicts, worries that a potential July 3 face-off between Iran and the U.S. in Texas might “increase tensions to kind of a cataclysmic degree.” Read more about UCLA in today’s Washington Times.
Beauty’s New Challenger Conglomerate Has Always Been Here
By shedding its food and ice cream businesses, Unilever is betting big on beauty. But matching the scale, valuation and category depth of rivals like L’Oréal and The Estée Lauder Companies will require sharper focus and strategic discipline.
Slime mould has no brain, no neurons and no central control, yet when scientists placed food at 36 locations matching cities around Tokyo, it grew a network strikingly similar to the rail system — with comparable efficiency, cost and resilience
A single-celled organism with no brain solved a transportation puzzle that took human engineers decades to perfect.
College football watchability tiers: Ranking every Week 1 game
There are 43 college football games matching two teams from the Bowl Subdivision. We ranked all of them and placed them into four distinct tiers.
Blakeman may meet matching funds criteria, review finds
An exclusive look at Blakeman’s fundraising data shows that if he wins his court battle, his campaign would likely qualify for public money.
Lewis Hamilton and Charles Leclerc arrive at Sepang in matching sports saloons
Lewis Hamilton and Charles Leclerc have arrived at Sepang in matching Alfa Romeo Giulia Veloces
The World Cup is turning Erling Haaland's style into big business
Erling Haaland is known for his style both on and off the pitch, whether that's matching his hair ties to his jersey or traveling with Hermès bags.
International Business Machines (IBM) Is Up 15.8% After Announcing $2 Billion Anderon Quantum Chip Foundry Partnership
Earlier this week, IBM and the U.S. Department of Commerce announced a Letter of Intent to create Anderon, America’s first pure-play quantum chip foundry in Albany, New York, backed by US$1.00 billion in CHIPS incentives and a matching US$1.00 billion cash commitment from IBM plus intellectual property and staff. This partnership not only cements IBM’s role at the core of the U.S. quantum ecosystem but also creates a dedicated 300‑millimeter quantum wafer facility intended to supply multiple...
Could dragons have ever existed? Science has a surprising answer
Dragons appear in stories as enormous reptilian creatures with wings, claws, armored bodies and, in many traditions, the ability to breathe fire. Science has found no evidence that an animal matching ...
Senator Baldwin is urging federal officials to dismantle a newly introduced 25 percent matching funds requirement that targets regional Dairy Business Innovation Initiative centers.
A major policy shift by the U.S. Department of Agriculture (USDA) is creating friction for local agriculture, prompting quick action from lawmakers.
Monkeys have a basic intuition for geometry, study suggests
Baboons and macaques appear to use some of the same mental strategies as humans when matching shapes, suggesting that the foundations of geometry evolved in a common ancestor.
Stevens Point launches $10K grant program for downtown businesses
The Stevens Point Downtown Business Improvement District is offering matching grants up to $5,000 to help local businesses invest in downtown.
CPI: Inflation rose to 4.2% in May, matching the forecast
The new CPI report showed inflation in May climbed to the highest rate in about three years.
Apple Announces 2026 Pride Band, Watch Face, and iPhone Wallpaper
Apple today introduced its 2026 Pride Collection, including a new Apple Watch band, watch face, and a matching wallpaper for the iPhone and iPad. The new Pride Edition Sport Loop is available to order now on Apple.com and in the Apple Store app in 40mm, 42mm, and 46mm sizes, and it will be available at Apple Store locations starting later this week. In the U.S., the band costs $49.
‘Send help’: LA GOP leader issues desperate appeal after Dem mayor’s campaign vid shocks viewers
LA County GOP Chair Roxanne Hoge says Karen Bass's viral 6-to-1 matching funds video reveals how Democrats codified electoral 'shenanigans' into law.
Mavs Block Knicks, Match Offer To Keep Promising Young Center
Dallas secured frontcourt depth by matching a $4.7 million offer sheet for Moussa Cissé, preventing the New York Knicks from poaching the defensive specialist after his standout rookie season.
Larry Gies Pledges Another $100 Million To His Namesake Business School
The matching commitment could generate $200M for scholarships, student experiences & faculty support, bringing Gies’ B-school giving to $250M
Reincarnation: What Science Says and Doesn’t (or Can’t) Say
Inside a University of Virginia lab, scientists have spent nearly six decades gathering unsettling evidence: children who recall violent deaths, bear matching birthmarks, and know facts they never could have learned. A grieving skeptic investigates whether reincarnation might just be real.
Arsenal's ambition matching Arteta's vision as new deal nears
The perception of Arsenal's transfer window varies depending on who you speak to - but there will be no disagreement from anyone at Emirates Stadium over how crucial their next expected signing will be. With the market closed until January, the club are now in the process of finalising an agreement with manager Mikel Arteta over his protracted new contract. Arteta moved unequivocally last month to remove any lingering doubt over his future: "Everybody feels comfortable that the timing of the contract is not going to be an issue because my will certainly is to be here and I'm very happy here."
Android users are finally starting to see Google's major Gemini app design overhaul
Google is rolling out a fresh redesign for the Gemini app for Android ahead of I/O 2026, matching the iOS app redesign in early May.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
Inside the Rise of Off-Market Business Acquisition Marketplaces
BusinessLocating is an example of this growing trend, highlighting its early growth, AI-powered matching, and concierge-led acquisition process.
iOS 27 Brings New Functionality to HomePod
With the launch of iOS 27 and HomePod Software 27, Apple is adding support for AutoMix, Apple's AI-powered Apple Music feature that blends songs using matching key and tempo. Apple says it has improved AutoMix's underlying algorithms to generate new transition types, making for more seamless blends between tracks, so this should also benefit the newly introduced feature for HomePod.
Pixel 11 Pro Fold leak shows off Google's classy Pine color and a sleeker camera design
The Pixel 11 Pro Fold has leaked again, this time in Google's new "Pine" colorway, matching previously outed renders.
iPhone 18 Pro Will Reportedly Start With 256GB of Storage
While the iPhone 17 Pro has double the base storage compared to the iPhone 16 Pro, there will apparently be no further increase this year. In a report this week estimating that the iPhone 18 Pro's bill of materials will be nearly 40% higher than the iPhone 17 Pro, Taiwanese research firm TrendForce said the iPhone 18 Pro will start with 256GB of storage, matching the iPhone 17 Pro's minimum capacity.
When what you see doesn’t make sense, your brain does something remarkable
The brain may have a built-in way to quickly settle disagreements between regions processing the same scene. Researchers found that matching signals between two visual areas lasted longer, while conflicting signals rapidly faded away. This “consensus building” mechanism could help explain how the brain turns many specialized inputs into one unified view of the world.
Wasatch County launches $90,000 small business microgrant program
The microgrant offers a 50/50 matching reimbursement of up to $5,000 for eligible projects that support business growth.
Larry Gies pledges $100M matching gift to Gies College of Business
CHAMPAIGN, Ill. (WICS/WRSP) - Larry Gies has announced a new pledge of $100 million to Gies College of Business in Champaign.
Eagles-Cowboys meet with matching records and mounting pressure
Eagles-Cowboys has become a desperation game for two struggling offenses
Bishop’s computer science chair says AI is eliminating ‘grunt work’ and reshaping digital jobs
Dr. Russell Butler, chair of Bishop’s University’s Department of Computer Science, says artificial intelligence is increasingly taking over routine digital “grunt work,” changing the skills students and workers may need in the years ahead. Photo courtesy of Bishop’s University. Click here to read our platform! Get local news like this every morning. Subscribe free below. Subscribe Pulse Newsroom Artificial intelligence is already taking over some of the routine digital work once performed by entry-level employees, according to Bishop’s University Computer Science chair Dr. Russell Butler — a shift he believes will make expertise, judgement and the ability to evaluate AI-generated work increasingly important. Butler described the change as automation reaching what he calls the “bottom of the cognitive pyramid” during an interview with The Pulse about AI, university education and the future of digital work. His argument is not that humans are disappearing from the workplace. Instead, he sees their role changing as AI becomes capable of handling more of the repetitive tasks involved in computer-based work. “Everything’s converging on just AI basically doing all the grunt work,” Butler said. The bottom of the cognitive pyramid Butler is from Lennoxville, completed his undergraduate studies at Bishop’s and later earned his PhD at the Université de Sherbrooke. He joined Bishop’s in 2019 and now chairs its Department of Computer Science. He uses AI in research, teaching and other creative work, and said the technology is increasingly capable of handling routine digital tasks that once required substantial human time. “You’ve got the grunt work, like moving things around in Excel, doing basic programming tasks,” Butler said. “That’s like the bottom grunt work that the entry-level worker would have done two or three years ago.” Butler went further, saying in his view that much of this type of work has already been absorbed by AI tools. He connected that change to a shift he sees taking place in computer science, where entry-level roles have declined while experienced workers can use AI to increase what they can produce. “A senior developer now has access to essentially an unlimited amount of junior developers on demand,” Butler said. He was describing AI systems metaphorically, not literal employees. His point was that one experienced developer can now ask AI tools to produce code or other technical work that might previously have been assigned to more junior workers. That raises a broader question for universities and employers. If some of the simpler work traditionally given to newcomers can now be done by machines, how do people gain the experience needed to become senior workers themselves? Students doing work that once required years of programming Butler said he is already seeing the change inside his classroom. He created a Bishop’s course called CS208, Coding in Plain English, to show students — including those without traditional programming backgrounds — what they can accomplish using AI. Some come from disciplines such as psychology or neuroscience with no previous programming experience. “What I’m finding is that students who have zero programming experience, they come in from another discipline like psychology or neuroscience or something, they are now able to get up and running with real data sets,” Butler said. Butler’s own doctoral work involved neuroimaging, and he said he has assigned students work he considers comparable to the kinds of analysis he performed during his PhD. He described giving students a real dataset, an expected result and instructions to use AI to complete the analysis. Butler said those students have been able to carry out work at a level he associates with tasks he once performed after years of programming experience. That does not mean a student using AI instantly acquires the same knowledge as an experienced computer scientist. But Butler sees it as evidence that AI can dramatically lower the technical barrier between having a problem to solve and producing a working result. The role of the person using the system then changes. They need to know what to ask for, understand enough about the subject to judge the answer and take responsibility for what is ultimately produced. What about AI hallucinations? One persistent concern surrounding generative AI is hallucination — when a system produces information that sounds convincing but is false or unsupported. Butler said that problem has improved substantially in newer systems and is not as severe as it was with earlier models. He pointed in particular to newer AI systems’ ability to search the web, consult scientific databases and return source links rather than simply generating a citation from their internal model. Butler nevertheless said users should verify what AI produces. “You should verify,” he said while discussing citations generated with AI. His position is that hallucinations have become less common in the systems he uses, not that incorrect AI output is impossible. Human checking remains part of the process. Hours of work compressed Butler offered another example from his administrative work at Bishop’s. The university has been comparing CEGEP courses with first-year Bishop’s courses to determine where students may qualify for advanced standing. Traditionally, Butler said, that means reviewing two sets of course descriptions and manually matching one institution’s courses with another’s. As department chair, that could require hours of reading and comparison. He said AI can now be given both sets of material and asked to generate an initial mapping automatically. “It saves me hours and hours of work,” Butler said. Butler said the AI-generated mapping can also produce a better result than he would produce himself. He sees similar opportunities in businesses. A company may receive specifications, drawings, emails or other digital material from customers and then have employees convert that information into an internal format before anything can be manufactured or delivered. AI can increasingly perform parts of that intermediate processing. In Butler’s view, the employee does not necessarily disappear. Instead, the job becomes more about checking the result. “The human is still there,” he said. Judgement could become more valuable That change is central to Butler’s view of where digital work may be headed. If AI can produce a first draft, write basic code, compare documents or process large amounts of information, he argues that knowledge and judgement become increasingly important. “The real scarce resource going forward is going to be domain knowledge, expertise, and… credentials, authority, the ability to work with other people,” Butler said. He is therefore encouraging students not only to learn AI tools but also to broaden their education. He mentioned acting, fine art and photography as examples of courses that can help develop what he described as taste and intuition — the ability to recognize what is good, what is not and what should be changed. “And that’s the skill that they need now because the grunt work has been automated and now it’s about evaluating what the AI produces and telling it how to improve or expand the output,” Butler said. That does not remove the need for technical knowledge. Butler’s argument is that the emphasis may shift away from manually completing every step of a task and toward directing, checking and improving work produced with AI assistance. He also stressed that humans remain responsible for final decisions. “At the end of the day, the human has to make the final call,” Butler said, pointing to the question of accountability. Physical work may be different Butler draws a distinction between digital work and jobs requiring people to manipulate the physical world. He expects AI to continue advancing quickly in tasks performed almost entirely on computers. He is more cautious about claims that humanoid robots will soon be able to replace workers such as plumbers or electricians. Butler said those trades would not be replaced “anytime soon” in his view and described some current robotics demonstrations as overhyped. He described the situation as counterintuitive. “It’s almost like we solved the highest level first,” he said, contrasting advances in digital AI with the harder problem of building robots capable of operating reliably in the physical world. Butler’s argument is that some digital occupations could face automation sooner than trades requiring complex physical work. The wider AI shift in the Townships Butler’s comments come as local institutions are increasingly grappling with how AI should be used. The federal government recently announced up to $162 million over five years for 10,000 AI-related placements through Mitacs. The Université de Sherbrooke told The Pulse that the number of its collaborative research and innovation projects supported through Mitacs has approximately doubled since 2018-19, while the number of placements has approximately tripled. UdeS also said it already has projects involving both AI adoption and the application of AI to other fields. At Bishop’s, Butler said part of his role involves building the Computer Science department’s local presence, connecting students with regional partners and strengthening relationships with the Sherbrooke technology ecosystem. Those developments put universities in a difficult position. They have to prepare students to use the tools employers increasingly have available while also making sure graduates understand enough to recognize when those tools are wrong, incomplete or being applied to the wrong problem. The risk of losing human skills Butler does not see AI as risk-free. Later in the interview, he raised a separate concern: as AI becomes better at reading, writing, programming and other cognitive tasks, people could lose some of the underlying skills that historically helped produce new ideas. “The other danger is that we’re going to lose the human skills,” Butler said. He specifically mentioned reading and writing and argued that people could lose some of the lower-level understanding that contributes to breakthroughs. Butler said AI systems are based on existing human knowledge and argued that they become much more powerful when paired with a capable person. That tension runs through his view of the technology. AI can remove hours of routine work. It can allow beginners to perform tasks that once required substantial technical training. It can give experienced workers significant leverage. But the more capable the technology becomes, the more important it may be for people to develop the judgement needed to decide what should be done in the first place. For Butler, that is where education may have to change. Students still need to understand their field. They still need to know when something is wrong. And they still need to be able to make the final decision. But if AI increasingly handles the bottom of the cognitive pyramid, the value of a worker may depend less on how quickly they can perform the grunt work and more on whether they understand what the work is supposed to accomplish. Don’t miss the next story that affects your community. Join thousands of readers getting The Pulse every morning—plus breaking news alerts when it matters most. If you value this kind of local journalism, consider supporting it. Subscribe, share and like! Subscribe Share
Duke shrugs off health issues, sets sights on Siena
GREENVILLE, S.C. -- Duke enters the 2026 NCAA Tournament with a familiar goal and matching expectations as the No. 1 overall seed.
Aetna Developing Preferred Network for Autism Therapy Providers
CVS Health’s (NYSE: CVS) payer arm, Aetna, plans to create a preferred autism therapy provider network that may make a debut in 2026. Aetna first
Lamine Yamal chasing another Barcelona record after matching Messi feat
Lamine Yamal has barely given La Liga defences time to breathe this season. The Barcelona forward has already scored six times across the opening five league matches, including three braces, and his ...