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What you should know about hidden science behind sports betting apps
Sports betting apps use behavioral science to keep users engaged, often outpacing state regulations and rules.
'Biermann' Doc Film on German Political Singer for Trump Era: Viennale
Jens Meurer discusses his doc, screening at Austria's Viennale and showing Wolf Biermann narrating his life in various iterations of Germany, and how the outspoken artist inspired 'The Lives of Others.'
Manny Pacquiao mentioned in Marvel’s ‘VisionQuest’
Photo: Screengrab from Disney+ Filipino boxing champion Manny Pacquiao receives a brief mention in Marvel Television’s VisionQuest, when a conversation about an injured hand turns to his record in the sport. The reference comes in “Reboot,” the third episode of the Disney+ series, released October 21. Thomas Shepherd, played by Ruaridh Mollica, tells Vision (Paul Bettany) that he can manage…
Manchester United will consider Julian Nagelsmann if Michael Carrick sacked
Julian Nagelsmann is expected to be a leading candidate for the Manchester United job if the club decide to sack under-fire head coach Michael Carrick.
Arch Manning, Steve Sarkisian and the mess at Texas: Can Longhorns right ship before it takes them all down?
Miami-Dade Small Business Program: New opportunities
Getting your Trinity Audio player ready... For a small business owner, winning a government contract can be a significant milestone — obtaining steady revenue, scaling up your business, and achieving long-term growth. In Miami-Dade County, an important first step for many businesses is becoming certified through the county’s Small Business Development programs. Today, Miami-Dade County […]
Midseason bowl projections for Duke football
A myriad of bowls and opponents dots the latest bowl projections for Duke and head coach Manny Diaz.
Smucker, Mannion to go head to head in debate this Friday
Republican Congressman Lloyd Smucker and Democratic challenger Nancy Mannion will debate Friday afternoon at a forum hosted by the Lancaster Chamber and York County Economic Alliance.
A week of disgraces dominates state politics
In a recent segment of Colorado Inside Out, Eric Sondermann highlights multiple current outrages in the state and beyond.
Volkswagen bet on Xpeng to save its China business. It’s not going to plan
By Ju-min Park and Christina Amann BEIJING/BERLIN, Oct 20 (Reuters) - When Volkswagen turned to EV maker Xpeng in 2023 to help fix its flailing Chinese business, executives touted the partnership as a shortcut to developing cars tailored for China at t...
MTSU group selected for prestigious Berkeley Lab learning opportunity
MURFREESBORO, Tenn. — Five students from Middle Tennessee State University will travel to California this November for an immersive “mini-semester” at Lawrence Berkeley National Laboratory, also known as Berkeley Lab. Nyah Bentley, Addison Berry, Tomy Chet, Sarah A. Holzmann, Gavin Liles and Gloria Silva will join groups from two other universities, Spelman College and the University of […]
FMOL Health, LSU partner to develop saliva-based concussion test
Researchers are working with up to 60 LSU football players this season to develop a non-invasive sideline test...
Election stakes are high for Colorado’s farming future
U.S. Rep. Gabe Evans is running to defend his seat against Manny Rutinel. I don’t know either of the two, but I was able to visit with Evans for half an hour earlier this week and while we aren’t aligned on everything, we have similar feelings about dear Manny. Evans said he’s hearing the same […]
Porch Light Health speaks on the importance of mental health awareness
Chief Clinical Officer at Porch Light Health speaks with Blake Sammann on 11 News at 9 about the importance of mental health awareness.
Arch Manning struggles, Colin Simmons injured as Florida scores 24 straight to upset No. 7 Texas
The Longhorns lost a 14-point lead and fell to an unranked Gators team quarterbacked by a backup making his first career start.
2026 Nobel Prize in Medicine Honors Breakthrough That Lets Scientists Control the Brain With Light
An algal protein helped scientists reactivate a fear memory in mice, turning light into a tool for testing what specific brain cells do. Scientists who worked out how to control brain cells with light have won this year’s Nobel Prize in Physiology or Medicine. Karl Deisseroth, Peter Hegemann, and Georg Nagel were honored for their
Manny Rutinel smashes Colorado House race fundraising record in 8th CD
Democratic congressional candidate Manny Rutinel raised more than $4.2 million in the most recent quarter in his bid to unseat Republican U.S. Rep. Gabe Evans in Colorado’s most competitive U.S. House race, hauling in more than twice as much as Evans and setting a new state record. Across the board, the state’s Democratic nominees outraised […]
Manny Diaz has Suggestion to Fix Transfers in College Athletics
Duke football head coach Manny Diaz has a great suggestion on how to fix transfers in college athletics.
Raiders wide receivers Week 5 snap and production review
Undermanned unit doesn’t produce much in defeat
Crown Sports Center is the Perfect Place for Proactive Entertainment and Games
We're exploring Crown Sports Center and discover why it's the perfect place for all manner of entertainment, games, and skill development.
Political reporter Shaun Boyd gives a Reality Check on an ad attacking Democrat Manny Rutinel
D.C. Everest's Kampmann wouldn't let multiple health challenges prevent state goal
She faced health challenges, a new doubles partner and long odds of reaching state. But D.C. Everest senior Brynn Kampmann refused to give up on her dream.
Cincinnati Parks receives $17.5K grant for cardiac emergency preparedness
Each year, more than 350,000 people in the United States experience an EMS-assessed cardiac arrest outside of a hospital, and about 90% do not survive, according to the American Heart Association.
Longhorns and Gators clash, needing win to keep their seasons on track
Both teams now limp into Saturday's game in Austin with bruised bodies and egos.
CD1 debate turns feisty
A mild-mannered, televised debate in the U.S. First Congressional District race took a heated turn Wednesday (Oct. 14) when incumbent U.S. Rep. Rick Crawford, R-Jonesboro, and Steve Parsons, a Libertarian...
Padres' offseason storylines include Sheets' health, Pivetta's contract
SAN DIEGO -- A fly ball that doesn’t hit a roof cable, a ninth-inning liner a few inches to the right, a deep drive from Manny Machado that carries just a bit farther -- with any of those things, maybe the Padres are preparing to host Game 3 of the
Rep. Kevin Mannix faces political newcomer in fight to hold onto Oregon swing seat
A business law attorney and a safety professional with different levels of political experience are seeking to win an Oregon swing district.
A Major Labor Boom in CNY? Not Here Yet
With so many major projects going on — Micron, I-81 viaduct and others — job growth is predicted to increase. But so far the number of jobs in the region has declined By Aaron Gifford [caption id=attachment_11065 align=alignright width=350] Amy Stage, deputy director at the Manufacturers Association of Central New York (MACNY): “For us, the conversation isn’t just about filling jobs. It’s about creating sustainable pathways that help people see a future for themselves in manufacturing.”[/caption] The I-81 viaduct project in Syracuse and Micron facility construction in Clay are expected to create a major labor boom for Central New York. But for the time being, the number of jobs here has actually decreased in the past year. The New York State Department of Labor reported that, for the annual comparison of June 2025 to this past June, private sector jobs decreased by 2,200 or less than 1% to 260,000. Job gains were concentrated in leisure and hospitality (+700), private education and health services (+400) and other services (+300). Job losses for that annual period were reported in the areas of trade, transportation and utilities (-1,500); professional and business services (-1,000); financial activities (-500); mining, logging and construction (-300); manufacturing (-200); and information (-100). The public sector job count rose over 12 months, with most growth concentrated in education, the state Department of Labor reported. Looking ahead, the Central New York economy is expected to benefit from both the Micron and I-81 viaduct projects over a period of several years. Initial job growth is foreseen in construction and computer and electronic manufacturing. Spin-off jobs will be created in the areas of professional and business services, health care and education, the state Department of Labor said in an email response to Oswego County Business magazine. “Population growth tied to the buildout of Micron Technology semiconductor complex in Clay is also expected to bring more workers and residents to the region, increasing demand for transportation services,” the agency said. New York Department of Labor highlighted current or projected job growth trends in various sectors. An increase in defense-related contracts at local high-tech employers has continued to support employment growth in the computer and electronic product manufacturing sector and Micron is expected to generate thousands of direct and indirect jobs as the project progresses. This sector paid an annual average wage of $117,500 in 2025 and employment in the sector is projected to grow by over 60% through 2032, making it the fastest-growing industry in the region. Typical occupations in this industry include electrical, electronic and electromechanical assemblers, software developers and industrial engineers, the state agency reported. Specialty trade contractors include several different types of tradespeople — electricians, plumbers, pipefitters and steamfitters and HVAC (heating, ventilation and air conditioning) mechanics and installers. Many of these positions are trained through apprenticeships, the state Department of Labor reported. The Interstate 81 construction project is generating local jobs, including construction laborers, projected to grow at a 6.4% rate, and operating engineers and other construction equipment operators, projected to grow at a 7.3% rate over the next several years. Construction of the Micron Technology facility is also “creating thousands of job opportunities that will continue over the next two decades,” the state agency reported. The specialty trade contractors sector paid an annual average wage of $86,200 in 2025. For Central New York, the challenge isn’t creating jobs, it’s filling them. Amy Stage, a deputy director at the Manufacturers Association of Central New York (MACNY), said meeting this unprecedented growth is a much larger task than just replacing retirees. “We’re seeing workforce gaps at every experience level,” she said. “Companies need entry-level employees, experienced technicians, supervisors, engineers and skilled trades professionals. The opportunity is tremendous, but we need more people entering these career pathways.” Employers are looking for people who can troubleshoot, read technical information, use computers and learn new processes, not just perform repetitive production work, Stage said. To address this demand, the MACNY created the Manufacturers Talent Institute, which aims to connect students and job seekers with meaningful career pathways while helping employers build their workforce. Twenty-one companies have so far signed up to provide opportunities for more than 800 students. “For us, the conversation isn’t just about filling jobs,” Stage said. “It’s about creating sustainable pathways that help people see a future for themselves in manufacturing.” Several manufacturing facilities in the region are in the midst of expansion: • TTM Technologies, a leading U.S. manufacturer of advanced electronics and interconnect solutions for aerospace, defense and high-technology markets, which has a plant in DeWitt, completed its buildout of an additional facility, adding 400 jobs and expanding production of high-tech circuit boards for defense and critical electronics applications. • In Cortlandville, the Byrne Hollow Crossing Plant, a dairy manufacturing and processing facility, is increasing its operations, creating 100 new jobs. • The Chobani yogurt company is building a 1.4-million square foot dairy processing facility in Oneida County. This will create more than 1,000 good-paying jobs and double Chobani’s New York state workforce, Stage said. Stage noted several ways that local, state and federal governments can help spur manufacturing job growth in this region. Elected leaders and public agencies could work with industry representatives to create pre-apprenticeship and registered apprenticeship programs seeking to upskill workers and improve employee retention. New York state has a variety of grants, tax incentives and financing programs to support site preparation, infrastructure, workforce development and capital investment. The U.S. Department of Labor has a pay-for-performance incentive program that provides employers $3,500 per new apprentice hired and retained for 90 days. MACNY was previously awarded an $87,000 federal grant that will cover 25 apprentices at nine companies. The manufacturing skills gap in the United States, at its current rate, could result in 2.1 million unfilled jobs by 2030, according to a study by Deloitte and The Manufacturing Institute. In New York state, that gap is on pace to exceed 100,000 unfilled positions within six years. Manufacturing companies will be counting on more women to help fill that gap. While women make up half of the overall U.S. workforce, they only account for 29% of the manufacturing workforce in this country, Stage said. “Pre-apprenticeship programs like Real Life Rosies help to bring awareness to the manufacturing industry to fill some of the gaps, but we have a long way to go and it starts with educating people at younger ages about careers in manufacturing and earn-and-learn opportunities,” she said. As for Micron, that $100 billion-plus project, considered the largest private investment in New York state history, is expected to eventually create up to 50,000 jobs throughout the region, factoring in the spin-off opportunities for construction and supply chains. The plant’s foundation was poured on July 9. “As America celebrates its 250th anniversary, data and memory are foundational to the modern economy — and Micron is increasing our U.S. investments to more than $250 billion through 2035 to meet that moment,” the company’s president and CEO, Sanjay Mehrotra, said in a news release. Bechtel, Micon’s construction partner in the project, reported that 4,500 people will be employed to help build the facility, including skilled craft professionals, local union members representing various trades and apprentices. The Syracuse-based CenterState CEO organization tallies the regional labor force at 397,582 workers (Onondaga, Cayuga, Cortland, Madison and Oswego counties). Job growth isn’t limited to the Central New York region. For the larger area covering portions of the Mohawk Valley, the North Country, the Southern tier, and the western part of the state, there are 155,601 employees in the advanced manufacturing sector, and 155,275 construction workers. The agency’s 2026 Economic Forecast report noted that 41% of community and business leaders surveyed said a shortage of skilled workers in this area remains a problem, though 77% shared a positive economic outlook for the year ahead. Beyond the semiconductor and advanced manufacturing areas, local business leaders also see growth in small manufacturing companies, storage businesses, housing, unmanned flight technology and general construction. “Productive reuse of property,” the report said, “will hopefully continue to preserve unique architecture while driving business.” The report identified several challenges for economic growth in the region, including an aging workforce, outdated equipment, the rising cost of raw materials and “the disconnect between the speed of business needs and the pace of talent readiness.”
From Oberweis Dairy to the Pittsburgh Penguins, this family is buying
The Hoffmann family has assembled an eclectic portfolio of more than 50 businesses, guided by a simple philosophy: Buy companies worth keeping — and don't sell them.
Registered nurse runs against incumbent Smucker in 11th Congressional District
Democrat Nancy Mannion is confident in her ability to oust longtime Lancaster County Congressman Lloyd Smucker and take the 11th District seat.
NFL Draft QB rankings for 2027: Arch Manning's stock falls after 4th-quarter meltdown
Arch Manning's disappointing finish in an upset loss damaged his stock in Week 6.
U.S. House Speaker Johnson returns to New Mexico for GOP congressional hopeful's fundraiser
By Patrick Lohmann, Source New Mexico — U.S. House Speaker Mike Johnson (R-La.) made his second New Mexico visit Monday evening in support of Republican Greg Cunningham, where he led a fundraiser in Las Cruces in the final stretch of the closely watched 2nd Congressional District race. Johnson last visited New Mexico in late August […]
Venables and Arbuckle recap Red River ahead of clash with No. 15 Kentucky
soonersvenablestexaskentuckyredrivermateermanning
‘Who Would Watch That?’ — Sports Media Analyst Not Sold on ESPN’s Super Bowl Alt-Casts Featuring Pat McAfee, Peyton Manning
Pat McAfee’s role with ESPN has only increased since the company decided to go all-in on the former Indianapolis Colts punter. But the most recent addition to his portfolio hasn’t gone over too well with fans and others in the media.
The SEC in a Sentence
It’s that time again, time to cram all that happened this weekend and will happen next weekend in the nation’a premier college football conference into a single sentence that will make our English teachers wonder what the point even was. It’s the SEC in a Sentence. It’s prettier than an Arch Manning interception, except when […]
‘Being Heumann' trailer brings Judy Heumann's fight to life
The crowd-pleasing new movie "Being Heumann" was inspired by the spirit and legacy of its firebrand namesake.
‘Being Heumann' trailer brings Judy Heumann's fight to life
The crowd-pleasing new movie "Being Heumann" was inspired by the spirit and legacy of its firebrand namesake.
7 ways science is changing the Arctic expedition experience
As travellers seek more meaningful experiences, HX highlights seven ways that science-led travel is changing the Arctic expedition experience.
Aaron Rodgers surpasses Ben Roethlisberger, Peyton Manning in major achievements
Steelers QB Aaron Rodgers sets multiple new milestones.
Roy Kaufmann discusses Oregon House District 18 campaign
Roy Kaufmann is running for Oregon House District 18 against Amanda Staehely following the retirement of Republican state Rep. Rick Lewis.
Miss Manners: Mind your own business at the nail salon
Advice from Judith Martin, Nicholas Ivor Martin and Jacobina Martin.
NYCC apologizes for ‘repeated disturbance’ during panel, actor slams fan for ‘disrespecting’ his castmates (exclusive)
“I will always step in to protect that space,” Rogers tells EW, while NYCC producer ReedPop says it’s “taking steps to ensure any future incidents are addressed in a swifter manner.”
The Real Alexis Lafrenière Is Standing Up
We likely never will know what manner of offers Chris Drury fielded when trade talk involved Alexis Lafrenière. For all we know, Laffy could have wound up anywhere – including Lower Slobbovia.
2027 NFL mock draft: First version includes a huge trade that powers Arch Manning to No. 1 spot
I typically avoid trades in early mock drafts, but with the Jets armed with a war chest full of draft capital, they decide to move to the top and take Manning as their quarterback of the future.
Week 6 brings major opportunities in Heisman Trophy race
Arch Manning's Heisman case needs a spark, and the Texas quarterback will have plenty of opportunities to make one.
Publication is not the finish line for open science
Tracking of open science must look at wider cycle, say Christopher Erdmann and Eleonora Colangelo
GA-ASI Recognizes Three Small Business Suppliers for Quality Performance
General Atomics Aeronautical Systems, Inc. (GA-ASI) has launched a new annual Supplier Quality Recognition program intended to recognize small businesses...
Arch Manning and mother sign NIL for heart health supplements
University of Texas Quarterback, Arch Manning commits to a NIL nationwide brand-deal alongside his mother, Ellen Manning, to Humann.
Leipzig Rule Out Nagelsmann Return Despite Demichelis Pressure
Internal unrest grows as Martín Demichelis faces a season-defining gauntlet, but the Red Bulls are dismissing rumors of a sentimental reunion with their former Champions League mastermind.
Manny's exit boosts McCoy in supervisor race
Three candidates remain in the battle to represent D8.
Texas QB Arch Manning Receives Bad News From “NFL Folks”
The Texas Longhorns quarterback Arch Manning entered the 2026 season carrying enormous expectations, including plenty of discussion about eventually becoming one of the first players selected in the NFL draft. Just four games into the season, however, at least one prominent NFL draft analyst believes Manning has significant work to do before reaching that level.CBS […] The post Texas QB Arch Manning Receives Bad News From “NFL Folks” appeared first on HEAVY.
CAPE 35th Anniversary Gala: Randall Park, Manny Jacinto Celebrated
The Coalition of Asian Pacifics in Entertainment celebrated 35 years of advancing Asian and Pacific Islander representation in entertainment.
Longhorns and Sooners bring dominant defense, sputtering offense to Cotton Bowl
Texas quarterback Arch Manning has been inconsistent and Oklahoma's John Mateer has had a rash of turnovers.
'I've learned a lot ': John Mateer trusts his confidence ahead of Red River Rivalry
redriverrivalryoutexasmateermanningvenablessarkisian
The Harvard Crimson (@theharvardcrimson)
83 likes, 0 comments - theharvardcrimson on October 6, 2026: "Harvard’s Faculty of Arts and Sciences is launching 25 tenure-track faculty searches, FAS Dean Hopi E. Hoekstra announced in a Monday email to faculty, further loosening a University-wide hiring freeze instituted last spring as the school draws an influx of philanthropic support. The searches, which include positions across the FAS’ three divisions and the School of Engineering and Applied Sciences, come less than a week after Hoekstra announced the school would also be upping Ph.D. admissions for the upcoming admissions cycle — and as the University continues soliciting support from donors for its academic programming. Full story linked in bio. 🖋: Abigail S. Gerstein and Amann S. Mahajan 📷: Mae T. Weir".
The Ankler-MIPCOM CANNES Future of Entertainment Award to Honor Dhar Mann
MIPCOM CANNES and The Ankler will present the inaugural Future of Entertainment Award to Dhar Mann
Terance Mann featured in 9.1% of trades built on …
Terance Mann featured in 9.1% of trades built on …
Authorities ID body of man found behind Fairview business
Authorities identified the man found dead behind a Fairview, Oregon business as 49-year-old Kerry Cottrell. Investigators suspect a medical condition, with the medical examiner to confirm cause and manner of death.
Dhar Mann says YouTubers aren't his rivals. Hollywood is.
BURBANK, CALIFORNIA − Dhar Mann doesn't consider other digital content creators his competition.
Stanford Professor One Of Three Scientists Awarded The Nobel Prize In Medicine
Stanford professor Karl Deisseroth joins Peter Hegemann and Georg Nagel as winners of the 2026 Nobel Prize in Physiology or Medicine for their work on optogenetics.
Nobel Prize in medicine jointly awarded to Karl Deisseroth, Peter Hegemann and Georg Nagel
The Nobel Prize in medicine was awarded Monday to Karl Deisseroth, Peter Hegemann and Georg Nagel for their research into light-gated ion channels and optogenetics. The prize money this year is 12 million…
American Deisseroth and Germans Hegemann and Nagel win 2026 Nobel medicine prize
Scientists Karl Deisseroth, Peter Hegemann and Georg Nagel won the 2026 Nobel Prize in Physiology or Medicine for "discoveries concerning light-gated ion channels and optogenetics," the award-giving body said on Monday.
Nobel Prize in medicine awarded to three scientists for their work ‘concerning light-gated ion channels and optogenetics’
The 2026 Nobel Prize for physiology or medicine has been awarded to three scientists – Karl Deisseroth, Peter Hegemann and Georg Nagel – for “their discoveries concerning light-gated ion channels and optogenetics.”
Scientists win Nobel Prize in medicine for work on ‘light-gated ion channels and optogenetics’
Scientists to Karl Deisseroth, Peter Hegemann and Georg Nagel won the 2026 Nobel Prize in Physiology or Medicine.
2026 Nobel Prize in Physiology or Medicine awarded to Karl Deisseroth, Georg Nagel and Peter Hegemann for work on optogenetics
Karl Deisseroth, Georg Nagel and Peter Hegemann developed optogenetics, which uses light and genetics to control individual cells
Turnover issues, Jalen Washington highlight Tennessee basketball scrimmage
Jalen Washington, Manny Green and Terrence Hill Jr. were stars of Tennessee basketball's open scrimmage on Oct. 3 at Food City Center.
Memorial Hermann In the Pink of Health holds 26th Annual Luncheon
Today Memorial Hermann In the Pink of Health held the 26th Annual Luncheon at The Woodlands Waterway Marriott Hotel & Convention Center. Memorial
New stationery business opens in the Midlands
Mayor Daniel Rickenmann also attended a ribbon-cutting ceremony for a new business Friday, October 2.
National media voices concerns for OU ahead of Red River Rivalry
ouredrivertexasvenablesmateermanningsarkisian
Allianz names new CEOs at Allianz Partners and Allianz Direct
Philipp Kroetz moves from Direct to lead Partners, with Partners COO Laurent Floquet taking over Direct, as Tomas Kunzmann heads to the Allianz SE board
Manny quits D8 race after sex assault charge
The latest story in news followed a June allegation.
Manny Yekutiel drops out of SF supervisor race after new allegations of sexual assault
Manny Yekutiel is dropping out of the District 8 supervisor race in San Francisco following new sexual assault claims.
'This is what happened with Claude and me': AI's failed attempt to crack the Riemann hypothesis led mathematician to a breakthrough
An attempt by Anthropic's Claude failed to prove the Riemann hypothesis, but it did produce something genuinely useful: inspiration.
Ubisoft Adopts Massive Entertainment for Group Led by Christoph Hartmann
Games company Ubisoft has landed on Massive Entertainment as the name for what it has been calling "Creative House 2," led by GM Christoph Hartmann.
Ubisoft Adopts Massive Entertainment as Name of Studio Group Led by Christoph Hartmann
Games company Ubisoft has landed on a name for what it has been calling “Creative House 2,” led by general manager Christoph Hartmann, the former head of Amazon Games who recently joined the team. The group is being named Massive Entertainment, adopting the name of Ubisoft’s Sweden-based studio that has been part of the company …
Nathan J. Nordmann, M.D., Joins Baptist Health Miami Neuroscience Institute as Director of Spinal Oncology and Co-Director of Spinal Radiosurgery
August 27, 2026 – Fellowship-trained neurosurgeon Nathan J. Nordmann, M.D., has joined Baptist Health Miami Neuroscience as director of spinal oncology and co-director of spinal radiosurgery. He specializes in the surgical treatment of conditions affecting the brain and spine, with advanced expertise in primary and metastatic spinal tumors, complex spinal pathology and minimally invasive surgical techniques. […]
Miss Manners: How to stay on good terms with the neighbors when you support different political candidates
Advice from Judith Martin, Nicholas Ivor Martin and Jacobina Martin.
Senate passes sweeping college sports bill
The Senate overwhelmingly passed the Protect College Sports Act Monday in a bipartisan manner to bring stability to the industry.
Primetime Review: That’s Entertainment?
If you decide to see Lance Oppenheim’s Primetime, it’s important to remember the title as you watch. Yes, this is a biopic of sorts about Chris Hansen and his work on To Catch a Predator, but it is more accurately about the quest for fame and using people’s trauma to attract ratings. True crime entertainment continues to have a prominent place in many people’s television habits, and this film asks us to examine what that means both for those whose stories have become our viewing pleasure and those of us watching. Primetime starts as Chris Hansen (Robert Pattinson) is told that his show, To Catch a Predator, is moving to a 9 PM spot opposite LOST. Chris and his producer, Andie (Merritt Wever), see this as an opportunity to make the program even more sensational, looking for bigger, more horrific predators. As part of their plan, they hire a young actor, Dan Plum (Skyler Gisondo), to play “Decoy Dan,” the person who greets the would-be predators who were catfished by Xavier Von Erck (Matthew Maher). Oppenheim, along with writers Ajon Singh and Luke Dittrich, is less concerned with an accurate retelling of the show as much as they are interested in interrogating the why of it all. That decision sometimes leaves Primetime feeling less like a biopic and more like a satirical look at the nature of programming like this. Visually, the movie is impressive. Oppenheim uses light and color effectively to cast Hansen as both villain and savior. Pattinson plays Hansen in an almost comical manner, as we see him wake his two young sons to watch a clip of the show, just to brag that he was moving into a prime spot on television. Even Andie struggles to accept a “nice” job when there is so much more fame to be found producing salacious true-crime content. Wever does an excellent job showing how the hunger for fame is not just in front of the camera, but in every aspect of the production. The heart of the movie, and the standout performance, belongs to Gisondo as Dan Plum. He is someone who just wants to get enough hours to be admitted into the Screen Actors Guild, and stumbles into this job without really knowing what it is. Throughout the film, we watch him suffer one trauma after another, ending with him witnessing the suicide of a District Attorney who is about to become the next unwitting star of Hansen’s show. If there is a sympathetic character in Primetime, it is Decoy Dan, and Gisondo plays him brilliantly. If you’re a fan of programming like To Catch a Predator, then Primetime will probably make you feel uncomfortable, and I think it’s worth sitting with that feeling and examining why we turn on shows that display the worst of humanity while we judge from our couches. Yes, it is correct to want to see people who would hurt children brought to justice, but perhaps it shouldn’t be something that we watch as entertainment. Rating: 3.5/5 This review originally appeared in The Dominion Post on September 25, 2026. MacGuffin or Meaning: Film & TV Reviews and Reflections is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Dana White Kills Stevenson-Pacquiao Talk
Dana White shut down Shakur Stevenson vs. Manny Pacquiao at a Zuffa Boxing press conference. An offer is out to Gary Antuanne Russell to unify at 140.
Nathaniel Brown: 'Keep going!'
A left-back wearing the number of a forward? It’s unusual, but it’s the perfect fit for our new No.11 Nathaniel Brown. The summer signing – known to his teammates as Nene – has spoke to member...
Naughty Dog Will 'Fully Reveal' Intergalactic in 2027, but No Release Window Yet
Naughty Dog studio head Neil Druckmann concluded this year's "The Last of Us Day" by giving updates on the developer's current projects, teasing two new The Last of Us projects that "will expand the canon of The Last of Us beyond Part I and Part II" without confirming whether or not either one of them is a game, as well as saying that its next game, Intergalactic: The Heretic Project, will be "fully reveal[ed]" next year.
Two new The Last of Us projects in “very early stages” at Naughty Dog
Two new projects set in the world of The Last of Us are in the “very early stages” at Naughty Dog, studio head Neil Druckmann said in a note marking the end of The Last of Us Day 2026.
Mann says voters are ready for a change from ‘Politics as it is’ during recent campaign fundraiser in Emporia Monday
It is the opinion of Democratic Candidate Chris Mann that voters are tired of "politics as it is" and ready fo...
Top Memorial Hermann Health System executive announces retirement
Dr. David Callender, who has been president and CEO of Memorial Hermann Health System since 2019, will retire at the end of the year.
A Front Desk That Never Sleeps
One job where AI chatbots have proven their utility is 24-hour customer service for all manner of businesses.
Youngster Sullivan's numbers speak for themselves
Cavan Sullivan's performances, goals, and assists since the World Cup put him up there with the MLS's top individual stars, including Lionel Messi, Antoine Griezmann and Luis Suarez. Few players beyond those mentioned can match Sullivan's goal contribution rate in MLS since the World Cup, and there is a strong argument to say the youngster has been the best player in the league during that time. Sullivan has seven goals and five assists in MLS this season.
Klopp sees no reason for negativity after Germany's setbacks
Jürgen Klopp has refused to be hit by a resurgent wave of negativity after two setbacks in his first two games as Germany coach. Following a disappointing last-32 exit from this year's World Cup, Klopp replaced Julian Nagelsmann.
Recommended Reads: 'Lessons From the Front Lines' offers practical wisdom for running a business
Lessons From the Front Lines by Kurt Schauermann Readers looking for practical business wisdom grounded in real-world experience will find this book informative and inspiring. Drawing on more than four […]
Arch Manning discusses close wins against Tennessee, Ohio State
Arch Manning discusses winning close games at Tennessee and Ohio State.
8th Congressional District race is essentially tied, poll shows, with warning signs for both Gabe Evans and Manny Rutinel
The poll was conducted by a Republican firm on behalf of a conservative political nonprofit that doesn’t reveal its donors and is backing Evans, the district’s Republican incumbent.
Qua Moss injury update for Tennessee football vs Texas
Qua Moss suffered an injury while tackling Arch Manning in Tennessee football's game vs Texas on Sept. 26 at Neyland Stadium.
Ilyas Sahin Shares New Science Study on Colorectal Cancer Liver Metastasis
Ilyas Sahin Shares New Science Study on Colorectal Cancer Liver Metastasis / Abdullah Burak Yildiz, Akhouri Kishore Raghawan, Albert Sickmann, Alpaslan
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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