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The Fitzroy Grove in Rogers sells for $51.85 million
A 250-unit luxury apartment complex east of Interstate 49 in Rogers sold recently for $51.85 million. The purchase price equals $207,400 per unit. An Arkansas limited liability company, whose manager...
Best business insurance for online startups and e-commerce stores
Get the business insurance your e-commerce store needs, including cyber liability and general liability coverage.
I-81 widening aims to improve freight reliability
Virginia has started a $219 million project to widen I-81 through Harrisonburg and Rockingham counties, improving freight reliability and traffic flow.
Trump Promotes Data Centers at Rally With Republican Facing Heat on Them
The president defended the complexes, which have become a liability for Senator Jon Husted in a challenging midterm race.
Ohio University Chemistry Professor Eric Masson develops open-source software to advance chemical research
New computational platform, Equilibrist, simplifies complex chemical data analysis and improves the reliability and reproducibility of scientific results.
Inc. Names Counterpart a 2026 Power Partner for Supporting Small Businesses
Counterpart, the AI-native insurance platform providing management and professional liability solutions to small businesses, has been named a 2026 Inc. Power...
Steelers Defense Struggles Again in Week 4 Loss to Browns
The Pittsburgh Steelers defense, after being the star of the show in Week 1 against the Atlanta Falcons, has regressed significantly and is clearly now the liability. Head coach Mike McCarthy has figured out the offensive issues, and the Steelers have averaged 27 points in their last two games. That's not to say the offense …
Why Is Caesars Entertainment (CZR) Reassessing Guest Safety After A Liability Verdict?
Caesars Entertainment (NasdaqGS:CZR) was found liable in a high-profile lawsuit over alleged systemic security failures at the LINQ Promenade, following a severe assault that left a guest with life-altering injuries. The verdict highlights concerns about security management and guest safety practices across Caesars properties. Investors are weighing potential reputational effects along with possible changes to operating procedures and regulatory scrutiny. This kind of legal and operational...
Rangers Could Trade Eovaldi to Create Payroll Flexibility
Chris Young must weigh Nathan Eovaldi’s reliability against a looming $25 million salary as the Texas Rangers prioritize financial agility and roster youth after a tough year.
In Mexico, dual citizenship is starting to sound like a political liability
A lot more people have dual citizenship today than in the past. But in Mexico, this has once again become a political issue.
Detroit Tigers Long for Someone Like Todd Jones Again
As Detroit’s bullpen struggles to close the door in 2026, we revisit the dominant, mustachioed reign of franchise saves leader Todd Jones and his unmatched ninth-inning reliability.
Trump threat to Taiwan’s Washington office sparks debate over island’s US policy
Ahead of expected Xi-Trump summit, some in Taiwan question whether Taipei’s funding of American think tanks has become a political liability.
KFF HEALTH NEWS: Medicaid Work Rule Leaves Homeless People in the Cold
By Katheryn Houghton KFF Health News August 6, 2026 MISSOULA, Mont. — Tywon Pugh has seizures that make it hard to find and keep a job. “They called me a ‘liability to the job site,’” Pugh said, recalling the words of his manager when a seizure cost him his last job at a fast-food restaurant
Scientists used centuries-old aurora sightings to reconstruct 8 solar cycles from 1560 to 1640; their method placed solar minima within 2 years with more than 90% reliability
Centuries-old reports of strange lights in the night sky have helped scientists reconstruct a missing chapter in the Sun’s history. A study published in Scientific Reports by Kristof Petrovay, Laura G.
Cash-hungry college sports programs are starting nonprofits to make money to stay competitive
To compete in the increasingly commercialized world of college sports, a growing number of universities are turning to nonprofits, limited liability companies and other “associated entities” to generate more revenue
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Editor’s Note: This is the second in a three-part series on how the Right should think about environmental and climate policy. Read Chris Barnard on Reclaiming Environmental Policy from the Left. More than a decade ago, the world’s governments negotiated and signed the Paris Climate Agreement, committing to hold global warming well below 2 degrees Celsius. In the following years, climate had immense cultural power. Greta Thunberg emerged. Fortune 500 companies established net-zero plans. The U.S. got the Inflation Reduction Act. Then the pendulum swung back. President Donald Trump returned to the Oval Office, speaking of green energy as a “scam” and carbon footprints as a “hoax” and on all matters of international policy emphasizing bilateral engagement and power over globalism and cooperation. The technology companies that had been at the forefront of net-zero pledges and green leadership discovered the importance of all-of-the-above power to their visions for artificial intelligence and began quietly postponing or removing their targets. On the left side of the political spectrum, rising concerns about inflation and cost pushed climate lower down in the stated priorities of voters and stump speeches of politicians. The moment is ripe for a reset on the politics of climate change and for conservatives especially to chart a course that acknowledges and addresses the real challenges in plausible ways. So what should we think about climate change as we enter a post-peak climate era? If it is neither an apocalypse nor a hoax, what will hold up as a durable view of climate change? And how does it project onto the concerns and priorities of the right-of-center’s emerging coalition? New to Commonplace_? Subscribe below to get the magazine in your inbox._ Subscribe A Solid Foundation As the politics and economics of climate careened over the past ten years, the physics carried on regardless. In 2015, the year the Paris Climate Agreement was adopted, the world emitted 41.2 gigatonnes of carbon dioxide. By 2025, emissions had risen only 2.4%, to 42.2 gigatonnes, because falling emissions from land use offset increasing emissions from fossil fuels. But slow growth in annual emissions is not rapid decline, let alone net-zero, so carbon dioxide kept accumulating in the atmosphere, going from 399 to 426 parts per million. Global temperature kept rising too, from about 1.1 degrees Celsius above the 1850–1900 average in 2015, to 1.4 degrees above it in 2025. None of this should surprise anyone. Even most prominent skeptics, like the authors of the 2025 report commissioned by the Trump administration’s Department of Energy, accept the basic physics. Carbon dioxide added to the atmosphere at industrial volumes accumulates and traps heat that would otherwise escape to space. That heat warms the upper ocean and increases temperatures at the surface. Increased ocean heat and melting of land ice cause sea levels to rise. Changes in the climate become noticeable to us as subtle shifts in temperature and precipitation, seasons arriving early or late, changes in the surrounding ecosystem, and weather extremes. The much more meaningful debate is not about whether these things are happening, but about what it all means for human societies. (While it is a proxy measure of overall risk, no one experiences global surface temperature.) This debate invokes at least three interesting questions: how much today’s warming is showing up in regional climate trends, how much more warming we should anticipate, and how extreme weather events can be understood in the context of climate change. Recent scientific advances give us new insights into each of these, but there is still much to learn. This is the context in which the next generation of conservative leaders will be the first to deal with significant climate change as a fact, not a forecast. It will be with them for their entire careers. Our evolving scientific picture of climate change will come from weather and climate records stretching further into the past, new kinds of observations in the present, better modeling tools for the future, and simply more time to observe the emergence of climate signals and their tangible effects on ecosystems and communities in the United States and around the world. The policy landscape will be shaped by not only the impacts of changes in the climate, but also by the ways in which societies respond and by the emergence of new technologies for both altering the trajectory of emissions and adapting to new climate realities. Global climate records now show the fingerprints of warming in different phenomena around much of the world. The IPCC, in its most recent assessment report, documents warming trends over all land regions, even as natural variability adds substantial variance to local trends. And the highest temperature extremes have become more intense and frequent, almost everywhere, since the 1950s. Scientists are highly confident that these changes are attributable to human influence. But confidence in detecting trends and attributing them to human influence degrades across heavy precipitation events; drought trends are heterogeneous and not attributable to human activity with great confidence. For hurricanes, tornadoes, and other severe storms there is even less confidence in trends or their relationship to climate change. In general, a fair summary of the evidence is that for well-observed phenomena, like surface temperature or heavy rainfall, with a clear relationship to warming, our multidecadal observations are consistent with human influence overcoming natural variability over long time periods and extremes increasing. For regions that are sampled more sparsely, or phenomena with a higher noise-to-signal ratio, we will need to observe them longer to understand the magnitude of the climate signal or improve dynamical understanding using models and observations together. But for Climate For those who can’t wait, we also have new techniques that attempt to understand the role climate change has in influencing particular extreme events. When the climate is changing and disaster strikes, it is natural to ask whether that disaster was somehow “caused” by climate change. For scientists and policymakers acting in good faith, answering that question helps develop a more accurate picture of the problem, how it may be getting worse, and what preparations we should be making to respond to it. It may, at some point, give some weight to how liability is assigned by courts or adaptation funding is distributed by society. But how we ask this question is extremely important. It is easy to get the analysis wrong by discounting the role that meteorology plays. As meteorologist Theodore Shepherd explained in a clear 2016 review of climate attribution methods, “if a weather or climate event is truly extreme in the present climate, then perforce it requires unusual meteorological conditions, which means that climate change is at most a contributing factor.” Share Scientists have two ways to probe climate as a contributing factor, both of which have entered media coverage of extreme weather events. One asks a probabilistic question: How much more likely is a particular event (e.g., a temperature record over a particular area) amid global warming? The answer involves using historical records and computer simulations to estimate the likelihood of such an event in both a changed and a preindustrial climate. The findings are less about the specific event, and more about events of that nature. The other question is: How has the changed climate affected the specific event in question? Here, scientists try to understand what a similar event would have looked like in the preindustrial climate. This is sometimes called the storyline approach, where the story is the specific meteorological details of the event. These methods offer ways to test the intuition of scientists about real weather extremes. In late June and early July of 2021, a persistent high-pressure ridge, or heat dome, set up over the Pacific Northwest and an extraordinary heat wave affected the area from Oregon to British Columbia. For six days, it shattered temperature records across the region and hundreds died from heat-related causes, in an area where such high, and persistently high, temperatures were well outside of experience and many live without air conditioning. Scientists have studied its connection to climate change using multiple approaches. This specific event was created by a rare combination of meteorological factors, a strong high-pressure ridge created the conditions for extreme heat, which occurred on top of higher average temperatures in the region from global warming. Probabilistic analyses showed that climate change increased the likelihood of such an event by at least 8-fold to more than 100-fold. One standout example found that such an event had effectively zero probability of occurring in the preindustrial climate. The enormous range in these assessments reflects how hard it is to estimate probabilities of events at the tail of the historical record. Estimates of the effect on the temperature of the event are more clustered. A recent review paper documents how multiple methodologies have found a positive influence, roughly 1-2 degrees Celsius of an anomaly that exceeded 15 degrees, of climate change on the temperature magnitude of the event. Multiple studies have investigated and found some positive influence of climate change in other extreme events. Attribution studies found climate likely increased the heavy rainfall that accompanied Hurricane Helene in North Carolina and surrounding regions in 2024. The extensive fires that struck Los Angeles in 2025 illustrate how the causal chain can become messy, though. Studies do detect a positive influence of climate on the event’s likelihood, but while climate change likely contributed to underlying aridity, it would not have played a role in the heavy winds or land practices that preceded disaster. These event attribution studies will become more common for extreme, or damaging, weather events. They can be produced quickly, and often are reported before peer review. As the Pacific Northwest heatwave example shows, when multiple methods converge on a positive attribution, the finding should probably carry some weight even if you have to be careful about accepting the results from a single study. I expect that as climate change proceeds and the climate thus departs further from a preindustrial counterfactual, the influence will become more detectable across a variety of extreme events and more easily identified. This will be used to cast blame, but can also be used to inform how communities and society adapt to ongoing change. We May Still Be Surprised One positive development, insofar as less climate change is better, has been that our central estimates for future climate change should probably be revised downward. Mostly, that is because the high-end warmings that scientists regularly analyzed about ten to 20 years ago, driven by high emissions throughout the twenty-first century, now appear to be somewhere between unlikely and impossible. At one time, the upper end of mainstream climate projections extended well into 4 to 6 degrees Celsius of warming by the end of this century, which, models suggest, would have wrought enormous real-world damage. Current energy and policy trends now point toward 2.5 or 3 degrees. Damages and risks are commonly modeled as increasing steeply with more warming, so this is already a better-than-previously-expected outcome for the climate (which is independent of the physical response to emissions). But we should maintain a wide range for plausible outcomes and prepare for the possibility of being surprised. Emissions trajectories are subject to deep uncertainty, the physical climate response is still developing, and whatever change occurs in the climate will then be mediated through unpredictable economic, social, and political institutions. Over the past decade, the pace of warming surprised some keen observers and appeared to accelerate, though not yet outside the range of expectation provided by climate models. The reasons for that apparent acceleration are being actively studied (as was the apparent pause in warming from 1998 to 2012), but no single driver has emerged. Some blame it on the El Niño, variability which would have no bearing on climate. Some think it is a result of factories in East Asia and global shipping fleets cutting aerosol emissions, which in the strongest version of the argument would indicate higher climate sensitivity to carbon-dioxide emissions. Others are more measured, not yet ready to draw solid conclusions as to whether climate projections require revision. We will have to see. Long-Term Thinking Climate change asks us to think over long time scales. But the pace of human-driven warming is compressing a large global change into a century. Changing weather patterns and extreme events are already causing adjustment costs and damages and will do more. Adaptation will help, but it is not free. For some communities, these costs will erode livelihoods and well-being, and may force migration. Are we prepared for large-scale managed retreats in the United States? Thankfully, American wealth, geographical diversity, and moderate climates may leave us better prepared than many around the world. But wealthy countries can still suffer serious disruption from narrowly concentrated costs, even if they appear entirely manageable in aggregate. Readers of Commonplace are familiar with the challenges of rapidly adapting to economic forces. The displacement that came from the China Shock is barely perceptible in aggregate GDP and employment data, but it affected millions of people and those people were far less mobile than economic models tended to assume. Deindustrialization rippled through the nation with enormous effects for not only our economic vitality, but also our national security. The forces surrounding climate change may not be so different; the world gets richer and must accept some diffuse costs. Those may be modest overall, but cause all manner of unpredictable effects with which policymakers must cope. In the case of the China Shock, our faith in a growing pie served us poorly. We’ll need to do better on climate. Leave a comment
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I found myself fielding a lot of questions from folks who don’t usually talk much about AI this week. They were mostly along the lines of “do you think AI is going to kill us all?” or “how worried should I be about this human extinction stuff?” Motivating this wave of existential anxiety was the highly dramatic resignation of now-former Anthropic employee Jacob Coxon, who quit his job while publicly sharing his concerns about safety practices at the leading AI companies. More specifically, he declared that almost everyone at OpenAI and Anthropic, the leading AI labs, believes that there’s a decent chance the AI systems they’re producing could “kill us all” by the end of the decade, and the companies aren’t “acting responsibly.” Other AI safety researchers, including those still employed at Anthropic and OpenAI, all confirmed that yes, Coxon is correct, they’re all worried that their company’s products might prove fatal for the entire human race as well. Two more AI employees quit and joined the chorus. Now, the warning shot has been covered everywhere from the Wall Street Journal to Fox News to WIRED to the Guardian. I understand why all this sounds scary, but my response to those who have asked, has generally been: No, you don’t need to worry that AI will kill go rogue and kill us all. But that does not mean we shouldn’t worry, period. Far from it. The companies building AI products are now among the wealthiest and most powerful entities in the world. And they very much are building enormous engines of mass surveillance, extraction, and automation. They can and have allowed their AI systems to carry out felony hacks of other companies, provided the government with autonomously generated kill lists, and sold enterprise technology to firms around the world that is explicitly intended to replace jobs. But “AI” has done these things not because they have all-powerful minds of their own but, ultimately, because people have programmed, calibrated, and directed them to. In other words, it’s not AI we need to worry the most about. It’s the people and corporations working to profit from and gain power by deploying it. The technology is sophisticated, sure, and, especially in cybersecurity contexts, potentially disruptive to plenty of existing systems. But if we want to stop this predatory, profiteering, and extractive form of AI—and it’s worth noting that at this point, most people do—we absolutely can. A quick note/plea: I can only do all of this with the support of readers like you, so if you find value in independent, critical tech journalism and analysis, please consider becoming a paid subscriber. I want to keep as much of this un-paywalled as absolutely possible, and I need your support to do so. Many thanks to all who continue to chip in, it’s very much appreciated. Onward. Subscribe First, some context: AI industry folks like Coxon have been discussing the prospect that AI will destroy humanity for years. Even before the beginning of the AI boom, many working in the industry, from the executive staff to the rank and file researchers, have obsessed over ‘x-risk’, or the possibility that AI will become sentient or semi-sentient and move one way or another to exterminate humanity. This is ostensibly why Elon Musk bankrolled OpenAI in the first place, and is the grounds for his lawsuit alleging OpenAI betrayed its charter by abandoning its nonprofit status to become a commercial enterprise. Many AI engineers and startup founders have calculated their own personal p(doom), or the probability that the tech product they are working on will initiate an actual humanity-extinguishing apocalypse. 10-25% p(doom)s are pretty common. (I wrote about a long weekend I spent among these folks at one of their top conferences here, to give you an idea of their ideas and belief systems.) Sam Altman himself drove the narrative of the imminent rise of a super-powerful AI, or artificial general intelligence, to prominence by declaring that the technology he was building posed an existential risk to humanity. This idea is in other words baked into the DNA of modern AI companies and into the products they engineer. It’s also why the industry is routinely accused, by myself and others, of “doom marketing,” ie, using such proclamations and framings to impart the sheer power of the technology behind your product onto investors, partners, consumers, and the state. Some ambient understanding of this tendency may have helped prevent the press from repeating the claim every time one of the x-risk folks made it over the years, including when they quit their jobs at AI companies while doing so. Yet Coxon’s AI x-risk alarm has broken containment, as they say, and has exposed the idea to the mainstream media once again. This has happened, I think, for a number of reasons. First, when AI CEOs were going around saying AI might kill everyone in 2023, their companies were well-capitalized, but not nearly to the extent they are today. They were more easily dismissed as eccentric geeks of the sort that Silicon Valley is supposed to produce. Now, not only do their products have much greater market saturation, but people are more aware of a) the often unethical ways the executives and companies comport themselves b) the other adverse impacts of AI that have already arrived, and c) the physical cost of building these systems, particularly when it comes to data centers. Finally, toss in the constant stream of headlines in 2026 about AI models going rogue or potentially upending the world’s infrastructure. [ ](https://www.bloodinthemachine.com/p/with-the-backlash-to-data-centers) [ With the backlash to data centers, Flock and AI glasses, a mass opposition to big tech is underway. Silicon Valley is in denial. ](https://www.bloodinthemachine.com/p/with-the-backlash-to-data-centers) Brian Merchant · Aug 27 [ Read full story ](https://www.bloodinthemachine.com/p/with-the-backlash-to-data-centers) As a result, general sentiment was already overwhelmingly skeptical of AI and its overlords, so the table was pretty well set for someone to come along and say ‘just a reminder, the companies that are building the product that promises to take your job and leave a data center in your neighborhood also think that it might exterminate the human race’ and get a strong reaction from the media and the public. The question is: Should we understand this stuff as hype, strategically fanned to feed already swelling valuations? Is it doom marketing? Genuine cause for alarm that the infrastructure that undergirds modern life is facing a novel threat vector? Or reason to be sincerely worried that AI companies are amassing too much power, and that their products are genuinely dangerous? The answer, I’m afraid, is “yes.” Let me try to untangle all of this a bit, because arguments over how to navigate this moment are extremely heated right now, as they are essentially arguments over how to approach the politics of AI at a moment where there may be a unique opening for action. Those sympathetic to AI alignment concerns and x risk arguments—which increasingly includes a faction on the left who want to shut down AI over safety concerns—argue that people who dismiss AI as all hype have their heads in the sand. Meanwhile, critics of the x-risk narrative—which I might note includes a cadre of investors and tech folks on the right, too—argue that it is hype and can be used to further inflate valuations or for pursuing regulatory capture. The challenge is that many feel that dismissing AI as just hype or purely marketing also diminishes the urgency of taking on the AI industry as the novel and threat to labor, civil society, and the public sphere it is; others that by accepting the industry’s own terms, we imbue it with undue power and enable it. But let’s be clear: Declarations that AI is so powerful it might end the world are a kind of marketing, and anyone who says otherwise is just as off base as those who say that’s all that it is. If you don’t think that these sub-trillion dollar companies have higher-ups who noticed that when their founders talked about super-powerful dangerous AI they got spikes in media interest and phone calls from investors, or that those founders didn’t notice that themselves, and lean into certain narratives to advantage their products, then I don’t know what to tell you. Not all marketing is a Pepsi ad campaign with a celebrity spokesperson. Yet confronting the AI industry should certainly be considered an urgent project. Do I share the x-riskers’ fear that out-of-control, super-intelligent AI agents might end the world? I do not. I’ve read a good deal of AI extinction literature over the last couple of years and I have not come across a credible, step-by-step documentation of how exactly AI might move from self-recursively improving AI to killing every single human on the planet. Most of what I’ve read seems predicated on a sort of reverse Ian Malcolmian logic: Eventually, it becomes smart enough and AI, uh, finds a way (to exterminate humanity). Are the AI companies also overstating and dramatizing what their products can do? Yes, pretty much all the time. They’re in a knife fight for market share and are trying to win customers and government contracts before their investors come knocking. And yet. They have concentrated enormous amounts of compute, have extensive data collection and surveillance capacities, have inserted themselves into the state in numerous capacities, including military kill chains, and they are being run by egomaniacal billionaires who are rushing to monopolize an entire new market. The way I think about their most recent frightening-seeming exploits is not as a “swarm of rogue AI agents building a new civilization” or whatever, but as corporations with a hitherto-unimaginable amount of compute at their disposal recklessly experimenting with automation programs, completely unafraid of any repercussions because we have been unwilling or unable to impose any on them. So I think we should welcome any newfound imperative to hold them accountable. I also think that ultimately, the AI critics, Pause AI folks, leftists, doomers, effective altruists, and, honestly, most of the public, want a lot of the same things: legitimate checks and limits on AI companies’ power, actual transparency into what the companies are doing, and for more of AI to be under public control. (Ultimately, a lot of what animates the x-risk fears are rooted in just that: a fear of losing control.) How we move towards all this, exactly, is the question of the day, and while there’s much to be argued over in terms of building a viable political platform to challenge the AI industry’s power, I do want to cast a vote against one particular approach. Not to pick on Chris here, as there are a lot of folks out there proposing stuff like this, and the policy ideas actually stem from AI safety groups. But not only would this be challenging to land politically (I can already hear the ‘China will beat us to AGI’ calls) and all but unworkable in practice, this approach is a) far too limiting, b) fails to address the current harms caused by AI and c) would likely only wind up serving Anthropic and OpenAI; it’s what regulatory capture looks like in action. Full model transparency is the floor for what should be on offer here. If these companies believe their products will kill us, the very least we deserve is to know how. It’s in the public interest. I would also argue we might get a lot of the way to stopping any currently envisioned robot apocalypse simply by forcing AI companies to assume liability, and to submit to the full brunt of the law. If Sam Altman were liable to be charged with a felony for approving the hack on Hugging Face1, if Google was forced to pay defamation fines each time it published a false and injurious AI Overviews, these companies might suddenly find cause to restrain their models’ output, and we might hear less about rogue AI. We would need to introduce new frameworks and available tools for tracking automated lawbreaking, to be sure, but I’d wager that little would frighten the AI companies more than actually being held accountable for what their products enable. To that end, Illinois has passed an AI liability law, which the industry fought tooth and nail, and Florida is considering one. The next steps would be towards moving AI under public control; again, it’s only reasonable, since everyone, not just AI insiders, should get a say over how a technology whose developers say might kill us is developed and deployed. Dismantling the whole industrial project as currently structured should be on the table, too, pending democratic input. But that’s for another post. For now, suffice to say that while I won’t be losing any sleep about an AI-enabled extinction event, Mr. Coxon and co. have given us an opportunity to underscore the urgency of the clear and present damage AI companies are doing, the extreme power they wield and the extent to which they hold themselves unaccountable, and the abundance of political capital there is out there for taking them on. Subscribe 1 Purely speculative! I do not know if he did or not.
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Pioneer of China NewCo model sued in US over trade secret misuse, double-dealing
A legal feud unfolding in New York is putting a spotlight on the work of a business development veteran who is credited for pioneering one of biopharma’s hottest dealmaking mechanism: the China “NewCo” model. In a lawsuit originally filed in New York state court and recently moved to federal court, China’s Lepu Medical Technology has alleged that biopharma business development consultant Su Zhang, who was hired to help shop its GLP-1 weight-loss candidates to Western partners, engaged in corporate double-dealing and trade secret leaks. According to the complaint, while acting as Lepu’s primary dealmaking liaison for a group of obesity and metabolic disease drug candidates, Zhang was secretly double-dipping as the acting chief business officer for a direct competitor, BrightGene Pharmaceutical. “She never adequately disclosed the role, never sought Lepu’s consent, and never proposed any safeguard,” Lepu alleged in its complaint, which was filed in July after Zhang’s consulting firm, CoDevCo, sought certain transaction-based success fees from its angry customer through an arbitration process in Singapore. Lepu, the parent company of Lepu Biopharma, has asked Zhang to pay back its $500,000 retainer and disgorge all benefits she received during the alleged breaches of fiduciary duty, plus other damages and relief. The company has also requested the court grant injunctions to protect Lepu’s trade secrets. The ill-fated partnership officially kicked off in December 2024, when Lepu tapped CoDevCo as its “exclusive business development mechanism” to identify collaborators for the company’s drug candidates. According to Lepu’s complaint, Zhang personally negotiated and signed the agreement as managing director for CoDevCo, which used her home address. Before the Lepu deal, Zhang made a name following a short stint as the global head of business development for Hengrui Pharmaceuticals. It was during her tenure that Hengrui signed a landmark deal granting exclusive rights for a portfolio of GLP-1 assets to Hercules, which was at that time newly established by a group of private equity and venture capital firms. In addition to the regular upfront and milestone payments, Hengrui also gained an equity stake in Hercules, which later became Kailera Therapeutics. The Hengrui-Hercules deal opened a new paradigm, where a Chinese biopharma company spins off certain early-stage assets to investors for further development through the creation of a new company abroad. The “NewCo” model quickly came into vogue as it allows Western investors to access high-potential assets originating from China at an early stage while giving the Chinese licensors an opportunity to reap long-term benefits through equity stakes in the new firms. The NewCo model proved its value when Kailera staged a record-breaking $625 million IPO on Nasdaq this April, merely two years into the Hengrui deal. Related Kailera CEO 'knew we were in a good spot' before obesity biotech's record-breaking $625M IPO On her LinkedIn page, Zhang described her work at Hengrui as “[b]uilding team and capability from the ground up,” forming NewCo and major pharma partnerships worth billions of dollars. Lepu clearly wanted that kind of track record to help boost its own cardiometabolic portfolio, which includes a range of assets for obesity, Type 2 diabetes, fatty liver disease and muscle preservation during weight loss treatment. “Lepu’s pipeline is very valuable, but only if Lepu could secure the right international partner to expand into the overseas market during the available commercial window,” the company argued in its complaint. The Chinese biotech said it had little knowledge of U.S. laws, customs or business practices in the business development field, and therefore “needed to rely entirely” on the expertise of Zhang and her team as the firm’s first engagement of a U.S.-based BD consultant. “Zhang’s dominating influence on the business development strategy is further evidenced by the fact that she personally controlled the business-development communications on behalf of Lepu with potential partners,” Lepu said in its complaint. After entering the deal, Zhang introduced Lepu to her four associates. According to Lepu’s version of events, all of them were allegedly employed at different time points to perform similar jobs at other Chinese companies that Lepu described as its competitors, while having access to Lepu’s confidential information. As such, Lepu described Zhang’s team as “a roster of individuals whose primary professional loyalty, by virtue of their concurrent full-time employment, ran to Lepu’s competitors.” As well as the specific examples set out in the case, a look at Lepu’s deals over the period suggests Zhang may have been involved in at least one transaction. During their partnership, Lepu, through its subsidiary Shanghai Minwei Biotechnology, also out-licensed its GLP-1/GIP/FGF21 agonist MWN105 to a NewCo called Sidera Bio in the fall of 2025. The deal included an upfront and near-term payment of $35 million, up to $1.01 billion in milestones, and a 9.99% stake in the Danish startup. It seems likely that Zhang facilitated the Minwei deal given that Lepu is on record as having used CoDevCo as its “exclusive business development mechanism.” The big shock for Lepu came in the form of a news article on June 25, 2025. The article, reporting on phase 2 data for BrightGene’s GLP-1/GIP receptor agonist BGM0504, identified Zhang as acting chief business officer of the Lepu rival. Blindsided by her association with BrightGene, Lepu confronted Zhang in July 2025. “Lepu was given assurances that there was nothing to be concerned about and told that Zhang would explain the matter to Lepu,” Lepu alleged in its complaint. “Zhang never did.” Lepu claimed that Zhang had the motive and opportunity to steer potential prospective partners toward BrightGene or other competitors. Later, in February 2026, one of Zhang’s associates joined BrightGene as the vice president for global business development, according to the complaint. Around the same time, Lepu sent written demand letters asking Zhang to account for her BrightGene role, identify what confidential data were shared with the rival firm, and provide any conflict-of-interest or firewall policies during the engagement. According to Lepu, neither CoDevCo nor Zhang answered the questions in their responses. Related Novo vs. KBP: How a $1.3B deal turned into a fraud accusation and an international legal fight In a motion to dismiss filed with the U.S. District Court in the Eastern District of New York on Sept. 4, Zhang’s legal team argued that Lepu’s agreement was signed with CoDevCo, and that an employee of the contractor does not owe fiduciary duties to the client. In its complaint, Lepu said: “That CoDevCo was the contracting entity does not insulate Zhang from personal liability for duties she personally undertook and personally breached.” Taking the argument one step further, the defending party argued that the consulting agreement “does not create a fiduciary relationship even between CoDevCo and Lepu; instead, it identifies CoDevCo as an independent contractor retained to market Lepu’s business to potential western partners.” Although CoDevCo was Lepu’s exclusive business-development contractor, there were no terms stipulating that the consulting firm should serve only Lepu, Zhang’s lawyer noted. As to Lepu’s claims that Zhang misappropriated trade secrets, the defendant argued that Lepu authorized the use of the information so Zhang’s team could perform their service per the agreement. In a rebuttal filed on Sept. 11, Lepu’s lawyer set out why they believe the Chinese biotech satisfied New York law’s misappropriation definition by alleging that the defendant used a trade secret “in breach of a duty or through improper means.” As an alternative to dismissing the suit, the defendant suggested the action should be stayed pending outcomes from the arbitration of a separate case in Singapore. While NewCo pioneer Zhang is defending her business arrangements, momentum behind the NewCo trend has continued unabated into 2026. Through August, Chinese biotech assets have spurred 15 NewCo deals this year, according to local trade publication PharmaDJ.
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Parliamentarians representing 16 countries from across the Asia-Pacific region concluded the Ninth Meeting of the Asia-Pacific Parliamentarian Forum on Global Health (APPFGH) today, reaffirming their key role in advancing universal health coverage (UHC) amid the risks and opportunities posed by AI and climate change. In adopting the Phnom Penh Communiqué, parliamentarians urged fellow legislators regionwide to strengthen sustainable financing for UHC to widen access to health for all, including the most vulnerable populations; promote responsible governance of AI amid ethical concerns over this fast-evolving technology; and build climate-resilient health systems to anticipate and respond to mounting pressures ranging from rising sea levels in coastal areas to air pollution and other environmental degradation.The National Assembly of Cambodia, with support from Cambodia’s Ministry of Health and the World Health Organization (WHO), hosted the Forum in Phnom Penh from 11 to 13 August 2026 – the first time the Forum has convened in a Mekong country.Parliamentarians urge action to close gaps in accessIn the Communiqué, parliamentarians recognized that at-risk and marginalized groups are the ones most severely affected by gaps in access to health services. These groups include people living in poverty, women and children, persons with disabilities, older people, migrants, refugees, and those in rural, remote or island communities. The Communiqué urges fellow parliamentarians and policy-makers to advocate for laws and policies that support sustainable financing to protect people from financial hardship, with a focus on primary health care, prevention and equity. "The Communiqué is a call to action. It sets out ambitious, concrete measures that deliver meaningful impact on the ground. We are all accountable for advancing universal health coverage and translating our commitments into tangible results. Cambodia is fully committed to advancing UHC, including the promotion of ‘healthy people, prosperous country’ campaign,” said Samdech Maha Rathsapheathika Thipadei Khuon Sudary, President of the National Assembly of the Kingdom of Cambodia.His Excellency Professor Chheang Ra, Minister of Health of the Kingdom of Cambodia, highlighted the need for collaboration beyond the health sector. “Universal health coverage cannot be achieved by the Ministry of Health alone. It requires support, particularly from parliamentarians, across political, legislative, financial, social protection, education, infrastructure, and environmental domains. While each country follows its own path, one factor is universally critical for success: strong governance and leadership. We all believe in this principle, and in our respective political roles, we remain committed to strengthening these key success factors to ensure that no one is left behind.”Promoting responsible AI adoption Parliamentarians acknowledged that, while AI has already demonstrated its ability to improve access to health services and support delivery, careful and ethical governance is necessary to safeguard quality, safety, privacy and public trust. This underscores the importance of parliamentarians in promoting legal and regulatory frameworks addressing liability, records ownership and data governance, while embracing innovation that protects ethical practice.“Without strong governance, safeguards for privacy and data security, sustainable financing, and attention to those most at risk of exclusion, new technologies may widen existing gaps instead of closing them. This is why parliamentarians matter. We pass laws. We approve budgets. We scrutinize government action. We represent communities. We can ask whether health services are reaching rural, remote, ageing, poor, and marginalized populations. We can ask whether innovation is being guided by equity, evidence, and ethics,” said Hon. Man Hee Lee, President of the Asia-Pacific Parliamentarian Forum on Global Health.Building climate-resilient health systemsParliamentarians also reiterated that the climate crisis is a direct threat to people’s health and to achieving UHC more broadly, deepening the same gaps in access already faced by at-risk and marginalized communities. They recognized the need for WHO Member States to ensure sufficient national appropriations and oversight, and for parliamentarians to raise awareness in their constituencies and mobilize local action in building climate-resilient and sustainable health systems.“Universal health coverage, climate change and AI cannot be addressed in isolation. The same communities struggling to access health services today are often the ones most exposed to climate shocks, and most in need of the opportunities AI can offer if this technology is governed responsibly,” said Dr Saia Ma’u Piukala, WHO Regional Director for the Western Pacific. “Having served previously in this Forum myself as a parliamentarian from Tonga, I recognize how the Phnom Penh Communiqué reflects the shared resolve of legislators across the Asia-Pacific region: the laws parliamentarians pass and the budgets they approve help ensure this progress reaches the people who need it most.”As the Forum drew to a close, delegates reflected on what they would carry back to their own parliaments and constituencies.“I wish to share three points here worth carrying home from Phnom Penh: we need to invest in primary health care as the foundation of coverage; we need to remove the barriers that keep people from care, whether financial, geographic or social; and we need to build systems that are inclusive by design, protecting those most at risk of being left behind,” added Hon. Ouch Borith, First Vice-President of the Senate of the Kingdom of Cambodia.###Notes for editors:The Asia-Pacific Parliamentarian Forum on Global Health (APPFGH) is a platform for parliamentarians to exchange ideas, build political will, strengthen capacity and foster collaboration towards sustainable health action. This was the ninth meeting of the APPFGH, with the theme “Universal Health Coverage in the era of Climate Change and Artificial Intelligence”. Target 3.8 of the Sustainable Development Goals calls on countries to achieve universal health coverage, including financial risk protection, access to quality essential health services, and access to safe, effective, quality and affordable essential medicines and vaccines for all. In the Western Pacific, UHC service coverage index (SDG 3.8.1) rose from 63 in 2000 to 81 in 2023 (figures include Indonesia), and roughly one in four people in the Western Pacific have experienced financial hardship (SDG 3.8.2). Progress towards UHC in the Asia-Pacific region remains uneven, with hundreds of millions of people still lacking access to essential health services or facing financial hardship due to health-related expenses. Strengthening the role of parliaments – through legislation, financing and oversight – is central to closing this gap and accelerating progress towards UHC across the region.Parliamentarians participating in APPFGH in Cambodia this week include: Hon. Pehin Dato Adanan YUSOF, Brunei Darussalam; Hon. Rosmawatty ABDUL MUMIN, Brunei Darussalam; Hon. LORK Kheng, Kingdom of Cambodia; Hon. YOS Phanita, Kingdom of Cambodia; Hon. KHOUN Khundy, Kingdom of Cambodia; Hon. HENG Halim, Kingdom of Cambodia; Hon. KHOENG Noupheap, Kingdom of Cambodia; Hon. SENG Nhak, Kingdom of Cambodia; Hon. LY Sukry, Kingdom of Cambodia; Hon. NHOEURN Raden, Kingdom of Cambodia; Hon. Dr Ratu Atonio LALABALAVU, Republic of Fiji; Hon. Vijay NATH, Republic of Fiji; Hon. Man Hee LEE, Republic of Korea; Hon. Dr Jiho CHA, Republic of Korea; Hon. Jonghun BAEK, Republic of Korea; Hon. Youngsuk SEO, Republic of Korea; Hon. Dr Phayvanh KEOPASEUTH, Lao People’s Democratic Republic; Hon. Suhaizan Bin KAIAT, Malaysia; Hon. Dr Perpetua KONMAN, Federated States of Micronesia; Hon. Ganmaa DAVAASAMBUU, Mongolia; Hon. Charmaine SCOTTY, Republic of Naoero; Hon. Vincent Ambance KUMURA, Papua New Guinea; Hon. Dr Edwin CRUZADO, Republic of the Philippines; Hon. AUUAPAAU Mulipola Aloitafua Mulipola, Samoa; Hon. ASIATA TAVUI Tafu Salevao, Samoa; Hon. Dr Alani Petelo TANGITAU, Tonga; Hon. Paul PAOLO, Republic of Vanuatu; Hon. Franklyn Ezra WILLIAM, Republic of Vanuatu.For more information, contact: WHO Regional Office for the Western Pacific: wprocom@who.int National Assembly of the Kingdom of Cambodia (International Relations Department): ir.nacambodia@gmail.com
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