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Detroit Tigers Named a Landing Spot for Seiya Suzuki
Seiya Suzuki reaches free agency with Detroit's right field unsettled, and the Tigers are not the favorite. #Tigers
Phillies Mentioned as Possible Landing Spot for Teruaki Sato
The Philadelphia Phillies could look to add a power hitter to the lineup.
Pirates Named Surprising Landing Spot For NPB Star Teruaki Sato
The Pirates' front office has some work to do this offseason to add to the team.
Regional Science Consortium Researching Harmful Algal Blooms
If you've noticed large buoys or boats out on the bayfront and wondered what they were, you're not alone. The Regional Science Consortium is collaborating with Princeton Hydro on a research project funded by the U.S. Army Corps of Engineers to study ways to control harmful algal blooms. Dr. Jeanette Schnars, the Executive Director of the Regional Science Consortium, explained the goal of the research."We are researching different ways to control blue-green algae, which creates harmful algal blooms and releases toxins," Dr. Schnars said.The project aims to identify potential techniques for controlling harmful algal blooms in Presque Isle Bay.Schnars explained that people may notice circular floats in the water near Perry's Landing and Liberty Park. Those floats are part of the testing process."You might see a circular float, almost like a hula hoop, that is out in the bay, near Perry's Landing and Liberty Park area, and those limn corrals go all the way to the bottom. And what we will do are some treatments within the limn corral in the bottom," Schnars said.After samples are collected, they are brought back to the laboratory at the Tom Ridge Environmental Center for analysis."A lot of those samples are coming back here. We are going to test them for the harmful algal bloom toxins before, during, and after, and see how effective the testing was," Schnars said.Sarah Magyan, an aquatic biologist with the Regional Science Consortium, explained that the team also collects samples from locations throughout the region."We pull samples every week from 30 different sites, and then we bring those back here, we preserve them and run them through the ELISA test," Magyan said.Schnars said researchers hope the results will help them develop effective ways to reduce harmful algal blooms in the future."If we can do some treatments over space and time in upcoming seasons, we may be able to reduce the number of harmful algal blooms we have in this area," Schnars said.The research is also important for public and animal safety. Magyan explained that toxins produced by certain algae can affect the skin, nervous system or liver.While toxin levels may be low for people, she emphasized the importance of protecting pets that swim in local waterways."Toxins can either be skin toxins, nerve toxins, or liver toxins. While we have low levels for people, it is important that we are keeping our pets safe because we recreate with our animals in the water, and we see hundreds and hundreds of dogs on Presque Isle and the rest of the shoreline," Magyan said.Testing began in September, and Schnars said researchers expect to conduct at least another six to eight weeks of testing to better understand the effectiveness of the treatments.
Guardant Health (GH) Stock Looks Below Fair Value On A Huge Run
Guardant Health has turned into a dramatic long term story for shareholders, yet the real question now is whether the current US$158.60 price can be supported by the cash flows its business is expected to produce. With the stock sharply higher over several years and new clinical and regulatory developments landing, the focus has shifted to what the Discounted Cash Flow (DCF) view of its intrinsic value suggests about that price. Over the past 3 years the share price has risen by very large...
Yankees Named Top Landing Spot For Tarik Skubal Entering Offseason
The New York Yankees could look to make a big splash this offseason.
Yankees get $120 million prediction for NPB Triple Crown winner
The Yankees are a potential landing spot for the NPB star.
Troy Aikman responds to reported MNF contract tensions with Joe Buck: 'I'm looking forward to … where my next landing spot might be'
‘Business is booming:’ Broward welcomed many employers, expansions, Greater Fort Lauderdale Alliance says
Broward County welcomed a wealth of new companies in 2026 as the tri-county region remained an attractive landing spot for those seeking a better business climate.
Clearwater moves ahead with negotiations to turn The Landings golf course into sports complex
Ubisoft plans cuts at German studios, adding to wave of workforce reductions
Ubisoft is planning to reduce its workforce in Germany, where it operates a trio of studios, by about 100 workers, Game File has learned. The company wants to offer employees buyouts to, should enough people accept, avoid having to lay anyone off. “In Germany, we initiated discussions with the Works Council last week regarding a proposed voluntary departure plan across Ubisoft Dusseldorf, Ubisoft Berlin & Ubisoft Mainz,” a company rep told Game File. A “works council” is a union-like group representing employees. “The voluntary plan is the primary measure being proposed to support the intended organizational changes,” the Ubisoft rep added. The company declined to confirm the scale of the potential headcount cut. Of the impacted studios, Mainz might be the best known to the public. It leads development of the Anno series and shipped the well-reviewed strategy game Anno 117: Pax Romana in November 2025. Berlin and Dusseldorf operate as support studios within Ubisoft’s creative network. Berlin recently supported the development of Rainbow Six Siege and the Rayman Legends Retold remake. Dusseldorf also contributed to those projects, as well as The Settlers and Ubisoft-branded escape rooms. Dusseldorf is the biggest of the three studios, with some 400+ workers, compared to just over 100 at the other two, a source familiar with the reductions and the teams told Game File. More than half of these new reductions of about 100 people are expected to happen at Dusseldorf. The planned cuts were announced at a town hall for the German studios on Tuesday of last week. In an email follow-up, the studio group’s managing director, Benedikt Grindel, said the cuts were intended to “best position our German studios for the future... with a clearer focus on their role, capabilities and organizational setup needed for the work ahead.” The email was an echo of the past. In January 2025, Grindel had emailed the Ubisoft developers in his region (or studio “zone”) to explain that a round of 185 cuts at the time, including about 65 at Dusseldorf, were “essential to improve our operational efficiency and ensure the long-term sustainability of our studios, the zone and the company.” A half-decade of continued job cuts Ubisoft has been aggressively cutting its headcount for years. At the end of September 2022, it had 20,729 workers. By the end of March 2026, that total was down to 16,590. Studio management is trying to trim costs as it grapples with a changing industry and a drought of releases, let alone hits. The company announced earlier this year that it had reduced its costs since 2022 by “nearly €325 million” ($362m) and planned to lower them through 2028 by another €180 million ($200m). In June the company said it was closing down its Winnipeg and Belgrade studios and cutting roles in its Barcelona team. Even commercial and creative success hasn’t spared studios from this ongoing company-wide contraction. As Game File was nailing down details around the proposed cuts in Germany, Ubisoft management was informing workers of cuts in its Singapore studio, which shipped a hit remake of Assassin’s Creed IV: Black Flag this past July. Some 70 positions in Singapore are being eliminated “to align the studio with upcoming production needs,” per a company rep’s statement to Game File. In early 2024, a large team in the Singapore studio launched the multiplayer pirate game Skull & Bones. It performed poorly but has been supported with regular content updates since. Many of Ubisoft’s studios around the world are heavily subsidized via regional grants and tax breaks. Singapore had been among them for years, but received no such local assistance in the 12 months ending this past March. News of the Singapore cuts broke today alongside word that Ubisoft is also proposing the closure of RedLynx, pending negotiations with officials. The Finnish studio behind the motorbike series Trials was founded in 2000 and sold to Ubisoft in 2011. As reported by VGC (and corroborated by Game File), Ubisoft management told employees it could not come up with a new, sustainable assignment for RedLynx. The 2025 workforce at Ubisoft Dusseldorf were straight-up cuts. This time, Ubisoft is hoping the reductions at its trio of German studios will largely come from workers taking a payout to leave. The company offered such voluntary dismissals at its Massive Entertainment studio (The Division) a year ago. For the German studios’ buyouts this time around, Ubisoft and the Works Council had discussed a formula that’d pay a worker’s monthly salary multiplied by 1.5 and by the number of years they’ve worked at the company, according to Game File sources. The formula is still subject to negotiations with the Works Council and has not yet been part of an official offer to workers. It could be adjusted up or down, and it could be supplemented with additional bonuses. Asked about the floated payout formula, a Ubisoft rep told Game File, “The terms of a potential voluntary departure program remain subject to negotiation with employee representatives. No final agreement has been reached, and we won’t comment on specific proposals while discussions are ongoing.” Game File is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe Item 2: Epic’s AI adventures Epic Games (Fortnite, the Unreal engine) is all-in on using AI to try to transform the way it makes video games and game-making tools. It’s leaders appear to be undeterred by any resistance among gamers and some game developers around generative AI—and instead emboldened by advances, particularly in AI-assisted programming. A recap of the last three days: On Monday, Bloomberg reported that Epic management told workers last week that development of an upcoming game combining Star Wars and Marvel characters would be “AI first.” Employees would be expected to use AI models such as Claude to code the game. A manager told Epic’s developers there would be “[n]o more hand-written code” and that art for the game would be “generated with full AI workflows,” per the outlet. Just ahead of that story running, Epic founder Tim Sweeney tweeted: “We have a huge pivot underway here at Epic, moving developers around to retool for maximum AI acceleration. The aim isn’t to do the same stuff with fewer people, but to enable everyone here to build MORE and BETTER stuff, and to bring the benefits to all teams using Unreal.” In a follow-up, Sweeney predicted that most game development processes would be at least three times faster a year from now than they were in January 2026, thanks to AI. To a person on X who told him he was failing to read the room, Sweeney said: “Much of the room wants it to be 2016 again, but it’s not. Our job, as the provider of tools and technology to much of the industry, is to design for the present that is and the future that will soon be.” On Wednesday, Epic announced it was releasing a faster launcher for its Epic Games Store marketplace. It did so by stating in a blog post as clear as could be that the launcher is an AI-enabled, vibe-coded project: Programming is hard. So, instead of doing that, we vibe coded a new Epic Games Launcher that’s way faster and more responsive than the current one, and has a new look. Programming is hard? That was unexpected phrasing from a company founded by a legendarily great programmer. Back in 2011, Sweeney told me that he’d picked up programming quickly as a kid and rejoiced at the power it gave him. “I could look at any program that anybody else had written and, with enough effort, build something cooler.” Item 3: The Xbox Labs experiment (and one of the people behind it) Microsoft’s Xbox division, which is flooding the zone with announcements lately, yesterday revealed a new internal tech-tinkering team called Xbox Labs. In the words of Xbox boss Asha Sharma Labs is “a small group of game makers, engineers and scientists whose job is to turn emerging ideas into things our players and developers can experience.” Conventional wisdom coming out of the announcement is that Labs is a team that’ll focus on ideas driven by generative AI. In her announcement, Sharma cited some of the dizzying achievements in tech and gaming over the past month as AI agents and other AI tools have been deployed to swiftly figure out how popular games work, then rebuild them and mix them up. She mentioned seeing ”games rapidly decompiled and rebuilt to run on hardware they were never originally designed to support” and said “[p]erhaps more surprisingly, we’ve seen many of the biggest games in the world have been remixed into the source code of another.” (Minecraft plus Elden Ring, for example, or Fortnite + Super Monkey Ball + Overwatch + Diablo + others.) Sharma also cited the work of Windows PC games being ported to run in browsers, a seeming reference to a recent AI-assisted fan port of Halo. Or perhaps Call of Duty or GTA. Sharma didn’t use the specific term “AI” in her memo, but she came close, citing AI “agents” and their potential for game-making tools that Labs could help craft: I think XBOX has an important role to play here. Coding became the first major workload for agents because they can write, run, and test software. Games share many of those same properties, and people spend more than 72 billion hours a year playing XBOX games, roughly five times the estimated time spent writing code worldwide. We’ve spent 25 years learning how to make great games, and I want our game makers to help shape what these new technologies make possible. As we learn, we’ll share the tools we build with developers across the industry, just as we always have. When I asked an Xbox rep if Labs was an AI-centric team, they said genAI was not the focus, describing it as having a broader mandate for using new tech in new ways in gaming. As an example, they pointed to Xbox’s recently launched disc-to-digital gaming usage rights program. Microsoft didn’t specifically name anyone involved full-time in Xbox Labs yesterday, but on social media and LinkedIn, I spotted Adrian Mato IDing himself as leading the creatio of tools at Labs and talking up the launch. Mato first caught my attention in late September, when he said on X that he was “starting to build a new team at Xbox focused on products and tools for how games get built and distributed as agentic tools become more capable.” At the time, he framed AI-based tools as a supplement to traditional game dev tools. “I don’t think we need to replace them,” he said. Since then, he’s publicly shown interest in AI and in games. He’s recently spent some of his X feed marveling at the power of AI agents and praising the lighting in the latest Gears of War. Following the Labs announcement yesterday, he enthused about the Xbox Labs’ stylish landing page. He wrote: “We built some fun tools to art-direct shaders in real time, experimented with interactive ASCII art, and sprinkled in lots of tiny details. “Move your mouse to leave a colorful trail that reveals the original footage, or interact with the video to trigger bursts of particles. “A lot of love went into making it all feel just right. “More to come”
Week 8 Student Athlete Spotlight: James Stough, West Hills
West Hills High School senior James Stough was recognized in the Hollandia Dairy Student Athlete Spotlight for his dedication to football, academics, and community service.
Juventus Mental Health Week: Dedicated Landing Page Now Live
The dedicated Juventus Mental Health Week landing page is now live, marking another step in the Club's commitment to promoting mental well-being through content, personal stories and support resources...
49ers Get Blunt Take Amid Speculation on Vikings’ Jauan Jennings
Former San Francisco 49ers wideout Jauan Jennings doesn’t appear to be having an ideal time with the Minnesota Vikings. The veteran wideout has two catches for nine yards in four games. As a result, with the trade deadline nearing, there’s speculation about whether Jennings could be on the move.Moreover, one potential landing spot is reuniting […] The post 49ers Get Blunt Take Amid Speculation on Vikings’ Jauan Jennings appeared first on HEAVY.
Cincinnati Reds Named Potential Landing Spot for Top Free Agent
The Cincinnati Reds could make a splash on the free agent market.
Twins Earn National Spotlight For Work Away From The Diamond
A losing season did not stop Minnesota from landing a shot at one of baseball's top team honors, and fans can help decide it this week.
Astros named top landing spot for 34-HR Yankees outfielder
This Yankees outfielder could help finalize the Astros' outfield situation.
Life Science Tools Market Forecast to 2035: Growth Accelerates on Genomics and Biomanufacturing Demand
The global life science tools market is forecast to expand through 2035, supported by rising genomics research, biomanufacturing scale-up, and lab automation adoption.
Islandia condo project advances with zoning change
Kelly Real Estate received a zoning change to build a $10 million condominium development for buyers 55 and over in Islandia.
Wellcome Global Monitor 2026: Trust in science under pressure
The Wellcome Global Monitor is the world's largest study of how people think and feel about science and health. The 2026 edition draws on surveys of more than 140,000 people in 140 countries, making it a uniquely rich and globally comparable data set on public trust in science.
Inside Silicon Valley's bet on a new path to landing a job in the AI era
Andreessen Horowitz-backed Horowitz Andreessen Academy is betting that "proof of work" and AI skills can offer some students an alternative to the traditional college path.
Panthers Named Landing Spot For Intriguing Eagles CB
The Carolina Panthers need to address some issues on defense this season.
ESA astronaut Sophie Adenot returns from her first mission to the International Space Station
ESA astronaut Sophie Adenot has arrived back in Europe, landing in Cologne, Germany, following her return to Earth with Crew-12 after 237 days, nearly eight months, aboard the International Space Station for her εpsilon mission.
Bears can solidify contender status by landing 17.0 sack veteran
Chicago could use one last piece.
Lions Predicted to Land ‘Physical’ Eagles CB Before Trade Deadline
The Detroit Lions are named as a top landing spot for Philadelphia Eagles cornerback Kelee Ringo on the trade market. The post Lions Predicted to Land ‘Physical’ Eagles CB Before Trade Deadline appeared first on HEAVY.
Detroit Tigers Named Top Landing Spot for Yankees Polarizing Star
The Detroit Tigers will be a fascinating team to keep an eye on during this offseason.After struggling immensely this season and missing the playoffs, the Tigers should be on the hunt for new talent. They have multiple needs to address on their roster, so it will be intriguing to see what moves they make.Now, with […] The post Detroit Tigers Named Top Landing Spot for Yankees Polarizing Star appeared first on HEAVY.
Steelers Land Big-Bodied Wide Receiver in 2027 Mock Draft
Rob Rang of Fox Sports has the Pittsburgh Steelers landing Texas wide receiver Cam Coleman at 13th overall in his […]
Margaret Hamilton, trailblazer whose software powered Apollo 11 moon landing, dies at 90
MIT computer scientist led development of software for moon mission and earned Presidential Medal of Freedom
Margaret Hamilton, trailblazer whose software powered Apollo 11 moon landing, dies at 90
MIT computer scientist led development of software for moon mission and earned Presidential Medal of Freedom
Panthers Named Landing Spot For Former First-Round Defender
The Carolina Panthers could be a strong candidate to land a former first-round defender.
Islandia approves zoning revision for mixed-use project
The Village of Islandia approved revised zoning for a 12.6-acre mixed-use project by Motor Parkway Associates, including 366 apartments and a hotel.
Cedar Point's HalloWeekends gains national recognition
It's spooky atmosphere has gained national recognition, landing on USA Today's 10Best for theme park Halloween events.
Singapore Pledges Ocean Science Cooperation at OceanX Summit 2026
At the OceanX Summit 2026 aboard the OceanXplorer, Singapore's DPM Gan Kim Yong pledged knowledge, capabilities and connections to global ocean protection, highlighting marine climate science, coastal protection standards, the Into the Deep expedition and the BBNJ Agreement.
Druski Shares Clip of Ye's HBO Pilot After Congrats Over 'TIME' Cover
"Thank you Kanye," Druski also said after Ye congratulated him for landing the 'TIME' cover.
The Googlebook era is here: some first impressions of the hardware and a whole new OS
Today is the day. After months of tracking code commits, dissecting leaks, and getting that unforgettable first taste at Google’s media showcase in New York City, Googlebooks are officially landing...
McAllen’s Soft-Landing Program Generates Business Interest in Tampico, Mexico
The City of McAllen is expanding its economic diplomacy efforts following a successful business engagement in Tampico, Tamaulipas, Mexico, where approximately 25 prospective business owners expressed interest in expanding into the United States through McAllen’s Soft-Landing Program.
Where’s Blade? Fans wonder why Marvel Studios cutbacks seem to be landing on Black heroes
Mahershala Ali has said he’s moved on from the “Blade” reboot, making it another MCU project that’s fallen by the wayside. Black fans are asking whether Black characters are being purposely neglected and sidelined.
Hawks Avoid Costly Jalen Duren Gamble After Pistons Extension
Jalen Duren signed a five-year, $200 million deal with Detroit, ending Atlanta's chances of landing him and potentially saving the Hawks from a costly mistake.
Kings’ Sabonis Sent to Raptors in 4-Team Trade Idea
A blockbuster proposal ships the three-time All-Star north to anchor Toronto’s frontcourt, landing Sacramento a massive haul of veteran defensive depth and promising future draft capital.
Could the International Space Station win a Nobel Peace Prize? Here's what to know
Not-so-outlandish, prognosticators say: The Nobel Peace Prize this year could go galactic, with an award to the International Space Station.
B/R Names Tigers Top Landing Spot for Kevin Gausman
A national outlet just put Detroit first in line for a veteran starter Scott Harris may not want. #Tigers
Flydubai flight FZ1073 passenger recounts incident, emergency landing
A passenger recounts the incident aboard Flydubai flight FZ1073 where a pilot was attacked, explaining how he kept his family calm mid-crisis.
Siesta Entertainment picks up sales rights to Puerto Rican preschool show
Barcelona-based animation distribution and brand development company Siesta Entertainment has acquired the worldwide sales rights to Puerto Rican musical preschool series Rockolandia Las Cabritas.
Mideast Emergency Landing
A plane takes off as a flydubai aircraft sits on the tarmac at Dubai International Airport in Dubai, United Arab Emirates, Wednesday, Sept. 30, 2026. (AP Photo)
Tiffani Thiessen said she was ‘questioning my career’ after not landing role in James Bond film
‘Saved by the Bell’ alum Tiffani Thiessen said she was one of the final three candidates in an audition process for a James Bond film and the rejection was ‘one of the hardest’ she endured.
Lesbian Bar Project Co-Founder: Purity Politics Could Destroy Our Remaining Spaces
Subscribe As a professional lesbian and Massachusetts native, I’ve recently been asked by a lot of folks what I think about the saga unfolding at Last Ditch. The now-viral story, first reported by The Boston Globe, centers on a Western Massachusetts lesbian bar that lifted its mask requirement for one night a week to help drum up business. The decision ignited an intra-queer controversy that has been feasted on by media outlets across the political spectrum—from the New York Post to LGBTQ Nation—and is even reportedly being eyed for a Hollywood adaptation. Apparently nothing is more entertaining than a bunch of lesbians and queers fighting with each other over KN-95s. What has been lost in all of the chatter and media coverage is the very real possibility that Last Ditch, which just opened in April 2025, will have to close its doors. The venue’s one remaining founder, Jackie Matellian, revealed in a community Zoom meeting that she’s working four jobs, is now solely responsible for the bar’s $50,000 business loan and is struggling to keep up with the bills. So as we laugh about the controversy’s similarity to a “Portlandia” skit and how one of the bar’s founders left to enroll in clown school, we forget that yet another lesbian bar is facing an existential crisis—and this time the call is coming from inside the house. In 2020, my friend Elina Street and I created The Lesbian Bar Project, an Emmy-, Webby- and GLAAD Media Award-winning docuseries and initiative that tells the stories of lesbian queer bars around the world. We were moved to act because at the time there were only an estimated 16 lesbian bars in the United States, and the pandemic threatened to bring that number down even further. There are now more sapphic bars than there were just before the pandemic—about 36 of them in total—but this is down from approximately 200 in 1980. Maybe that doesn’t mean much to you, but for the millions of sapphics living in the U.S., this number is calamitous. As the world laughs at lesbians and sapphics, I want to take a second and tell you what I feel when I walk into one of these bars, which are all unique and irreplaceable in their own way: I feel seen. Sometimes I think Cubbyhole in New York City’s West Village neighborhood knew I was gay before I did. When I walked in there for the first time, before I was even out, I was transfixed by the colorful array of tchotchkes hanging from the ceiling and how the women standing next to me were completely unafraid to express their desire for one another. I knew the minute I was ready to come out, I had a home. I also felt the joy of a new couple falling in love at Seattle’s Wildrose, the quiet confidence of a short king lining up her shot at the pool table at Ginger’s in Brooklyn and the kick of cayenne pepper in Julie Mabry’s crawfish at Houston’s Pearl Bar. Subscribe Lesbian bars don’t just serve lesbians; they serve queer folks across the spectrum, including bisexual, pansexual and trans people. As Elina and I traveled across the U.S. and Europe and to parts of Latin America to document the bar owners, staff and patrons that make up the ecosystems of these spaces, we also became uniquely acquainted with the factors that threaten their existence: gentrification, wage gaps, sexism, environmental disasters, gun violence, rising insurance premiums and political administrations working to annihilate queer people and their families. Lesbian bar owners, like all leaders and entrepreneurs, are imperfect. There have been significant issues over the years at lesbian bars: employee harassment, racism, lack of accessibility, sexual assault and transphobia. All bar owners should be held accountable and should listen to their communities to evolve into safer and more equitable spaces. I also acknowledge my privilege: I am able-bodied, white, cis and from a family system that loves me for who I am. Not everyone has that. Queer people, especially trans and bisexual people, are suffering from disproportionately high levels of depression, and our mental health system isn’t equipped to support them. Immunocompromised people and long COVID are real, and many of my friends are suffering to this day. The people with the least safety net are often the ones for whom a bar closing costs the most. And yet, as we’re seeing with Last Ditch, the queer community often lashes out at each other. It’s also the mainstream media taking the internal conflict and making a mockery out of it, distracting from the real possibility that this bar could close due to financial pressures. A bar that many people loved and needed is facing extinction. Perhaps it’s safer to dissent with one another than with the larger forces trying to eradicate us, but in doing so, we risk destroying the few spaces we have left. Due to the constraints of purity politics—some in good faith, some not so much—lesbian bar owners, almost all of whom are queer women themselves, are forced to be everything for everyone, similarly to how women are forced to be everything for everyone. By asking these bars to uphold impossible standards—standards very few other third spaces are asked to consider—we all end up losing. I want to move as a community toward dialogue, compassionate dissent and collaboration to make our spaces better with the goal of keeping them OPEN and thriving, rather than destroying them from the inside with expectations that are arguably unattainable. Subscribe While I have your attention—for this fleeting second of the news cycle—may I urge us to spearhead a way to keep these small businesses afloat without attacking our own community along the way? Bar owners are left with an impasse: They want to be community-centered, but they also have to make money to keep their doors open. Sometimes they might make business decisions that don’t work for everyone—and that’s partly because different patrons have different priorities and want different things—but these owners deserve the opportunity for productive dialogue**.** We have to work with them and with each other to keep our spaces open, to keep them growing. Lesbian bars raised me into the queer woman I am today. One thing I think about as I reflect on the six years of work we’ve done to document these spaces is that shared, unspoken language I have with a stranger the moment we both walk into one of these bars: the nod, the ease, the not having to explain ourselves. I don’t want to lose that, and neither should you. If objective, nonpartisan, rigorous, LGBTQ-focused journalism is important to you, please consider making a tax-deductible donation through our 501(c)(3) fiscal sponsor, Resource Impact, by clicking this button: Donate
J.J. McCarthy trade grades as Giants, Vikings swing QB deal
The Giants took bold action after Jaxson Dart's season-ending injury, landing J.J. McCarthy from the Vikings. But who won the deal?
Sixth annual Oktoberfest! returns to Barefoot Landing on Oct. 3
On Saturday, Oct. 3 from noon to 6:00 PM, the sixth annual Oktoberfest! returns to Barefoot Landing, promising family-friendly fun with German and fall-inspired food and drink specials on offer from participating restaurants.
5 Things to watch for Cowboys-Ravens in Brazil. Cowboys on business trip, came to win
The Dallas Cowboys have been largely sequestered in their hotel at the Grand Hyatt since landing in Rio de Janeiro, Brazil on Friday ahead of Sunday’s game against the Baltimore...
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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gamescom 2026’s Steam wishlist winners
gamescom wrapped up last weekend, and it was bloody fantastic. It really felt like the industry had a spring in its step again. The show itself was BUZZING, with 368K attendees (+3% over last year), maxed-out exhibit space, and Opening Night Live pulling over 78M online views (+7.5%). Let’s have a look at the games at the event that brought in the most new Steam wishlists between August 23 and 30. One quick thing before we start, and stop me if you’ve heard this one before, but wishlists are NOT a barometer for launch sales (they’re bookmarks, not baskets is what we always say over here at Alinea). With that aside, wishlists are a nice gauge of hype, so let’s dive in. Witche(r)s and Warlocks take the top two spots The biggest game of the event (by new wishlists, anyways) wasn’t a game at all. It was an expansion. The Witcher 3: Wild Hunt’s upcoming expansion, Songs of the Past, nabbed 451K Steam wishlists by the end of the weekend. It’s a big example of something we bang on about constantly: proven IP with built-in fandom is the most powerful force in this market. But said IP can also ripple into other external success stories (more on that later!). Anyway, Songs of the Past debuted at Opening Night Live, and it’s the first Witcher 3 expansion in over a decade, landing next year after a full Witcher 3 remaster (free for existing owners!) arrives next month. The Witcher 3 has sold around 66M copies, and I’ll be one of those owners jumping back in to refresh myself on the core game (like there isn’t enough to play!), then play the expansion next year. This is all part of CDPR’s plan. The studio is clearly whetting everyone’s appetite for The Witcher 4 in 2028 via a classic bridge strategy. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Releasing a free 4K remaster next month – followed by a proper expansion in 2027 – keeps IP top-of-mind across a huge gap between content (games-wise, anyway). It kind of echoes Capcom’s evergreen catalogue strategy. And outsourcing co-development to Fool’s Theory (a studio led by trusted Witcher 3 veterans) keeps CDPR’s internal headcount focused on The Witcher 4. #2 by wishlists between Aug 23 and 30 went to another giant IP: Warlock: Dungeons & Dragons, published by Wizards of the Coast and developed by Invoke Studios (a team of ex-Far Cry, Watch Dogs, and Splinter Cell devs). It’s due to launch in 2027, and it looks brilliant so far. It’s a dark-fantasy open world with third-person spell-slinging. It’s a very Witcher-ish aesthetic. As you might expect, 48% of Warlock’s Steam wishlisters have played Baldur’s Gate 3, and 46% have played The Witcher 3. One to watch. For sure! Mash-ups: Anime GTA (!?) and a city-builder for kids (and adults) Ananta took #3 with 302K new wishlists. It’s an open-world game that looks like GTA and Persona had a baby. It was published by NetEase, developed by Naked Rain, and got a trailer at Opening Night Live. I got hands-on at the show, and it wears its influences openly; there’s literal web-slinging (very Spider-Man) and a LOAD of mini-games (Like a Dragon). It’s free-to-play and out in January. For Ananta, Naked Rain is taking the free-to-play, cosmetics-only route. That’s certainly a choice for a single-player open-world game. Without gacha mechanics driving high ARPU, Ananta is betting purely on top-of-funnel reach and long-term retention. This puts pressure on skin appeal when there’s no multiplayer lobby to flex in (although, co-op is reportedly coming later). Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Then there’s Lego Skylines (273K wishlists between Aug 23 and 30), which does exactly what it says on the tin. It’s a cosy Lego twist on the city-builder genre, as shallow or as deep as you fancy (five min quick sesh or ten-hour no-lifer session; latter for me). There’s some family-friendly stuff in there like couch co-op, which is only really viable on console. Iceflake Studios, which Paradox acquired back in 2020 is developing this one. So Paradox is probably looking for a family-friendly onramp to its rad Cities: Skylines games. The overlap there is plain, with 33% of Lego Skylines wishlisters having played Cities: Skylines and 16% Skylines II. There’s no doubt plenty of parents here (and uncles, ahem) planning to indoctrinate the next gen of city-builders. I’ll definitely be playing with my youngest nephew. This one could be big and educational. I’m very curious to see more. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Mature IP, new and old, rounds out the list As for the rest of the list of gamescom games by new wishlists between Aug 23 and 30: Heroes of Might & Magic III Remake got 189K new wishlists. It remakes the iconic 1999 turn-based-strategy classic in full 3D and 4K. It follows this year’s Heroes of Might & Magic: Olden Era (~1.8M copies sold, as per our estimates), and around a quarter of the III Remake wishlisters have played Olden Era, including 7% of them this month. Wardogs – a $40 PvP shooter – added another 146K to an already massive pile (nearly 1.6M total). It’s published by Team17 and made by Bulkhead. It plays somewhere between the tactical squad stuff of … Squad and the all-out-chaos battlefield of … Battlefield. It’s up to 100 players, and it’s out in about 10 days. It’s already pre-sold over 500K copies on Steam ($16.6M), boosted by a pre-order-only beta. It sold another 70K copies during gamescom, too. Afterworld managed 121K new wishlists. It’s a Paradox-made post-apocalyptic grand-strategy game, and it was announced at the show. It’s a departure from Paradox’s usual historical stuff, and the studio’s first new setting in over a decade. The Paradox purists are into it, with over half its wishlisters having played Hearts of Iron IV (19% this month) and 41% Crusader Kings III (17% this month). Metro 2039 got 110K during the show, tunnelling its total past 1.3M. Nearly 40% of wishlisters have played 2020’s Metro Exodus, the previous mainline title in the series. The Metro novels are Russian, dev 4A Games is Ukrainian, and it’s set in Moscow, so it’s unsurprising that – after the US (17.3% of wishlisters) – the next two countries are Russia (12.7%) and Ukraine (10.0%). The Blood of the Dawnwalker drew in (the blood of) 108K new wishlisters, now totalling an impressive 1.7M (at a $70 price point, though). It’s an open-world dark-fantasy action-RPG set in 14th-century Europe (with vampires!), made by some former Witcher devs at Rebel Wolves. Again, it shows. Over half of Blood of the Dawnwalker’s wishlisters have played The Witcher 3, and its #2 market is Poland, home of Rebel Wolves. That’s that hometown-hero effect we keep banging on about again! And Blood of the Dawnwalker plays very well, by the way. While it looks like a Witcher clone on the surface, it actually brings a lot to the table mechanics-wise. I love the whole time-as-a-currency spin on RPG gameplay. It gives the game a different, refreshing pace. Essentially, you start Blood of the Dawnwalker with a pool of 480 action points spread across 30 days and 30 nights. As for how the game performs, we’ll be posting some numbers next week, so hit subscribe below to get that in your inbox when it’s ready. Subscribe The Witcher’s legacy ripples Make no mistake: on a high level, this was The Witcher‘s gamescom. The #1 game by wishlisters was a Witcher 3 DLC. Warlock is clearly Witcher-inspired – as is Blood of the Dawnwalker, which was made by ex-Witcher devs. There was a lot of other cool stuff on the floor that we’ll no doubt be covering in subsequent newsletters, though! As always, wishlists went through the roof for sequels, remakes, DLC, and licensed IP. As always, though, these wishlists will likely convert to about 5% to 10% of launch-day buyers, with the probable exception of The Witcher DLC – the exception that proves the rule. Either way, we’ve got a nice, diverse list here – one that is very Witcher-y, Paradox-y, and – if you’re a fan of great games on Steam – a bloody good list. We even got a bunch of new IP to get excited for. Great gamescom! Even if we are still processing that unfathomable number of mini Kölsch beers! One more thing: GTA 6 broke the internet (again) Move aside, Spider-Man and The Odyssey (I love you both, really). But the decade’s defining entertainment zeitgeist is round the corner. Unless you’ve been living under a rock, you’ll know that Rockstar dropped an extended look at GTA 6 last week. It was INSANE, the most impressed I’ve ever been by a showcase like this. You can see the budget seeping through every second of the extended look, and this level of game is unobtainable for any other publisher. Everyone’s going nuts, and rightly so. GTA 6 is out in holiday 2026, and it’ll be the biggest entertainment release ever, full stop. For those without a PS5 or Xbox Series console, a $500-$900 console is a big ask in this economy, but GTA will pull a lot of last-generation-console fence sitters over the current-gen fence either way: The autumn timing puts GTA 6 on (digital) shelves for the holidays, meaning a PS5 or Xbox (let’s be honest, mostly the former) will be on many a Christmas and Hanukkah list. Demand will outweigh the struggling supply, though, and PS5 Pros are already sold out and being sold at a markup via scalpers. Every console that isn’t on a shelf is a sale deferred or lost, and worse, it hands scalpers the margin. GTA has cultural clout that reaches everyone. It’s been a mainstream fixture since 2001’s GTA III and its clout has only grown exponentially since then. There’s a touchpoint for every generation alive. The FOMO-word-of-mouth double punch does the rest. Loading... It’ll reactivate the lockdown cohort, the millions who picked up gaming in 2020-21 and churned. GTA 6 will bring them back. Remember when College Football 25 brought a bunch of US gamers to current-gen consoles? GTA will do that globally. Once they’re back (or upgraded), and all GTA’d out, the fresh current-gen-console folks will check out the rest of the current-gen catalogue they missed. GTA Online, if not free to play, will also lead to a boost for PS+ and Xbox Game Pass, another boost for the ecosystem players. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Even some of the smug PCMR 60FPS crew won’t be able to resist their FOMO and will bite the bullet on a console to play this one early (then double dip). The consoles cost the same as a decent stick of RAM these days anyway lmao… Don’t get me wrong, though. GTA 6 is no silver bullet for the mature console market, but it does prime the current gen for a couple of strong swan-song years. And it’ll also give the consoles more users from which to maximise ARPU. ‘’We are in the latter half of the lifetime cycle of [the PS5],’’ said Sony President and CEO Hiroki Totoki in a Wall Street Journal interview. ‘’That means we do not need to aggressively sell the console today; rather than that, we are focusing on the current revenue from the current user base.’’ The biggest, best premium games always arrive late in a console cycle, so getting more players aboard now, ahead of that content storm (the new current-gen-only Call of Duty included), is a clear win for the platforms. On the Netflix thing, though: let’s all chill out a bit, like. Half my LinkedIn feed was going bonkers treating the reveal debuting on Netflix like it’s the future of entertainment. It wasn’t. It was a six-hour head start, and Netflix left that detail out of the “first-of-its-kind partnership” press release. The extended look hit Netflix at 3pm ET on 27 August, then went up on YouTube and Rockstar’s site for everyone six hours later. And it was all over social immediately, anyways. This reveal was going to reach an untold number of people whether it debuted on Netflix, YouTube, a Times Square screen, or a group chat. The last trailer did nearly half a billion views in a day with no gatekeeper at all. Netflix just stood next to that audience for six hours, borrowing it. It’s was a tidy deal for Netflix, sure. But every outlet on earth was breaking the thing down frame by frame by the evening anyway. Anyway. I’m hype. And we’ll be covering some GTA numbers on the newsletter soon. So hit subscribe below to get that in your inbox when it’s ready! Subscribe The last word Reply to this email – or reach out here – if you have any feedback for the newsletter – or want to request a game for us to cover. [Alinea Analytics boasts the most accurate PC and console estimates in the business. Game makers use our platform to understand their audience, keep an eye on the competition, monitor sales trends, and spot new opportunities. We equip game studios and financial institutions with accurate data and the confidence to make smarter, data-driven decisions. Want to talk about all things games market data? We’d love to chat!]
Packers Pegged as Strong Landing Spot for Former Lions QB
The Green Bay Packers are a strong potential destination for either Will Levis or a former Detroit Lions quarterback. The post Packers Pegged as Strong Landing Spot for Former Lions QB appeared first on HEAVY.