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'All INdiana Politics': Cost of living and AI regulation dominate Indiana’s most competitive House race

INDIANAPOLIS — The race for Indiana’s 5th Congressional District has emerged as the state’s most competitive contest as Democratic State Sen. JD Ford challenges Republican incumbent Rep. Victoria Spartz. The district, which includes Hamilton, Tipton, Howard, Grant, Madison, and Delaware counties, has historically served as a Republican stronghold. However, shifting trends in the northern Indianapolis […]

Oct 10 • 12:59 PM EDT • Politics • wishtv.com

Mayor Johnson’s campaign cash dips below $380,000, while frontrunner Giannoulias has $19 million on hand

The freshman incumbent has just $379,471 in the bank — yet another indication of his struggle to raise money for the uphill reelection bid he announced last month.

Oct 16 • 1:57 PM EDT • Politics • wbez.org

Political insiders break down N.Y. gubernatorial debate

Republican Bruce Blakeman and incumbent Democrat Kathy Hochul faced off in their only debate of the election cycle right here on Spectrum News 1.

Oct 16 • 6:00 PM EDT • Politics • spectrumlocalnews.com

The Political Beat Candidate Guide: Mecklenburg Soil and Water Conservation Board

Incumbent Barbara Bleiweis is running for reelection. She faces Michael Betterly, Makenzie Pearce and Long Tran. Jillian King will also appear on the ballot, but her campaign has been suspended.

Oct 14 • 2:23 PM EDT • Politics • yahoo.com

In tight R.I. lieutenant governor’s race, Matos, Loughlin to face off in first debate

Republican John Loughlin is seen as having the best chance to win a statewide election for his party since 2006. But incumbent Lieutenant Governor Sabina Matos has an advantage, she doesn’t approach politics as a my-way-or-the-highway proposition.

Sep 25 • 10:37 AM EDT • Politics • bostonglobe.com

Oregon's governor struggles for reelection despite blue tide

In Oregon, a progressive bastion, voter discontent has incumbent Tina Kotek on the defensive. Her struggle shows the perils of incumbency this angry election season.

Oct 18 • 6:00 AM EDT • Politics • latimes.com

Strategic sovereignty, social movements, and political agency: Evidence from the US-Israeli military campaign in Iran

Military intervention may be undertaken to weaken a hostile regime and strengthen the position of its opponents. This column argues that evidence from the 2026 US-Israeli strikes on Iran points to a different outcome: the strikes left total protest levels broadly unchanged but sharply reoriented mobilisation away from anti-government protest and toward pro-government activity. The findings suggest that overt foreign intervention can make sovereignty politically valuable to incumbent governments by making domestic opposition easier to portray as aligned with an external adversary.

Oct 2 • 8:00 PM EDT • Politics • cepr.org

Housing, Iran, and public lands divide 4th Congressional District candidates

Republican Incumbent Mike Kennedy and Democratic challenger Jonny Larsen consistently offered competing stances on the role of the federal government in Utah's future.

Oct 12 • 12:47 PM EDT • Politics • upr.org

Trump to head to Kansas to show support for embattled Marshall

Incumbent Republican senator is facing strong challenge from Democrat Adam Hamilton in state that has been red for almost a century

Oct 19 • 5:39 AM EDT • Politics • theguardian.com

Bolsonaro and Lula head to a runoff in Brazil's presidential election

Sen. Flávio Bolsonaro, an ally of President Donald Trump, and Brazil’s incumbent President Luiz Inácio Lula da Silva will face off in a runoff Oct. 25 for the top job of Latin America’s powerhouse economy after neither won a majority in Sunday's vote.

Oct 5 • 8:51 AM EDT • Politics • pbs.org

Kansas’ 94-year streak is unlike anything else in American politics

Democrats are dreaming of a revolution in Kansas in November, trying to believe in polling that shows a tight race in the Senate contest there between the Democrat, Rev. Adam Hamilton, and the Republican incumbent, Sen. Roger Marshall.

Oct 7 • 5:00 AM EDT • Politics • cnn.com

Farmers, Health Care and Highways: 5 Takeaways from the Kansas Senate Debate

The Republican incumbent, Roger Marshall, is facing a surprisingly tough challenge from the Democratic nominee, Adam Hamilton.

Oct 21 • 10:54 PM EDT • Health • nytimes.com

Trump campaigns for ‘the real’ Dan Sullivan in Alaska

President Donald Trump traveled to Alaska to campaign for incumbent Republican Senator Dan Sullivan, whose race for reelection pits him against another man named Dan Sullivan. CNN’s Kristen Holmes reports.

Oct 13 • 8:00 PM EDT • Politics • cnn.com

Wyman Duggan launches campaign for Jacksonville Mayor

The Republican argues incumbent Donna Deegan isn't functioning like a 'strong Mayor' should.

Oct 2 • 12:48 PM EDT • Politics • floridapolitics.com

Why the lieutenant governor race is this year's nail-biter

If John Loughlin beats Lt. Gov. Sabina Matos, it would be the first time a Republican toppled an incumbent Democrat for lieutenant governor since 1966

Oct 19 • 6:02 AM EDT • Politics • providencejournal.com

Adam Greenman on how he’s preparing to be the next mayor of Pawtucket

The former nonprofit executive defeated a longtime incumbent in the Democratic primary

Sep 29 • 5:00 AM EDT • Politics • oceanstatemedia.org

Political analyst talks about upcoming 2nd Congressional District debate and race

NEW MEXICO (KRQE) – Friday night, KRQE News 13 will host candidates for the hotly contested 2nd Congressional District in New Mexico in a live debate at 5 p.m. Democratic Incumbent Gabe Vasque…

Oct 16 • 1:30 PM EDT • Politics • krqe.com

WATCH LIVE: U.S. House candidates set to debate in North Dakota, without incumbent Fedorchak

Oct 8 • 5:08 PM EDT • Politics • pbs.org

‘This is disgusting’: Nebraska’s independent Senate candidate rips dark money in politics

Democrats are hoping to whittle away at the Republican Senate majority in unexpectedly vulnerable red states like Nebraska. Incumbent Senator Pete Ricketts, a multimillionaire former governor, is defending his seat against independent challenger Dan Osborn, a Navy veteran and industrial mechanic. Osborn says he wants Congress to take back its power, end the war in Iran, lower fuel costs, so we “can worry about little league and bake sales.”

Oct 18 • 1:46 PM EDT • Politics • ms.now

Dems take the lead in fundraising this quarter in Oregon’s congressional swing districts

The Democratic incumbents representing Oregon in the U.S. House are far outraising their Republican challengers.

Oct 19 • 9:00 AM EDT • Politics • oregoncapitalchronicle.com

GOP governor candidate Stacy Garrity touts experience in business, military, state government

Editor’s note: This is the first of three profiles on this year’s candidates for Pennsylvania governor. A profile of Democratic incumbent Gov. Josh Shapiro is scheduled to be published on Tuesday, Sept. 29, and one on Libertarian Ken Krawchuk is scheduled for publication on Thursday, Oct. 1. HARRISBURG — It’s

Sep 26 • 4:00 AM EDT • Business • triblive.com

Poll: Cotton takes lead over Shoffner

A new Talk Business & Politics-Hendrix College Poll released Thursday (Oct. 15) shows incumbent Republican U.S. Sen. Tom Cotton with a nine-point lead over his Democratic challenger, Hallie Shoffner. The...

Oct 15 • 6:18 PM EDT • Politics • talkbusiness.net

Race for 17th Senate District could determine State Senate control

Republican incumbent Howard Marklein is being challenged by Democratic State Assembly Rep. Jenna Jacobson.

Oct 13 • 5:26 PM EDT • Politics • spectrumnews1.com

Rep. Moore says he puts policy over 'toxic' politics; Crosby calls himself a chance for change

In a debate for Utah’s newly-drawn 2nd Congressional District, Republican incumbent Rep. Blake Moore squared off with Democrat Peter Crosby.

Oct 14 • 7:02 AM EDT • Politics • utahnewsdispatch.com

Renewable Energy Super PAC Targets 7 Republicans With $15 Million War Chest

Most of the Republicans, such as Lauren Boebert of Colorado and Victoria Spartz of Indiana, are incumbents in districts that President Trump won comfortably in 2024.

Oct 1 • 9:36 AM EDT • Politics • nytimes.com

Campaign 2026: Chloe Pierce (D) vs Scott Bendett (R) in NYS 107th Assembly District

Democratic nominee Chloe Pierce is challenging Republican incumbent Scott Bendett.

Oct 19 • 5:00 AM EDT • Politics • cbs6albany.com

Democrat Troy Jackson apologizes for Holocaust reference

The Senate nominee’s bid to unseat incumbent Susan Collins (R) is critical to Democrats’ hopes for reclaiming control of the chamber.

Sep 30 • 11:35 AM EDT • Politics • washingtonpost.com

Incumbent, political newcomer to face off in race for Texas House District 91

Republican David Lowe and Democrat Yisak Worku are running to represent the northeast Tarrant district.

Sep 20 • 3:00 PM EDT • Politics • fortworthreport.org

Darren Soto laps Dan Green in CD 9, even with Republican's $700K in self-funding

But every election prognosticator till sees the incumbent at a disadvantage thanks to Florida's new congressional map.

Oct 17 • 8:11 AM EDT • Politics • floridapolitics.com

State House District 15 candidates answer questions for residents

SOUTHWEST HARBOR — At a time when Maine residents are facing inflation, high heating costs, and rising property taxes, incumbent Holly Eaton and challenger Clifford Noyes aim to help residents

Oct 8 • 4:30 PM EDT • Politics • mdislander.com

‘All INdiana Politics’: Cost of living and AI regulation dominate Indiana’s most competitive House race

INDIANAPOLIS — The race for Indiana’s 5th Congressional District has emerged as the state’s most competitive contest as Democratic State Sen. JD Ford challenges Republican incumbent Rep. Victoria Spartz. The district, which includes Hamilton, Tipton, Howard, Grant, Madison, and Delaware counties, has long been a Republican stronghold. However, shifting trends in the northern Indianapolis suburbs […]

Oct 12 • 12:15 AM EDT • Politics • wrtv.com

Newcomer faces incumbent Zimmerman in 99th House District

Republican Dave Zimmerman has represented the 99th District in the Pennsylvania House for 12 years. This year, 23-year-old Democrat Ethan Gabrick, a teacher’s aide, hopes to take over as an

Oct 14 • 5:00 AM EDT • Politics • lancasteronline.com

In Ohio, a Humbling Question For Senator Jon Husted: Are You the Incumbent?

Even some devoted conservatives know more about Sherrod Brown, the Democratic challenger, than the Republican incumbent, who needs the MAGA base to turn out.

Sep 28 • 12:31 PM EDT • Politics • nytimes.com

Collins, Jackson spar over energy costs, health care in third Maine Senate debate

Hosted by WABI and WAGM, the incumbent Republican and her Democratic challenger went head-to-head on affordability, energy, health care and tariffs.

Oct 13 • 10:07 PM EDT • Health • wabi.tv

José Javier Rodríguez launches multimillion-dollar ‘Give ’Em Hell’ statewide ad campaign

The 30-second spot follows poling showing him and the Republican incumbent statistically tied in the Attorney General’s race.

Sep 25 • 1:23 PM EDT • Politics • floridapolitics.com

Q&A with candidates for Leesburg Town Council and mayor

In Leesburg, the county’s largest town with a population of nearly 50,000, incumbent Mayor Kelly Burk, a resident of Crestwood Hamlet, is running unopposed for a sixth term.

Oct 16 • 6:00 AM EDT • Politics • loudountimes.com

Political Beat Preview: House District 98

Incumbent Democrat Beth Helfrich is seeking re-election and facing a challenge from former Republican representative John Rhodes in North Carolina’s 98th House district that covers the northern part of Mecklenburg County.

Sep 20 • 12:06 PM EDT • Politics • wsoctv.com

In one of the countrys most competitive districts, a Democrat tries to keep her seat

In a highly competitive Washington congressional race, the incumbent Democrat has angered part of her party base and the Trump-backed Republican challenger faces backlash against the party in power.

Oct 11 • 11:00 PM EDT • Politics • opb.org

CD1 debate turns feisty

A mild-mannered, televised debate in the U.S. First Congressional District race took a heated turn Wednesday (Oct. 14) when incumbent U.S. Rep. Rick Crawford, R-Jonesboro, and Steve Parsons, a Libertarian...

Oct 14 • 7:52 PM EDT • Politics • talkbusiness.net

Turner trying to stave off challenge from Lesko in senate campaign

Frank Lesko defeated a popular incumbent in 2024, but to do it again, he will have to navigate state political waters.

Oct 21 • 5:04 AM EDT • Politics • sj-r.com

Students weigh in on rhetoric in Maine political advertisements

It is no secret that the Senate race in Maine is hotly contested. Republican incumbent Susan Collins and former Maine Senate President Troy Jackson, a…

Sep 28 • 3:03 AM EDT • Politics • mainecampus.com

China has nominated health official Song Li as WHO head

China has nominated health ​official Song Li ‌as a candidate to lead the World ​Health Organization, China's ​Foreign Ministry said on ⁠Thursday, confirming ​a Reuters exclusive that said ​Song was put forward to succeed the incumbent ​director general, ​Tedros Adhanom Ghebreyesus.

Oct 8 • 3:29 AM EDT • Health • reuters.com

Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL

Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Sep 26 • 9:36 AM EDT • Technology • newsletter.semianalysis.com

Affordability is on voters’ minds in Pa. swing districts as the cost of gas and groceries skyrockets

The cost of living is the rise as the war in Iran continues. That could hurt Trump-aligned incumbents in key Pennsylvania swing districts.

Oct 2 • 5:01 AM EDT • Politics • inquirer.com

A 41st House District rematch: Brett Miller vs. Brad Chambers

Lancaster County’s 41st state House District race features a rematch between Republican incumbent Brett Miller and Democrat Brad Chambers.

Oct 14 • 5:00 AM EDT • Politics • lancasteronline.com

Will Republicans help this underdog liberal unseat a longtime Democratic congressman?

As young progressive Democrats across the country successfully unseat older incumbents, one California Democratic challenger is courting Republicans instead

Sep 29 • 8:15 AM EDT • Politics • calmatters.org

Cook Political Report Shifts 18 House Races Left, Including Four GOP-Held Seats from Toss Up to Lean D

The Cook Political Report shifted 18 House races to the left Friday — including four currently held by Republican incumbents.

Oct 9 • 6:10 PM EDT • Politics • yahoo.com

House District 13 candidates discuss heating costs and housing

Maine House District 13 candidates Republican incumbent Russell White and Democrat Michael Cunningham shared their input on hot topics such as heating costs and access to rural healthcare during a

Oct 19 • 5:15 PM EDT • Politics • ellsworthamerican.com

Stephens talks property tax relief, literacy, mental health ahead of election

Georgia House District 164 incumbent discusses priorities if re-elected

Oct 18 • 6:00 PM EDT • Health • wtoc.com

South Korean official says Trump announcement on Alaska LNG went ‘far beyond what was agreed’

The governor and Republican incumbents in competitive U.S. Senate and House races said they expect South Korea to ultimately invest $54 billion. Some industry observers cast doubt on that prospect.

Oct 2 • 11:04 PM EDT • Politics • adn.com

In one of the country's most competitive districts, a Democrat tries to keep her seat

In a highly competitive Washington congressional race, the incumbent Democrat has angered part of her party base and the Trump-backed Republican challenger faces backlash against the party in power.

Oct 11 • 5:00 AM EDT • Politics • kosu.org

Darren Soto showcases bipartisan support in 6-figure ad buy

A conservative supporter makes a case for the Democratic incumbent — and delivers barbs at Dan Green.

Sep 29 • 11:12 AM EDT • Politics • floridapolitics.com

Full Debate: Letitia James, Saritha Komatireddy go head-to-head in AG debate

Incumbent state Attorney General Letitia James and Republican challenger Saritha Komatireddy debated in the Spectrum News NY1 newsroom.

Oct 8 • 10:00 PM EDT • Politics • spectrumlocalnews.com

Voters in pre-election poll mixed on state of Massachusetts

Many respondents to a new poll believe Massachusetts has become a worse place to live over the past four years and they still favor keeping incumbent Gov. Maura Healey in

Oct 20 • 1:30 PM EDT • Politics • statehousenews.com

Democrats Show Strength in Michigan Senate Race but Trail in Maine, Polls Find

The party’s nominees lead in Michigan and New Hampshire but the Republican incumbent is ahead in Maine, according to New York Times/Siena polls of the three battlegrounds.

Sep 24 • 5:02 AM EDT • Politics • nytimes.com

How Mainers are weighing the pay-to-play allegation involving Susan Collins

Tom McShane of Windham will likely split his ticket in November. He likes a Republican candidate running for his legislative district but plans to vote for Democrat Troy Jackson for Senate, although reluctantly since his first choice dropped out. His choice in the Senate race is irrespective of the recent corruption allegations against incumbent Republican […]

Oct 1 • 2:28 PM EDT • Politics • mainemorningstar.com

Full Debate: DiNapoli, Hernandez face off in debate

Incumbent state Comptroller Tom DiNapoli and Republican challenger Joseph Hernandez are expected to participate in the debate.

Oct 1 • 8:00 PM EDT • Politics • ny1.com

The record and the alternative

Elections involving incumbents offer voters something elections between newcomers cannot: evidence. Tom Sullivan need not tell Senate District 27 voters what kind of legislator he might be. After four years in the Colorado House and nearly four in the Senate, he has accumulated something more revealing than campaign promises. A record. Danielle Lammon offers something […]

Oct 16 • 3:00 AM EDT • Politics • coloradopolitics.com

Can U.S. Rep. Don Davis beat a gerrymander?

A year ago, Republican state lawmakers redrew North Carolina’s 1st Congressional District to make it more conservative. But as Election Day draws near, incumbent Congressman Don Davis appears to have an increasingly strong shot at keeping his seat.

Oct 20 • 12:51 PM EDT • Politics • wunc.org

8th Congressional District race is essentially tied, poll shows, with warning signs for both Gabe Evans and Manny Rutinel

The poll was conducted by a Republican firm on behalf of a conservative political nonprofit that doesn’t reveal its donors and is backing Evans, the district’s Republican incumbent.

Sep 27 • 8:00 AM EDT • Politics • kunc.org

Battenfeld: Maura Healey’s Trump tactic is why Americans hate politics

The incumbent Massachusetts governor was allowed by a weak moderator to dodge every question. The late, legendary Tim Russert would never have tolerated that.

Oct 10 • 5:52 AM EDT • Politics • bostonherald.com

Five mayoral contenders file ballot signatures as incumbent Johnson waits

Mayor Brandon Johnson is struggling in fundraising, but plans to file "far above" the 12,500 signature threshold to make the ballot

Oct 19 • 3:35 PM EDT • Politics • chicagobusiness.com

5 Takeaways From the Senate Debate in Maine

The race’s fourth and final debate centered around whether Senator Susan Collins, the Republican incumbent, was as independent as she claimed to be from President Trump.

Oct 15 • 9:42 PM EDT • Politics • nytimes.com

Massachusetts labor union endorses nearly all incumbents as businesses, workers flee

The Massachusetts AFL-CIO is endorsing 14 of 15 incumbents in major state and federal races in the general election as a massive outmigration of businesses and working-aged residents continues.

Sep 19 • 5:18 PM EDT • Business • bostonherald.com

Candidates for Congressional District 2 talk political parties, affordability

Incumbent Maggie Goodlander and challenger Lily Tang Williams face off in NH's 2nd District race, focusing on affordability and energy.

Oct 16 • 7:12 AM EDT • Politics • concordmonitor.com

Meet the Candidate: Jerry Schillinger

There are two candidates for Montana House District 34 on the general election ballot: incumbent Jerry Schillinger, a Republican, and Jasmine Erickson, a Democrat.

Oct 8 • 7:00 AM EDT • Politics • terrytribune.com

Meta denies accusation of anti-Lula political bias in Brazil after electoral court ruling

SAO PAULO (AP) — Tech giant Meta denied accusations Friday that it acted with political bias during Brazil’s presidential campaign, less than a day after the country’s electoral court ruled the platform must give equal treatment to incumbent Luiz Inácio Lula da Silva and opposition candidate Fláv...

Oct 16 • 6:43 PM EDT • Politics • wral.com

Cook Political Report sees Anna Paulina Luna, María Elvira Salazar in risky territory, opens CD 22 as a jump ball

2 GOP incumbents now sit in 'Lean R' territory, while an open race Republicans wanted to flip is a 'Toss Up.'

Sep 25 • 4:15 PM EDT • Politics • floridapolitics.com

Political Pulse: Rep. Steve Duffy campaigns on Rapid City workforce development and retention in District 32

GOP incumbent Rep. Steve Duffy shares why workforce housing, keeping young families in Rapid City, and smart growth are central to his District 32 reelection bid.

Sep 26 • 11:00 AM EDT • Politics • kotatv.com

Pat Daley, a political freshman focused on affordability, Medicaid expansion and infrastructure

Pat Daley is running against longtime incumbent Jesse Petrea for a seat in the Georgia House of Representatives representing Chatham and Bryan counties.

Oct 19 • 6:39 PM EDT • Politics • wtoc.com

To fix California, make its politicians afraid to lose

The state has the nation’s largest homeless population and some of its most expensive housing — yet incumbents rarely pay a price. A slew of new parties is the answer.

Oct 18 • 9:00 AM EDT • Politics • sfstandard.com

Chris Murray challenges Palumbo with affordability, health care focus

Democrat Chris Murray has placed affordability, health care and environmental protection at the center of his campaign as he tries to unseat incumbent Republican state Sen. Anthony Palumbo. Mr. Murray — an attorney who was elected chairman of the Suffolk County Community College Board of Trustees in 2019 and has also chaired the Citizens Campaign...

Oct 16 • 11:00 AM EDT • Health • suffolktimes.timesreview.com

Three Bucksport residents vie for two town council seats

Bucksport voters will have a choice of three candidates for two open town council seats on Nov. 3: Incumbent Mark Eastman and newcomers Jon Goss and Ralph Chapman.

Oct 7 • 11:55 AM EDT • Politics • ellsworthamerican.com

Rift escalates as Trump targets Miami GOP Rep. María Elvira Salazar in Truth Social posts

The race for Florida's 27th Congressional District flared up over the weekend when President Donald Trump reposted on his Truth Social account more than a dozen posts excoriating incumbent Elvira Salazar.

Sep 28 • 7:01 AM EDT • Politics • wusf.org

Fish, Oil and Corruption: 6 Takeaways From Alaska’s Senate Debate

The Republican incumbent, Dan Sullivan, and his Democratic challenger, Mary Peltola, veered from serious discussion of high prices and economic challenges to blistering personal attacks.

Oct 16 • 3:28 AM EDT • Politics • nytimes.com

Registered nurse runs against incumbent Smucker in 11th Congressional District

Democrat Nancy Mannion is confident in her ability to oust longtime Lancaster County Congressman Lloyd Smucker and take the 11th District seat.

Oct 14 • 5:00 AM EDT • Politics • lancasteronline.com

Candidates for Attorney General share vision of leadership for DOJ

Democratic incumbent Josh Kaul is being challenged for the second consecutive election cycle by Republican Fond du Lac County District Attorney Eric Toney.

Oct 9 • 5:27 PM EDT • Politics • spectrumnews1.com

State comptroller candidates set to square off on NY1

Democratic incumbent Tom DiNapoli and Republican challenger Joseph Hernandez will meet in a televised debate Thursday at 7 p.m.

Sep 30 • 7:22 PM EDT • Politics • ny1.com

WATCH LIVE: Trump campaigns for Sen. Dan Sullivan in Alaska

President Donald Trump on Tuesday will devote a big chunk of his dwindling time ahead of crucial midterm elections to head all the way to Alaska — attempting to bolster a Republican incumbent senator in another sign of GOP fears about retaining control of Congress after Election Day on Nov. 3.

Oct 13 • 9:49 AM EDT • Politics • pbs.org

Comptoller DiNapoli fends off attacks from challenger Hernandez in NY1 debate

Republican challenger Joseph Hernandez assailed incumbent Tom DiNapoli's record and ethics.

Oct 1 • 9:04 PM EDT • Politics • ny1.com

U.S. Rep. Richard Hudson confident in his record

Washington correspondent Reuben Jones had the opportunity to speak with the incumbent Republican in that race, U.S. Rep. Richard Hudson.

Oct 15 • 5:39 PM EDT • Politics • spectrumlocalnews.com

Full Debate: Letitia James, Saritha Komatireddy go head-to-head in AG debate

Incumbent state Attorney General Letitia James and Republican challenger Saritha Komatireddy debated in the Spectrum News NY1 newsroom.

Oct 8 • 10:00 PM EDT • Politics • ny1.com

House District 15 candidates answer questions from residents

At a time when Maine residents are facing inflation, high heating costs and rising property taxes, incumbent state Rep. Holly Eaton and challenger Clifford Noyes aim to help residents in

Oct 14 • 9:22 AM EDT • Politics • ellsworthamerican.com

Tonko, Ambrosio make their cases in 20th Congressional District race

Voters in the 20th Congressional District will choose between a longtime Democratic incumbent and a Republican who has never held elected office.

Oct 20 • 2:00 PM EDT • Politics • spectrumlocalnews.com

Candidates with strong education credentials square off in 96th House District

Two Manheim Township educators from opposite sides of the political aisle are vying for control of the 96th District. Democratic incumbent Nikki Rivera will face Republican Babita Rusyn, a former

Oct 14 • 5:00 AM EDT • Politics • lancasteronline.com

Poll: Cotton takes lead over Shoffner

A new Talk Business & Politics-Hendrix College Poll released Thursday (Oct. 15) shows incumbent Republican U.S. Sen. Tom Cotton with a nine-point lead over his Democratic challenger, Hallie Shoffner. The...

Oct 15 • 6:18 PM EDT • Business • talkbusiness.net

GOP hopes fade in Georgia and North Carolina as party shifts focus in battle for Senate

The party is spending heavily to defend GOP-heavy Texas, and Trump plans to campaign for the Republican incumbent in Ohio. They're both places Trump won easily in 2024.

Sep 29 • 1:29 PM EDT • Politics • pbs.org

Full Debate: Letitia James, Saritha Komatireddy go head-to-head in AG debate

Incumbent state Attorney General Letitia James and Republican challenger Saritha Komatireddy debated in the Spectrum News NY1 newsroom.

Oct 8 • 10:00 PM EDT • Politics • spectrumlocalnews.com

Democrat José Javier Rodríguez launches 'Give 'Em Hell' statewide ad campaign in Florida AG race

The ad, released in both English and Spanish, centers on Rodríguez's background and career while sharply criticizing incumbent Republican Attorney General James Uthmeier.

Sep 27 • 7:53 AM EDT • Politics • wusf.org

Longtime Davie mayor gets challenge from political newcomer

The incumbent mayor of Davie has held the seat for more than 15 years but her opponent in November’s election is a newcomer who says she has fresh eyes.

Sep 22 • 6:35 PM EDT • Politics • local10.com

Tonko, Ambrosio make their cases in 20th Congressional District race

Voters in the 20th Congressional District will choose between a longtime Democratic incumbent and a Republican who has never held elected office.

Oct 20 • 2:00 PM EDT • Politics • spectrumlocalnews.com

Two candidates compete to succeed a New Orleans constable who served for over 20 years

The race pits the incumbent’s second-in-command, and his cousin, against a New Orleans East businessman.

Oct 20 • 5:00 AM EDT • Politics • nola.com

Utah Senate District 1: Claudia Bigler, Scott Sandall and Julie Quinlan face off

In the 2026 race for Utah Senate District 1, Claudia Bigler and Julie Quinlan are challenging incumbent Scott Sandall. Read The Salt Lake Tribune's voter guide here.

Oct 12 • 4:00 AM EDT • Politics • sltrib.com