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One of three Jensen Huang-signed RTX Spark laptops won at NVIDIA launch event is already listed for $17,150
An ASUS ProArt RTX Spark laptop bearing Jensen Huang's signature is reportedly being offered for $17,150. The asking price exceeds regular Turkish retail pricing by more than two times.
Nvidia CEO urges German manufacturers to adopt AI
FRANKFURT, Germany — Nvidia CEO Jensen Huang urged Germany’s makers of cars and industrial machines to quickly adopt artificial intelligence to “re-engineer” the country’s struggling business model by tapping its
Nvidia CEO among top business execs to attend German investment summit
Germany is set to host top business executives, including Nvidia boss Jensen Huang, on Monday for a summit that Chancellor Friedrich Merz hopes will help to attract private investment to boost the sluggish economy. Europe's largest economy has struggled to attract foreign investment amid years of weak growth, with high energy prices and labour costs continuing to deter businesses.
Nvidia is no longer a PC gaming company. Get used to it
The disappearance of the GeForce RTX 5090 graphics card shouldn't come as a surprise, because PC game fans are no longer Nvidia's audience—AI companies are.
Aspirus Health sees trend of younger women being diagnosed with breast cancer
“We’re seeing more breast cancer cases in younger women than we did in the past, and there isn’t one simple reason why,” Dr. Huang said.
Huang Qifan, China’s political tumbler, falls after a decade of close corruption calls
Until this week, Huang had appeared to weather scandals that had ripped through Chongqing over the years.
Trump’s ‘golden age’ push hands top science honours to big tech. Will it work?
Top medals for big tech chiefs like Musk and Huang signal shift to market-driven research but Chinese analysts doubt viability of model.
Trump Honors Musk, Huang, and Tech Leaders as US Unveils $2.4B Science Push
Trump honored Musk, Huang, and other tech leaders as the US outlined new science initiatives, highlighting AI research commitments and immigration questions.
NVIDIA CEO Jensen Huang receives National Medal of Science for turning gaming GPUs into AI powerhouses
NVIDIA CEO Jensen Huang received the National Medal of Science for advancing GPUs into general-purpose computing engines that power modern AI.
Trump awards science medal to Elon Musk, Jensen Huang
US President Donald Trump will award the National Medal of Science to Nvidia CEO Jensen Huang and several other tech leaders, with major figures from the industry set to gather again on October 8, local time. The honors highlight Trump's push to spotlight technology executives as his administration emphasizes US innovation leadership.
Trump presents National Medal of Science to billionaire Elon Musk and three other tech leaders
President Trump presented the National Medal of Science to Elon Musk, Sergey Brin, Jensen Huang and Lisa Su, and the technology medal to Michael Dell and Satya Nadella, at a White House science summit.
President Trump awards big tech donors with nation's highest science prizes
On Thursday, President Trump awarded Elon Musk, Jensen Huang, Sergey Brin, and AMD’s Lisa Su the National Medal of Science, the nation’s top science prize.
Trump awards Musk and other tech titans National Medals of Science
President Donald Trump joined Michael Kratsios to award the Medal of Science to Elon Musk, Jensen Huang, Lisa Su and Sergey Brin amid announcements on new science funding.
Trump awards science, technology medals
Speak at the New Golden Age Summit at the Institute of Peace in Washington D.C., President Trump awarded Elon Musk, NVIDIA president and CEO Jensen Huang, CEO of Dell Technologies Michael Dell and more with the National Medal of Science and the National Medal of Technology and Innovation.
Trump awards National Medals of Science, Technology to U.S. tech leaders
The awards went to SpaceX founder Elon Musk, Nvidia co-founder Jensen Huang and Google co-founder Sergey Brin, among others
Trump awards National Medals of Science, Technology to U.S. tech leaders
The awards went to SpaceX founder Elon Musk, Nvidia co-founder Jensen Huang and Google co-founder Sergey Brin, among others
Nvidia Commits $1B To US Science As CEO Jensen Huang Backs Trump’s Genesis Mission
Nvidia commitment will be dispersed over five years with the aim of advancing U.S. scientific research and computing capabilities.
Nvidia commits $1 billion to US science over five years
“Putting advanced Super Intelligence in the hands of America’s scientists,” says Jensen Huang as Nvidia commits $1 billion.
Watch live: Trump speaks at science and technology summit
Watch live coverage as President Trump participates in a summit on science initiatives, including artificial intelligence advancements. The president will be awarding medals of recognition to technology leaders including Elon Musk, Jensen Huang and Michael Dell.
Trump Will Award Musk National Medal Of Science At D.C. Tech Summit
Musk and Jensen Huang, who’s also being honored, were two of the six tech moguls who signed the voluntary "White House Accord on Super Intelligence" last month.
Trump to give Musk top US science medal
Tech bosses Sergei Brin, Jensen Huang and Lisa Su will also receive the National Medal of Science.
Trump's Science Medals Go to Musk and Huang: Where Are Altman and Amodei?
Trump will award Musk and 5 tech CEOs top US science medals. OpenAI's Altman and Anthropic's Amodei are missing.
Trump to Give Musk Top US Science Medal
President Donald Trump will present close ally Elon Musk and other tech bosses with the top US scientific award at a ceremony on Thursday, the White House said. Google co-founder Sergei Brin, Nvidia CEO Jensen Huang and AMD chief Lisa Su will also receive the National Medal of Science at the "Science: A New Golden Age" summit. Computer mogul Michael Dell and Microsoft CEO Satya Nadella will get the National Medal of Technology and Innovation, the top award in its field.
Trump to award National Medal of Science to Musk, Brin, Huang, and Su at White House
A high-profile group of tech leaders is expected to be honored at the White House on Thursday, with President Donald Trump planned to present.
Trump to award National Medal of Science to Musk, Brin, Huang, and Su at White House
A high-profile group of tech leaders is expected to be honored at the White House on Thursday, with President Donald Trump planned to present.
Trump to award National Medal of Science to Musk, Brin, Huang, and Su at White House
A high-profile group of tech leaders is expected to be honored at the White House on Thursday, with President Donald Trump planned to present.
Trump to award National Medal of Science to Musk, Brin, Huang, and Su at White House
A high-profile group of tech leaders is expected to be honored at the White House on Thursday, with President Donald Trump planned to present.
Trump to award National Medal of Science to Musk, Brin, Huang, and Su at White House
A high-profile group of tech leaders is expected to be honored at the White House on Thursday, with President Donald Trump planned to present.
Trump to award National Medal of Science to Musk, Brin, Huang, and Su at White House
A high-profile group of tech leaders is expected to be honored at the White House on Thursday, with President Donald Trump planned to present.
Trump to award National Medal of Science to Musk, Brin, Huang, and Su at White House
A high-profile group of tech leaders is expected to be honored at the White House on Thursday, with President Donald Trump planned to present.
FIRST ON FOX: Elon Musk heads back to White House as Trump marks prestigious first of presidency
Trump will award Elon Musk, Sergey Brin, Jensen Huang and Lisa Su the National Medal of Science at a White House summit on super intelligence.
Trump to award National Medal of Science to Musk, Brin, Huang, and Su at White House
A high-profile group of tech leaders is expected to be honored at the White House on Thursday, with President Donald Trump planned to present.
Nvidia Takes Aim at Intel’s $32 Billion PC Business With Microsoft’s Surface Laptop Ultra
Microsoft (MSFT:NASDAQ) and Nvidia (NVDA:NASDAQ) are set to unveil the Surface Laptop Ultra in San Francisco on Wednesday, October 7, with Satya Nadella and Jensen Huang taking the stage together. The laptop runs on Nvidia’s RTX Spark chips, announced in June, and it’s built to run AI agents on the PC itself instead of in the cloud.
Oct. 8 talk to discuss building a new era of materials characterization
Pinshane Y. Huang, Racheff Faculty Scholar in the Department of Materials Science and Engineering at the University of Illinois, Urbana-Champaign, will give the talk “Building a new era of atom-by-atom materials characterization with electron ptychography” at 3:05 p.m. on Thursday, Oct. 8, in 10 Sparks Building on the University Park campus.
Yale School of Medicine On the Science of Childhood Anxiety, Say, Anxiety Disorders Are the Most Common Mental Health Challenges In Youth
Credit: Matt Bradbury October 5, 2026 - By Isabella Backman - Anxiety disorders are the most common mental health challenges in youth. Left untreated, they can disrupt the lives of both children and their families. The good news is that with intervention, most children will overcome these conditions. Across Yale School of Medicine, scientists are working to understand anxiety at every level, from common anxious behaviors to molecular biomarkers in the brain. They are using their findings to develop and disseminate new evidence-based treatments for childhood anxiety. Today, the go-to treatment for childhood anxiety disorders is cognitive behavioral therapy (CBT). This is a form of psychotherapy that teaches children skills for confronting anxious thoughts and helps them practice managing situations that cause anxiety. While it is the gold-standard treatment backed by considerable scientific evidence, up to 50% of children will not see sufficient benefit from CBT alone. Wendy Silverman, PhD, Alfred A. Messer Professor in the Child Study Center, co-directs the Anxiety and Mood Disorders Program alongside Eli Lebowitz, PhD, associate professor in the Child Study Center. One of their main interests is learning how to improve outcomes beyond CBT. “We’re developing cutting-edge, research-based knowledge that can reduce the suffering that anxiety causes children and their families,” says Silverman. Changing parent behavior YSM experts are investigating how to improve CBT outcomes for children by involving the parents. Silverman’s research has uncovered two main components of parent intervention that improve childhood anxiety: not enabling children to completely avoid the things that make them anxious and taking steps to enhance their autonomy. Parents may unintentionally reinforce their child’s anxiety by allowing them to avoid what makes them anxious. They also may unintentionally limit the children’s sense of autonomy by being overly intrusive. “One of the things that we take pride in is that we’ve focused on trying to understand what parents need to do, and to test our ideas and see if changing the parents’ behaviors is enhancing the effects of CBT,” Silverman says. “Our findings thus far suggest that they do." As much as CBT can be helpful, it can also be challenging to get one’s child to do the necessary steps for CBT to work. This is one important reason why Lebowitz created a novel intervention program for parents named Supportive Parenting for Anxious Childhood Emotions (SPACE). Existing intervention programs often teach parents to act as therapists for their child, such as training them on how to practice breathing exercises. “It makes sense, but this doesn’t work very well in practice,” says Lebowitz. “And part of the reason, I think, is that it’s not easy to get your kid to do things, especially if they’re not excited about doing it.” SPACE is unique because it focuses entirely on parent involvement and changing parental behavior—children are not involved in the sessions. For example, parents learn how to use supportive messages that convey confidence that their child can tolerate and manage distress. “It might sound like a parent saying to a child, ‘I get that this is really hard for you, but I know that you can handle it,’” Lebowitz says. The program also works with parents to identify the ways in which they are accommodating anxious behaviors. “We’ll pick one thing that parents are doing that is an accommodation and help them make a detailed plan for how they’re going to change that,” Lebowitz explains. Treating Anxiety in Children and Adolescents Much of the existing research on SPACE has focused on parents of children under age 14. Ongoing studies are now exploring its use with parents of older teens. “Both anxiety and accommodation can interfere with normative developmental shifts during the teen years, including increased autonomy and individuation from parents,” says Rebecca Etkin, PhD, associate research scientist in the Child Study Center. “In this sense, SPACE may be particularly well-suited for anxious teens and their parents. We want to see whether it is effective during this distinct developmental window.” Unfortunately, many families in need of CBT face barriers, including limited availability of services and geographic constraints. One way to improve access is digital interventions. Silverman and her team are developing an evidence-based digitized intervention program for parents that they can access directly from their computer or smart phone. “The work we’re doing will be one of the very few parent interventions that is digitized and importantly tested for effectiveness,” she says. Creating interventions for anxiety-related challenges Silverman and Lebowitz recently received a generous gift to develop and test other interventions that help parents reduce other child anxiety-related behavioral and emotional difficulties, such as restrictive eating and unexplained somatic symptoms. One of these projects in particular focuses on understanding the risks of social media and its potential benefits, including offering a sense of connection. “A lot of research has focused on the idea that social media is harmful and the less of it the better,” says Lebowitz. “But we actually see is that this is not quite right—there are negatives, but there are also positives. So, we’re trying to get a little bit more nuanced of a picture.” The team is working with teens with social anxiety and their parents over an extended period to better understand their social media habits and how their anxiety levels affect engagement with different platforms. The teens will answer questions sent to an app on their phones about mood and social media usage in an effort to capture emotional responses as they unfold. “We hope to develop interventions that can help make the best of social media while protecting against the more problematic effects,” Lebowitz says. The brain’s role in anxiety Researchers are also testing therapies to address anxiety at the neurological and molecular levels. In collaboration with Dylan Gee, PhD, professor of psychology in Yale's Faculty of Arts and Sciences, and Hilary Blumberg, MD, John and Hope Furth Professor of Psychiatric Neuroscience at Yale School of Medicine, Lebowitz and Silverman are using brain imaging to identify changes in a child’s brain before and after parents enroll in SPACE. In one study, children viewed anxiety-inducing images while undergoing magnetic resonance imaging (MRI); the researchers conducted scans with and without the children’s parents nearby. Before SPACE, children’s brains were better able to activate the regulatory circuitry needed to turn off an anxious response when their parents were nearby. But after SPACE, children could activate this circuitry even without the parent around. “As parents work on gradually reducing some of their accommodations, you can see a child get better at regulating their own fear system in the brain,” Lebowitz says. “It’s remarkable.” Research into the molecular underpinnings of anxiety can also inform new childhood anxiety treatments. In a recent study, Lebowitz, Silverman, and Flora Vaccarino, MD, Harris Professor in the Child Study Center, discovered that a protein known as fibroblast growth factor 2 (FGF2) could be protective from the toxic effects of stress. FGF2 levels in children and their parents were linked to the children’s risk of developing anxiety and depression, the study showed. The findings could help explain why some children who are exposed to early life trauma such as poverty or abuse are more prone to developing mental health disorders. And FGF2 could be a target for treatment. “This is very novel because it starts to give a clue to what is the molecular chain that connects those lived experiences to the actual psychological outcomes,” Lebowitz says. New ways to study and treat childhood anxiety Michael Crowley, PhD, associate professor in the Child Study Center, collaborates with Silverman and Lebowitz to study the role that attention plays in development and maintenance of childhood anxiety. There is a large body of research that shows that anxious children, like anxious adults, are prone to focus on threatening stimuli such as angry faces compared with neutral faces. This has led to innovative interventions that involve attention retraining. The idea is that if experts train children to look away from threatening stimuli, it may reduce their anxiety—especially children with social anxiety who are most prone to attend to threats. The researchers have just completed a clinical trial for attention retraining with 10- to 14-year-olds with social anxiety disorders and are currently analyzing the findings. Besides this innovative attention retraining research, as Crowly notes, “I like to design tasks that are engaging to kids,” Crowley says. “My goal is to assess something without the kids knowing what we are assessing.” With this goal in mind, Crowley has created a virtual game, named Boom, to study threat processing in children with anxiety disorders. The game is similar to that of hot potato—the child and three digital players take turns virtually passing a ball to each other’s gloves. At some point, the ball turns into a bomb, and as the bomb lands in each player’s glove, the outline of the glove turns yellow. The goal is to avoid having the bomb go off in your glove. What isn’t obvious is that the game is designed to measure different types of threatening stimuli, both ambiguous and direct. In the game, the direct threat occurs as the bomb is traveling towards your glove. The ambiguous threat is the yellow outlined glove as it is unknown where the bomb will travel next. While children play the game, Crowley’s team measures their brain activity using electroencephalography (EEG). The researchers have discovered that in kids with anxiety, the brain reacts more strongly to ambiguous threats than it does in their peers, but less strongly to direct threats. They believe that the initial abnormally large brain response to not knowing where the bomb is going impairs the brain's ability to properly respond when the threat is actually traveling the child’s way. “The brains of children with anxiety are unable to differentiate between threats you need to do something about and those that are not your problem.” Michael Crowley, PhD, develops innovative games for studying anxiety in children and adolescents.Credit: Matt Bradbury Based on these insights, Crowley hopes to study whether interventions like attention training could restore appropriate threat processing. Crowley’s team is also working on a test called the Balloon Risk Avoidance Task, which evaluates risk-taking and avoidance behaviors. It features a digital balloon that is full of air and about to burst. Kids have six seconds to let air out of the balloon. The more air they let out, the less risk they face that the balloon will pop. But at the same time, the balloon becomes less valuable as it deflates. “The more air you keep in the balloon, the more points you get,” Crowley explains. So far, the researchers have found that when the balloons pop unexpectedly, teens with social anxiety show distinct brain responses. Studying these responses can help psychologists understand the underlying pathways driving the various manifestations of anxiety. The genetics of anxiety When Thomas Fernandez, MD, associate professor in the Child Study Center and of psychiatry, was still in training, there was a lot of excitement about understanding the genetics associated with autism spectrum disorder. Since then, scientists have identified around 250 genes associated with autism. The genetic contribution to anxiety disorders, on the other hand, has historically received less attention. Anxiety is less heritable than autism, but the genetic contribution for anxiety disorders that emerge in childhood may be higher than for anxiety disorders overall. While scientists estimate the heritability of anxiety disorders in general to be around 30% to 50%, some studies suggest higher heritability for certain childhood-onset anxiety presentations. “I saw firsthand how researchers in the field went about finding vulnerability genes for autism,” Fernandez says. “So, we’re using a very similar playbook for childhood anxiety.” “I saw firsthand how researchers in the field went about finding vulnerability genes for autism. So, we’re using a very similar playbook for childhood anxiety.” Thomas Fernandez, MD Associate Professor In the Child Study Center and in Psychiatry Now, Fernandez and Emily Olfson, MD, PhD, assistant professor in the Child Study Center, are studying children and their parents to identify genetic changes that are present in the child but not the parents, known as “de novo mutations.” “All of us have some de novo mutations—maybe about 50 to 100 sprinkled throughout the genome,” Olfson says. “But when they occur within the coding regions of genes, they can be really disruptive.” Previous research shows that people with autism have higher rates of damaging de novo mutations than the general population. In 2022, Olfson, Lebowitz, Silverman, and Fernandez published a study on 68 children and their families that found that children with anxiety had similarly high levels of these mutations. Studying de novo mutations can help point the researchers to where they should be looking for genes associated with anxiety. “The end game is using the genes to steer us toward the right part of biology that we can then target to come up with better treatments,” Fernandez says. Building on those findings, the team is now studying more families to better understand how these de novo mutations, along with other genetic and environmental factors, shape pediatric anxiety disorders. They recently received a National Institutes of Health grant to enroll 750 new families over the next five years. Olfson is the principal investigator, with co-investigators Lebowitz, Fernandez, Silverman, and Shuangge Steven Ma, PhD, department chair and professor of biostatistics at Yale School of Public Health. Neurodevelopment, Risk Genes, and Mental Health Conditions - The Olfson Lab Joel Gelernter, MD, Foundations Fund Professor of Psychiatry, is interested in how different anxiety disorders differ genomically. “We are studying social phobia, panic disorder, and generalized anxiety disorder, working to understand why people differ in their risk to these specific anxiety disorders and evaluating various risk factors,” he says. Gelernter was recently involved in one of the largest studies to date of the genomics underlying anxiety disorder. The study included around 122,000 people with anxiety disorders and around 730,000 without. It found that some genetic differences associated with anxiety were linked to signaling that helps reduce overactivity in the nervous system. Many anxiety medications available today work by targeting this process. “It’s nice when the biology that you get out of a large genome-wide study ratifies things that we already know because that can help increase confidence in further findings from the study,” Gelernter says. Uncovering the neurobiology of psychiatric disorders John Krystal, MD, Robert L. McNeil, Jr. Professor of Translational Research and chair of the Department of Psychiatry, is interested in the neurobiology of psychiatric disorders, including post-traumatic stress disorder (PTSD), of which anxiety is a major symptom. In the late 1980s, Krystal’s team discovered that the drug yohimbine activated symptoms in patients with PTSD. “This was the first time we could link a specific biological mechanism to the symptoms of PTSD,” Krystal says. At the time, he adds, this finding was highly controversial. “A lot of people felt that PTSD was a purely psychological syndrome that didn’t have an underlying biology.” Since then, Krystal has dived deep into understanding the neurobiology of PTSD to learn how to better treat it. His team is evaluating the use of ketamine and psychedelics. These would be among the first treatments to be developed specifically for PTSD. They may also be applicable for other disorders including anxiety disorders, Krystal adds. An important gap in PTSD treatment is the absence of biological tests that inform how to best help patients manage their PTSD symptoms. A doctor doesn’t diagnose cancer based on how they feel. Rather, they use tests of the biology of the cancer to determine the best course of treatment. “And we can’t do that in any psychiatric disorder other than Alzheimer’s disease,” Krystal says. “But now we are building a foundation for this approach to the treatment of anxiety disorders for the first time.” Source: Yale School of Medicine
NVIDIA and Microsoft tease RTX Spark announcements for October 7 Windows event
RTX Spark will be a key focus of Microsoft’s October 7 Windows event with Jensen Huang in attendance. The first systems appear aimed at premium laptops and workstations rather than gaming PCs.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Huang says 1 number in the AI debate isn't science-based at all
Nvidia's CEO took aim at a figure that has shaped careers and portfolios, and the man behind it has his own doubts.
Pandas and Eagles and A.I., Oh My! Trump Throws a State Dinner for Xi
Altman. Musk. Huang. Bezos. They all came to the White House Thursday night, though you might not have seen it on TV.
Nvidia CEO Doesn't Care That Kids Are Forgetting Basic Math Because Of AI: 'I Actually Don't Know My Address'
Who needs to know things like your own phone number or home address or how to solve a simple equation like 3x2?
Jensen Huang: AI CEOs have 'ulterior reasons' in doomsday warnings
Nvidia CEO Jensen Huang says current regulations are enough to ensure AI is safe — and profitable.
AI leaders to attend state dinner with Jinping: Report
Several of the technology industry’s most prominent artificial intelligence leaders are expected to attend President Donald Trump’s state dinner for Chinese President Xi Jinping next week, putting AI and the growing U.S.-China technology rivalry in focus as the two leaders prepare for their Sept. 24 summit. OpenAI CEO Sam Altman, Nvidia CEO Jensen Huang, and […]
Jensen Huang said China isn't debating AI doom. Weibo disagrees.
Nvidia CEO Jensen Huang's remarks are trending on Weibo, the country's version of X.
Nvidia CEO Jensen Huang dismisses AI doomsday fears as 'not grounded in science'
Stuart Varney and Madison Allworth report on Nvidia CEO Jensen Huang dismissing AI doomsday fears. Jensen Huang explains why extreme AI concerns are not grounded in science, as President Donald Trump calls into the event.
CEO Jensen Huang offers candid advice to departing Nvidia staff
Nvidia CEO Jensen Huang gives blunt feedback to departing employees, influencing startups like Flexion Robotics and INT21 with direct insights.
Nvidia CEO Jensen Huang dismisses "hysterical" AI fears
Nvidia CEO Jensen Huang dismissed fears of out-of-control AI creating outright havoc, but he's at risk of losing control of the narrative.
Jensen Huang’s AGI Claim Is A Business Case, Not Settled Fact
Jensen Huang says AGI has arrived, but the claim reflects AI’s business value more than proof of human-level, general-purpose intelligence.
Nvidia's Jensen Huang says 'AGI has arrived' and congratulates OpenAI
Nvidia CEO Jensen Huang made the comment on Sunday, days after OpenAI released Astra, its newest and most powerful AI model.
Judge blocks Trump admin from moving FBI headquarters to DC office building
U.S. District Judge Theodore D. Chuang ruled that the move was "not in accordance with law"
Judge blocks Trump admin from moving FBI headquarters to DC office building
U.S. District Judge Theodore D. Chuang ruled that the move was "not in accordance with law"
From Curiosity to the Frontiers: ICBS Honors Four Women Scientists
Among the nine recipients of the ICBS Medal awarded at the 2026 International Congress of Basic Science (ICBS), four are women: Claire Voisin, Andrea J. Liu, Bao Zhenan, and Zhuang Xiaowei. Shing-Tung Yau, chair of ICBS, highlighted this in his opening address, noting that 'women researchers are contributing to every stage of scientific progress through their distinctive intellectual perspectives and sustained dedication.'
Jensen Huang says this is the greatest time in history to start a business—and his advice is to stop overthinking it: ‘How hard can it be?’
The billionaire CEO has spent the last three decades building Nvidia —but says one simple mindset helped turn a diner-booth idea into a $4.7 trillion giant.
The Science Behind the AI Panic Is Shakier Than You Think
A column by Sascha Lobo Is AI making us dumb? So asked DER SPIEGEL on its cover a while ago. After a few weeks of recovery and a therapeutic intervention with the help of my AI, I feel able to respond. That’s a bit unfair, of course; the article itself is more nuanced than the loud cover, the image of a schoolkid with dull prompt questions, or the subtitle: “AI is conquering the schools, and educators fear a disaster.” The short answer to “Is AI making us dumb?” is: no. The long answer is more interesting, and even carries a preliminary glimmer of the spectacular. Unfortunately, it requires a detour into the sphere of artificial intelligence, into the mogul-field terrain of technology assessment, the attention economy, and the destructive virus of cultural pessimism. Along with narrowing the scope to AI’s effects on education and work rather than on intelligence. Because the honest version of the question would be: Does AI help us learn and work, or not? Generative AI, which set off the still-ongoing hype with ChatGPT, has only existed in relevant distribution since late 2022, early 2023. For a technology-driven transformation of people and society, that is extremely short. For that reason alone, research is still in its infancy. And technology assessment is not a fast discipline anyway. Prominent voices from Elizabeth Eisenstein to RAND to Tom Wheeler say we still cannot conclusively judge the consequences of the printing press. Its invention is a mere 580 years back, and some scholars would rather not circulate assessments that might have to be retracted in two or three hundred years. We’re Going Through Growing Pains A phenomenon that already caused upheaval in social media research makes serious assessment of AI’s consequences even harder: the “moving target” problem of LLM-ology, as the linguist Sean Trott called it in 2025. AI develops so quickly and so unpredictably that researchers often end up studying snapshots of the past. There are concepts, from morphological analysis to anticipatory governance, for keeping research, planning, and regulation halfway meaningful anyway. But even with those, universally valid statements are rare. DER SPIEGEL - The German View is a reader-supported publication. To receive new posts and support our work, consider becoming a free or paid subscriber. Subscribe We should therefore treat findings about the interplay between humans and AI as far more procedural and situational. Unfortunately, this challenge comes at the worst possible time. We are going through growing pains: AI’s everyday impact has grown very large very fast, and with it the longing for guidance. Annoyingly, the body of solid knowledge has not exploded along with it. Experts cannot be moved to broad consensus on even banal statements about AI. Sascha Lobo, born in 1975, is an author and strategy consultant focusing on the internet and digital technologies. Together with Jule Lobo, he explores the debates of the day in the podcast “Feel the News – Was Deutschland bewegt” (”What Moves Germany”). Nvidia CEO Jensen Huang says software developers are dying out. Bill Gates considers coders one of only three professions that will survive the AI tsunami. Top tech economists find virtually irrefutable arguments both for and against an AI bubble. The same naturally applies to the structurally youth-hostile debate over whether AI is good or bad for young people. The gap between the demand for insight and the supply of solid knowledge creates an orientation vacuum. This vacuum of AI cluelessness is filled, as the attention economy described by Georg Franck in 1998 would have it, with half-knowledge (funnily enough, often AI-generated), marketing, and self-marketing. After all, infinite money is at stake, along with academia’s best current shot at global fame. But this iridescent froth of interpretation operates more by the algorithmic principles of the digital public sphere than by seriously earned insight. That is why dramatized, fear-feeding claims about AI are so promising. It tempts parts of academia into distorted drivel, and parts of the media then sensationalize the published drivel once more. Was the Research Aimed at a Desired Result? How badly this can influence academia and public perception is demonstrated by one of the most-discussed studies on AI’s effects: “Your Brain on ChatGPT.” The MIT study by Nataliya Kosmyna also gets plenty of space in the SPIEGEL cover story. What was measured and interpreted: lower brain activity in people who write with AI assistance, compared to people who only google or write without any tools. As is common with preprints, the study has not yet been peer-reviewed, and it contains substantial weaknesses that experts have sharply criticized. The first round had 54 participants in three groups, the second only 18, who reportedly also came from MIT’s own orbit. There was no preregistration (committing in advance to what you want to find out with which data). In their analysis, Stanković et al. even discovered an opposite effect that the study does not further explain. Some measurement data has not (yet) been published. And the EEG analysis method used is considered too imprecise to support such far-reaching conclusions. The biggest criticism, though, is the suspicion of an activism-driven study. In an interview with Time, lead author Kosmyna said she published the study immediately, rather than after full peer review, because she feared politicians might otherwise decide to put ChatGPT in kindergartens. She considers that absolutely harmful. It is legitimate to hold such a view. It just seems unscientific to approach a study with it, and then to design the setup so that the chance of a fitting desired result remains as high as possible. Ideologies Collide It is not easy to separate genuine AI insights from studies that trivialize and weaken well-founded AI criticism. The same goes for the opposing, AI-enthusiastic narratives, because the pro-AI side works against it with billions in resources. Ideologies collide, fed by egos, PR strategies, moral posturing, and once-in-a-lifetime opportunities. Doomsday marketing makes the search even harder: AI companies can profit from warnings about the dangers of AI, whether through the notoriety of apocalypse narratives or because, in some target groups, danger translates into power. Some seemingly negative findings are therefore quite welcome in the AI industry. If you try to get at the findings presumably less influenced by interest groups, the picture in education seems relatively clear: AI can improve educational outcomes when the right AI is used the right way, namely pedagogically. Simply dumping an AI chatbot into a classroom, by contrast, accomplishes little. Huge surprise. But something else is also obvious: whether they are allowed to or not, kids use AI for school, which is why the controlled integration of AI tools into education is, in the medium term, entirely without alternative. In the world of work, the landscape of findings is more complex and requires more differentiation. A series of serious studies points to an AI effect that suits neither the alarmists, regulation fetishists, and AI opponents, nor the trillion-dollar corporations with their armada of paid scientists, PR professionals, and ecosystems: working with AI helps the inexperienced (at least for now) considerably more than it helps the pros, in certain fields of work, and provided they know how to use it correctly. Missing Domain Knowledge Among the experienced, the professionals, and the high flyers, by contrast, despite frequent time savings, partially negative effects and new problems are emerging. Take the jagged frontier problem: AI solves task A brilliantly and fails completely at task B, even though both look similar even to professionals. Or the verification-cost problem, in which AI’s greater productivity gets eaten up by the enormous effort of checking its output. Or the illusion of competence, because AI makes new domains seem easily penetrable, until you painfully discover that deep domain knowledge is missing. Taken as a whole, the effects of working with AI do lean positive. But the promise that AI works as a turbocharger for everyone and boosts practically everything simply refuses to materialize. The AI magic the world has been feeling since ChatGPT arrived in late 2022 has so far barely shown up in most companies’ numbers. The consulting firm McKinsey has coined a term for this, the “gen AI paradox,” and believes that work processes and corporate structures would have to be rebuilt quite fundamentally to realize AI’s benefits at scale. Reuters just reported that only 3.3 percent of Microsoft’s customers have subscribed to the AI package Copilot. That may be down to the product; in other areas we continue to see soaring successes and new AI triumphs. But after the first quarter of 2026, disillusionment is the word for all too many AI projects at traditional companies: because the promised revolution of AI agents has so far failed to arrive or been postponed, and because of the leveling effect that many of the studies cited here suggest. Against Inequality The societal effects, on the other hand, appear rather encouraging. Many previous technologies operated on the Matthew principle, named for the Gospel verse about giving to those who already have: they tended to reward the more competent and more privileged. AI, however, seems more often to have an equalizing effect once a threshold of access and education is crossed. Some anecdotal insights point in this direction, for example, how an unemployed man in Leipzig successfully defended himself in court in 2025 against fraud accusations from Germany’s federal employment agency — without a lawyer, armed only with ChatGPT. The AI made mistakes and cited invented court rulings, but in the end the man walked away unpunished. And a key capability of artificial intelligence is its capacity to learn: set up correctly and fed with data, it can keep getting better. It is a question of time, or more precisely of AI innovations and training data, until even free AI chatbots write better legal briefs than law graduates with perfect exam scores. Whether that will make anyone dumb is something the world’s press will surely inform us of in due time. Subscribe Leave a comment
Nvidia CEO to Washington: Don't fall for "science fiction" AI fear
Jensen Huang railed against AI doomerism in an interview with Axios' Mike Allen.
Watch Manycore Tech CEO on Business and AI Strategy
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In 1997, with dwindling cash, the Nvidia CEO ordered mass production of a graphics chip tested entirely in a simulator.
Jensen Huang's leather jacket could fetch $60,000 at auction
Nvidia CEO Jensen Huang's black Tom Ford leather jacket is up for auction, with proceeds benefiting charity, Sotheby's said.
Cambridge city manager says Wu’s business summits are a ‘wakeup call’
Boston Mayor Michelle Wu has held three economic summits to address issues facing the region. Yi-An Huang has attended all three.
Toward a uniform business tax system: Examining proposals to tax large pass-through entities as corporations
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Toward a uniform business tax system: Examining proposals to tax large pass-through entities as corporations
Miles Johnson, Thalia T. Spinrad, Kathleen Bryant, and Chye-Ching Huang analyze a proposal to tax large pass-through businesses as C corporations.
Nvidia CEO Jensen Huang Just Declared War on Intel, AMD, and Qualcomm -- and the PC Market Will Never Be the Same
If Huang is right, the PC market could now be experiencing its iPhone moment.
Nvidia wants to supercharge your laptop
Jensen Huang is bringing the firm’s AI act to the PC
Jensen Huang calls Marvell 'next $1 trillion company,' stock spikes
Marvell Technology's share price jumped more than 20% in out-of-hours trading after Nvidia's CEO praised the lesser-known chipmaker.
Jensen Huang Says Nvidia and Microsoft Just Reinvented the PC. But There Might Be 1 Problem
For years, the PC industry has been stuck in a rut. Consumers stretched upgrade cycles from three years to five or more, smartphone sales stole attention, and innovation often boiled down to slightly faster processors and better battery life. So when Nvidia (NASDAQ:NVDA) CEO Jensen Huang declares that the PC has been “reinvented,” investors should ... Jensen Huang Says Nvidia and Microsoft Just Reinvented the PC. But There Might Be 1 Problem
3 big takeaways from Jensen Huang's keynote speech at Computex
Jensen Huang's speech was jam-packed with new releases, including the RTX Spark which aims to reinvent the personal computer as we know it.
NVDA Stock Set For Strong Open Today: CEO Unveils First PC Chips At Computex 2026
During a keynote address at Taiwan’s Computex conference, Nvidia CEO Jensen Huang unveiled a new N1X processor developed in partnership with Microsoft.
Nvidia CEO Jensen Huang fuels South Korea stock surge
The Nvidia chief is reportedly meet with executives from some of the country's largest companies later this week.
Leak Tips Potential New ASUS ROG Xbox Ally Gaming Handheld
It was previously revealed that ASUS may be launching an update to the ASUS ROG Ally gaming handheld at Computex 2026, but not much was known about the new handheld at the time. Now, thanks to licensing documentation from the Korean National Radio Research Agency, shared by Huang514613 on X, a littl...
Nvidia CEO discusses AI impact on education and future jobs
Nvidia CEO Jensen Huang says the same skills that mattered before AI will still matter in the future.
America's most powerful CEOs don't have much to show from their China trip so far
With red-carpet treatment, selfies and culinary diplomacy, America's richest and most powerful executives - from Tesla's Elon Musk to Nvidia's Jensen Huang - sought to rekindle business ties with China this week at a leadership summit in Beijing.
Nvidia Stock Extends Winning Streak On China News
Nvidia stock gapped higher on Thursday on a report that Chinese firms are lining up to buy its AI chips if they can secure China's approval.
China Will 'Open Wider' For U.S. Business, Xi Tells Trump Delegation—Including Musk, Cook, Huang
U.S. executives, with a combined $1 trillion net worth, joined Trump on his trip to China.
Trump, Elon Musk are trying to open up China for business
President Trump's summit in China with President Xi is underway, with Nvidia (NVDA) CEO Jensen Huang and Tesla (TSLA) CEO Elon Musk tagging along. Yahoo Finance Washington Correspondent Ben Werschkul explains what you need to know from the first day of the summit.
Xi tells Musk, Tim Cook and other CEOs on Trump's trip: China will 'open wider'
Tesla and Space X boss Elon Musk, Nvidia's CEO Jensen Huang and Apple CEO Tim Cook were part of Trump's delegation.
‘The reality, for better or worse’: Columbia comp sci students and faculty grapple with AI’s disruption of the field
‘The reality, for better or worse’: Columbia comp sci students and faculty grapple with AI’s disruption of the field ‘The reality, for better or worse’: Columbia comp sci students and faculty grapple with AI’s disruption of the field A field that once seemed like a direct path to stable, lucrative work is becoming less certain under AI, students and faculty told Spectator. By Ria Vasishtha and Arjun Menon May 3, 2026 Shanying Liu / Deputy Illustrations Editor Asia Genawi, SEAS ’29, first encountered artificial intelligence during her sophomore year at her high school in Indiana. Back in 2023, policies on AI varied widely—even within the same district—and some schools had no guidance at all. As Genawi began to see the effects of AI trickle into her classroom, she turned to guidance from her home state’s Department of Education, which she said she found “outdated and inaccessible.” Genawi spent the rest of her high school career dedicated to the issue, including writing a 15-page memo exploring varying AI policies across Indiana schools, which she sent to every Indiana state senator and representative whose contact information she was able to find. She later helped draft a bill that would have required public high schools to establish and share their own AI policies with students in an accessible format. But with so many other bills already awaiting referral, hers never made it to committee. When Genawi arrived at Columbia to study computer science, she found that the gaps she had spent years trying to address in Indiana had followed her there. Many students and professors were also grappling with what AI meant for the field. Across Columbia’s undergraduate schools, computer science has become the most popular major—accounting for around 11 percent of degrees awarded in Columbia College, 32 percent in the School of Engineering and Applied Science, and 12 percent in the School of General Studies in 2024. While the number of computer science majors in SEAS grew from 166 to 173 during the 2024-25 academic year, the total number across the three schools fell around 4.5 percent from 393 to 375, driven by declines at Columbia College and General Studies. At Barnard, it has grown to become the second most popular major as of 2025, up from third the year prior. The number of degrees awarded have grown fivefold since 2016. Faculty members and students in the department told Spectator that the surge in the major’s popularity has been driven in large part by its apparent promise of a secure, well-paid career path. However, they noted that the recent rise of generative AI has compromised the sense of stability that once defined the field, even as interest in technical skills among students persists. According to data from the Federal Reserve Bank of New York in 2024, out of 74 majors tracked, computer science had the fifth highest unemployment rate among majors at 7 percent, while computer engineering had the second highest at 7.8 percent. “Anecdotally, people are moving away from CS as a major,” Daniel Bauer, a senior lecturer in the computer science department, said. “They’re still taking some of our classes, right, because they think they need that, but they’re instead majoring in other things.” Bauer described a field that had shifted from what he called a “nerdy outlier discipline” to one that “everyone needs,” a sign that technical skills have become a baseline expectation across industries with the emergence of AI. “A lot of people thought, ‘Oh, it’s a guaranteed path to a stable income. You get a six-figure job right out of your undergrad,’” Bauer said. Now, companies may see AI as a way to reduce demand for entry-level programmers, especially in what he calls “code monkey jobs,” roles where a large number of employees are “just writing out code nine-to-five.” Chris Murphy, a senior lecturer in the computer science department, described the current moment as the convergence of two forces: the downturn of the job market and generative AI coming onto the scene. “Things kind of started to really pick up in 2014, 16,” he said, recalling the years after the weaker 2010 market. Murphy added that this was also a period where “students were getting more experience outside of class than they were inside of class” through internships, jobs, and side projects. Murphy suggested that the earlier momentum helped make computer science feel like both an academic program and a reliable pathway into work. That feeling is harder to sustain now as the industry reconfigures, which is a shift that students are seeing firsthand. Rebecca Yu, SEAS ’27, said that during a recent internship in Big Tech, she saw that “every single tech company was racing to integrate” large language models. She added that her manager said her intern class was the first to complete their assigned projects, which she attributed to the increased efficiency that comes with AI. Frank Liu, SEAS ’29, said that with AI lowering the barrier to coding, companies now expect everyone to write code. “A lot of companies outright say if you’re not using coding in your job, you might get fired for not being productive enough,” Liu said. Yu similarly expressed that students increasingly have to accept AI being a part of industry workflow, adding that many also “make use of it to maximize their productivity.” Richard Li, CC ’28, described a “franticness” among his peers as the pace of change accelerates. He explained how “some new tool” is released regularly, noting that tools rise and fall in prominence within weeks. He has come to believe that he doesn’t need to “match that speed all the time” and keep up with every development. Li has learned that AI tools allow him to “take a breath” and “get back into the loop much easier than before” when he needs to. While some companies specifically target Columbia when hiring, sending representatives to campus career fairs and recruiting large numbers from Columbia, a computer science degree cannot be treated as a static credential, Yu described. “You can’t just get your degree and stop learning after that. You have to always be learning,” Yu said. “That is something you basically have to expect for your job.” AI has not only affected students’ decisions to major in computer science, but also reshaped how the subject is taught. Across departments, faculty members no longer treat work done outside the classroom as a reliable measure of understanding, shifting instead toward in-person exams, quizzes, and attendance checks. While homework once made up as much as 60 to 70 percent of a student’s grade in computer science classes, Murphy said that breakdown has since flipped, with exams and quizzes now accounting for the majority. “The assumption—especially among pessimists—is that they’re using it to do their homework,” Murphy said. “They take the homework assignment. They put it into generative AI. Out comes the solution. Submit solution. The end.” Murphy said that faculty members ranged in their responses from fully prohibiting AI use to actively teaching students how to effectively work with AI. He said he shifted his approach this year after his teaching assistants called his belief that students weren’t using the technology “naïve,” and now permits students to use AI on assignments. His surveys of students in his introductory classes have told a more complicated story than the one so-called pessimists offer: Around 60 to 70 percent of students who reported using AI said they used it to have concepts explained to them, to clarify assignment instructions, to generate test cases, or to create practice questions. “Those are all ways that you might have had a tutor in the past to do that, and now you have this AI essentially as your tutor,” he said. Bauer has taken a different approach, teaching students how to use AI productively without sacrificing the core principles of the discipline. “People who are trained to actually use AI tools productively, while being in charge of designing the overall project, will be very much in demand in the next couple of years,” he said. Over the past year, a working group of computer science faculty has been redesigning the introductory and intermediate programming sequence to integrate generative AI as both a subject and a tool, representatives from SEAS wrote in a statement to Spectator. The effort is “coordinated” across the department, “not course-by-course,” with a systematic assessment of how AI integration is affecting student outcomes underway to shape the next round of changes. The goal, the department explained, is for students to be able to “read, verify, and reason about code, whether they or a model wrote it.” Tony Dear, senior lecturer in the computer science department, is piloting individualized AI feedback in a discrete mathematics course, while a machine learning course is also testing a Socratic AI dialogue system designed to “guide inquiry rather than supply answers,” the statement reads. Beyond individual courses, SEAS funded seven cross-departmental faculty projects in generative AI this past academic year, spanning biomedical engineering, chemical engineering, industrial engineering, and computer science, according to the statement. This phenomenon extends beyond the computer science department. SEAS’ new AI minor, which it announced in November 2025, reflects the University’s attempt to adapt. The minor is specifically designed for noncomputer science majors and aims to provide “essential AI knowledge” while emphasizing practical and responsible use across disciplines, according to the SEAS website. At the center of the minor is AI in Context, a course taught by a team of faculty from the departments of computer science, applied mathematics, philosophy, music, literature, and the Writing Center, the representatives told Spectator. Bauer described it as targeted at students who want to bring AI into fields like economics or biology, rather than as a path into software engineering itself. At the graduate level, SEAS announced a new Master of Science in artificial intelligence in February, with the inaugural cohort starting in the fall. While recognizing how AI has helped them navigate coursework, students also described its rise as isolating, even among members of the Application Development Initiative, one of Columbia’s largest computer science clubs. “As people start to ask AI for questions that they would normally ask students and members, it starts to isolate people” Li said. Alexa Kafka, BC ’27, echoed Li’s sentiment, pointing out that computer science has always been a collaborative discipline with code reviews and pull requests, even as AI makes independent work easier. Despite this, Kafka noted that she hasn’t been to office hours “in at least a year.” Bauer added that faculty are exploring long-term solutions to the assessment problem. “One of the things that we’re trying to do at the department or school level is to maybe move towards computerized testing facilities,” Bauer said, referring to ideas in the department to revitalize computer labs as an alternative to pen-and-paper exams. “We have to accept that this is the reality, for better or worse.” But more exams, students say, does not mean better learning, nor does it reflect how computer science is actually done. “Code is so variable and can be approached in so many directions, there’s never just going to be one correct answer. There can be multiple optimal solutions,” Kafka said. Students also expressed concern that the shift toward exam-heavy grading pulls focus away from the applied, project-based work that better reflects both discipline and industry expectations. ADI has tried to respond more quickly than the curriculum can. Through a vibe coding workshop this past semester, club members said they wanted to help students understand not just that AI exists, but how to use it deliberately. “Vibe coding” refers to the practice of prompting AI to write code for a task or project, and has become widespread enough that ADI felt the gap in formal instruction was worth addressing, according to Sophia Huang, BC ’29. The workshop introduced students to the concept of context engineering, which Shaina Sahu, SEAS ’27, described as not just writing a prompt, but optimizing “the rest of the relevant information that you would feed into the model.” Without that, students said that AI-generated code can fail at scale or introduce difficult-to-detect bugs. Genawi said the shift toward AI has changed what it means to be good at computer science. “I think the shift has kind of gone towards what can you create and what can you do, instead of, what do you know,” she said. Indeed, during ADI DevFest, its annual hackathon, Li said more teams are trying to complete their projects than in years past. While sign-ups have historically outpaced submissions, Li said this is beginning to change because teams “have a tool that completes the vision for them.” While many students see AI as an equalizer that lowers the barrier to entry for coding and technical work, Murphy said it also creates new equity concerns inside the classroom around who can afford stronger tools and who already knows how to use them. “The equity issues I worry about are students who have access to paid versions of things versus free versions of things,” he said. Although popular AI models like ChatGPT and Claude have free versions available, both have paid models that can reach over $100 per month, which output different qualities of code. Murphy also pointed to differences in prior exposure to AI literacy itself. “Students who go to high schools or K-12 education, where they’re taught AI literacy, prompt engineering, context engineering, they understand how to do this, as opposed to students who go to schools who don’t teach that,” he said. “Then they come in, and then they’re somehow expected to know how to use these tools.” For Genawi, those disparities begin long before students arrive on campus. “It’s very interesting to consider how lucky you were geographically,” she said. “To be born where you were is influencing your ability to get access to these spaces.” Students like Yu, though broadly apprehensive about the future of computer science, are not without hope. “I’m optimistic, because I think if you’re truly passionate about CS, there will definitely be a place in the field to do something you want to do,” she said. Senior Staff Writer Ria Vasishtha can be contacted at ria.vasishtha@columbiaspectator.com. Follow Spectator on X @ColumbiaSpec. Staff Writer Arjun Menon can be contacted at arjun.menon@columbiaspectator.com. Follow Spectator on X @ColumbiaSpec. Want to keep up with breaking news? Subscribe to our email newsletter and like Spectator on Facebook. Produced with Spectate by Emily Ta
Changing This One Marketing Question Helped Her Build a Business That's Thrived for Over Three Decades
Julia Huang is the founder and CEO Intertrend Communications, which prides itself on being "the Most Award-Winning Result Driven Asian American
Research commissioner pitches EU to US scientists and investors
Research Commissioner Ekaterina Zaharieva is just back from a two-day trip to San Francisco, where she pitched the EU as the place to be for US researchers looking to move and US venture capitalists looking to invest. A Commission spokesperson told Science|Business that Zaharieva used the trip to “promote Europe as a stable, rule-based and vibrant innovation destination.” She emphasised Europe’s excellent infrastructure and predictable funding, particularly through the European Research Council (ERC) and Europe Innovation Council.These are already proving tempting, with applications from US-based researchers to ERC and Marie Skłodowska-Curie Actions (MSCA) calls increasing substantially over the past few years. According to the Commission, the number of US-based applicants for the annual ERC Consolidator Grant call rose from 19 in 2025 to 64 in 2026, while US bids to the ERC Advanced Grant call rose from 23 in 2024 to 114 in 2025. Meanwhile, US applications to the MSCA Postdoctoral Fellowships scheme rose from 352 in 2024 to 998 in 2025.Pressure on US scientists to seek alternative employment has increased since Donald Trump’s return to the White House. Jobs at federal science agencies have been slashed, funding cut in some research areas and international scientific partnerships turned upside down. He has also made unprecedented attempts to control university affairs.During her trip, Zaharieva made a point of highlighting the protection of academic freedom in Europe, “especially in areas like climate change, renewable energy, and health, where US funding has faced cuts,” the spokesperson said.She also underlined the EU’s “attractive long-term career opportunities and relocation support for top researchers from anywhere in the world,” especially through its new Choose Europe for Science initiative.“Transatlantic cooperation remains essential to tackle global challenges while safeguarding shared values such as academic freedom and openness,” Zaharieva wrote on social media ahead of her visit.Related articlesERC walks back stricter resubmission rules for 2027Don’t feel guilty about poaching scientists fleeing Trump, US science body tells EuropeHer itinerary took in Stanford University’s business school and school of medicine, where topics for discussion included entrepreneurship and interdisciplinary collaboration. She also met with venture capital firms, including Playground Global, Forgepoint Capital and Akkadian Venture Capital, as well as the California Public Employees’ Retirement System, the largest public pension fund in the US.Other meetings included Jensen Huang, the chief executive of AI chip manufacturer Nvidia, and local business associations such as the Bay Area Council and EuroCham. European delegations in the area also received visits, including Advantage Austria and France’s La French Tech, and the Consulate General of Ukraine in San Francisco.
Two inducted into Thomas Green Clemson Academy of Engineers and Scientists
Gary Mercer and Jim Kaplan receive college's highest honor, and Jie Huang, Thomas Kuckhoff and Toni Bloodworth Pence are honored as Outstanding Young Alumni.
Laptops Are About to Get Very Exciting Again... Thanks to Nvidia
Nvidia is about to throw another wrench into laptops led by Intel, AMD, and Qualcomm.
Pose-based embodied interaction for digital Dunhuang dance heritage
npj Heritage Science - Pose-based embodied interaction for digital Dunhuang dance heritage
Q&A with Dallas County public health director
Dr. Philip Huang has worked on HIV prevention efforts, tobacco and secondhand smoke measures and more.
Q&A with Dallas County public health director
Dr. Philip Huang has worked on HIV prevention efforts, tobacco and secondhand smoke measures and more.
Trump names David Sacks co-chair of tech advisory council, expanding AI, crypto role
Trump names David Sacks as PCAST co-chair, expanding his AI and crypto czar role, with Nvidia's Jensen Huang, Meta's Mark Zuckerberg and Oracle's Larry Ellison also joining.
Trump names Jensen Huang, Mark Zuckerberg to 13-member science and tech council
Trump has made securing U.S. leadership in artificial intelligence a central priority of his second term.
Trump to name Zuckerberg, Ellison, Huang to tech panel, WSJ reports
U.S. President Donald Trump plans to appoint Meta Platforms CEO Mark Zuckerberg, Oracle Executive Chairman Larry Ellison and Nvidia CEO Jensen Huang to a panel that weighs in on AI policy and other issues, WSJ reported on Wednesday
Exclusive | Trump to Name Mark Zuckerberg, Larry Ellison and Jensen Huang to Tech Panel
The President’s Council of Advisors on Science and Technology is to weigh in on policies affecting the development of AI.
Advancing Science, Students Provide Fun and Free STEM Programs for Low-Income Youth
Alyssa Huang seriously loves science and math. And she’s on a mission to make every kid feel the same way.
Live Science Today: Jensen Huang AGI claim and major leap to reanimation after death
Tuesday, March 24, 2026: Your daily roundup of the biggest science stories making headlines.
Jensen Huang softens DLSS 5 response, says “I don’t love AI slop myself”
Jensen Huang changes tone on DLSS 5 Jensen Huang has shifted to a softer tone on DLSS 5 criticism, saying he understands why some players reacted
Nvidia CEO Says He Hates AI Slop Too After DLSS 5 Panic
Jensen Huang tried again to defend one of the company's most unpopular initiatives
New dispute emerges around Subnautica 2’s early access release
Lawyers for the ousted—and now partially reinstated—leadership team of Unknown Worlds, the studio behind Subnautica 2, are crying foul over news that the game will be released into early access in May. The release announcement earlier this week was made improperly, potentially “damaging the game and sowing additional confusion among the Subnautica community,” the lawyers said in a letter sent on Tuesday to Vice Chancellor Lori Will of Delaware’s Court of Chancery. In their letter, the lawyers also floated the idea of asking Will to find Krafton in contempt of the court’s ruling. The letter was sent just one day after Will’s bombshell ruling that publisher Krafton had breached its contract with Unknown Worlds’ executive team, when it fired them last June. The new issue isn’t necessarily the May early access timeframe, but how the news was announced. The letter and Krafton’s response have not been previously reported. A quick recap of prior events: Subnautica 2 is an unreleased, underwater survival adventure and the most-wishlisted game on Steam. Last year, longtime Unknown Worlds CEO Ted Gill, along with studio co-founders Charlie Cleveland and Max McGuire, were fired by Krafton. They swiftly sued, saying the publisher had terminated them to avoid paying out up to $250 million in potential performance-based bonuses. The studio leaders had hoped to earn that with an early access release of the game, which Krafton had blocked. The publisher argued in court that Subnautica 2 wasn’t ready, which the ousted execs disputed. On Monday, Will ruled that Krafton had violated its contract, firing the execs to avoid the performance payouts, and that it had to reinstate Gill and give him full authority over any early access release for Subnautica 2. On Tuesday, IGN reported on a new memo issued that day to Unknown Worlds staff by Steve Papoutsis, the executive Krafton had put in charge of Unknown Worlds after the 2025 firings. In the note, Papoutsis said that Subnautica 2 had passed a key development milestone “last week” and that he and Krafton had determined the game “is ready for Early Access release in May.” This news appeared to catch the lawyers for Gill, Cleveland and McGuire by surprise. On Tuesday night, they sent a letter to Will expressing “serious concerns” about whether it would be possible to forge an agreement with Krafton consistent with the judge’s order. Papoutsis’ memo was a problem, they wrote. He didn’t have the authority to declare anything about Subnautica 2’s release. As of 9am ET on Monday, March 16, the effective date of Will’s order, Papoutsis wasn’t CEO of Unknown Worlds. Gill was. And, per Will’s order, only Gill could make Subnautica 2 release decisions. They continued: Krafton self-servingly announced the launch without any regard to its impact on the game, the team, or the community—let alone this Court’s Opinion. Announcing the release of a game is momentous, and it is typically accompanied by significant marketing activity, fanfare, and community coordination. And most importantly, the announcement is carefully designed to maximize excitement for the game. That entire process was supposed to be driven by Mr. Gill. However, in defiance of the Court’s Opinion, Krafton has now taken that away, further damaging the game and sowing additional confusion among the Subnautica community. The lawyers speculated that Krafton had “intentionally leaked” Papoutsis’ memo and then issued an official statement to confirm the leak. Game File is a reader-supported publication. My reporting is only possible through support from readers like you. To support my work, consider becoming a free or paid subscriber. Subscribe On Wednesday, lawyers for Krafton defended their client in their own letter to vice chancellor Will, saying nothing they did violated her order nor showed contempt: Papoutsis’s message was simply celebrating the UW employees’ efforts toward a past event: Krafton’s pre-Opinion determination that Subnautica 2 was ready for Early Access release. There was nothing improper about conveying the results of the milestone review or thanking the development team for their dedication and talent. They added that Gill could still make his own call about Subnautica 2’s release: In his role as CEO, Gill will be able to assess independently his views on the state of Subnautica 2 and the appropriate release schedule; nothing in Papoutsis’s message alters Gill’s authority or discretion. Vice chancellor Will has not responded to the letters and doesn’t necessarily have to. Both parties were previously ordered by Will to confer this week and submit a proposed judgment consistent with her ruling. The letter from Gill’s attorney’s this week doesn’t indicate whether he would or would not support a May release for Subnautica 2. But it could limit his options. And, if Gill’s lawyers are right, the lack of marketing fanfare around the leak of the May date could dull the launch of the game. Any harm to Subnautica 2’s launch is an extra sensitive issue given the context of the legal dispute: millions of dollars of payouts are on the line, tethered to the scale of the game’s initial performance. In her ruling on Monday, Will noted that there was obvious “bad blood” between Gill’s side and Krafton but that the two would need to work together: “They can—and must—act in good faith to navigate their remaining contractual relationship.” Item 2: A new kind of couch co-op game A highlight of GDC each year is the Alt.Ctrl showcase that features games played with extremely experimental controllers. Perusing this year’s offerings last Friday, I found a game controlled with giant scissors, another with big toothbrushes and one that amounted to dumpster diving. My favorite was Pivot, a co-op game about collectively maneuvering a couch. It was developed by students at the University of Utah’s masters of arts and engineering games program. Players lift and tilt the physical couch in order to control the position of a virtual one. That virtual one is moving through an obstacle course on-screen, while being pursued by a giant skull. Developer Nishant Verma told me at GDC that the couch is made of styrofoam (this became more evident as I watched!) and that the name was a riff on an episode of the sitcom Friends. Item 3: In brief… 🚫 Ubisoft is laying off more than 100 workers at its Red Storm studio, as the North Carolina location known for decades for its Tom Clancy games, ceases in-house game development, VGC reports. 👀 On Monday, Nvidia’s revealed its DLSS 5 AI-driven graphics technology that purports to improve game graphics… and it has been roasted about it by the media and the online gaming public for the remainder of the week. The tech changed the faces of characters in footage from Resident Evil Requiem, Hogwarts Legacy and EA Sports FC, drawing accusations of giving carefully art-directed games the generic look of AI “slop.” Nvidia CEO Jensen Huang had said on Monday that “DLSS 5 is the GPT moment for graphics—blending handcrafted rendering with generative AI to deliver a dramatic leap in visual realism while preserving the control artists need for creative expression.” By mid-week, Huang was telling Tom’s Hardware that the new tech’s critics were “completely wrong” because game-makers could still “fine-tune the generative AI” to suit their game’s aesthetics.
Nvidia CEO says disgusted gamers are wrong about its controversial AI tech
Amid a litany of memes and disses, CEO Jensen Huang tries to correct the public about Nvidia's DLSS 5 by clarifying what kind of generative AI it is.
Nvidia CEO says critics are "completely wrong" about DLSS 5 technology
Following concerns that upscaling feature detracts from creative expression, Jensen Huang says it "doesn't change artistic control"
Nvidia's Jensen Huang pitches tokens as recruitment strategy
Jensen Huang said engineers will soon be asking "how many tokens comes along with my job?" and is willing to pay them tokens worth half their salary.
NVIDIA CEO Jensen Huang says supply scarcity is "fantastic" for the company
Huang says scarce memory and wafers work in NVIDIA’s favor NVIDIA CEO Jensen Huang made an interesting comment this week during the Morgan Stanley
Virginia Science Olympiad at UMW Celebrates STEM Learning Across the Commonwealth
Eliora Teshome held her breath while her balsawood bridge was put to the test. The Lake Braddock Secondary School student from Burke, Virginia, had worked for months – in her school’s testing lab, during library hours and late at night – with fellow eighth-grader Rebecca Huang to build the miniature model into a winning weight-bearing […]
North Bay student promotes science and math at Santa Rosa science fair
Alyssa Huang’s project at upcoming science fair in Santa Rosa is all about building confidence.
North Bay student promotes science and math at Santa Rosa science fair
Alyssa Huang’s project at upcoming science fair in Santa Rosa is all about building confidence.
Software sell-off: What smart people are saying
Jensen Huang called the sell-off "the most illogical thing in the world." He's not the only one who has qualms with Wall Street's reaction.