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SCIENCE-LEMURS/
An indri sits in a tree on Sept. 29, 2018, in Madagascar's Maromizaha Forest.
Berkshire author Hannah Fries finds poetry in the science of trees
Hannah Fries explores the science and poetry of forests in “A Forest Language.” What tree word changes how you see the Berkshires?
What To Watch For: Wake Forest Demon Deacons
LOUISVILLE MUST AVOID NEGATIVE PLAYS Wake Forest comes into this game with 17 tackles for loss on the season, while UofL has given up 8 tackles for loss in each of their games against FBS competition. A strength for the Wake defense is a clear weakness for the Cards, but they will need to find […]
I On Politics
HUNDREDS ATTEND ADDABBO’S AUTUMN E-WASTE EVENT: State Senator Joseph P. Addabbo, Jr. hosted his free bi-annual electronic waste recycling event on October 4, 2026, at the Forest Park Bandshell Parking Lot. The Lower East Side Ecology Center collected electronic waste including new, outdated, and broken devices. A partnership with PaintCare allowed Addabbo’s Office to
I On Politics
ADDABBO CONCERT RE-SCHEDULED: Senator Joseph P. Addabbo Jr.’s Big Band Swing Concert, co-sponsored by Flor Cawley/State Farm, originally scheduled for Friday, September 25, was postponed due to forecasted rain and will now take place on Friday, October 2, 2026, at the Forest Park Bandshell. GREEK AMERICAN HOMEOWNERS ASSN MTG: The next General Meeting of
Biodome, future home to rainforest animals, takes shape at Greensboro Science Center
GREENSBORO, N.C. (WGHP) — The Greensboro Science Center is one step closer to welcoming new species like sloths, spider monkeys and clouded leopards. Construction on the Greensboro Biodome, which w…
How much is DeForest Buckner worth on the trade market?
DeForest Buckner is still one of the Colts’ best defensive players, but age and his contract complicate his trade value.
STHS Tahoe Science students clear 2,000 pounds of forest debris
SOUTH LAKE TAHOE, Calif. – Tahoe Science students at South Tahoe High School recently put on hard hats, picked up loppers, and put in the kind of work that makes […]
Does an Arnaud Kalimuendo Loan Move Make Sense for Olympiacos?
Arnaud Kalimuendo is struggling for playing time at Nottingham Forest, and a loan move to Olympiacos could make sense in January. The two clubs share ownership.
STAAR Surgical Appoints Andrew Pilon, OD, as Vice President of Business Development
LAKE FOREST, Calif.—STAAR Surgical Co. (NASDAQ: STAA), a leader in phakic intraocular lenses (IOLs) with its EVO family of Implantable Collamer Lenses (EVO ICL), has appointed Andrew Pilon, OD, as vice president of business development, which is a new position, the company told VMAIL. Dr. Pilon will report to Warren Foust, STAAR’s president and CEO, and work closely with the company’s senior leadership team to capitalize on opportunities that support STAAR’s innovation strategy and expand its product portfolio, according to the announcement from the company.
Wake Forest Stuns No. 16 Louisville in 30-27 Upset
The Wake Forest Demon Deacons pulled off one of the biggest upsets of the college football season Saturday, taking down No. 16 Louisville 30-27 on the road. Wake Forest entered the game looking to bounce back after a loss to No. 5 Miami, while Louisville came in riding a two-game winning streak. Instead, the Demon…
SCIENCE-LEMURS/
An indri sits in a tree on Sept. 29, 2018, in Madagascar's Maromizaha Forest.
Oliver Glasner Issues Injury Warning for Nottingham Forest
Nottingham Forest have been dealt a major injury blow ahead of their trip to Crystal Palace on Sunday.
Susan Collins turning mundane part of job into a reelection pitch
Susan Collins is relentless in promoting money she's steered to Maine — for community colleges and hospital expansions or hyperlocal examples like a program to control the spruce budworm, a threat to the state's forests and timber industry.
Plague is stoppable. The next health threat may not be.
The word plague is scary. Centuries ago, the Black Death killed tens of millions of people and changed the course of history. Plague still kills people around the world, and the word still evokes catastrophe. New fears of plague surfaced on October 2, when a lab worker in Irkutsk, Russia, died of pneumonia. Reports suggested that she may have contracted plague through a laboratory exposure. Understandably, people were alarmed. On October 7, the World Health Organization called for the Russian Federation to be transparent about what it knew. WHO issued an update on October 10. Russian authorities told WHO that testing did not identify plague and that investigations found no laboratory release. WHO said confidence in its risk assessment remained limited and that further clinical, epidemiological, and laboratory information was needed. The cause of the woman’s illness remains unknown, and WHO says a laboratory-associated exposure cannot be excluded. As I explained in a recent interview, this incident is very unlikely to lead to a pandemic. Plague is still active, including in the U.S., which sees a handful of cases each year. But it is a disease we can prevent and treat. Plague doesn’t spread readily, and it responds to antibiotics. The standard response—isolate the patient, trace contacts, and administer antibiotics and monitor for symptoms among contacts for seven days—works. We have even planned for antibiotic-resistant plague. At CDC, we developed a playbook for antibiotic-resistant plague and ran exercises on how to find and stop it. CDC guidance anticipates engineered resistance and recommends two different classes of antibiotics if there’s reason to suspect it. There is no evidence that resistance—or even confirmed plague—is involved in this incident. We have thought through how to address plague, but we’re not ready for the next major health threat that emerges from a lab or from animal spillover to humans. What should concern people is how little stands between the world and the next pathogen to get loose. Since peak COVID, epidemic preparedness has fallen off the political agenda, but the risk is greater than ever. More labs handle dangerous pathogens with more ways to make those pathogens deadlier, and more people live and work in close contact with animals. There are actions we can take now: We need better lab safety in every country. The number of labs that work with dangerous pathogens has increased worldwide over two decades, but there’s no enforceable international standard and no inspection regime; the Biological Weapons Convention, fifty years on, still has no verification mechanism. Labs that study dangerous germs need strong safety systems, training, and oversight. We need to reduce spillover events. Three in four emerging human infections start in animals, and there’s a lot we can do to reduce spillover risk, but the world is doing very little of it. Live-animal markets are one place to act. For instance, closing live-bird markets helped control H7N9 influenza in China. Reducing opportunities for people to encounter infected animals can prevent infections before they become outbreaks. In The Formula for Better Health, which is now out in paperback along with the hardcover, Kindle, and audiobook versions, I argue that labs do too many risky experiments with too many dangerous pathogens in too many institutions, and that every experiment should first answer one basic question: Is the likely benefit greater than the risk? Spillover risk can also be reduced: In the book, I discuss how Brazil cut its deforestation rate by 70% from 2004 to 2012 while increasing agricultural production and reducing risky contact between people and forest animals. We need faster detection and response. Delay costs lives. Strong surveillance, good labs, and trained responders can turn a single case into a small cluster of infections instead of an epidemic. Resolve to Save Lives has worked for nearly a decade to help countries find and stop outbreaks faster. The 7-1-7 target, which Resolve to Save Lives developed with partners in Uganda and elsewhere, provides a clear standard: detect within 7 days, notify within 1 day and complete all essential early response actions within 7 days. In Uganda’s Kasese district, for example, a review of a measles outbreak using 7-1-7 identified shortages of accessible funds, fuel, and vehicles that delayed the response. District leaders established funds they could access quickly. When, a few months later, the Crimean-Congo hemorrhagic fever appeared, the district detected it in three days, notified authorities in one, and mounted an effective response in two. Only one case was confirmed, and the patient survived. Because funds were available before the emergency, authorities were prepared and able to act. This kind of preparation can’t wait until the next crisis begins. Plague is an old disease we that know how to stop. The next threat may be harder to recognize, harder to treat, and easier to spread. Safer labs, less risk of spillover, and faster outbreak detection and response need sustained investment now, while we still have time to prevent the next emergency. Share
New Wellness Concierge tool supports campus mental health
Wake Forest faculty, staff and students now have a new tool to help increase access to mental health resources through Wayhaven’s Wellness Concierge. Developed by Christine Nicodemus (’15), the Wellness Concierge has been in a pilot phase since the summer and is now available [...]
SCIENCE-LEMURS/
An indri sits in a tree on Sept. 29, 2018, in Madagascar's Maromizaha Forest.
Packers Urged to Go After DeForest Buckner Amid Trade Rumors
The Packers should be looking to make some additions on defense.
Afternoon Explorations at Roper Mountain Science Center: Your Thursday & Friday Ticket to Dinosaurs, Stingrays, and the Rainforest (2026–2027)
Have you always wondered how you can visit Roper Mountain Science Center? Afternoon Explorations! From September to May, explore on select Thursdays and Fridays.
Crystal Palace 3-1 Nottingham Forest: Oliver Glasner's Selhurst Park return ends in defeat as Eagles complete remarkable comeback
Report and free match highlights as Crystal Palace come from behind to beat Oliver Glasners Nottingham Forest 3-1 in their first reunion since his summer exit; Dan Ndoye gave Forest the lead before goals from Daichi Kamada, Jefferson Lerma and Yeremy Pino completed a turnaround
Nottingham Forest Women Earn Comeback Draw at Southampton
Southampton Women 1-1 Nottingham Forest Women: Match report
The Next Pandemic Might Already Be Taking Shape at the Edge of the World’s Vanishing Forests
Outbreaks cluster where people, livestock, and damaged ecosystems collide, a new Nature study finds.
Summary of Business: FRA 2026 Joint National and Lake States Region Fall Meeting
FRA’s Joint National and Lake States Region Fall Meeting brought members and friends from across the country to Green Bay, WI, September 29 to October 1, for committee business…
25 best places to travel to in 2027
From national parks in Kenya to California's ancient redwood forests, these are the 25 places to add to your 2027 travel bucket list.
Opponent Breakdown: Wake Forest Offense
Wake Forest enters the second year of the Jake Dickert era with a 2-1 record and a clear identity built on their coach’s mentality. Dickert has his team playing with relentless belief that they can win any game, and that has shown up in each game this season. While last year surprised many, Dickert’s offense […]
Fall is full of ways to connect with nature, get creative, and recharge at Trailside Nature & Science Center
The Union County Board of County Commissioners invites residents to explore a variety of upcoming programs, including sound bowl meditation, acrylic painting workshops, forest bathing and tea cerem…
Ten bucks says you’ll love this community science project
Today marks the first day of Rut Watch 2026 With another season of Deer Spy in the books thanks to community scientists like you, biologists are now on a mission to pinpoint the peak of the white-tailed deer breeding season in Maine. Every observation of deer breeding behavior and sign helps define the timing of the rut, and this project uses the power of community science to collect deer data all fall long. Hunters, hikers, and wildlife watchers - Rut Watch pairs well with any outdoor adventure you have planned this season. It’s a perfect excuse to slow down and connect with nature as you look for clues. So get outside, rack up that deer data and submit rut reports from now through December 1. The online form is science made simple: Location Date and time Breeding behavior observed Submit a Rut Report What to watch for Active Breeding The most obvious breeding behavior to observe is a buck mounting a doe, but that is a rare sight as it only lasts a moment. You are more likely to witness a buck “tending” a doe, following closely, chasing, nuzzling, or pawing at her rump until she is receptive. Sparring After bucks shed their velvet, sparring helps sort out who is who in the dominance hierarchy. Early season matches are often less intense than later season matches between similar sized bucks. Most sparring is complete by the time breeding begins. Rubs Don’t just look for deer, pay attention to the trees. Rubs are marks made by bucks when they rub their antlers on trees, removing bark and leaving their scent calling card in the process. Scrapes Look to the forest floor for this sign of breeding season behavior. Scrapes consist of two parts - a licking branch, and a patch of cleared earth. Bucks break a low branch around head height, then paw at the leaves below to expose the dirt. Covered in scent, a scrape tells does and other bucks, “I’m here!” Learn More More information What’s next for deer community science: Northern Maine Wintering Deer Survey Other active community science projects: Fish Tag Reporting Maine Golden Eagle Study Maine Amphibian & Reptile Atlas Project Maine Deer Management: Maine’s Big Game Management Plan Game Species Conservation & Management Report The Benefits of Hunting: Supporting Wildlife, Conservation, and Community Subscribe Share Leave a comment
Sources: Gibbs-White eyes Nottingham Forest exit amid offers deluge
Football Insider exclusive as Nottingham Forest star Morgan Gibbs-White is in action, while owner Evangelos Marinakis watches from a circular inset.
SCIENCE-LEMURS/
An indri sits in a tree on Sept. 29, 2018, in Madagascar's Maromizaha Forest.
SCIENCE-LEMURS/
An indri sits in a tree on Sept. 29, 2018, in Madagascar's Maromizaha Forest.
Wake Forest-CINCIA researchers brief pope on Amazon mercury pollution
"We put more than a decade of Wake Forest and CINCIA-led scientific evidence on mercury contamination in the Amazon directly into the hands of the pope."
Wake Forest vs NC State Prediction: The Wolfpack Are Back
NC State bounced back from a nightmarish first few weeks with two big wins, but Wake Forest is the biggest test yet. Here's the CFN game preview and prediction.
Watershed Education Summit connects students with science & nature
High school students in bright orange vests and hard hats carried clipboards, buckets and ice cube trays into the forest to collect specimens from the Jones Fork Creek, near Wench
Arsenal is considering a move for Nottingham Forest star
Morgan Gibbs White remains one of the best midfielders in the Premier League and one of the most in form English players since the start of 2026. His performances have continued to attract attention, ...
Arsenal eye deal for teenager Mora
Arsenal eye deal for Mexico teenager Gilberto Mora, AC Milan in pole position for Endrick, Nottingham Forest braced for Murillo interest
Heat reduces photosynthesis in California redwoods
California redwoods reduce photosynthesis at high temperatures, which may affect their long-term survival and forests’ capacity to store atmospheric carbon.
Arsenal get controversial referee for Nottingham Forest trip
Michael Oliver is back on Premier League duty this weekend, with the referee handed Arsenal’s trip to Nottingham Forest for his first Gunners involvement of the season.Arsenal visit the City Ground ...
Striker Noonan agrees to join Forest
Michael Noonan will join Nottingham Forest on 1 January next year.
College football on TV today: Sept. 26
Let’s have a day. Saturday, Sept. 26No. 1 Texas at No. 14 Tennessee | 12 p.m. | ABCIllinois at No. 7 Ohio State | 12 p.m. | FOXSam Houston at No. 11 Texas Tech | 12 p.m. | TNTWake Forest at No. 16 Louisville | 12 p.m. | ESPNColorado at Baylor | 12 p.m. | […]
Florida Gators get new bowl destination in SI's latest projections
Sports Illustrated projects Florida to face Wake Forest in the Gator Bowl following UF's upset win over Texas in Week 7.
Stunned scientists discover new wild cat species after a century—see the photos - Futura-Sciences
A Mysterious Cat in the Clouds High in the Andean forests—almost always wrapped in mist—a pint-sized cat was living its life unnoticed by the scientific community, although locals might have crossed its path many times. The story kicked off in 2016, when a Bolivian animal shelter contacted biologist Paola Nogales-Ascarrunz...
Five Premier League home games back on sale next week
City’s Premier League home clashes with Spurs, Nottingham Forest, Arsenal, Newcastle United and Everton will all go back on sale on Friday 16 October. Club News Make a Night of It: Champions League ...
Catching the Light: Taking the Pulse of Puerto Rico’s Forests
Our team from NASA Goddard Space Flight Center’s Biospheric Sciences Laboratory is working to improve how satellites monitor plant health.
Autumn Paints Poland’s Bieszczady Mountains
Fall color covers the forested slopes of Bieszczady National Park, while patches of polonina, a type of high-mountain meadow, have turned tan.
Forest Green allow Savage to talk to another club
Forest Green give manager Robbie Savage permission to speak to another club, amid speculation linking him to Peterborough United.
Forest landscapes and birdsong soundscapes have independent physical health benefits
A new study finds that exposure to birdsong soundscapes or forest landscapes reduces physiological stress. These findings of physical health effects complement previous research showing mental health ...
What will be classed as a successful season under Glasner?
Will: What do you think represents success for Glasner this season? If we trend as we are into Christmas, do you think the owner will look to replace him, or will Glasner be given the full season regardless, assuming we're not close to relegation? Nick: After last season, Forest desperately need stability, and it would be a huge surprise to see the manager leave, unless it is an irretrievable situation.
I visited Iguazú Falls at night. It was better than I imagined.
I took a nighttime tour of Argentina's Iguazú Falls during a full moon. Walking through the rainforest in darkness made the experience unforgettable.
NFL fans question officiating after Mahomes call
Ringo Chiu/Shutterstock.com Mahomes penalty sparks debate over NFL officiating NFL fans are debating a roughing-the-passer call involving Patrick Mahomes and Dolphins linebacker Chop Robinson. The penalty came during Kansas City’s 24-10 win over Miami and sparked questions about how quarterbacks are protected. A similar-looking play involving Indianapolis Colts defensive tackle DeForest Buckner and Washington rookie…
Why Smithsonian scientists flood an Anne Arundel forest every summer
On a large campus in Edgewater, scientists at the Smithsonian Environmental Research Center flood a forest every summer to learn about climate change. It's just one of the large-scale experiments conducted at the institution which has, so far, escaped some of the scrutiny and critique that Donald Trump has lobbied at the rest of the Smithsonian.
Launching the search for our next dean of the School of Business
This message is shared on behalf of President Peter Rodriguez. Dear Wake Forest colleagues, Today, we begin a national search for the next dean of the Wake Forest University School of Business. The School of Business plays a vital role in our University’s overall mission [...]
SCIENCE-LEMURS/
An indri sits in a tree on Sept. 29, 2018, in Madagascar's Maromizaha Forest.
Friday, September 25th: Wake Forest Mental Wellness Fair, Launch Family Entertainment, One Hit Wonder Day
Join Trent and Brea for a fantastic Friday show filled with area businesses and fun events.
A forgotten 30-year forest experiment just delivered a huge surprise
A 30-year forestry experiment in Australia found that heavily thinned mountain ash forests grew unusually large trees while recovering enough carbon to match or exceed untouched areas. The results suggest carefully managed thinning could support timber production, wildlife habitat, and carbon storage at the same time.
Science Snapshots: October 4, 2026
Three new science finds: forest fragmentation alters temperatures, black-hole jets illuminate pre-existing gas, and butterfly wing patterns confuse predators.
Climate System Warning: The Hidden "Multiplier" Discovery That Has Scientists Deeply Worried - Futura-Sciences
The Unseen Threat: Nature’s Own Greenhouse Gas Emissions For years, the scientific consensus has been clear: today’s climate change is driven first and foremost by massive deforestation and, above all, greenhouse gas emissions from human activities. According to the latest report by the Intergovernmental Panel on Climate Change (IPCC), this...
Meet the former MMA fighter building his business in Prince William County
Ever the family man, Woodbridge resident and small business owner Elder Ramos, 42, attended Forest Park High School and now runs HaiJoe Stamped Concrete Patios & Decks. The company fell under the purview of the “Haijoe Property” rezoning that came before the board Sept. 1.
SBTN Releases New Framework for Corporate Science-Based Nature Target Setting
The Science Based Targets Network (SBTN) announced today the release of Science-Based Targets for Nature 2.0, marking a major update of its methods and guidance for corporate nature-focused sustainability target setting and implementation across areas including land, freshwater and oceans. The new release follows the SBTN’s inaugural corporate science-based targets for nature, launched in 2023, […]
Colts announce firing of general manager Chris Ballard after loss to Titans, DeForest Buckner criticism
Chris Ballard is out after nearly a decade as the Colts' general manager.
Dale Vince’s latest idea: No manager at Forest Green Rovers
Dale Vince, the owner of Forest Green Rovers, has said there is no manager vacancy at the club following Robbie Savage’s departure, but if there were he would not recruit a “big ego”.
North Carolina Could Play a Key Role in This Year’s Midterm Elections, Wake Forest Expert Says
Scientists clone Southern Africa’s wild fruit trees as forests disappear
Plant geneticist Alice Muchugi recalls meeting a group of furious fruit sellers on the side of a dusty road not far from Zimbabwe’s capital, Harare, in 2024. They told her that a group of men armed with chainsaws had felled some of the district’s most prolific fruit trees, robbing the women of a steady source […]
Scientists discover 'D-rex', a giant fungus from Chinese forests whose unique lineage dates back 65 million years
Deep in the forests of Yunnan, China, scientists have discovered a "fungal giant" that challenges our understanding of how large fungi can become. The newly described species, Dianjunus rex, produces ...
Fires Arrive in the Amazon Rainforest
During El Niño, a cascade of fires across the tropics begins in equatorial Asia and continues in the central and eastern Amazon.
Brave of Lampard to start Thomas-Asante
Former Coventry City goalkeeper Steve Ogrizovic says it was "brave" to play Brandon Thomas-Asante as the number nine on Saturday against Nottingham Forest - but it was a decision that paid off for manager Frank Lampard. Ghana striker Thomas-Asante got the nod ahead of Ellis Simms and summer signing Sidiki Cherif as Lampard opted to shake-up his attacking line-up. Thomas-Asante was supported by wingers Ephron Mason-Clark and Jack Rudoni, with the trio's regular interchanging of positions leaving Forest players wondering who to mark.
Bears Receive New Trade Take on Colts DT DeForest Buckner
Harrison Graham of Chat Sports believe the Bears should look to make a trade for Colts defensive tackle DeForest Buckner. The post Bears Receive New Trade Take on Colts DT DeForest Buckner appeared first on HEAVY.
Focus, calm and flow: The science behind relaxation
The vagus nerve connects the brain to the organs. Stimulating it can be beneficial - but some social media hacks lack science to back them up. Plus: Forest or city walk — which is more relaxing?
2026 Western & Southcentral Region Fall Meetings: A Summary of Business
FRA 2026 Western Region Fall Meeting September 16–18, 2026 | Eagle Crest Resort, Redmond, Oregon The Forest Resources Association Western Region gathered September 16–18 at Eagle Crest Resort in…
Brazil investigates Amazon wildfires that disrupt daily life and have fueled political attacks
SAO PAULO (AP) — Brazilian authorities are investigating whether a recent surge in wildfires in the Amazon rainforest have been set on purpose for political motives ahead of the second round of presidential elections later this month.
Drake's Bucksbaum business lecture to feature journalists on AI
Drake University will hold its fourth annual Bucksbaum Lectureship in Business on Oct. 21 featuring journalists Karen Hao and Nicholas Thompson speaking how artificial intelligence has evolved and how it will shape America’s future. The event is at 7 p.m. Knapp Center, 2601 Forest Ave. in Des Moines and is open to the public. The event…
SCIENCE-LEMURS/
An indri sits in a tree on Sept. 29, 2018, in Madagascar's Maromizaha Forest.
Carlo Ancelotti Labels Jair Cunha a 'Positive Surprise' for Brazil
Jair Cunha has taken another leap, and was praised by Brazil boss Carlo Ancelotti after his first involvements for the senior Brazil squad.
Forest Vindication Does not Make Man City Verdict a Victory
Nottingham Forest may feel vindicated after Manchester City's guilty verdicts, but there are no winners from the Premier League's worst-ever scandal.
Gorgeous Lost Bird Species The Ghana Cuckooshrike Rediscovered In Forests Of The Cote d'Ivoire
The bird had not been seen in over 13 years.
Business priorities for mobilising and scaling finance for biodiversity - ICC
COP17 provides a window to turn global biodiversity finance commitments into investment at scale. With at least US$200 billion a year needed for biodiversity by 2030, this ICC policy paper sets out the frameworks, financing solutions and market conditions needed to reduce investment risks and channel capital towards measurable outcomes for nature.
Learning the language of trees with the Orlando Science Center
The science of it: We're heading to the rainforest to dive deep into the communication of trees.
County preserves to host activities at Ryan Woods
The Forest Preserves of Cook County will host the following events at the Dan Ryan Woods, 87th Street and South Western Avenue.
Scientists Solve a Decades-Old Stick Insect Mystery
The discoveries could help manage stick insect outbreaks and reduce their impact on forestry and agriculture. Australia’s coastal landscapes are home to large stick insects belonging to the genus Anchiale, a group of closely related species. For decades, scientists and nature enthusiasts have documented them, uploading more than a thousand observations to databases like iNaturalist
A ‘devil-like’ flower from Thailand is new to science
Botanists in Thailand have identified a new-to-science species of “fairy lantern” — plants that live almost entirely buried under leaf litter, emerging aboveground only occasionally to flower. Researchers were surveying evergreen forests in the mountains of Thong Pha Phum National Park when they chanced upon a plant none of them had ever seen before, at […]
Mangrove restoration is becoming big business, but benefits don't always reach local people
On Pakistan's Indus delta coast, a 350,000-hectare (865,000-acre) mangrove project is turning a growing forest into something that can be sold to companies thousands of miles away: carbon credits.
The science behind ‘fairy rings’: Why mushrooms grow in circles
Folklore once blamed dancing fairies for rings of mushrooms appearing in fields and forests; a new Swedish study suggests fungi spread outward to escape temporarily unfavorable conditions underground
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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