SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " electrical " 100 found 🔀 AI-powered Shuffle
Sign in to save shuffle history.
Boniakowski: Electrical supply business buys Princeton commercial buildings for $1.9 million
An electrical supply company has acquired two adjacent buildings in Princeton for a combined $1.9 million, in a set of deals arranged by The Boniakowski Commercial Real Estate Group.
Fire damages multiple Branford businesses
A fire has damaged multiple businesses in Branford. Firefighters were called to the 200 block of East Main Street around 12:45 a.m. for a report of wires down. When crews arrived, they said they found primary electrical wires down and actively arcing in the road. They said they also saw smoke and fire coming from the side of the building…
DOJ’s Recent Small Business Administration FCA Settlement Highlights Risks for Contractors
A recent $21.3 million False Claims Act (FCA) settlement with an electrical contractor and its subsidiary highlights the U.S. Department of Justice’s (DOJ) focus on U.S. Small Business Administration (SBA) set-aside programs and scrutiny of whether companies improperly represent themselves as qualifying small businesses or—importantly for larger businesses—improperly represent their use of qualifying small businesses to secure federal contracts.
Pharr Global Business Hub Expands Workforce Training With Skills-to-Certification Program
The Pharr Global Business Hub is expanding workforce development efforts through a “Skills to Certification” program offering training in blueprint reading, estimating, workplace safety and preparation for the electrical journeyman examination.
The “impossible” LED that could change everything
Scientists at the University of Cambridge have achieved what was once considered impossible by electrically powering insulating nanoparticles to create a completely new kind of LED. Using tiny organic “molecular antennas,” the team found a way to funnel energy into materials that normally cannot conduct electricity, producing ultra pure near infrared light with remarkable efficiency.
AI data center boom drives $3.2 billion Chicago-area deal
Atkore, an electrical-products manufacturer based in Harvey, has decided to sell the company for $3.2 billion to Prysmian, a top maker of cables used in data centers.
Electrical Manufacturers See Stronger Business Conditions
Survey respondents cite stronger activity despite inflation and policy uncertainty
BUSINESS UPDATE: A 138-year-old New York Manufacturer Gets Another Life in Fulton
E.J. Willis Co. was founded in New York City in 1888 and for generations it has made ship’s bells and other equipment for the U.S. Navy and American shipbuilders. This summer, the new owner moved the company’s equipment to Fulton By Stefan Yablonski E. J. Willis Co. cast brass ship’s bells — handcrafted in the United States since 1888. Ship bells, “built to last a lifetime at sea,” are now manufactured in Fulton. E.J. Willis Co. has moved its operation and manufacturing business to Fulton. They are currently operating out of N.E.T & Die. The company is now under the ownership of Jonathan Hyatt. He recently acquired the company after seeing a for sale note on Craigslist. [caption id=attachment_11110 align=alignright width=400] Entrepreneur Jonathan Hyatt is the new owner of E.J. Willis Co. He bought the business this summer after finding a listing on Craigslist by chance.[/caption] “I had been looking for something to do. I had been 20 years in corporate America and I was just tired of building someone else’s empire, you know what I mean? I was in consulting, pretty much a jack of all trades. I wanted to do something that I could call my own,” he explained. “I’d been on this path of trying to find a business to buy for about a year. One night I am on Craigslist about 11:30 in mid-April searching for something completely unrelated. At the bottom of Craigslist was a ‘things you might be interested in from outside of your area.’ There was an ad that said 138-year-old bell manufacturing company for sale. So, I clicked; why not, right? I wasn’t looking to buy a manufacturing company, but I went down the rabbit hole, absolutely fell in love with the history and ended up buying it.” He read the ad and responded. “I called and I am talking to the owner of the business for about two hours. We ended with, let’s have another chat and then come on out here and have a look. I figured, well I might wind up getting kidnapped and getting murdered or there is a real business here. But I gotta see it through,” he quipped. “And sure enough, there is a big machine shop operation there. The gentleman who owned it was retiring and in the corner of this shop is a little room where they make bells and they have been doing this ever since the company had started.” That’s the one constant thing that has survived the changes of the business. [caption id=attachment_11061 align=alignright width=300] Sales 1929 general catalog published by E. J. Willis Co, listing all the merchandise it sold. It’s like the Sears Roebuck and Co. catalog for marine parts.[/caption] “I drove home and told my wife, ‘This is what I am doing for the rest of whatever we are calling this — mid-life crisis.’ And she said, ‘absolutely you got to do it.’ I took out a loan and off we go.” He put in an offer on the business and they closed on July 1. He didn’t disclose what he paid for the company. “In terms of price, the seller and I have agreed to keep those terms private.” “I am finding that I am a business owner, an archeologist, opening files and cabinets that haven’t been opened in 100 years. It’s just amazing, just cool things that I am finding,” he said. “I want to build the business back. I want to be able to sell the bells to outsiders. I think they are beautiful. “It’s really a wild story about a company that started in lower Manhattan, exploded in the automotive space, sold parts to the Wright Brothers, moved into the aeronautical world and then landed in marine. The cool thing, I have been digging around and the gentleman who owned the company prior to me was not a digital guy. There is nothing out there. “Now I am sitting here with all the art from like the 1930s, the E.J. Willis boat catalog it’s like 250 pages of things this company used to make. It’s like the Sears-Roebuck and Co. catalog for marine parts. We are modernizing, we are staying true to the heritage of the business. It’s exciting to be the next steward of the whole business.” Initially he thought he’d move everything from the company’s plant in Middleville, Herkimer County, to Boston, out of convenience. “Then I thought let’s keep the foundry where it is. Let’s not move anything right away,” he said. “I want to get a good sense of what we’ve got, what works and what doesn’t. “I went to the foundry and met with the people there, lovely people, and said here is my position — I am buying a company where everyone is retiring. There is machining and polishing to be done, who would you work with around here? Without hesitation they said, ‘you need to go to NET Tool & Die and talk to Michelle [Shatrau]. She is a third-generation machinist and she runs the company now.’” So, he drove to Fulton. “I knocked on the door, they let me in. And she said, ‘how’d you get in here?’” he said with a laugh. “We became fast friends. I told her what I am doing. It must have struck a nerve. She has a very entrepreneurial background. I must have said something right because she came out and she said, ‘I’d love to help you. Why don’t we move the equipment that you have into my large building and I will give you a space to work at and use my team?’” [caption id=attachment_11058 align=alignleft width=300] Bell in progress awaiting assembly[/caption] It’s a great relationship so far. “We are bringing the business into the modern world. It’s been a lot of stuff all at once. But it has been very exciting,” he said. “We moved in a month ago [in July]. We closed on the business July 1. We moved a couple weeks later. We had all our equipment set up, electrical being run, everything. [caption id=attachment_11059 align=alignright width=300] Bell attached to a lathe going through the machining process[/caption] “We’re working with NET Tool & Die to rebuild production and preserve manufacturing processes that, in some cases, existed mostly in the heads and hands of the people who had been doing them for decades. We’re currently working on several 200-pound ship’s bells and bringing an old two-way manual bilge pump back into production.” He said he will be working with NET employees for the time being, adding, “I’d love to get to a point where I have so much growth that I need to hire people.” No one wakes up and says, ‘I am buying a bell today,’ Hyatt admitted. [caption id=attachment_11060 align=alignleft width=225] Bell after receiving a custom etching toward the bell mouth[/caption] “Everyone does wake up and has things that deserve acknowledgment and remembering — a promotion, a marriage, the birth of a child,” he said. “These are the things I feel like if there was something that could capture a particular moment in time and will literally outlast the person that bought it, a bell is that. We can engrave a bell if you get married or the birth of a child. We can put anything on a bell. “I have orders, yes. I am working on several orders right now. We have a little bit of busyness. But there are still some things to work out. I want to make things consistently and continue to move forward.”
Scientists just overturned a century-old physics assumption
Scientists at Carnegie Mellon University have discovered an unexpected form of the Hall effect, overturning the long-held assumption that this electrical response only appears when a magnetic field points perpendicular to a material. Beyond expanding a century-old principle of physics, the finding could eventually lead to simpler magnetic sensors for electronics, transportation, and medical technologies.
Astronomers finally solve Saturn’s decades-long spin mystery
A decades-old mystery about Saturn has finally been solved thanks to the James Webb Space Telescope. Scientists discovered that Saturn’s changing “rotation rate” was never caused by the planet speeding up or slowing down, but by powerful winds high in its atmosphere. Webb’s unprecedented observations revealed that Saturn’s northern lights actively heat the atmosphere, creating winds that generate electrical currents, which then power the aurora all over again in a self-sustaining cycle.
UL Solutions Inc. Broadens Portfolio with Agreement to Acquire Eurofins Scientific's Electrical & Electronics Business1
UL Solutions Inc. (NYSE: ULS), a global leader in applied safety science, today announced it has entered into a definitive agreement to acquire the electrica...
Business sentiment surges in Germany's electrical industry
Business sentiment in Germany's electrical industry has surged to its highest level in years, the Munich-based ifo Institute said on Thursday. The sector's business climate index rose by 8.
Heard on Campus: Tanya Berger-Wolf on AI for nature
Tanya Berger-Wolf, professor of computer science engineering; of electrical and computer engineering; and of evolution, ecology and organismal biology at Ohio State University, gave a lecture titled “AI for Nature: From Science to Action" as part of the Distinguished Lectures in Life Sciences series presented by the Huck Institutes of the Life Sciences.
Forget LASIK: Safer, cheaper vision correction without lasers or surgery
Researchers are developing a futuristic alternative to LASIK that reshapes the eye without lasers or incisions. Using mild electrical pulses and platinum contact lenses, they temporarily soften the cornea so it can be molded into a new shape. Early tests on rabbit eyes successfully corrected nearsightedness in about a minute while preserving the eye’s structure.
Fire breaks out at Long Beach electrical business
Owner Henry Schepens said he received a call informing him the building on Beatline Road was on fire.
UToledo To Celebrate Expansion of Health Science Campus Solar Array
The expansion increases the array’s nameplate capacity from 330 to 750 kilowatts, more than doubling its expected annual electrical production.
The National Academy of Sciences Elects Two Berkeley Lab Researchers
Two Lawrence Berkeley National Laboratory (Berkeley Lab) scientists have been elected to the National Academy of Sciences (NAS) in recognition of their distinguished and continuing achievements in original research. They are part of a cohort of 120 new members and 25 international members. The National Academy of Sciences is a private, nonprofit institution that was established under a congressional charter signed by President Abraham Lincoln in 1863. It recognizes achievement in science by election to membership, and — alongside the National Academy of Engineering and the National Academy of Medicine — provides science, engineering, and health policy advice to the federal government and other organizations. The 2026 electees bring the total number of active members to 2,705 with 557 international members. Gary Karpen is a biologist senior faculty scientist in Berkeley Lab’s Biological Systems and Engineering Division and a Professor of Cell and Developmental Physiology in the Department of Molecular and Cell Biology at UC Berkeley. Karpen studies how the structure, organization, and maintenance of genetic material impact inheritance and cell function. His lab focuses on chromatin — a packaged form of DNA strands wrapped around proteins that comprises our chromosomes — with a particular emphasis on centromeres, rarely expressed sequences called heterochromatin, DNA repair, and regulatory RNAs. His research reveals insights into fundamental aspects of nuclear organization and genome regulation that are shared across the tree of life, broadening our understanding of cancer and other diseases, birth defects, and aging. Kam-Biu Luk is a Professor Emeritus of physics at UC Berkeley and a retired senior faculty scientist in Berkeley Lab’s Physics Division. He is an experimental particle physicist whose research has focused on neutrinos: nearly massless, electrically neutral elementary particles that can pass through matter virtually undetected. Neutrinos are created during radioactive decay processes, including the fusion process occurring in stars and the fission process that powers nuclear reactors. Luk initiated and co-led the Daya Bay Reactor Neutrino Experiment, a project based in China with more than 200 international collaborators. In 2012, the Daya Bay experiment discovered a new form of a phenomenon called “neutrino oscillation” in which neutrinos change from one type to another. For this discovery, Luk and his collaborator Yifan Wang received the 2014 American Physical Society Division of Particles and Fields W.K.H. Panofsky Prize for outstanding work in experimental particle physics, and he was also the co-recipient of the 2016 Breakthrough Prize. Luk is currently participating in the Deep Underground Neutrino Experiment (DUNE) hosted by Fermi National Accelerator Laboratory, which will investigate any potential difference in behavior between neutrinos and antineutrinos that may shed light on the evolution of the universe, especially why antimatter is absent in the present universe. ### Lawrence Berkeley National Laboratory (Berkeley Lab) is committed to groundbreaking research focused on discovery science and solutions for abundant and reliable energy supplies. The lab’s expertise spans materials, chemistry, physics, biology, earth and environmental science, mathematics, and computing. Researchers from around the world rely on the lab’s world-class scientific facilities for their own pioneering research. Founded in 1931 on the belief that the biggest problems are best addressed by teams, Berkeley Lab and its scientists have been recognized with 17 Nobel Prizes. Berkeley Lab is a multiprogram national laboratory managed by the University of California for the U.S. Department of Energy’s Office of Science. DOE’s Office of Science is the single largest supporter of basic research in the physical sciences in the United States, and is working to address some of the most pressing challenges of our time. For more information, please visit energy.gov/science.
Scientists Watched Two DNA Double Helices ‘Zip’ Together for the First Time
Metal ions may help DNA molecules overcome their mutual electrical repulsion.
National Science Foundation honors KU Engineering professor for protecting public trust in global supply chains
Sumaiya Shomaji, assistant professor of electrical engineering & computer science, received an NSF CAREER award.
Four ECEE students earn major National Science Foundation research fellowships
Four students from the Department of Electrical, Computer & Energy Engineering at CU Boulder have been recognized with 2026 National Science Foundation Graduate Research Fellowship Program awards. NSF GRFP recognizes and support outstanding grad students from across the country in science, technology, engineering and mathematics (STEM) fields who are pursuing research-based master’s or doctoral degrees.Awardees receive a $37,000 annual stipend and cost of education allowance for the next three years as well as professional development opportunities.Learn more about their research below
Incredible new material makes heat programmable
A newly developed material can control and "program" heat, allowing it to direct thermal radiation, switch modes, and remember its settings without continuous power. The innovation could lead to smarter infrared sensors, better energy technologies, and memory devices that use light and heat instead of electrical charges.
New Orleans’ Section 8 housing has ‘life-threatening’ problems, HUD inspector finds
New Orleans' public housing authority failed last year to fix electrical hazards, inoperable windows, and other life-threatening problems in its subsidized apartments, federal regulators said.
'Risk of electrical shock' prompts recall of imaging systems
A handful of fluoroscopy units manufactured by GE HealthCare are the subject of a new recall by the U.S. Food and Drug Administration.
Downtown Tallahassee business expects slower day after nearby underground electrical fire
Metro Deli is located just two blocks from where Tallahassee city officials said the fire-related incident unfolded and left damage on Monroe Street Tuesday morning.
Scientists discover a quantum effect that could eliminate batteries
Researchers have discovered how microscopic imperfections and atomic vibrations can be used to control a powerful quantum effect in an advanced material. The effect can turn alternating electrical signals from the environment directly into the kind of current electronic devices need, without traditional components. As temperature changes, the signal can even flip direction, giving scientists a new way to tune device performance.
The Family Business Advantage: Third Quarterly Power Breakfast of 2026 explores how family businesses balance legacy and innovation
Photo by GFBJAnother successful Power Breakfast is in the books. The Greater Fayetteville Business Journal hosted its third quarterly Power Breakfast of 2026 on Tuesday, Sept. 29. Local leaders and decision-makers gathered to network and learn from the panel about how established principles drive long-term stability while allowing for operational evolution. The panel featured Managing Partner of Luigi’s Italian Chophouse & Bar, Nate Ernst; Inside Sales at Hubbard Supplyhouse, Mary Grace Hurley; Chief Operations Officer for Copiers Plus, Drew Smith; and CEO of Holmes Security Systems, Stephen Wheeler. The panel was moderated by Lauren Willets, director of the Family Enterprise Center at UNC’s Kenan-Flagler Business School. Throughout the discussion, the panelists returned to a common idea: family businesses thrive when they preserve the relationships and values at their core while remaining open to change.Each panelist shared personal stories that carried practical lessons. Stephen Wheeler emphasized the role of relationships with customers and employees, saying, “What makes a family business successful today is relationships.” Mary Grace Hurley echoed Wheeler’s sentiment, describing relationships as a lasting inheritance, including a customer connection that began when she was young and continued into her working life. “If something’s given to you, that’s going to cost you too,” added Nate Ernst. He explained this philosophy by sharing that, in his view, earning responsibility builds credibility and confidence.Another hot topic was the idea of tradition versus change. For these businesses that have been around for a century or even more, it can be difficult to escape the “we’ve always done it this way” caveat, but these speakers emphasized how change has been an integral part of their growth and longevity. A family business can honor its history without being bound by it.“Innovation and tradition–they don’t have to be competing with one another,” shared Hurley. She pointed to changes in how businesses operate, including the adoption of computers and new management practices. Ernst stressed that adaptation is essential, while Wheeler described how his family’s electrical contracting business had evolved into a security-focused company. The details of the work may change, but identifying and upholding core values is key to embracing change while maintaining the character of a business. “I think it’s just important to remember why you started in the first place. What was your mission? What are your core values? And to reevaluate those,” shared Drew Smith.In addition to the first-hand accounts and wisdom shared by panelists, Moderator Lauren Willets recommended two novels during the panel for those seeking additional educational resources. Those two novels are “Hug of War: How to Lead a Family Business with both Love and Logic”by Cathy Carroll and “In the Company of Family: How to Thrive When Business Is Personal” by Melissa Mitchell-Blitch. Preparing the next generation requires more than handing over a title or company. Wheeler argued that future leaders need genuine passion and a vested interest in the business. The panelists were in agreement that succession is a process, and there is not one clear answer for how to perfectly prepare for it. Leaders must cultivate readiness, keep communication open and make room for the next generation to earn responsibility while being sure not to neglect the business in the here and now. “Today’s Power Breakfast was one of our best events yet! Between the passion and in-depth knowledge of the panelists, the great audience questions and the guidance and expertise of Mrs. Willets, the conversation was both engaging and informative,” shared GFBJ Publisher Faith Hatton. “A lot of small businesses in Fayetteville are family-owned and grown, and it’s great to be able to spotlight some of the businesses that have stood the test of time by strengthening the next generation of leadership and preparing them for ownership. I hope everyone received some inspiration and ideas that they can bring back to their own businesses and organizations!”We thank everyone who attended this Power Breakfast and hope you’ll all join us for the next Power Breakfast on Dec. 8. Details about the event will be shared on our social media and in future email updates. To learn about becoming a Power Breakfast sponsor, contact the Greater Fayetteville Business Journal at 910.240.9697 or marketing@bizfayetteville.com.
New Business Licenses: 8.14.26
Chesterfield reports licenses for electrical services, a convenience store, a clothing retailer and more. (BizSense Pro required)
Electrical fire forces Buckhead business evacuation
Crews battled an electrical fire at a business in Buckhead late Tuesday night, forcing an evacuation and temporarily shutting down a busy roadway.
Porsche Patents Racing Stripes That Appear When You Switch Into Sport Mode
Using an electrical current to change the outward appearance of certain body panels, this Porsche tech could make racing stripes appear on command.
Gratitude and honor
Louis Campos, who works in the facilities electrical department, installs new ground lights on the Northeastern Veterans Memorial in preparation for the upcoming Veterans Day ceremony on the Boston campus.
Art that serves others: How a Harnett County muralist is making a lasting mark in her community
Van Goat Studios, which has been operating since 2019, has allowed Johnson to express herself and reflect the spirit of local communities through murals. Photo provided by Elyse Johnson.Elyse Johnson of Van Goat Studios in Dunn wants to spread her artistry and make a lasting mark in her community. Van Goat, which has been operating since 2019, has allowed Johnson to express herself through murals and decorating electrical boxes in the urban landscapes of North Carolina. On top of traditional mural painting, Johnson offers what she calls “portable murals,” an option tailor-made for structure owners who do not want to commit to a design for their wall.“A contractor builds a framed piece of wood, and then they can frame the ‘mural’ onto the wood, whether it’s into their building, whether it’s interior or exterior,” Johnson said. The beginnings of Johnson’s journey into establishing Van Goat Studios reflect the teachings she wants artists to take away today: everything is a learning opportunity. When she started Van Goat, she shared it was a joint venture with a business partner. “I mainly did that because I didn’t feel like I was ready to go and do this on my own,” Johnson said. Her business partner eventually dropped out of the project, deciding she wanted to pursue other forms of art. That is when Johnson was thrust into growing her business on her own during and in the aftermath of the COVID-19 pandemic. “I had built up my confidence enough to go out and reach new heights,” she said. “And I was probably one of the few that benefited from COVID.”The moment presented a silver lining for Johnson. One of her first projects was a Farmers Day mural for the town of Coats. “When COVID-19 hit, Coats was not able to hold their annual festival, so they had a little bit of savings. They decided they wanted to do something for their community without getting anyone sick,” Johnson said.From there, word of mouth spread. Now, Johnson has an organic way of approaching projects. “Like a lot of muralists, if I feel inspired by a building, I will just go up and talk to that building owner and tell them a mural is something they should consider,” Johnson said. But above all, Johnson says she wants art to be accessible to everyone. Johnson said she is trying to stick to projects that benefit “the little guys.” “I’m not trying to go for a project in downtown Raleigh to get the eight-foot-tall building,” Johnson said. “I’m not trying to go to those major cities and get those huge buildings for two reasons: one, I don’t want to go that high; two, my passion really lies with the small guys.” But due to financial constraints and the material reality of art commerce, that requires open communication, she added. “I don’t want to just snowball you with this huge price, and then you just shut me down because it wasn’t what you were thinking,” Johnson said. “At the same time, I am an advocate for the arts, so I’m not going to give you a $10,000 mural when you’re only going to pay $5,000.” There is a healthy balance in explaining the artistic process and working with clients and the surrounding community, Johnson said.“Your municipality invested this, and this is why they invested this, and this is how it’s going to help and improve your community,” she noted. “Same thing when I’m talking to a small business. You asked for me to come at you with this that is outside your budget. How do we make this still your same exact goal, but within your budget lines?” Johnson also provides lessons to aspiring artists. She does so with a mission: how do you master the balance between being a great artist and a competent business owner? “We still do art lessons, but I’m also going to give you business scenarios,” she noted.One of the scenarios she has come up with for her students is a T-shirt competition. “The kids have to think about ‘okay, I can’t just draw whatever I want on a T-shirt. I need to think about what colors Miss Elyse likes. What does Miss Elyse’s logo look like? What would Miss Elyse like?’” Johnson said. “So the design needs to be around that kind of concept.” As Johnson looks toward the future of Van Goat Studios, she is thinking of time, longevity and succession. Johnson is a new mom, which she said has shaped how she sees the future of the studio.“I still want my name and my business out there continuing, so that when my daughter is of age and she can be more independent, then I can be out there doing more and more,” Johnson said. “I would love to get a student to pass this on to, or an intern. I would love for this business to be passed on to the next generation and let them go.”
Scientists just pushed superconductors beyond their usual current limit
Ultrashort electrical pulses allowed scientists to push superconductors closer than ever to the point where their electron pairs actually break apart. The method revealed hidden differences between superconducting materials and could open new ways to probe and control their quantum behavior.
BUSINESS MONDAY: Spotlight on Henry's Electric in Lee
The family operation, celebrating its 80th anniversary, offers appliance sales, service, and electrical contracting.
Office of Economic Development continues to provide small business energy efficiency grants
“Reducing energy use benefits individual businesses and strengthens our community as a whole as we reduce our reliance on the electrical grid,” said Kauaʻi County Office of Economic Development Director Nalani Bru.
Scientists built implants that talk to each other through body tissue
It's possible to send electrical signals right through human tissues.
Fire breaks out at Long Beach electrical business
Owner Henry Schepens said he received a call informing him the building on Beatline Road was on fire.
Fire Remains Costliest Cause of Business Interruption Globally as Claim Severity Surges
Average business interruption claims now run 70% higher than property damage claims and continue rising sharply, Allianz Commercial found.
Scientists create an “electron lighthouse” with laser light
Scientists have created an “electron lighthouse” that uses laser light to launch and steer electrons through a semiconductor without an applied electrical field. The quantum effect could eventually improve optical sensors, communications, imaging, and information storage.
Single 2D crystal transforms into transistor with built-in insulation and electrical contacts
A transistor normally requires several fundamentally different materials—a semiconductor to carry current, an insulating dielectric to control it and metallic contacts through which current enters and ...
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
Scientists Find Hidden Information in The Shape of Neurons' Electrical Signals
"When we turn an action potential into a binary event, we throw away information."
Pacific North Sports comes back late for victory in 53rd running of Ski to Sea
MARR's Heating AC, Plumbing/Electrical finishes second after holding a nearly two-minute lead in final leg
A Major Labor Boom in CNY? Not Here Yet
With so many major projects going on — Micron, I-81 viaduct and others — job growth is predicted to increase. But so far the number of jobs in the region has declined By Aaron Gifford [caption id=attachment_11065 align=alignright width=350] Amy Stage, deputy director at the Manufacturers Association of Central New York (MACNY): “For us, the conversation isn’t just about filling jobs. It’s about creating sustainable pathways that help people see a future for themselves in manufacturing.”[/caption] The I-81 viaduct project in Syracuse and Micron facility construction in Clay are expected to create a major labor boom for Central New York. But for the time being, the number of jobs here has actually decreased in the past year. The New York State Department of Labor reported that, for the annual comparison of June 2025 to this past June, private sector jobs decreased by 2,200 or less than 1% to 260,000. Job gains were concentrated in leisure and hospitality (+700), private education and health services (+400) and other services (+300). Job losses for that annual period were reported in the areas of trade, transportation and utilities (-1,500); professional and business services (-1,000); financial activities (-500); mining, logging and construction (-300); manufacturing (-200); and information (-100). The public sector job count rose over 12 months, with most growth concentrated in education, the state Department of Labor reported. Looking ahead, the Central New York economy is expected to benefit from both the Micron and I-81 viaduct projects over a period of several years. Initial job growth is foreseen in construction and computer and electronic manufacturing. Spin-off jobs will be created in the areas of professional and business services, health care and education, the state Department of Labor said in an email response to Oswego County Business magazine. “Population growth tied to the buildout of Micron Technology semiconductor complex in Clay is also expected to bring more workers and residents to the region, increasing demand for transportation services,” the agency said. New York Department of Labor highlighted current or projected job growth trends in various sectors. An increase in defense-related contracts at local high-tech employers has continued to support employment growth in the computer and electronic product manufacturing sector and Micron is expected to generate thousands of direct and indirect jobs as the project progresses. This sector paid an annual average wage of $117,500 in 2025 and employment in the sector is projected to grow by over 60% through 2032, making it the fastest-growing industry in the region. Typical occupations in this industry include electrical, electronic and electromechanical assemblers, software developers and industrial engineers, the state agency reported. Specialty trade contractors include several different types of tradespeople — electricians, plumbers, pipefitters and steamfitters and HVAC (heating, ventilation and air conditioning) mechanics and installers. Many of these positions are trained through apprenticeships, the state Department of Labor reported. The Interstate 81 construction project is generating local jobs, including construction laborers, projected to grow at a 6.4% rate, and operating engineers and other construction equipment operators, projected to grow at a 7.3% rate over the next several years. Construction of the Micron Technology facility is also “creating thousands of job opportunities that will continue over the next two decades,” the state agency reported. The specialty trade contractors sector paid an annual average wage of $86,200 in 2025. For Central New York, the challenge isn’t creating jobs, it’s filling them. Amy Stage, a deputy director at the Manufacturers Association of Central New York (MACNY), said meeting this unprecedented growth is a much larger task than just replacing retirees. “We’re seeing workforce gaps at every experience level,” she said. “Companies need entry-level employees, experienced technicians, supervisors, engineers and skilled trades professionals. The opportunity is tremendous, but we need more people entering these career pathways.” Employers are looking for people who can troubleshoot, read technical information, use computers and learn new processes, not just perform repetitive production work, Stage said. To address this demand, the MACNY created the Manufacturers Talent Institute, which aims to connect students and job seekers with meaningful career pathways while helping employers build their workforce. Twenty-one companies have so far signed up to provide opportunities for more than 800 students. “For us, the conversation isn’t just about filling jobs,” Stage said. “It’s about creating sustainable pathways that help people see a future for themselves in manufacturing.” Several manufacturing facilities in the region are in the midst of expansion: • TTM Technologies, a leading U.S. manufacturer of advanced electronics and interconnect solutions for aerospace, defense and high-technology markets, which has a plant in DeWitt, completed its buildout of an additional facility, adding 400 jobs and expanding production of high-tech circuit boards for defense and critical electronics applications. • In Cortlandville, the Byrne Hollow Crossing Plant, a dairy manufacturing and processing facility, is increasing its operations, creating 100 new jobs. • The Chobani yogurt company is building a 1.4-million square foot dairy processing facility in Oneida County. This will create more than 1,000 good-paying jobs and double Chobani’s New York state workforce, Stage said. Stage noted several ways that local, state and federal governments can help spur manufacturing job growth in this region. Elected leaders and public agencies could work with industry representatives to create pre-apprenticeship and registered apprenticeship programs seeking to upskill workers and improve employee retention. New York state has a variety of grants, tax incentives and financing programs to support site preparation, infrastructure, workforce development and capital investment. The U.S. Department of Labor has a pay-for-performance incentive program that provides employers $3,500 per new apprentice hired and retained for 90 days. MACNY was previously awarded an $87,000 federal grant that will cover 25 apprentices at nine companies. The manufacturing skills gap in the United States, at its current rate, could result in 2.1 million unfilled jobs by 2030, according to a study by Deloitte and The Manufacturing Institute. In New York state, that gap is on pace to exceed 100,000 unfilled positions within six years. Manufacturing companies will be counting on more women to help fill that gap. While women make up half of the overall U.S. workforce, they only account for 29% of the manufacturing workforce in this country, Stage said. “Pre-apprenticeship programs like Real Life Rosies help to bring awareness to the manufacturing industry to fill some of the gaps, but we have a long way to go and it starts with educating people at younger ages about careers in manufacturing and earn-and-learn opportunities,” she said. As for Micron, that $100 billion-plus project, considered the largest private investment in New York state history, is expected to eventually create up to 50,000 jobs throughout the region, factoring in the spin-off opportunities for construction and supply chains. The plant’s foundation was poured on July 9. “As America celebrates its 250th anniversary, data and memory are foundational to the modern economy — and Micron is increasing our U.S. investments to more than $250 billion through 2035 to meet that moment,” the company’s president and CEO, Sanjay Mehrotra, said in a news release. Bechtel, Micon’s construction partner in the project, reported that 4,500 people will be employed to help build the facility, including skilled craft professionals, local union members representing various trades and apprentices. The Syracuse-based CenterState CEO organization tallies the regional labor force at 397,582 workers (Onondaga, Cayuga, Cortland, Madison and Oswego counties). Job growth isn’t limited to the Central New York region. For the larger area covering portions of the Mohawk Valley, the North Country, the Southern tier, and the western part of the state, there are 155,601 employees in the advanced manufacturing sector, and 155,275 construction workers. The agency’s 2026 Economic Forecast report noted that 41% of community and business leaders surveyed said a shortage of skilled workers in this area remains a problem, though 77% shared a positive economic outlook for the year ahead. Beyond the semiconductor and advanced manufacturing areas, local business leaders also see growth in small manufacturing companies, storage businesses, housing, unmanned flight technology and general construction. “Productive reuse of property,” the report said, “will hopefully continue to preserve unique architecture while driving business.” The report identified several challenges for economic growth in the region, including an aging workforce, outdated equipment, the rising cost of raw materials and “the disconnect between the speed of business needs and the pace of talent readiness.”
$150M in Federal Funds for Beluga-Healy Electrical Intertie
The US Department of Energy awarded $150 million in defense readiness funds for an electrical intertie between Beluga and Healy.
Scientists built a battery-free device that turns sunlight into fuel
Scientists have developed an artificial photosynthesis system that essentially regulates itself, eliminating the need for batteries used in many current designs. The key innovation is an electrolyzer that automatically adapts to changing sunlight by altering its electrical properties as it heats up. This keeps solar fuel production more stable while reducing cost and complexity.
Smart, hybrid, integrated, and engineered geothermal (SHIEG) systems
npj Thermal Science and Engineering - Geothermal sources can supply clean, sustainable, baseload thermal or electrical energy to fulfill societal demands in diverse climates via various...
More than 1 million Jeep vehicles recalled over fire risk as owners warned not to park inside
Stellantis is recalling over 1 million Jeep Wrangler and Gladiator vehicles over an electrical defect that could spark a fire, urging owners to park outdoors.
Smartphones passively monitor heart health
Nature Reviews Electrical Engineering - A study in Nature uses deep learning to passively monitor resting heart rates via front-facing smartphone cameras, yielding highly accurate cardiovascular...
Scientists discover a hidden brain rhythm that could improve Parkinson’s treatment
Scientists have pinpointed a brain network—and its distinctive electrical rhythm—that appears to drive the benefits of deep brain stimulation for Parkinson’s disease. The discovery could lead to more precise, personalized stimulation settings and better results for patients.
What Makes a Trailblazer: TSTC graduate always dreamed of business ownership
What do dyslexia, jewelry and an angry mother all have in common? Give up? They all put Mathew on the path to business ownership. Mathew Joseph is a graduate from Texas State Technical College’s Industrial Electrical Technician (now Advanced Manufacturing – Industrial Maintenance) program. He is also the owner and president of C3 Industrial Technologies…
Several Buckhead businesses damaged in electrical fire
At least four businesses appear to have suffered damage.
Electrically activated quasi-BICs in metasurfaces through atomically thin semiconductors
Light: Science & Applications - Electrically tunable nanophotonic device based on the integration of resonant dielectric metasurfaces supporting quasi bound states in the continuum with...
Chartbook 464 The"China squeeze" - the politics of development counterfactuals.
There are three types of China shock discourse. Each has a distinct temporal register. China shock 1.0 was a phrase coined by US academics in the 2010s to retrospectively summarize the impact on particular US labour markets, which they identified through painstaking empirical investigation. China shock 2.0 on everyone’s lips in Europe in the mid 2020s is an alarm raised by trans-Atlantic policy thinkers warning of a coming disaster which they project onto Europe’s ailing car industry. The third type of China shock discourse - commonly known as the “China squeeze” launched most recently by Indian economists Shoumitro Chatterjee and Arvind Subramanian in the pages of Foreign Affairs - mobilizes a different, more speculative temporal register: the counterfactual realm of alternate history. The China squeeze argument asks not what has happened, or what is going to happen, but what might have been. Specifically, what options for economic development might have been open to Global South economies like India or the economies of sub-Saharan Africa, had it not been for China’s spectacular industrialization since the late 1990s and the persistent competitiveness of China’s manufacture in low-skilled segments. Chatterjee and Subramanian’s argument is that whilst China has built a powerful position in electrical machinery and other high-skill manufacturing, which is now delivering China Shock 2.0, it also continues to run a trade surplus in low-skill, labour-intensive manufacturing. This surplus is large and has remained largely unchanged in fifteen years. Indeed, in the 2010s, in trade with low-income countries, China’s surplus rapidly increased. On their reading, this squeezes low-income producers in low-skill sectors in which they “should” be able to compete. Source: “China’s Mercantilist Squeeze on Developing Countries” Shoumitro Chatterjee and Arvind Subramanian. Peterson Institute for International Economics 26-7 May 2026 Chatterjee and Subramanian’s wording is telling: (emphasis mine) The canonical trajectory of economic development in the post-World War II period is for countries to transition from agriculture to manufacturing, first in low-skilled manufacturing and then later on to high-skill manufacturing (Herrendorf, Rogerson, and Valentinyi 2013). At the global level, this implies that high-income countries (HICs) that once specialized in low-skilled activities cede manufacturing export space to poorer countries that come along to occupy that space. In 1965, advanced economies accounted for about 60 percent of global value-added exports in four key low-skilled manufacturing sectors, i.e., apparel, leather, textiles, and footwear. Over time this share declined and began to be occupied first by the East Asian tigers and, beginning in the late 1990s, by China. Today China accounts for about 50 percent of the global market. The question is whether China, with its rising prosperity, is continuing to behave like its richer counterparts and ceding export space to poorer followers or to behave unlike them and continuing to occupy space. In terms of the conceptual maneuvers it performs, of the three China shock discourses, the “China squeeze” argument is by far the most ambitious. After all, it bases its critique of China on a counterfactual imagining of the world. Like any counterfactual argument, to construct this alternative reality it must rely on a heuristic model. To make their argument Chatterjee and Subramanian mobilize two key claims. The first reference point is the actual history of rich-country industrialization, what they refer to as the “canonical path”. The idea is that countries transition from agriculture to light industry and low-skilled manufacturing and from there up the value chain. To make this useful as a standard of comparison and a means to construct a normative standard, they adjust sectoral export shares for two factors: 1. the underlying level of economic development of the exporting country, as measured by national income and 2. the degree to which the sector in question is internationalized. The idea being that for a high income country to have a high export share in low-skill sectors is anomalous and even more so if that particular product is highly internationalized and thus suitable for being “conceded” to lower-income competitors. Where should this process end? Here Chatterjee and Subramanian introduce their second benchmark. Their normative idea of a global development path is one in which, in due course, low-skill manufacturing exports are distributed in proportion to a country’s share in the global labour force. They imagine, in other words, a world of proportional, polycentric global development without much national specialization in low-skill manufacturing. A useful benchmark is that, in labor-intensive manufacturing sectors, a country’s share of world exports should be broadly commensurate with its share of the world’s low-skilled labor endowment. … In the Heckscher-Ohlin model, this would be true if value added per worker and export propensities, i.e., fraction of output that is exported, are the same across countries. It is this pleasant liberal vista of orderly global development, progressing towards a general distribution of low-skilled manufacturing against which they judge reality and conclude that the low-income countries are suffering a “China squeeze”. China is not exiting low-skill sectors fast enough Allowing for its gdp level and the degree of globalization, China’s share of low-skill manufacturing exports is far higher than it “should” be. Relative to population, its low-skill share of exports is far too high. That in turn yields the conclusion that huge numbers of jobs - the authors suggest tens of millions - are being hoarded by China. For the four sectors captured in figure 4, this excess in value-added exports is $110 billion in 2022. For all low-skilled sectors overall captured in appendix figure D.1, excess value-added exports amount to $365 billion. The crowding out of LMIC exports by China is therefore substantial. Both these claims have in common that they are strong structuralisms. The first is that development paths ought to resemble each other. The second is that broadly speaking as far as low-skilled manufacturing is concerned, all countries are alike. If the world currently diverges from the distribution of trade implied by these assumptions, if China is not following the advanced economy path and has huge exports, this must be the result of “policy”, which the authors then put in question as illegitimate or unfair. Thus the naturalistic construction of a canonical path leading to a “level” distribution of low-skilled manufacturing reveals itself to be a polemical tool. From the point of view of China shock polemics, this discourse is no doubt welcome. But as an account of economic history, it must surely be regarded as nothing short of bamboozling. Development paths do not follow a regular, natural sequence. As David Fishman put it aptly, “development is not a queue”. They are always and everywhere, through and through political. Development is not so much a process, as a project. Each such project is more or less well adjusted to its context. As Gerschenkron taught uneven and combined development implies differentiation rather than simple imitation on a single parth. It may be true that Europe and the US exited relatively early from low-skill work. But clearly technology has changed. As C&S themselves point out, China no longer enjoys a low wage environment. Do they really believe that such huge differences can be accounted for either by industrial policy, which as they admit does not operate powerfully in low-skill sectors, or by exchange rate manipulation? What is overwhelmingly dominant in explaining the persistence of “low-skill” manufacturing in China are surely the network effects of complex supply chains. Indeed the label of “low-skill” may miss the point. The degree of globalization which Chatterjee and Subramanian decide to conjure away in their model of the development path - to allow for the fact that Europe and American textiles exporters did not enjoy just-in-time logistics in the 1950s - obscures the point that the networks through which Chinese factories supply the world are themselves key parts of the low-skill industrialization project. China isn’t knocking out 1970s style “cheap”. It has redefined the entire product cycle. C&S’s casual reference to “T-shirts” is telling. In today’s “fast fashion”, there is weight on both terms. Fashion and fast. China’s success in delivering on both at unprecedentedly high speed and at unprecedentedly low cost, isn’t a low-skill operation at all. If we see development trajectories not as the serial repetition of the same, but as distinctive, crafted projects that cumulate in complex agglomerations of skill, technology and labor, then this explains why the assumption that low-skilled manufacturing should follow the distribution of population flies in the face of all experience. As countless cases attest, low-wage, low-income developed economies are not by themselves the makings of a competitive production base. As Leon Liao puts it quite fairly: “International trade has never been allocated according to population. A country’s population gives it no natural claim to an equivalent share of global exports." And the remarkable fact is that Subramanian alone and with co-authors has long been making this point, not to pillory China, as is the case of the tendentious _Foreign Affair_s and Peterson pieces, but to highlight the great counterpart to China’s industrial success, namely India’s relative failure. The much-quoted Foreign Affairs piece showed low-skill export shares only for China, not for India. If you put both countries in the picture as Chaterjee and Subramanian have done on other occasions, the picture looks like this. China is far above the line, but India, almost as large in terms of population, is no less anomalous, just in the opposite direction. As far as global populations are concerned, and the imagining of tens of millions of “squeezed” jobs, it is this Sino-Indian pair that account for a huge share of the action. What this graph reveals is not China’s cheating, but India’s “greatest development failure”, at least this is the argument made Arvind Subramanian, this time in co-authorship with Devesh Kapur, in their major book, A Sixth of Humanity. Independent India’s Development Odyssey which appeared with Oxford University Press earlier this year. In this highly critical work on India’s development, China is repeatedly evoked, not to criticize but as a benchmark against which to illuminate what India’s political economy has not delivered i.e. large-scale formal employment for hundreds of millions of citizens. Kapur and Subramanian leave no doubt, if you want to understand why China, not India was the main driver of manufacturing globalization from the 1980s, don’t look to slots opening up in the division of labour thanks to the liberal mindedness of advanced economies, look to the contrasting political economy of the Maoist PRC and India’s post-independence political economy. As Kapur and Subramian note: The great divergence between China and India did not begin in 1978 with the Deng reforms—it was well underway by then. In one of the great ironies of modern history, the conditions created by Maoism turned out to be a great launching pad for industrial globalization. As the comparison of India and China in 1980 makes clear, to imagine manufacturing would be equally distributed when populations are so differently endowed in terms of educational and nutritional is fanciful. Here is the data from Kapur and Subramanian, data which I explored back at the very beginning of Chartbook. As Kapur and Subramanian insist, the striking fact is that even as India’s growth accelerated from the 1980s, structural change has not. Formal employment in India lags woefully behind. Why? As Kapur and Subramanian note, the path-dependent impact of India’s poor early start was devastating. The list of factors they mention is long and weighty: We argue for a new five-fold explanation applicable at different stages of Indian history: in the initial stages, the legacy of two key pre-1980s policies, the neglect of agriculture and the strangling of the domestic private sector, were critical. The failure of broad-based agricultural growth militated against rural industrialization, which would have been devoted to satisfying local needs that would have necessarily been labour intensive. Then, when the boom came after 1980, the thicket of regulation and broader labour protections that were legislated prematurely in a nascent democracy, underpinned by a deep ideological aversion to private capital in general and big capital specifically, became a barrier to attaining the size that would be necessary to compete globally. Similarly, the reforms after 1991, while wide-ranging, did not quite encompass non-tradeable inputs critical to manufacturing, namely, land, logistics infrastructure and power. A combination of low investment (logistics infrastructure), regulation (land) and the continued monopoly supply by state governments (power), combined with residual socialism, kept costs at 75–100 per cent above efficient supply. These factors were compounded on the supply side by the government, which dominated the formal labour market and established exorbitantly high wages at the lower end of the skill spectrum. This made their employment in the labour-intensive sector by the private sector less attractive. Finally, when the services sector and its exports boomed, wages soared even further via a Dutch Disease effect: one successful tradeable sector killed and cannibalized another less-skilled tradable sector, namely, manufacturing. Thus, scarcity-inducing policies of the planning era, precocious democracy and a Gandhian aversion to size; inefficient, monopolistic supply of critical non-tradable inputs; the behemoth of government; and super-successful skill-intensive services successively undermined India’s unskilled labour employment opportunities. The employment failure seems to have been over-determined. … Less quantifiable but no less important are some of the sociological factors that have undermined manufacturing and factory jobs. Take the impact of the success of the IT sector—located in urban areas with better working conditions, such as air-conditioned offices, good schools for children and attractive entertainment options. It became a more attractive place for engineering and management graduates to flock to. … Consider manufacturing and female employment. Indian society makes it difficult for women to work, reflected in India’s unusually low female labour force participation (elaborated in Chapter XIII). Indian society, in particular the routine harassment of women in public spaces, makes it even more difficult for them to travel long distances to take up work.37 Combined with onerous regulations on creating hostels and dormitories for women—which, in turn, prevents multiple shifts of operation—factories need to be located in areas with a large female labour pool. While firms can take apparel plants to female labour or bring them to the plants by building large-scale dormitories, this raises costs. If there was a case for subsidies to encourage labour-intensive manufacturing, housing subsidies to build dormitories for women workers would be a good place to start. All of this meant, that when opportunities did open up, in part thanks to adjustments in China, India was in no position to take advantage. Here is the account of the 2020s from Kapur and Subramanian. It stands in dizzying contrast to the one-sided, “China squeeze” argument delivered in the Peterson and Foreign Affairs pieces: In 2022, for example, India’s share of global exports in clothing (the canonical labour-intensive sector) was 3.1 per cent compared to 32 per cent for China. This is extremely disappointing because China started vacating export space in this sector after the Global Financial Crisis as its wages started rising; it then vacated further space in the aftermath of geopolitical developments that led investors to seek alternative investment locations. Between its peak and today, China lost about 7.5 percentage points of global export share (worth about $43 billion in 2022); over this period, India’s export share remained stagnant at 3 per cent, while that of Vietnam and Bangladesh rose by 3.5 to 4 percentage points. China’s loss did not translate into any gain for India in terms of low-skill exports and employment. Put differently, when the conditions for dynamism and prosperity were established after 1991, and even more tantalizingly when the global export opportunities opened up, it was as if India was a high-wage economy and only skilled labour could benefit from the dynamism. It had converted its physically abundant unskilled workforce into an economically expensive resource, penalizing its use. It is not my mission here to argue for or against Kapur and Subramanian’s interpretation of India’s development trajectory. The point in this context is simply that the “China squeeze” such as it is can only be understood, in relation to the heavy burden of domestic constraints that Kapur and Subramanian so unsparingly enumerate. I am concentrating here on India because it is the great counterpart to China and the unspoken reference point of the “China squeeze” discourse. But the point is more general. Can anyone with a straight face suggest that the main problems afflicting the development of South Africa or Nigeria, the great centers of mass underemployment in sub-saharan Africa, are cheap competition from China driven by Beijing’s industrial policy and an undervalued RMB? Likewise, is the main problem of the American working-class the threat of Chinese competition or the manifest crisis of social reproduction in the United States itself? The point here, as in the discourse around China shock 2.0 in Europe, is to insist that we should not normalize the world and pathologize China, without actually investigating what is going on in America’s industrial wastelands, the German car industry, or India’s lopsided labour market. One-sided pathologization should be understood for what it is, a polemical gesture. Concepts like China shock and China squeeze are, what Reinhart Koselleck, following Carl Schmitt, would have described as “asymmetrische Kampfbegriffe”, or “asymmetrical counter-concepts” or “asymmetrical combat concepts”. If the function of arguments like the “China squeeze” is to alert elites in the rest of the world of the need to rejuvenate and energize their development projects, so be it. But let us see the resulting discourses as the mobilizing interventions that they are. Interestingly, a significant slice of China’s public sphere - the so-called industrial party - have been obsessed for the last twenty years with precisely these questions of counterfactual economic history. Since the mid 2000s, a massive online discourse developed around an alternative history in which Chinese techno-patriots were asked to imagine how they would proceed if they had the possibility of traveling back in time to transport modern technology into the Ming dynasty (1368-1644) thus averting the “great divergence” of the 18th and 19th centuries. It is a fantasy of course, but also a goad. The point was not directed at Westerners. The alternate history is dramatically nationalist, but few n the West had even heard of it until recently. The adherents of the industrial party are not liberal moralists. They don’t project natural ladders of international development and ask why others don’t cede space. They take the Realpolitik of global economic development for granted. Their pointe was directed against fellow Chinese. The rallying cry of the alternative narrative was this: Now that we are beginning to gain steam and push forward on our national development path, now that we are breaking out of the inferior position assigned to us even in the early years following WTO accession, do not lose yourself in humanistic imaginings about better futures. In the spirit of Deng, they called on China to embrace the hard truth of development. Perhaps one might of the Industrial Party as a cultural trend born out of desire for symbolic revenge against those who had inflicted the century of humiliation. In terms of the various temporalities of the “China shock” - retrospective, prospective and counterfactual - one might think of the Industrial Policy discourse as truly speculative, conjuring up the China shock that never was. Or perhaps one might better think of it as imagining a world in which a powerful China was no shock at all, but simply a defining fact of modern history. I love putting out Chartbook. I am particularly pleased that it goes out for free to thousands of subscribers around the world. But, writing this newsletter takes a lot of work. If you are enjoying it and would like to support the project, sign up for one of the subscription options here. It is the equivalent of a fancy cup of coffee per month! Subscribe
Scientists make breakthrough in solving mystery of volcanic lightning
Research shows fine carbon coating on silica in updraught causes electrical charge – and spectacular display
Senators call on ICE to cancel plan to buy electric shock gloves
The devices are normal patrol gloves until an officer presses a button to activate the electrical mode
A quantum metasurface breakthrough could finally close the terahertz gap
Researchers have developed a compact quantum detector that makes terahertz radiation much easier to detect. A specially designed metasurface funnels incoming energy into tiny active regions, greatly strengthening the electrical signal produced. The approach boosted efficiency by roughly 20 times compared to earlier designs and could pave the way for more practical THz devices in healthcare, communications, and scientific research.
Florida business owner arrested after employees find hidden camera in bathroom: sheriff
NEW SMYRNA BEACH, Fla. (WFLA) — A Florida man was arrested on Monday after it was revealed that he hid a small camera inside an electrical outlet in the bathroom of his business. Donald Hemphill, 5…
Faezipour co-authors book on large language models in health care
Miad Faezipour, associate professor of electrical and computer engineering technology in Purdue Polytechnic's School of Engineering Technology, co-authored Applications of Large Language Models (LLM) in Healthcare Systems: Opportunities, Challenges, and Ethical Considerations.
Tiny graphene wrinkles create surprisingly powerful electrical effects
Scientists have discovered that tiny, sharply curved wrinkles in graphene can dramatically alter its electrical behavior, creating surprisingly strong charge separation. The finding suggests future electronics could be tuned by reshaping materials at the atomic scale instead of changing what they’re made of.
Scientists find a way to slash computer memory energy use by orders of magnitude
Scientists have devised a new way to switch magnetic computer memory while using far less energy than today's leading technologies. By mathematically optimizing the pulses used to flip digital bits, the method could reduce energy consumption by several orders of magnitude. Simulations suggest it may bring future memory devices surprisingly close to the fundamental physical limit for processing information. The same idea could eventually work with electrical currents or ultrafast lasers.
Echo Electric opens Sioux Falls facility
Echo Electric, a Sonepar company and full-line electrical distributor, has opened a location in Sioux Falls.
I Wore an Electrical Muscle Stimulation Body Suit to Zap Myself Into Fitness
Can electrifying your workout offer a shortcut to a stronger, fitter you? I sweated in a skintight EMS suit for two months to find out.
Smoak Power Laboratory honors family’s multi-generational electrical e
Louisiana Tech University's College of Engineering and Science recently celebrated the opening of the Smoak Power Laboratory with a ribbon-cutting ceremony recognizing the generosity of three electric
Apple Acquires Startup Working on 'Breakthrough Sensing Technology'
Earlier this year, Apple acquired California-based startup Sonera, according to a notice published today on the European Commission's website. Sonera previously announced that it had developed "breakthrough sensing technology" that "non-invasively measures magnetic fields" generated by the brain and body. The company said its technology can analyze neural data without direct skin contact, giving it an advantage over traditional electrical sensing techniques.
Scientists just captured trees glowing with electricity during storms
Scientists chasing thunderstorms in a retrofitted minivan finally captured something never seen before in nature: faint electrical glows shimmering from treetops during a storm. These “corona discharges,” long suspected but never observed outside a lab, appeared as tiny UV flashes at the tips of leaves. The discovery could reshape how we understand forests, since these bursts may help clean the air by breaking down pollutants.
Jameson Electric Builds a Family Business Rooted in Prescott Community
Jameson Electric is more than a local electrical company. Jameson Electric Builds a Family Business Rooted in Prescott Community
China’s self-powered neural device helps stroke survivors walk naturally
Prosthesis developed by mainland China and Hong Kong team uses electrical current to flex the wearer’s ankle while walking.
Renowned Energy-Storage Leader Aims To Expand University’s Impact
Dr. Babu Chalamala joined the Erik Jonsson School of Engineering and Computer Science as a professor of materials science and engineering last fall. He holds the Jonsson School Distinguished Chair and is supported by the Governor’s University Research Initiative. In June, he also will be a professor of electrical and computer engineering. Dr. Babu Chalamala, […]
Glowing algae could power the lamps of the future
The bioluminescent plants are a potential alternative to electrical light and batteries.
Scientists Think One of Earth’s Simplest Organisms May Work like a Giant Brain
One of Earth’s oldest plants appears to pass electrical messages through its dense green mats.
Scientists used tiny bursts of pink noise during sleep — and changed the waves that move fluid through the brain
Your sleeping brain is not quiet. Electrical waves roll across it, blood vessels rhythmically change size and cerebrospinal fluid moves in pulses that may help carry waste away. MIT researchers have n...
Scientists find a way to slash computer memory energy use by orders of magnitude
Scientists have devised a new way to switch magnetic computer memory while using far less energy than today's leading technologies. By mathematically optimizing the pulses used to flip digital bits, the method could reduce energy consumption by several orders of magnitude. Simulations suggest it may bring future memory devices surprisingly close to the fundamental physical limit for processing information. The same idea could eventually work with electrical currents or ultrafast lasers.
A 0.42-nanometer breakthrough could push transistors beyond silicon
Atomically thin semiconductors could enable dramatically smaller and more efficient chips, but a stubborn problem at the boundary between materials has limited their performance. Researchers have now engineered that atomic interface to protect electron flow while still allowing extremely thin insulating layers. The resulting transistors delivered an unusually strong combination of electrical control and performance.
Helix Electric, LLC Promotes Marcia Campbell to Director of Business Development
Helix Electric, LLC (Helix), a leading electrical contracting firm with operations across Nevada and Utah, has promoted Marcia Campbell from Business Development Manager to Director of Business Development, recognizing her leadership, industry expertise and contributions
BUSINESS MONDAY: Spotlight on Torrico Electric and Grenergy Solar—vertically integrated for holistic design, install, and service
Founded in 1985, the family business combines decades of electrical expertise with a growing focus on renewable energy and backup power systems.
Fine chandeliers are a specialty for New Orleans business | Home/Garden
Michael Melesurgo and Ricardo “Rico” Mencia purchased Classic Chandelier from the business’s founder, Peter Sather, in 2023, when he decided to retire. The business partners rebranded the company as Vintage Chandelier and relocated it to 455 Philip St. in the Irish Channel in December 2025.The company offers a variety of services including cleaning, moving, restoration, installation, pick-up, delivery and general maintenance of light fixtures, with a specialty in fine antique chandeliers.Additional specialties include the installation and restoration of mirrors and artwork, with pick-up and delivery included. googletag.cmd.push(function() { googletag.display('fixed-breakout-mobile-1'); }); googletag.cmd.push(function() { googletag.display('fixed-breakout-tablet-1'); }); “We mainly focus on older fixtures, but we have also worked on newer ones, especially with installation,” Melesurgo said. “We aim to be able to work on almost anything within reason. But chandeliers are the meat and potatoes of the business.” googletag.cmd.push(function() { googletag.display('fixed-sticky-rail-1'); }); googletag.cmd.push(function() { googletag.display('fixed-breakout-desktop-1'); }); The team at Vintage Chandelier has worked on some of the best-known chandeliers in New Orleans, at hotels including the Ritz-Carlton and the Hyatt Regency, the Milton H. Latter Memorial branch of the New Orleans Public Library and several prominent homes.Inside Out sat down with the duo to discuss the identification and care of fine chandeliers. googletag.cmd.push(function() { googletag.display('fixed-breakout-mobile-2'); }); googletag.cmd.push(function() { googletag.display('fixed-breakout-tablet-2'); }); What are some of the hallmarks of a fine chandelier?Melesurgo: Some of the finer points of elegant chandeliers are pristine crystal, clean craftsmanship, original pieces and parts and stamped pieces to ensure authenticity. Everything should be clean and working.How should you clean a fine chandelier?Melesurgo: The material in question determines the methodology for cleaning. Crystal chandeliers should be cleaned by hand, crystal by crystal, to ensure the best outcome, and to avoid deterioration of metal wiring typically used in connecting pieces together. Spraying cleaners can, over time, sit on the metal and end up rusting connections that compromise the connections. googletag.cmd.push(function() { googletag.display('fixed-breakout-mobile-3'); }); googletag.cmd.push(function() { googletag.display('fixed-breakout-tablet-3'); }); googletag.cmd.push(function() { googletag.display('fixed-sticky-rail-2'); }); googletag.cmd.push(function() { googletag.display('fixed-breakout-desktop-2'); }); What in your backgrounds led you to this business?Melesurgo: I have an electrical background. I started as an electrical apprentice in the local union (IBEW 130) in 2005. Then Katrina hit. I ended up going back to school and getting a degree in Hotel, Restaurant and Tourism and graduating in 2011. I started working for Peter (Sather) at Classic Chandelier & Mirror in 2012, which was supposed to only be temporary, but I ended up staying for a lot longer. I have always enjoyed working with my hands and being creative. This allows me to be creative and keep a lot of beautiful history alive. googletag.cmd.push(function() { googletag.display('fixed-breakout-mobile-4'); }); googletag.cmd.push(function() { googletag.display('fixed-breakout-tablet-4'); }); Rico, you worked as a draftsman alongside an engineer at YKM Consulting. googletag.cmd.push(function() { googletag.display('fixed-sticky-rail-3'); }); googletag.cmd.push(function() { googletag.display('fixed-breakout-desktop-3'); }); Mencia: The job was interesting, especially working on the Ochsner expansion, but staring at two monitors all day became unbearable. I went to work for Peter (Sather), which opened a new world to antiques and chandeliers that I find fascinating. Vintage Chandelier, 455 Philip St., (504) 309-8983, @vintagechandelier.504 on Instagram googletag.cmd.push(function() { googletag.display('fixed-sticky-rail-4'); });
Science Vs on the 49ers Substation: Anatomy of a Hatchet Job
In August, Pablo Torre Finds Out and Science Vs released an episode about my theory that electromagnetic fields from the electrical substation beside the 49ers facility may be contributing to the team’s run of soft-tissue injuries. As the originator of the theory, I was also a subject of the episode. I sat was interviewed by Wendy Zukerman and Rose Rimler of Sciene Vs. I sent them research, connected them with scientists, and spent hours digging through the City of Santa Clara’s and Silicon Valley Power’s records to help clarify critical details. Both Wendy and Rose came off as affable and professional, showing curiosity during the interviews, with Wendy going out of her way to question the “conspiracy theory” framing itself. Then they titled the episode We Solve the 49ers Viral Conspiracy Theory. I was familiar enough with their catalog that I never expected them to agree with my theory, but I did expect them to give it a fair hearing and to deliver their findings honestly. On both counts they came up short. They were not directly dishonest in anything they said, but rather in what they left out, in how what remained was cut, and in the picture painted by those two things in combination. They asked me to recorded the interview on my phone for better audio quality, and I held on to my copy for reference later. That turned out to be a fortuitous decision. Here is the raw audio of my first interview, unedited*. Only my side was recorded, so their questions aren’t on it, but you can generally infer them from the answers, and every claim I make below about what I said can be checked against my statements in this clip. (Note: Wendy had connection trouble at the beginning of the interview and was cutting in and out, which accounts for the false starts.) 0:00 -1:19:13 Audio playback is not supported on your browser. Please upgrade. Science Vs is a fun show. It is pitched at roughly a high-school understanding of science, for an audience that is skeptical, Snopes-oriented, and worried about misinformation. Take a claim circulating online, interview a supporter of the claim, interview consensus scientists, and then tell people which side of the line it lands on. I have listened to their episodes on raw milk, seed oils, 5G and other contested issues in the wellness space. I have problems with all of them, but each at least made an honest attempt to represent the actual range of scientific opinion by talking to credentialed scientists with differing perspectives. Dissenting researchers were heard from, answered, and often given a chance to respond. This episode did not do that. This article is not a relitigation of the science. I have written extensively about that already. This post is for the record. It is simply an accounting of what was wrong with their episode. Contents Is there a power plant next to the 49ers practice facility? — the clearest single example of getting something objectively wrong For the record — a high-level overview of all of the problems with their investigation Draw your own conclusions — why they had to make this episode at all What they left out about childhood leukemia — the exposure threshold, and playing games with statistics to minimize sick children What they left out about the mechanism — the body of literature they refused to cover, and evidence for the mechanism used against it The scientists Science Vs interviewed and did not air — four credential scientists who support myhe theory, recorded and cut, or not even called How they misrepresented me and my case — an answer severed from its question, and three telling edits How you would actually study the injuries — it doesn’t actually matter which team is the most injured, overall The theory: magnetic fields, oxidative stress, and collagen Since the episode never states my theory, here it is below. Those who are familiar with my work can skip this section. Electrical equipment produces magnetic fields, and those fields induce faint electrical currents in anything that passes through them, including people. My argument goes further than induced current. Mitochondria — the structures that generate a cell’s energy — run on continuous flows of electrons and protons, and those flows carry faint electromagnetic fields of their own. Maxwell’s principle of superposition shows that when two fields share the same space, they add together. An external field does not need to be strong to alter an internal field, it only needs to be present. The electron transport chain inside the mitochondria leaks a small fraction of its electrons by design, and those become reactive oxygen species — free radicals, which healthy cells use as signals. External magnetic fields cause the rate of leakage to change, increasing free radicals. When free radicals accumulate faster than the cell’s antioxidant systems can clear them, the result is oxidative stress. Oxidative stress is a recognized driver of chronic illness, including cardiovascular disease, neurodegeneration, diabetes and cancer, and it is in every medical school curriculum. One of its ordinary effects in connective tissue is that it switches on matrix metalloproteinases — MMPs, the enzymes that break collagen apart — while suppressing new collagen synthesis. Tendons are made of collagen. An athlete loading his soft tissue heavily six days a week is already creating oxidative stress in the tendons, so the addition of magnetic field exposure compounds the damage and inhibits repair, making him more susceptible to injury when enormous force lands on a tendon in a fraction of a second. That is the theory. We know that EMF causes oxidative stress, and we know that oxidative stress degrades collagen. The only thing missing is a study showing that direct connection. I have never claimed certainty that the substation is contributing to the elevated injury rate. I do believe it is likely, and I believe it warrants caution, and that a revenue machine like a major NFL team can easily afford to remove the exposure out of precaution. Is there a power plant next to the 49ers practice facility? Here is the clearest single instance of the problem with this episode. It requires no knowledge of electromagnetic fields at all. This story first came to me through Jon Feliciano, a former 49er, in an interview on Willard & Dibs on 95.7 The Game. Asked about why the 49ers are always injured, he said players used to joke that it was the power plant behind the practice fields. Wendy Zukerman corrects him on air. “It’s important to say that it’s not a power plant near the 49ers site.” Torre then asks her to explain the difference between a substation and a power plant. Her answer: a power plant generates electricity and transmits it to a substation, which converts the voltage into something your house can use and sends it on to your home or your business. There are two problems with that. The first is that there is a power plant on that site. The Gianera Generating Station is a natural-gas-fired peaker plant owned by Silicon Valley Power, and it has been there since 1986. I have published aerial photographs of the location from 1987 in which the gas plant is the only thing standing, before the practice facility was even there. I even mentioned the gas plant in my first interview. (Feliciano has since gone on record about this issue, and it is clear he had the substation in mind rather than the gas plant.) The second is that her definition describes a distribution substation, and the facility beside the 49ers is not that. It is the Northern Receiving Station, which takes in bulk power from outside the city’s grid and delivers it to distribution substations. Silicon Valley Power’s own map distinguishes receiving stations from substations, and Rose Rimler even reads the label out loud in the episode when she walks through that map on air. A few minutes before the map segment, Zukerman tells Torre: “like I said, we fact check everything.” Well, maybe not everything. I made a mistake On the morning of July 6th, at 10:20, I sent Rose and Wendy two studies. During the interview I had been asked which human studies show oxidative stress from electromagnetic fields, and I had not been able to name one on the spot. Rose emailed asking for the studies, I quickly searched for a couple, and I wrote that I thought these were the most relevant from that search. Unfortunately, I was busy and did not read either one closely at first. I picked them because they were topically relevant — one on substation workers, one on power plant workers. Neither were great studies, and their problems go past the ones raised in the episode. That was careless on my part. There is context that did not make the episode, though. Before that email I had been on a Zoom call with Rose talking about EMF and oxidative stress, and I pointed her to Dr. Henry Lai at the University of Washington, who has spent years aggregating the literature on this question. His tallies show that roughly 90% of studies since the late 1990s find oxidative effects from electromagnetic field exposure — hundreds of studies, systematically counted. Rose told me she was already aware of his work. So when she asked for studies, I understood her to have the aggregate view already and that she would report anything within that context. Not reading those two carefully was still a mistake, but the larger mistake was assuming the episode would be based on a thorough review of the actual body of literature, rather than on whatever I happened to send that morning. The second email At 1:49 that same afternoon — three hours and twenty-nine minutes after the first — I sent them a second email that I had been preparing for a while. It was a structured document in six numbered sections, written in response to a request they had made two weeks earlier, laying out my entire argument with citations attached to every link in the chain. The episode aired on August 13th, five weeks later, and not a single item from the second email is in it. Here is how it opens: The full email is included at the bottom of this post in Appendix B. Nearly 1,500 words in total. It contains two named mechanisms with the physics behind them. Occupational studies in humans. The literature on oxidative stress and collagen. A section addressing the strongest counter-evidence against my own theory, which I raised myself. And a closing section stating plainly what the theory cannot yet show. My entire argument, in writing, with detailed citations for every claim, provided to them five weeks before broadcast, and none of it made it into the episode. That is the single largest omission, but it is not an isolated one. The whole episode is riddled with similar problems, and the conclusion they came to is not merely a difference of opinion about the scientific evidence. Through omission and through strategic editing, Science Vs misinformed its audience — about what the evidence shows, about what I argued, and about who they spoke to. That is a notable outcome for a show whose stated purpose is correcting misinformation. For the record I am not going to tell you that Science Vs set out to discredit me, or that they had come to their conclusion before they reported the story, or that they used misleading editing to make me look like a man retreating from his own theory. I cannot know what was in anyone’s head, and I am not going to pretend otherwise, either. What I can tell you is what is on the record. They asked me for evidence and aired the weakest thing I sent. They interviewed three scientists who supported my theory and aired none of them. They discussed childhood leukemia without ever saying the exposure level at which it appears. And they took an answer I gave weeks before Ken Karipidis, the one EMF scientist who was put on air, was interviewed, and placed it directly after his critique, where it comes off as a major concession. A friend of mine who has worked as a journalist for thirty years read that last one and called it sleazy. I agree with her. Those are just the four issues that are impossible to defend as pure editorial decision, but they are not the only issues. The most glaring issues stem from what they left out: The exposure level at which the childhood leukemia association actually appears — three to four milligauss, a number the episode never states despite it being much lower than what I measured. The mechanism itself: The episode gets as far as “oxidative stress could weaken collagen,” which leaves it sounding like speculation, rather than a known pathway. The second email, and all the studies in it. Dr. Paul Héroux at McGill, whose work my proposed mechanism rests on, whose contact details I supplied, and who was never called. Dr. Beatrice Golomb at UC San Diego, who runs a research group on oxidative stress and mitochondrial function and has specific expdertice in collagen, interviewed and not aired. Dr. David Carpenter at Albany, the most prominent academic voice on the harm from magnetic field exposure, interviewed and not aired. Dr. Joel Moskowitz at Berkeley, interviewed and not even credited. The specific, testable condition I put in writing that would make me abandon the theory. My own unprompted statement of the theory’s evidentiary gap. My caveats about my own measurements. My ranking of EMF as one factor among several rather than the only one. The new equipment installed at those facilities between 2010 and 2014, and the sharp rise in system load from 2013 onward. But that is not all. What they kept, they selectively edited to serve a narrative that was not served by the raw transcripts of the interviews. A description of thousands of commercial routers in a workplace, reduced to the Wi-Fi in your house. My own acknowledgment, multiple times, that "I'm not a scientist" clipped in an episode that spends considerable energy pointing out that I am not a scientist. And a qualification I volunteered about my own measurements, cut from my answer and delivered later by their EMF expert as a correction. Together their edit produce a portrait of a wellness guy with Wi-Fi phobia and two bad studies, backing away from his theory the moment a “real” scientist looked at it. A practice facility where nothing changed because no new substation was built. Injuries written off as random because the 49ers were not quite the single most injured team in the league over the period in question. That portrait is false even though almost no individual statement made in the episode is. Draw your own conclusions At the top of the episode, Pablo Torre says his show had been flooded with requests to investigate the substation — that it was the thing they were asked to look into over and over again. Neither show went hunting for this story. It arrived from their own audience, in volume, and it could not be waved off. A thread I posted on X reached twenty-two million people. A guy with a gaussmeter and a brand-new Substack obligated a Pultizer prize winning program to spend an hour on a question about player health, that is considered fringe enough that most media operations won’t touch it. Pablo Torre Finds Out could not ignore it. So Science Vs came in and ran a “debunking” operation instead of an investigation. Everything below is what had to be left on the cutting room floor to deliver the “debunking”. They could not ignore it. So they tried debunked it instead. The demand was strong enough to force an episode, and since the episodes release the 49ers have sustained more injuries, including season ending ones, and interest has only grown. Demand from fans and playets is strong enough to force a better investigation from someone else. An omission is not a lie until you find out what was omitted. What follows is the detailed record so you can see the full picture. Draw your own conclusions. I have drawn mine. I am going to keep publishing. A note about Pablo Torre Finds Out After the episode aired I posted publicly, calling out Pablo Torre Finds Out for concerns I had about the integrity of their investigation, and about an interview directly with Pablo Torre which had been offered but never happened. I have since spoken with a producer at PTFO. The offer had rested on a misunderstanding about where things stood between us, and it fell away as the Science Vs part of the production widened past the science. He apologized for the miscommunication and I accepted. The producer also confirmed to me that they did essentially hand off the entire investigation to Science Vs for narrative purposes — so Pablo would be genuinely curious or potentially surprised by their findings — while still taking responsibility for what went out under their name. I appreciated the candor and the accountability, and I am comfortable with where we left things. So this post is not about PTFO. My disagreement is with Science Vs. What they left out about childhood leukemia Childhood leukemia appears at three milligauss. They gave no number at all. 1. They built an EMF ruler, then discussed childhood cancer without it. The sequence on air went like this: First I measured almost 9 mG, then I measured up to 50 milligauss. Torre reacts with concern — “that sounds high.” Cut to Karipidis: the public limit is 2,000 milligauss. Torre reacts again — “What happens at 2,000?” Karipidis explains that nothing happens at 2,000, that safety factors are built in. Then: at more than 50,000 milligauss you get flickers of light in the retina, and higher still, nerve stimulation. The listener now has a ruler (their ruler) to measure these numbers with. Fifty is nothing by their ruler. Then the episode turns to childhood leukemia and states, accurately, that there is a real association — but tellingly, they never give the exposure level at which that association appears. Childhood leukemia appears at three milligauss. They conveniently left that out. The pooled analyses that produced the World Health Organization’s carcinogen classification found roughly a doubling of childhood leukemia risk above three to four milligauss. That is the number that belongs in that segment, and it is more than ten times below the reading that had just been dismissed as trivial. I gave them that number myself, on tape, in the interview. Describing my own threshold, I said my comfort level for long-term chronic exposure is three to four milligauss, but preferably one. 2. Six children in thirteen million. The episode reports that these fields might explain one to four percent of childhood leukemias, then reframes it as a German estimate of perhaps six cases among thirteen million children. Torre, to his credit, is uncomfortable. What never gets explained is why that number is small. Almost no children lives above three milligauss in Europe. Fewer than two children in a hundred, in the Italian data. So even if the risk to those children doubles, the number of additional cases across an entire country stays small — not because the hazard is small, but because hardly anyone is exposed to it. Count the whole population and the few who are exposed disappear. And the reason hardly anyone is exposed is that siting rules keep housing away from transmission lines. In Europe, at least. The Dutch government has a standing precautionary policy against building new homes in any zone where the annual average magnetic field exceeds 4 milligauss — the same number the episode never mentioned. Denmark and Norway treat 4 milligauss as the level that triggers a look at mitigation. That is five hundred times below the ICNIRP figure quoted on air. The United States has no federal equivalent. That is evidence of infrastructure siting policy working. It is not evidence that there is no hazard. It is evidence that we already act as though there is one. If you listen to the raw audio you will hear that my proposed solution is EMF exposure is to build better infrastructure. What they left out about the mechanism 3. They accused me of cherry-picking, and then cherry-picked themselves. On air, Zukerman tells Torre that people who worry about electromagnetic fields dismiss the studies showing null results and collect the ones showing harm, and that this is why you have to be careful not to cherry-pick. They had two papers I had rattled off in a hurry, and a second email containing a carefully chosen set. They ran the two weakest, graded them on air, and presented the result as the state of the evidence for not only my theory, but the whole question of oxidative stress from magnetic fields. That is cherry-picking from my emails. The bigger picture is what they did with the literature as a whole. Zukerman acknowledges it exists, dismisses it, and disposes of it in a single stroke. You can go online right now, she tells Torre, and find scores of studies showing these fields increase oxidative stress. The issue, she says, is that they are not studies in people. Many of them are in people. The occupational studies in my second email are in people. That email had been in her inbox for five weeks. She waved off the literature on a factual claim that the documents in her possession contradict. (I have written separately about the evidentiary standard at work here). The effect was that they essentially baited me: ask the subject to supply the evidence, take the weakest thing he sends, and let that stand as a proxy for the whole argument. Wendy has been doing this show for ten years and clearly knows how to extract what she needs for her desired narrative. 4. They presented the collagen-improvement research as a gotcha, but I had already addressed it. The episode treats the existence of studies showing that EMF can improve collagen as a surprise that undercuts me, but I had pre-emptively addressed that five weeks earlier in the email they ignored. Those studies use measured, high-intensity pulsed dosing. The mechanism by which they work is oxidative signalling. The cell reads a controlled rise in reactive oxygen species as a warning, upregulates its antioxidant defenses, mounts a repair response, and the therapy stops before the system is overwhelmed. The key point is that it induces an oxidative response, which means those studies are actually evidence for my proposed mechanism, not against it. A field that produces a therapeutic effect cannot be biologically inert (which is the implication when they say “Nothing happens at 2,000 milligauss). Chronic ambient exposure is the same pathway with no off switch, and it is most consequential during the evening and while sleeping, when the body is in repair mode and the exposure does not stop. Section 5 of my email is titled What about the study showing improved collagen synthesis. I raised the counter-evidence myself, explained why I did not think it refuted the theory, and wrote that I was disappointed the question had not come up in the interview. That is worth holding against the cherry-picking charge in the item above: the studies they presented as inconvenient for me were studies I had gone out of my way to put in front of them. 5. Section 1 of my email stated a critical argument that was never put to the expert directly responsible for it. My email says the exposure limits exist to prevent acute effects and do not address chronic exposure at all, and that my dispute is with the entire framework. Zukerman gestures at this once. After Karipidis gives the 2,000 milligauss figure, she tells Torre that I would object because those levels do not capture “more subtle effects.” That is not my argument, and “subtle” is doing a lot of work here. My argument is that the limits are built to prevent acute effects — nerves firing, muscles twitching, etc — and were not designed to address chronic exposure at all. In fact, ICNIRP’s own documents state as much themselves. Mine is a structural objection to what the standard measures, reduced as a concern about subtlety, it becomes a matter of degree, rather than a categorical difference. They interviewed Ken Karipidis, vice chair of ICNIRP — the body that writes those limits. He was asked what the limit is, but he was never asked how it applies to chronic exposure. The scientists Science Vs interviewed and did not air 6. They interviewed four officials of the standards body. The episode credits roughly a dozen researchers. Four of them are associated with ICNIRP. Ken Karipidis is the vice chair. Rodney Croft chaired ICNIRP from 2020 to 2024 and led the development of its current guidelines. Dan Baaken is ICNIRP’s scientific secretary. Frank de Vocht sits on the Main Commission. One of them speaks in the episode. Their institution’s position is more than adequately represented — the 2,000 milligauss figure, the safety factors, the assurance that nothing happens below the line. 7. The four who were left out. Dr. Beatrice Golomb is Professor of Medicine at UC San Diego — a physics undergraduate degree, a PhD in biology, an MD. She directs a research group whose stated focus is the relationship between oxidative stress, mitochondrial function and health. That is the mechanism the episode spent its first half dismissing. Her published work includes the fluoroquinolone case series behind the FDA’s black box warning on an antibiotic class that ruptures tendons, where the accepted mechanism is oxidative stress and mitochondrial toxicity — the back half of my chain, already on a drug label. She is in the credits. She is not in the episode. She has told me she finds my theory biologically plausible, and that she has a recording of her interview. Dr. David Carpenter directed the Institute for Health and the Environment at the University at Albany for decades and is the most prominent academic voice arguing these fields cause harm. Childhood leukemia is the reason these fields carry a WHO classification at all, and Carpenter is the person you call if you want that case made by someone who has spent a career on it. He is in the credits. He is not in the episode. He has told me that when he was interviewed they could not have been less interested in what he had to say. Dr. Joel Moskowitz directs the Center for Family and Community Health at UC Berkeley’s School of Public Health. He told me directly that they interviewed him and that he thought it went well. He does not appear in the episode, and unlike Golomb and Carpenter, he does not even appear in the credits. Dr. Paul Héroux at McGill is the researcher whose work provides the foundation for the oxidative stress mechanism my theory rests on. I gave Rose his email address and phone number. He was never interviewed. They never even called him. 8. “He’s not a scientist.” The episode leans hard on the fact that I am not a credentialed scientist. Zukerman says it. Torre repeats it. “At all.” Having built a segment on that, they then left out the physicist-biologist-physician, the professor of public health, the director of a university environmental health institute, and the McGill researcher whose work the primary mechanism comes from. They spent the episode telling their audience I am not a scientist, and then kept four actual scientists who support the theory off because their argument does not survive otherwise. How they misrepresented me and my case 9. They played my words as a response to an interview I had never heard. Near the end of the hour, Zukerman says she went to me and told me the evidence was lacking. Then she plays me saying I am not wedded to it being an EMF, that I have staked my reputation on it needing more study, and that I am not certain of anything. That segment was placed immediately after Karipidis had finished taking the cherry-picked papers apart. It plays as a man folding under expert scrutiny. Commenters have used it against me since, but it is incorrect. Here is the sequence as it happened. I was interviewed. Karipidis was interviewed weeks later. I was never told what he said, or even who he was. I was never asked to respond to it. I did not know his name until the episode aired. That is not a simple editing decision. That is a quote from one interview, moved to follow a critique from a different interview it was not a response to, so that it would land as a concession. A friend of mine who has spent thirty years as a journalist read that sequence and called it sleazy. She is right. The full passage is reproduced in Appendix A, and it is worth reading. What airs is the preamble. Four paragraphs later I say “to directly answer your question” — and that answer, about what would change my mind if the team relocated, is not in the episode. Neither is the sentence two paragraphs on, where I say the EMF might turn out to be ten percent of the problem. I will say the underlying point again, though, because I meant it and I still do. I am not wedded to my theory that magnetic fields from the substation are contributing to the 49ers injuries. I could be wrong. What I am wedded to is the process of scientific inquiry, and the fact that we should be cautious around these exposures and we need more independently funded studies. 10. Three telling edits. They cut “I’m not a scientist” mid-sentence. What I said: “...and I am not certain of anything. I’m not a scientist. To me, I find the mechanisms compelling. I will go back to the fact that I got into this not because of the 49ers, but because of clients I was working with who suffer from EDS...” What aired: “...and that I am not certain of anything. I’m not.” The clip ends on the first two words of the sentence in which I say I am not a scientist, in an episode that spends considerable energy establishing that I am not a scientist. The full sequence is in Appendix A. They cut my own description of my work. Asked what I do, I said I run a wellness business, that I am focused on writing software to help people navigate environmental stressors, that environmental health is my focus, and that I also do independent journalism and research. What aired is the wellness business and the environmental health, with the software and the journalism removed from my own answer. The software engineering does come up later — narrated by them, as a hacker who grew up to write firmware — but my current work, in my own words, arrives as “wellness guy.” Thousands of commercial routers became home Wi-Fi. What I described: working at a wireless networking company surrounded by thousands of Wi-Fi routers, and a stress-induced health collapse afterward that working in that environment contributed to. What aired: Wi-Fi, the kind you have at home — reinforced by a clip of Christian McCaffrey talking about turning his router off at night. Three cuts, and every one of them makes me seem less credible. That is not a coincidence. 11. I gave them my own caveats and the test that would disprove me. In the first email I wrote that a well-designed chronic, ambient-level exposure study in tendon showing no collagen degradation, run over many months, would undercut my confidence in the theory. That is a specific, testable condition, stated in advance and in writing. There was a second interview, weeks later, which was not used in the episode, but in that I asked again for the falsification criterion to be included. What the episode presents instead is a man saying “we need more study,” which reads as a hedge, an open-ended request for the benefit of the doubt. It is the opposite of a hedge. Section 6 of my second email says, unprompted, that as far as I am aware there is not a single study showing EMF-driven oxidative stress degrading collagen in a human in vivo or in human tendon in a lab. I wrote that because it is true and because it is the first thing anyone should check. Under their standard it becomes the hinge of the entire first half, framed as something they had to surface without my cooperation. I had handed it to them five weeks earlier. And in the interview I said that my 25 to 50 milligauss readings were taken at knee level, and that these fields attenuate quickly, so by the time it reaches your head it is not that high anymore. That did not air either. The qualification arrives later, from Karipidis, as a correction. How you would actually study the injuries 12. They measured the wrong thing. The episode spends its final act on whether the 49ers are the most injured team in the NFL, finds no clean ranking, and lands on “injuries are random”. That is the wrong test. You would define the exposure — measured field levels at the facility — and the outcome narrowly: soft-tissue injuries, not a single MSK injury count that a broken finger and a ruptured Achilles both land in. Then you would compare the 49ers to themselves before and after the exposure changed, and compare that change against every other team over the same window. That controls for league-wide shifts in rules, turf and training load. It is a difference-in-differences design, and it is standard. I sent them that argument on July 28th, in writing, along with the fact that in eleven of the past twelve seasons the 49ers had finished top ten in Adjusted Games Lost. And by the episode’s own reporting, the 49ers are second in games lost to injury over the past decade, with FTN’s Aaron Schatz confirming that once you adjust for starters they come out second worst in the league — after having been one of the healthiest teams for years before that. A finding like that is where an investigation starts, not where it stops. 13. I did a lot of substation research for the episode that was never aired. I had reported that the substation next to the facility was expanded in 2014. That was wrong, and Rose Rimler and I sorted it out together. They gave me credit on air, which I appreciated, but framed it as a concession on my part to something they had found. In fact I had been investigating it myself, was uncertain before they asked, but was waiting for clarification from Silicon Valley Power. The uncertainty centered around a substation named “Esparanca” that was proposed right behind the facilities as part of the stadium construction, but now appears to never have been built. I spent days in Silicon Valley Power’s records, and did eventually reach Silicon Valley Power for confirmation and indentified the mistake myself. I also gave them highly detailed documents on what we do know about those facilities: new equipment installed between 2010 and 2014, and load growth across the system with an inflection around 2013–2014, with the Northern Receiving Station carrying the highest capacity in the system and sitting closest to the data center corridor. None of that is in the episode. I have a separate piece about it coming out soon. *I cut 2 seconds from the raw audio to remove personal information that had no connection to anything in the episode. Appendix A: the passage the clip was taken from This is the sequence from my first interview, in full. The episode uses one fragment of it. It’s tricky because my understanding is that there’s something like a 15-year half-life on collagen remodeling issues. They’re going to get a new crop of players. What I really need, though, is for the injuries to be broken down so we can see the soft tissue injuries. Right now, they’re categorized as MSK injuries, but let’s say we can actually identify them more specifically. Is that right? He was able to do that? Oh, cool. I wasn’t able to find that information. Interesting — I didn’t know that data existed. I tried so hard to get it, and I didn’t know it was available. Maybe you could connect me with that person. That would be amazing. I’m not wedded to it being an EMF, honestly. I’m not. I would say that, to a certain extent, I’ve staked my reputation on the fact that it needs more study. It’s important to look into it, and I am not certain of anything. I’m not a scientist. To me, I find the mechanisms compelling. I will go back to the fact that I got into this not because of the 49ers, but because of clients I was working with who suffer from EDS, Ehlers-Danlos Syndrome, a tendon hypermobility issue. This condition is documented to be partially caused by oxidative stress. I’ve worked with them to mitigate their EMF exposure and have seen people improve. I think it’s a bigger story. In a way, the 49ers represent an occupational cluster with specific exposure risks. If someone would conduct a study on this, I believe we could learn a lot. Perhaps we would discover that it’s like, okay, maybe it’s 10% of the problem. I don’t know the exact number, but I think either way, conducting the study would provide valuable insights. To directly answer your question, it’s challenging for me because it’s part of a bigger story. If the 49ers move and stop having injuries, I might conclude that it was related to the substation. However, if they move and still experience injuries, I would want to analyze the nature of those injuries. Are they primarily soft tissue injuries? I don’t think it’s necessarily a case closed, but the story might lose traction at that point regardless. Three things are worth noting. The aired fragment stops immediately before the sentence in which I say I am not a scientist — the cut described in item 10. It also stops four paragraphs before the words “to directly answer your question.” What the episode plays is the throat-clearing. The actual answer, about what would change my mind, never airs. And two paragraphs in, I say the EMF might turn out to be ten percent of the problem. That is the ranking the episode says I never gave. Appendix B: the full email, July 6th, 1:39 PM Hi Rose, You asked me to send you some studies a couple of weeks ago. I apologize for the delay. I have been incredibly busy. I also wanted to give you a chance to dig in yourself, and get your own perspective before I influenced you too much with mine. That said, I do want to make sure that the actual argument is abundantly clear, so here it is! One note before I begin, there are really two separate questions here: Does the substation cause the soft-tissue injuries? That was my specific claim, and what the podcast is about. Is the theory biologically sound? Can 50/60 Hz fields at these levels do anything biological below the safety limits? Question two is why people have been calling me a conspiracy theorist. The regulatory and advisory bodies (ICNIRP, etc) maintain that anything below their exposure limits is biologically inert, and that position is broadly accepted within the mainstream, but the actual science paints a different picture. To defend my theory I’ve had to defend a much larger claim: that the advisory bodies have the biology wrong. I can’t honestly answer question 1 without first addressing that. Here’s is a simplified outline of my theory, with links to studies: 1. Advisory body thresholds for biological effects The ELF magnetic-field limits (ICNIRP’s ~2,000 mG public / 10,000 mG occupational) exist to prevent acute effects from exposure. If a magnetic field is strong enough, it makes nerves fire and muscles contract. Muscles twitch. You can see faint flashes of light in your vision. People can even feel tingling or even a shock. That happens due to Faraday’s law, which states that a time-varying magnetic field induces an electric field inside the body via the creation of Eddy currents.The standards assume that those currents do nothing below the twitch threshold. They do not consider chronic effects at all. My argument is that they are biologically active and do have chronic effects. 2. There are multipe ELF-EMF mechanisms for inducing oxidative stress. This is basic biophysics. Below are the two primary mechanisms. Simplest first. Dr. Paul Héroux of McGill has the most intuitive explanation, which rests on Maxwell’s principle of superposition: because Maxwell’s equations are linear, two sets of electromagnetic waves sharing the same space simply add together. In the interview I pictured a pebble dropped into a pond, sending out clean ripples. Then a boat motors past at distance, sending larger waves, and where they meet the ripples, the two add together and the original pattern gets distorted. In our cells, the mitochondria run on continuous currents of electrons and protons that carry their own faint electromagnetic fields. An external field from a substation, by the principle of superposition, adds to those internal currents and shifts the pattern. The electron transport chain in the mitochondria leaks a fraction of its electrons by design as reactive oxygen species (ROS), which act as signalling molecules in a healthy cell. Distorting that field increases that electron leakage, creating oxidative stress. A tiny electromagnetic interference results in a large downstream effect. https://www.sciencedirect.com/science/article/pii/S2405844025006474 The more complex pathway is Dimitris Panagopoulos’s Ion Forced-Oscillation / Voltage-Gated Ion Channel (IFO-VGIC) mechanism. Weak, polarized, low-frequency fields force the ions (calcium, potassium, sodium) next to an ion channel’s voltage sensor to oscillate; because that force scales with the inverse cube of the distance involved, fields far below the stimulation threshold can still force the channel open, disrupting the cell’s ion balance and driving ROS overproduction (Nitric oxide and superoxide interact and produce peroxynitrite, a highly unstable cytotoxin that breaks down into free radicals). https://www.researchgate.net/publication/366088934 https://www.spandidos-publications.com/ijo/59/5/92 https://www.mdpi.com/1422-0067/22/18/10041 https://www.frontiersin.org/journals/public-health/articles/10.3389/fpubh.2025.1585441/full https://pmc.ncbi.nlm.nih.gov/articles/PMC3772193/ 3. Evidence of oxidative stress, in vivo, in humans from ELF-EMF There are many studies, and the strongest are occupational, which applies to the 49ers situation. 115 power-plant workers vs. 145 office controls. Serum malondialdehyde (MDA, the standard lipid-peroxidation marker), superoxide dismutase, and catalase were all significantly higher in the exposed group, and the markers rose with increasing field exposure. https://journals.sagepub.com/doi/abs/10.3233/WOR-203244 A follow-up where they reversed the oxidative stress in power plant workers. A double-blind randomized controlled trial: 91 power-plant workers given vitamin E, vitamin C, both, or placebo for 90 days. The antioxidant groups showed reduced lipid peroxidation and raised antioxidant capacity versus controls. https://pubmed.ncbi.nlm.nih.gov/32191586/ A spot-welder study: 46 welders occupationally exposed at 50 Hz, showed significantly altered red-blood-cell antioxidant enzyme activity and concluded ELF-MF “might act as an oxidative stressor… even at the recommended levels of exposure.” https://pubmed.ncbi.nlm.nih.gov/18504600/ A substation-specific study found oxidative stress and DNA damage https://pubmed.ncbi.nlm.nih.gov/24460415/ 4. Oxidative stress degrades collagen This half isn’t controversial at all. Oxidative stress activates the matrix metalloproteinases (MMPs) that break collagen down and suppresses its synthesis. Here are three example studies: Siwik et al. 2001: Oxidative stress raises MMPs and lowers collagen synthesis in cardiac fibroblasts. https://pubmed.ncbi.nlm.nih.gov/11121376/ Fisher et al. 2009: Collagen fragmentation drives oxidative stress and elevates MMP-1 in aged human skin. https://pmc.ncbi.nlm.nih.gov/articles/PMC2631323/ Varani et al. 2006: Decreased collagen production in oxidatively aged skin. https://pubmed.ncbi.nlm.nih.gov/16723701/ 5. What about the study showing improved collagen synthesis I’m glad you asked this question, and I’m bummed we didn’t get to it in the interview because it is a great question, and very important to understand. Superficially it may appear to be a refutation of my theory, but I would argue that it actually supports the underlying argument. That study used a short, high-intensity pulsed dose: therapeutic-PEMF, the same type of field used clinically to stimulate bone and tissue healing. The reason this works is because it triggers the very same biological pathways that can lead to oxidative stress. The exposure still stimulates ROS production, but done at a controlled dosage, for a limited duration it has a different effect. The cell reads the ROS as a warning signal and it upregulates its antioxidant defenses, and mounts a repair/proliferation response. The therapy is then stopped before the cell gets overwhelmed. That is essentially a hormetic response: a small dose of a stressor producing a beneficial adaptation. Two things follow: At the very least, this means the field is biologically active, which by itself undercuts the regulatory claim that these fields are inert below their thresholds. There is a wealth of literature on PEMF (pulsed EMF) bone regeneration and calcium channel signalling (which is the second mechanims in section one). Here is one. https://www.nature.com/articles/srep13856 At best, it leads us straight to my actual concern, which is that under chronic, chaotic and unregulated exposure, the cell’s antioxidant capacity gets overwhelmed, resulting in oxidative stress. There are plentiful examples of things that are beneficial at controlled doses, but harmful at uncontrolled doses. Excecise is one obvious, uncontroversial example. Botox is perhaps a more interesting example. 6. What about a study that shows EMF causing collagen degradation in humans? As far as I am aware there is not a single study showing EMF-driven oxidative stress degrading collagen in a human, in vivo, or in human tendon in a lab. There are studies involving isolated fibroblasts though, which secrete collagen. The most relevant one showed that human fetal scleral fibroblasts exposed to 50 Hz ELF-EMF showed a significant decrease in collagen synthesis and that MMP-2 expression was upregulated, which is the exact mechanism I described in section 2. https://pmc.ncbi.nlm.nih.gov/articles/PMC3626379/ That’s it! Thanks again for the interview. Best, Peter Anthony Cowan Environmental Health · Wellness Tech · Researcher & Journalist Publisher & Editor, Living Energy Bio: petercowan.comSocial: X · Instagram · TikTokApp: sunlightis.lifePhone: [redacted]
Max Verstappen Reveals What Went Wrong in Baku Qualifying
The Dutchman reveals that the internal combustion engine stopped working correctly from Q1 causing a loss of half a second and a chain of electrical failures. He trusts in changing the unit without penalty and aspires to the podium from eighth place.
UW Professor Releases New Edition of Teaching Book for New Engineering
Steven Barrett, a University of Wyoming professor of electrical and computer engineering, has released a new edition of his book “A Little Book on Teaching: A Beginner’s Guide for Educators of Enginee
Debate about data centers emerges in Donalds-Jolly gubernatorial race
Grassroots opposition to AI infrastructure because of its huge demand on local water supplies and the electrical grid had been growing more pointed since early this year, turning into an issue David Jolly and the Florida Democratic Party are using to attack Republican Byron Donalds in the Florida gubernatorial race.
In 1879, Edwin Hall discovered an electrical effect thought to need a perpendicular magnetic field; 147 years later, scientists have shown it can work with the field in-plane
For more than a century, the Hall effect has been taught with a simple picture that electricity flows through a material, a magnetic field pushes the moving charges sideways, and a voltage appears across the material. Now, scientists have found a way to make that familiar phenomenon work in a direction once thought impossible.
Daldrop Opens for Business in Southern Oswego County
$10 Million Facility in the L. Michael Treadwell Oswego County Industrial Park marks the largest expansion outside of Germany in the company’s 73-year history By Stefan Yablonski [caption id=attachment_11076 align=alignright width=450] Daldrop SBB CEO Jens Daldrop addresses attendees at the 2025 groundbreaking for the project. Daldrop also chairs the advisory board of Germany-based Daldrop Group.[/caption] A new era of cleanroom technology is underway in Central New York. The Daldrop Group’s advanced manufacturing facility and U.S. headquarters is physically built within the L. Michael Treadwell Oswego County Industrial Park. This industrial park is located in the town of Schroeppel. It marks the largest expansion outside of Germany in the company’s 73-year history. Daldrop SBB is based in Neckartailfingen, Germany. It is a global supplier of cleanroom technology, primarily to the pharmaceutical industry. It designs and builds advanced cleanroom environments for the pharmaceutical, biotechnology and medical technology industries. It nvested $10 million in the new project. “We broke ground in 2025; we were under construction all winter. We just opened this spring, early spring,” said Benjamin Morrow, operations manager and control. The company consolidated sites in Salina and DeWitt into the industrial park in Schroeppel, Morrow added. “The next move here is to maximize every square inch of this facility and then we are already looking at the expansion. So, it is more capital investment on equipment — definitely higher-end automation in additional equipment so we can produce more components and then to support the ever-growing base in North America,” Morrow continued. “We are the headquarters for service, maintenance and spare parts. So as Daldrop has more and more installations, they need more and more service, maintenance and spare parts. So that will come out of this facility as well — it already is.” “As a global leader in GMP (global manufacturing support) pharmaceutical cleanrooms for decades, I am very proud to bring manufacturing jobs to Upstate New York,” said Mike Sullivan, president of Daldrop US operations. Key to choosing Southern Oswego County [caption id=attachment_11077 align=alignright width=450] Daldrop SBB at the L. Michael Treadwell Oswego County Industrial Park when the company announced the start of construction.[/caption] Sullivan said that the selection of the Schroeppel industrial park was mainly due to the help of Operation Oswego County and two people in the organization. “Prior to being purchased by Daldrop International from the Stuttgart region of Germany, Vince Bongio was a founding partner in SBB Inc. as well as our head of engineering. We based out of Syracuse due to Vince’s skills in HVAC and the manufacturing capabilities found in Syracuse,” said Sullivan. Bongio moved to Syracuse from California in the 1970s to work in Carrier’s Industrial Division of Large-Scale Petrochemical Refrigeration. Next, he advanced to General Electric’s TV Tube Plant where he got into cleanrooms ,leading to his role of head of engineering for Clestra Cleanrooms where he met Sullivan, their New England distributor. “Vince Bongio is a phenomenal engineer. Formerly of Carrier, he grew up in California and went to Cal Poly,” Sullivan explained. “Carrier hired him right out of college and he moved to Syracuse. He is the reason we are in Syracuse today. He is retiring this year. We are very proud and his legacy is having brought Daldrop to Syracuse.” In 2000, Sullivan, Bazinet, Bongio Inc (SBB) was formed with engineering and manufacturing, based in Syracuse, and sales and construction based in Massachusetts as it is today. “SBB Inc. started in Syracuse. I had a design–build contracting firm out of Massachusetts that was primarily doing all the new technologies coming out of MIT,” Sullivan said. “I started a manufacturing side. A big thing for cleanrooms is the HVAC. Most cleanroom suppliers are architecturally focused people. The strength in Syracuse is HVAC. So, SBB developed with me running sales and construction out of Massachusetts and manufacturing out of Syracuse.” “Daldrop wanted to have a relationship in the States and of those who approached us, they were the only ones who really understood HVAC. So, we were the right fit for them. We did a joint venture focused out of Massachusetts from 2012 to 2018 leveraging their technologies,” Sullivan explained. “The commitment was if we brought their product to the States, we would do that if they built it here. “The pieces that had to be in place to make the investment, they wanted to acquire us, we were great with that. If you looked at business recommendations the general guidance was to build in a low labor area — something like North Carolina — but Syracuse had a strong background in HVAC and we chose Syracuse and Oswego County to be our headquarters in the States. So, it is built off of history, technology and the existing supply chain — bringing jobs back to the area.” During the initial discussions with Daldrop about coming to the U.S., SBB agreed to sell under the conditions Daldrop would manufacture in the U.S. There are many areas that offer incentives and economic packages, but the strength of HVAC expertise and skilled manufacturing was a big part of the discussions for site selection. Coming home [caption id=attachment_11078 align=alignright width=451] Construction moves forward in March at the L. Michael Treadwell Oswego County Industrial Park.[/caption] The second key person to building in Oswego County is Ben Morrow, Sullivan added. “Ben has been working with Daldrop SBB for more than 12 years and has advanced to COO of manufacturing and engineering. Ben grew up in Phoenix, so building a factory for the Germany company in Phoenix is a strong success for both his community and the appreciation of Ben’s skills as a team leader,” Sullivan said. “I went to high school in Phoenix. So, this is like full circle for me. It’s a small world,” Morrow said. “I hadn’t been back to Phoenix since graduation. This is one of the properties that John Trimble of C&S, he is the former president of C&S, he just retired, suggested. He and I were very good personal friends. John was from Mexico and I was from Phoenix. We knew each other from high school. And the architect of this building, Ed Smart of smartDESIGN Architecture in Batavia — I went to high school with him. So, this was a project that’s full circle a coming home kind of thing. The three of us knew each other — kind of like it was meant to be. Very serendipitous.” Schroeppel was one option for Daldrop to consider; the original intent was just to get a warehouse to store some product, he added. The facility is Daldrop’s largest outside of their native country. Total payroll at the facility will be approximately $2.4 million once fully staffed. “Here is 32,000 square feet and we plan to expand and put in an additional 10,000 square feet,” Morrow said. “We have 17.5 acres. We can put at least three more facilities here, just on this property. The master plan submitted for the current building is the first of possible three buildings on the campus.” “If we can find the right people and advance the production according to the plan, we should be able to grow for the next decade. One of the first jobs we filled was our new HR manager, with a primary focus posting and filling new positions,” Sullivan said. Stop the exodus, start hiring [caption id=attachment_11080 align=alignright width=452] Principals at the local Daldrop SBB headquarters, from left: Ben Morrow, Mike Sullivan and Jens Daldrop.[/caption] “I have been coming to Syracuse for 30 years. One of the things I had a hard time watching was the exodus of factories. One of the toughest things is to watch it with my partners’ kids who had to move away for jobs. It is important for us to give opportunity where people’s kids don’t have to leave the area to get work,” Sullivan said. “My responsibility is to find people who have skill sets that want to work and then I have to build opportunity for that work to happen. “After years of watching companies and Vince’s three sons all move out of the areas to get jobs, it is important to us to provide opportunities for the Syracuse region and help grow our company. We have been hiring for our new factory and will continue for the next few years.” “We are hiring and will continue to hire. Currently we have about 19 on staff right now,” Morrow said. “We expect to grow that by about 10 to 15 in the next 12 to 18 months or so. We are at 19 currently — one in the wings. It’s been great being able to hire locally. All these folks that we’ve been hiring, they all live within a few miles from here.” “We hired someone this past week (end of August). She grew up in the area, raised a family and is working down in Florida. She just took a job with us so she can move back and be with her family. We will be moving her back and she should be starting in October. We are very happy to see this happen,” Sullivan said. “I feel strongly about having a spot for the kids to not have to move out of the area. It is better to have people moving into the area.” Currently, Daldrop SBB has openings for finance manager, COO of construction and delivery, as well as mechanical, electrical designers and Revit modelers, construction managers, commissioning agents and many other skills that are needed. Along with Daldrop’s reputation in life science cleanrooms, there is a strong history in semiconductor, electronics, glass, photonics, aerospace and other markets. This may be helpful with any new technologies building in the market such as the Micron expansion and the support network, Sullivan said. “We acquired this property and closed on it two months before any announcement from Micron. It is serendipitous that they’re right down the street from us,” Morrow added. “Everybody started thinking ‘you guys are supporting Micron.’ We were here first. That is not a goal of ours. We may or may not … they are talking to us; it is an opportunity.” The long run [caption id=attachment_11079 align=alignright width=450] Benjamin Morrow, operations manager and control at Daldlrop, speaks during a recent ribbon-cutting event in Schroeppel.[/caption] “Long term, we will expand the Phoenix facility,” Sullivan said. “We built our facility with a campus approach. Sustainability is big. We designed our rooms to be more sustainable. Our building has no gas lines for heat. We put geothermal wells in the ground. We put heat pumps in for heating and cooling out of those wells and we put a large layer of solar panels up on the roof. We worked with National Grid for metering. Our building is a high efficiency model. We upgraded all the instillation and the glass filtering. So, it is a very green building. We will have a very minimal carbon footprint. It also adheres to LEED (Leadership in Energy and Environmental Design) construction standards.” “We are a bunch of HVAC engineers. We did a large scale geothermal and spent the money up front because we knew it made sense in the business sense in the environmental sense and sustainability,” Morrow said. “We have insulated metal panels on walls and roof; we are an envelope from the exterior.” Daldrop, as a global player, has a strong culture of sustainability that is found in all its products including the new facility. The building has been designed with (sixteen) 400-foot deep geothermal wells, high efficiency construction methods, approximately 70 kilowatt solar photovoltaic panels, electric vehicle chargers and 26% recycled content. “Daldrop thinks of long-term investing,” Sullivan said. “On the roof, photovoltaic panels supplement our power. Over half the energy that I use is coming from the sun. We have chargers up front for employee electric vehicles. This place is built to last. This slab that we are walking on, normal buildings are four inches, some go to six inches, we are nine inches all the way through — except where the heavy equipment is — that is 10 to 12 inches thick, solid concrete. It allows us to reconfigure for whatever type of equipment we want to bring in,” Morrow said. “We are authorized by Underwriters Laboratory to self-certify so we don’t need to have an inspector come out and recertify. We get audited often, but we certify our own electronics. The control system in this building is rather high-end. Our thermostat in every room is zoned, independent. We analyze the data; incorporate it with our solar panels.” “There is a lot of competition for people to work. It’s not just about how much salary they are going to make — it’s about the work environment, the ability for stability. We want to make sure our employees have the best environment to work in,” Morrow added. Similarities “One of the reasons I believe why Daldrop chose this area, Phoenix in particular, is because it is a village, a river-based village. Neckartailfingen in Germany where Daldrop is based is also a river-based village, manufacturing community. So, there is a lot of similarities — that smalltown feel,” Morrow said. “We have a lot of connections through multiple employees that lead back to Carrier, also. Everything came together, the timing everything.” “We are thankful for all the economic development support. Everyone has been helping make this happen. So, keep it up, it is working, that is all I got to say, Sullivan said. “If you look at historical industrial manufacturing, this region has skills that have been un-utilized. The northern industrial region has a lot of skills that if we can tap before they go away, we can leverage them. That is what we are trying to do. You’d be surprised at the supply chain left behind from Carrier — that supply chain is still there.” “Operation Oswego County has been fantastic,” Morrow added. “I can’t say enough good things about that group.” What Is Cleanroom Technology Cleanroom technology is a system of specialized engineering, filtration and operational controls used to maintain an extremely low concentration of airborne particles, microbes and chemical vapors. How It Works • Air Filtration: Uses HEPA or ULPA filters to remove 99.97% of tiny particles down to 0.3 microns. • Airflow Control: Directs air in a steady, unidirectional (laminar) or filtered turbulent pattern to push dust away from work areas. • Environmental Regulation: Maintains precise control over temperature, humidity and positive air pressure to block outside air leaks. • Specialized Attire: Requires personnel to wear full-body garments (“bunny suits”), gloves and masks to stop human shedding
Busani named director of Optical Science and Engineering
Tito Busani, an associate professor in the department of electrical and computer engineering, has been named the new director of the Optical Science and Engineering program at The University of New Mexico.
TEEMA global science park plan takes shape with Mexico leading
The Taiwan Electrical and Electronic Manufacturers' Association (TEEMA) is moving ahead with its global science park strategy, and Mexico's Sonora has emerged as the leading candidate for an early launch, TEEMA chairman Young Liu said before the group's 27th general assembly on May 15, 2026. Liu said Sonora has the strongest chance of becoming the first site because talks began earliest there and field inspections have already been carried out three times, putting it well ahead of other candidate locations.
UT Researchers in Electrical Engineering and Computer Science Receive NSF CAREER Awards
Two researchers at the University of Tennessee, Knoxville, have received 2026 National Science Foundation CAREER awards.
U.S. Embassy Supports Tunisian Business Delegation at 2026 SelectUSA Investment Summit - U.S. Embassy in Tunisia
U.S. EMBASSY SUPPORTS TUNISIAN BUSINESS DELEGATION AT 2026 SELECTUSA INVESTMENT SUMMIT The SelectUSA Investment Summit is the premier U.S. investment event, connecting thousands of investors, companies, economic development organizations, and industry experts to make deals happen. Media Note TUNIS, May 5, 2026 – U.S. Embassy Tunis is pleased to support a delegation of 11 Tunisian companies traveling to the United States to participate in the 2026 SelectUSA Investment Summit at National Harbor, Maryland, May 3-6, 2026. The Summit is an opportunity for these dynamic entrepreneurs to establish new connections and explore business and investment opportunities in the United States. This year, three Tunisian women entrepreneurs and members of the delegation representing Spiraw and Sotetel were accepted into the Select Global Women in Tech year-long mentoring program which will kick off at the summit. Since 2022, more than 50 Tunisian entrepreneurs in fields ranging from e-gaming, robotics, software engineering, coding, online fashion, and green tech have participated in SelectUSA Investment Summits, where they have taken their businesses to the next level. Hosted by the U.S. Department of Commerce, the SelectUSA Investment Summit is a one-stop shop for companies considering expanding to the United States and provides economic development organizations (EDOs) with the opportunity to meet directly with international companies to facilitate investment deals. Since inception, the SelectUSA Investment Summit has attracted tens of thousands of companies and economic development representatives, generating over $250 billion in new investment projects that support more than 125,000 jobs across the United States and its territories. The previous SelectUSA Investment Summit saw record-breaking numbers with more than 5,500 participants, including EDOs from 54 U.S. states and territories and over 2,700 business investors from 100+ countries, including Tunisia. The following Tunisian businesses will take part in this year’s SelectUSA delegation: AquaDeep – Revolutionizes aquaculture with AI-powered monitoring solutions, including a real-time larva counting system and a SaaS platform for environmental monitoring. The company is expanding operations across Tunisia, Europe, Africa, and the United States. Bouraoui Group – Specializes in event venues, hospitality experiences, innovative real estate development, and technology driven customer solutions. The business develops experience- focused and tech enabled lifestyle destinations that combine entertainment, culture, retail, and smart services, and is seeking international partners to co-develop hospitality, PropTech, smart retail, and experiential digital projects. Digital Cook – Builds HR and recruitment software solutions, including HRMS, ATS, and custom tools that streamline hiring, employee management, and talent development. It provides custom software, system integration, and scalable HR platforms for SMEs, large enterprises, and recruitment agencies seeking efficient, user-friendly ways to manage their workforce and improve recruitment. El Kanaouet – Provides high-quality and low-cost hydraulic infrastructure for the supply and distribution of drinking water. The company manufactures prestressed concrete structures based on current technological developments in the field and trends in integrated and digitalized management. El Kanaouet aims to enter the U.S. market with its production of centrifugal prestressed concrete pipes and other technical products and services. Fluoink Nanotechnologies – A deep‑tech startup developing next‑generation antimicrobial additives for paints, coatings, and industrial materials, enabling everyday surfaces to act as long‑lasting barriers against harmful bacteria and pathogens without changing their appearance or performance. Mare Custos – A subsea robotics company specializing in ROV-based underwater inspection services for offshore energy, ports, and marine infrastructure, using high-precision imaging, PAUT, and NDT to inspect structures in challenging conditions. SmartMed SA – A fast-growing digital health company operating in Tunisia, Algeria, and Morocco, offering an integrated ecosystem that helps patients book appointments (MedPro), enables clinics to digitize workflows and EMRs (MedLink), and supports targeted digital marketing for healthcare and pharma (MedAds). With millions of appointments and users, SmartMed has become a leading e-health platform in North Africa. Sototel – Builds telecommunications networks and services, including fixed, radio, and mobile networks. Sototel focuses on technological innovation and continuous improvement, providing high-value-added digital solutions. SOTUPRIN HGE – Specializes in manufacturing household electrical appliances under the brand HGE and OEM. Expanded from the local market to North Africa, Central Africa, the Middle East, and Europe. Spiraw by Food4Future – Designs and manufactures smart, AI-powered cultivation systems allowing individuals and businesses to grow fresh, highly nutritious food – starting with spirulina – directly at the point of consumption. Combining patented hardware, controlled-environment agriculture, and a connected app with an AI assistant, Spiraw aims to decentralize food production and create a new category at the intersection of agri-tech, consumer health, and smart home ecosystems. WaterSec (Istidama) – A climate-tech startup that uses IoT, AI, and smart sensors to help high consumption facilities (such as industries, hotels, and commercial buildings) monitor water use in real time, detect leaks, and optimize consumption. The company’s digital platform turns raw water data into alerts and actionable insights, making water management more transparent, proactive, and sustainable. Learn more about the SelectUSA Investment Summit at https://www.selectusasummit.us/. Follow live developments from the summit on X at https://x.com/SelectUSA.
Eaton to Merge Mobility Business With Dana in $10B Deal
The separation of the division will allow Eaton to focus on its electrical and aerospace businesses, which are benefiting from the AI-driven data center boom
Electrical Trade Attracts New Workers; Small Business Optimism Dips in August
WARREN, Ohio – Women are finding a growing place in the electrical trades, with apprenticeship programs in the Mahoning Valley reporting increased interest and enrollment. Young apprentices are gaining experience across residential, commercial and industrial work while preparing for careers in the field.
Men in NJ use tape and electrical cables to rob, sexually assault victims: court docs
NEW JERSEY (PIX11) – Police report that six men, including at least one who is gang-affiliated, have been charged with robbery and sexual assault in Edgewater, New Jersey, according to court docume…
Hoover East Sports Park reopens after $4.1M electrical overhaul
HOOVER, Ala. (WBMA) — Hoover East Sports Park is back open after a major electrical overhaul that shut down parts of the facility for more than a year.City lead
Engineering, Computer Science Faculty Earn Writing Mentorship Award
The Faculty Development Center’s Writing Across the Curriculum program recognized Cal State Fullerton faculty members Yoonsook Choi and Kanika Sood as the 2026 WAC Student Writing Mentorship Award recipients. Choi, professor of electrical and computer engineering, has been a faculty member at CSUF since 2014. He earned his Ph.D. in electrical engineering with a specialization […]
Montrose business targeted twice in less than a week in copper wire theft attempts
A Houston dessert shop owner says her business was targeted twice in less than a week by people trying to steal copper wiring. Doorbell camera video shows both of the incidents — leaving her with electrical damage, a power outage and thousands of dollars in lost inventory.
A new strategy enables precise fabrication of nanoporous carbon structures
Nanoporous carbon materials have attracted significant interest for applications in lightweight structural materials, microdevices, and bio-integrated systems due to their low density, chemical stability, electrical conductivity, and tunable mechanical properties. However, existing fabrication approaches often struggle to simultaneously achieve precise patterning, controllable porosity, and desirable mechanical performance. A research team led by Professor Min Qiu at Westlake University has developed a new fabrication strategy, termed Mix-ice lithography (Mix-IL), that enables direct construction of nanoporous carbon structures with tunable pore architectures and complex geometries. The study has been published in Science Bulletin.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Lights On: Burundi Hospital’s Maternal Health Unit Powered by Solar Energy
The monitors beep as doctors prepare for a cesarean. The suction machine and the bed warmer are arranged for the incoming baby. Unexpectedly, the lights go out, followed by all of the electrical me…
What Makes a Trailblazer: TSTC graduate always dreamed of business ownership
What do dyslexia, jewelry and an angry mother all have in common? Give up? They all put Mathew on the path to business ownership. Mathew Joseph is a graduate from Texas State Technical College’s Industrial Electrical Technician (now Advanced Manufacturing – Industrial Maintenance) program. He is also the owner and president of C3 Industrial Technologies…
Nearly $17 million headed to Wayland to power up business park
The Steuben County IDA will extend a 34.5kV electrical line six miles from the Meyer substation to the 152-acre business park.
UToledo To Celebrate Expansion of Health Science Campus Solar Array
The expansion increases the array’s nameplate capacity from 330 to 750 kilowatts, more than doubling its expected annual electrical production.
Scientists Turned Off Consciousness in Rats. Then Their Brains Started Going Wild.
Electrical activity that was fine-tuned in waking brains grew more chaotic under anesthesia.