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Business Beat: Residence Inn in Longview nears opening - Longview News-Journal
A new 100-suite Residence Inn by Marriott in Longview is preparing to welcome guests. Located at 3661 Estes Parkway, the extended-stay hotel is owned by Palisades Hospitality. It was developed […]
WHO recognizes healthy, innovative cities across the Western Pacific Region
Nine Healthy City champions from across the World Health Organization (WHO) Western Pacific Region received special recognition at an awarding ceremony during the 11th Global Conference of the Alliance for Healthy Cities in Sydney, Australia.The WHO Regional Office for the Western Pacific has presented the Healthy Cities Recognition Awards every two years since 2004 to celebrate innovative and impactful city-led initiatives that improve the health and well-being of urban populations.Eight cities received awards for their best practices, and one National Forum received the WHO Regional Director’s Special Award in recognition of its long-standing leadership in advancing the Healthy Cities movement.Awardees were selected through a rigorous evaluation process and recognized for demonstrating measurable, innovative and sustainable approaches to health challenges faced by cities.Remarking on the significance of the awards, Dr Huong Tran, Director of the Division of Health Promotion, Disease Prevention and Control at the Regional Office, said that, “There is no single blueprint for a healthy city. What works in one context may need to be adapted to another. But by sharing our experiences, including what worked, what was challenging, and what we learnt along the way, we can help one another move faster and further.”Award-winning cities and initiativesThis year's awards recognize outstanding city-led initiatives that have demonstrated measurable impact, innovation and sustainability in advancing health initiatives for urban populations.Baguio City (Philippines) – Data for equity: informing action, improving healthDr Donnabel Tubera-Panes, City Epidemiologist – Medical Officer IV of the Health Services Office accepted the award on behalf of Baguio City. Photo credit: Maria BoyadgisBaguio City was recognized for developing a pioneering Livability Index that provides village-level data across all 128 barangays (villages), enabling evidence-based planning and more equitable allocation of resources. By integrating community participation and institutionalizing the index within city planning and budgeting processes, the city has demonstrated how data can drive action to reduce health and social inequities.Eunpyeong-gu (Seoul, Republic of Korea) – Communities living in vulnerable situations: advancing health equity through community engagementVice Mayor Honourable Ahn Hyoung Jun accepted the award on behalf of Eunpyeong-gu. Photo credit: Maria BoyadgisEunpyeong-gu was recognized for its inclusive health equity programme supporting vulnerable populations, including isolated older adults and LGBTQI+ communities. Through peer-led community networks, social cooperatives and inclusive service design, the district has strengthened access to care, promoted social inclusion and advanced community ownership of health initiatives.Madiun City (Indonesia) – Adapting and mitigating climate-related crises: building heat resilience and preventing flood-related health risksMs Yuni Dwi Purwani, Secretary General of the National Forum for Indonesian Healthy Cities/Regencies, accepted the award on behalf of Madiun City. Photo credit: Maria BoyadgisMadiun City was recognized for its SUPERMIE (Sustainable Public Environmental Management Initiative) – a community-based environmental governance model that addresses urban flooding, climate resilience and environmental sustainability. The initiative contributed to reductions in flood-prone areas, greenhouse gas emissions, diarrhoeal disease and dengue fever, while at the same time improving food security through neighbourhood food gardens. The programme has already been replicated in 15 cities and regencies across Indonesia.Macao Special Administrative Region (China) – Protecting communities from tobacco and alcohol-related harms: tackling commercial drivers of riskDr LO Iek Long, Director of the Health Bureau, Macao SAR, China accepted the award on behalf of Macao. Photo credit: Maria BoyadgisMacao SAR was recognized for implementing a comprehensive and integrated approach to tobacco and alcohol control. Through legislation, monitoring systems, enforcement, public awareness campaigns and multisectoral partnerships, the programme has strengthened protection against major risk factors for noncommunicable diseases and established a model that is highly transferable to other urban settings.Phnom Penh Capital City (Cambodia) – Safe, active and health-enabling transport: advancing health and reducing inequities in urban mobilityH.E. Khoung Sreng, Governor of Phnom Penh Capital City accepted the award on behalf of Phnom Penh Capital City. Photo credit: Maria BoyadgisPhnom Penh received the award for its Safe School Zone Project, which combines infrastructure improvements, speed management, enforcement, education and stakeholder engagement to protect children and communities. The initiative has demonstrated measurable reductions in crashes and vehicle speeds while providing a scalable model for safer urban mobility across the country.Quezon City (Philippines) – Transforming food environments: addressing policy, market and urban design drivers of health and nutritionMs Jirah Asa M. Sideco, Chief of the Nutrition Section of the Quezon City Health Department accepted the award on behalf of Quezon City. Photo credit: Maria BoyadgisQuezon City was recognized for its public food procurement policy that promotes healthier diets through government-run institutions and feeding programmes. Supported by strong policy frameworks and monitoring systems, the initiative improves access to nutritious food for vulnerable populations while serving as a benchmark for other local governments.Samarinda City (Indonesia) – Preventing violence and promoting gender equality: transforming urban systems, norms and spaces Mrs Rinda Wahyuni, Chairperson of Samarinda Healthy City Forum accepted the award on behalf of Samarinda City. Photo credit: Maria BoyadgisSamarinda City was recognized for its multisectoral approach to preventing violence and advancing gender equality. Responding to local evidence on violence against women and children, the city has positioned violence prevention as a public health priority, bringing together health services, schools, social welfare institutions, law enforcement, civil society and community leaders to strengthen prevention, reporting, survivor-centred support and legal protection. Through inclusive policies, community engagement and sustainable city financing, Samarinda has developed a locally owned and scalable model for creating safer, more equitable and inclusive urban communities.Singapore – Age-friendly cities: transforming systems to bridge generations for a healthier tomorrowDr Tan Weng Mooi, Director, Integrated Health Promotion, accepted the award on behalf of Singapore. Photo credit: Maria BoyadgisSingapore received recognition for its Healthy Precinct Framework, which translates national healthy ageing priorities into neighbourhood-level action. The initiative integrates preventive care, social support, service coordination and age-friendly environments while actively engaging older persons, caregivers and community organizations. Its expansion across multiple precincts demonstrates its scalability and long-term sustainability.WHO Regional Director’s Special AwardNational Forum for Indonesian Healthy Cities/Regencies (Indonesia)Ms Yuni Dwi Purwani, Secretary General of the National Forum for Indonesian Healthy Cities/Regencies, accepted the award on behalf of the National Forum. Photo credit: Maria BoyadgisThe WHO Regional Director's Special Award was presented to the National Forum for Indonesian Healthy Cities/Regencies (FKKSI) in recognition of its long-standing leadership in advancing the Healthy Cities movement across Indonesia. As a national platform bringing together local governments, communities, academia and civil society, FKKSI has played a critical role in promoting collaboration, capacity-building, knowledge exchange and advocacy. Its efforts have strengthened and institutionalized healthy urban development nationwide and established a model for multisectoral engagement in the Region. Healthy Cities for allThe 2026 Healthy Cities Recognition Awards highlight how cities can lead transformative action on health by addressing climate change, inequity, ageing, nutrition, mobility, social inclusion, violence prevention and the commercial determinants of health. The recognized initiatives demonstrate that local governments, communities and partners can work together to create healthier, safer and more resilient urban environments for everyone. As urban populations continue to grow across the Western Pacific Region, WHO remains committed to supporting cities in advancing health, equity and sustainable development through the Healthy Cities approach and the Alliance for Healthy Cities. ###Note to editorsSince 2004, the WHO Healthy Cities Recognition Awards have provided a platform for cities to share innovative and effective approaches to improving health and well-being. The awards recognize achievements in areas including climate resilience, healthy ageing, health equity, gender equality, tobacco and alcohol control, urban mobility, nutrition and data-driven governance. In 2026, more than 150 submissions were received from cities and local governments across the Western Pacific Region. The titles and affiliations of awardees are presented as they were at the time the photo was taken.______________For more information, or to arrange media interviews, contact: WHO Regional Office for the Western Pacific: wprocom@who.int
New quantum chip taps into weird quasiparticles to get qubits to communicate over long distances
Scientists have developed a new type of architecture for quantum computing chips, and it could pave the way for machines capable of large-scale processing.
Robert E. Hall wins Nobel Memorial Prize in Economic Sciences
The professor of economics and senior fellow at the Hoover Institution, emeritus, developed models that help governments and central banks respond to economic volatility.
AI midwife seeks to fill gaps in Zimbabwe's maternal health care
With public health services stretched thin, women in Zimbabwe sometimes struggle to access reliable information about pregnancy and childbirth. A locally developed app aims to answer their questions…
The hidden math of Alzheimer's could point to new treatments
Mathematics may hold unexpected clues to understanding Alzheimer’s disease. Scientists have developed a model showing how common metals like copper and zinc may influence the buildup of proteins associated with the disease, while also exploring possible ways to stop the process. The findings could help researchers identify promising strategies for preventing harmful plaque formation.
Daldrop Opens for Business in Southern Oswego County
$10 Million Facility in the L. Michael Treadwell Oswego County Industrial Park marks the largest expansion outside of Germany in the company’s 73-year history By Stefan Yablonski [caption id=attachment_11076 align=alignright width=450] Daldrop SBB CEO Jens Daldrop addresses attendees at the 2025 groundbreaking for the project. Daldrop also chairs the advisory board of Germany-based Daldrop Group.[/caption] A new era of cleanroom technology is underway in Central New York. The Daldrop Group’s advanced manufacturing facility and U.S. headquarters is physically built within the L. Michael Treadwell Oswego County Industrial Park. This industrial park is located in the town of Schroeppel. It marks the largest expansion outside of Germany in the company’s 73-year history. Daldrop SBB is based in Neckartailfingen, Germany. It is a global supplier of cleanroom technology, primarily to the pharmaceutical industry. It designs and builds advanced cleanroom environments for the pharmaceutical, biotechnology and medical technology industries. It nvested $10 million in the new project. “We broke ground in 2025; we were under construction all winter. We just opened this spring, early spring,” said Benjamin Morrow, operations manager and control. The company consolidated sites in Salina and DeWitt into the industrial park in Schroeppel, Morrow added. “The next move here is to maximize every square inch of this facility and then we are already looking at the expansion. So, it is more capital investment on equipment — definitely higher-end automation in additional equipment so we can produce more components and then to support the ever-growing base in North America,” Morrow continued. “We are the headquarters for service, maintenance and spare parts. So as Daldrop has more and more installations, they need more and more service, maintenance and spare parts. So that will come out of this facility as well — it already is.” “As a global leader in GMP (global manufacturing support) pharmaceutical cleanrooms for decades, I am very proud to bring manufacturing jobs to Upstate New York,” said Mike Sullivan, president of Daldrop US operations. Key to choosing Southern Oswego County [caption id=attachment_11077 align=alignright width=450] Daldrop SBB at the L. Michael Treadwell Oswego County Industrial Park when the company announced the start of construction.[/caption] Sullivan said that the selection of the Schroeppel industrial park was mainly due to the help of Operation Oswego County and two people in the organization. “Prior to being purchased by Daldrop International from the Stuttgart region of Germany, Vince Bongio was a founding partner in SBB Inc. as well as our head of engineering. We based out of Syracuse due to Vince’s skills in HVAC and the manufacturing capabilities found in Syracuse,” said Sullivan. Bongio moved to Syracuse from California in the 1970s to work in Carrier’s Industrial Division of Large-Scale Petrochemical Refrigeration. Next, he advanced to General Electric’s TV Tube Plant where he got into cleanrooms ,leading to his role of head of engineering for Clestra Cleanrooms where he met Sullivan, their New England distributor. “Vince Bongio is a phenomenal engineer. Formerly of Carrier, he grew up in California and went to Cal Poly,” Sullivan explained. “Carrier hired him right out of college and he moved to Syracuse. He is the reason we are in Syracuse today. He is retiring this year. We are very proud and his legacy is having brought Daldrop to Syracuse.” In 2000, Sullivan, Bazinet, Bongio Inc (SBB) was formed with engineering and manufacturing, based in Syracuse, and sales and construction based in Massachusetts as it is today. “SBB Inc. started in Syracuse. I had a design–build contracting firm out of Massachusetts that was primarily doing all the new technologies coming out of MIT,” Sullivan said. “I started a manufacturing side. A big thing for cleanrooms is the HVAC. Most cleanroom suppliers are architecturally focused people. The strength in Syracuse is HVAC. So, SBB developed with me running sales and construction out of Massachusetts and manufacturing out of Syracuse.” “Daldrop wanted to have a relationship in the States and of those who approached us, they were the only ones who really understood HVAC. So, we were the right fit for them. We did a joint venture focused out of Massachusetts from 2012 to 2018 leveraging their technologies,” Sullivan explained. “The commitment was if we brought their product to the States, we would do that if they built it here. “The pieces that had to be in place to make the investment, they wanted to acquire us, we were great with that. If you looked at business recommendations the general guidance was to build in a low labor area — something like North Carolina — but Syracuse had a strong background in HVAC and we chose Syracuse and Oswego County to be our headquarters in the States. So, it is built off of history, technology and the existing supply chain — bringing jobs back to the area.” During the initial discussions with Daldrop about coming to the U.S., SBB agreed to sell under the conditions Daldrop would manufacture in the U.S. There are many areas that offer incentives and economic packages, but the strength of HVAC expertise and skilled manufacturing was a big part of the discussions for site selection. Coming home [caption id=attachment_11078 align=alignright width=451] Construction moves forward in March at the L. Michael Treadwell Oswego County Industrial Park.[/caption] The second key person to building in Oswego County is Ben Morrow, Sullivan added. “Ben has been working with Daldrop SBB for more than 12 years and has advanced to COO of manufacturing and engineering. Ben grew up in Phoenix, so building a factory for the Germany company in Phoenix is a strong success for both his community and the appreciation of Ben’s skills as a team leader,” Sullivan said. “I went to high school in Phoenix. So, this is like full circle for me. It’s a small world,” Morrow said. “I hadn’t been back to Phoenix since graduation. This is one of the properties that John Trimble of C&S, he is the former president of C&S, he just retired, suggested. He and I were very good personal friends. John was from Mexico and I was from Phoenix. We knew each other from high school. And the architect of this building, Ed Smart of smartDESIGN Architecture in Batavia — I went to high school with him. So, this was a project that’s full circle a coming home kind of thing. The three of us knew each other — kind of like it was meant to be. Very serendipitous.” Schroeppel was one option for Daldrop to consider; the original intent was just to get a warehouse to store some product, he added. The facility is Daldrop’s largest outside of their native country. Total payroll at the facility will be approximately $2.4 million once fully staffed. “Here is 32,000 square feet and we plan to expand and put in an additional 10,000 square feet,” Morrow said. “We have 17.5 acres. We can put at least three more facilities here, just on this property. The master plan submitted for the current building is the first of possible three buildings on the campus.” “If we can find the right people and advance the production according to the plan, we should be able to grow for the next decade. One of the first jobs we filled was our new HR manager, with a primary focus posting and filling new positions,” Sullivan said. Stop the exodus, start hiring [caption id=attachment_11080 align=alignright width=452] Principals at the local Daldrop SBB headquarters, from left: Ben Morrow, Mike Sullivan and Jens Daldrop.[/caption] “I have been coming to Syracuse for 30 years. One of the things I had a hard time watching was the exodus of factories. One of the toughest things is to watch it with my partners’ kids who had to move away for jobs. It is important for us to give opportunity where people’s kids don’t have to leave the area to get work,” Sullivan said. “My responsibility is to find people who have skill sets that want to work and then I have to build opportunity for that work to happen. “After years of watching companies and Vince’s three sons all move out of the areas to get jobs, it is important to us to provide opportunities for the Syracuse region and help grow our company. We have been hiring for our new factory and will continue for the next few years.” “We are hiring and will continue to hire. Currently we have about 19 on staff right now,” Morrow said. “We expect to grow that by about 10 to 15 in the next 12 to 18 months or so. We are at 19 currently — one in the wings. It’s been great being able to hire locally. All these folks that we’ve been hiring, they all live within a few miles from here.” “We hired someone this past week (end of August). She grew up in the area, raised a family and is working down in Florida. She just took a job with us so she can move back and be with her family. We will be moving her back and she should be starting in October. We are very happy to see this happen,” Sullivan said. “I feel strongly about having a spot for the kids to not have to move out of the area. It is better to have people moving into the area.” Currently, Daldrop SBB has openings for finance manager, COO of construction and delivery, as well as mechanical, electrical designers and Revit modelers, construction managers, commissioning agents and many other skills that are needed. Along with Daldrop’s reputation in life science cleanrooms, there is a strong history in semiconductor, electronics, glass, photonics, aerospace and other markets. This may be helpful with any new technologies building in the market such as the Micron expansion and the support network, Sullivan said. “We acquired this property and closed on it two months before any announcement from Micron. It is serendipitous that they’re right down the street from us,” Morrow added. “Everybody started thinking ‘you guys are supporting Micron.’ We were here first. That is not a goal of ours. We may or may not … they are talking to us; it is an opportunity.” The long run [caption id=attachment_11079 align=alignright width=450] Benjamin Morrow, operations manager and control at Daldlrop, speaks during a recent ribbon-cutting event in Schroeppel.[/caption] “Long term, we will expand the Phoenix facility,” Sullivan said. “We built our facility with a campus approach. Sustainability is big. We designed our rooms to be more sustainable. Our building has no gas lines for heat. We put geothermal wells in the ground. We put heat pumps in for heating and cooling out of those wells and we put a large layer of solar panels up on the roof. We worked with National Grid for metering. Our building is a high efficiency model. We upgraded all the instillation and the glass filtering. So, it is a very green building. We will have a very minimal carbon footprint. It also adheres to LEED (Leadership in Energy and Environmental Design) construction standards.” “We are a bunch of HVAC engineers. We did a large scale geothermal and spent the money up front because we knew it made sense in the business sense in the environmental sense and sustainability,” Morrow said. “We have insulated metal panels on walls and roof; we are an envelope from the exterior.” Daldrop, as a global player, has a strong culture of sustainability that is found in all its products including the new facility. The building has been designed with (sixteen) 400-foot deep geothermal wells, high efficiency construction methods, approximately 70 kilowatt solar photovoltaic panels, electric vehicle chargers and 26% recycled content. “Daldrop thinks of long-term investing,” Sullivan said. “On the roof, photovoltaic panels supplement our power. Over half the energy that I use is coming from the sun. We have chargers up front for employee electric vehicles. This place is built to last. This slab that we are walking on, normal buildings are four inches, some go to six inches, we are nine inches all the way through — except where the heavy equipment is — that is 10 to 12 inches thick, solid concrete. It allows us to reconfigure for whatever type of equipment we want to bring in,” Morrow said. “We are authorized by Underwriters Laboratory to self-certify so we don’t need to have an inspector come out and recertify. We get audited often, but we certify our own electronics. The control system in this building is rather high-end. Our thermostat in every room is zoned, independent. We analyze the data; incorporate it with our solar panels.” “There is a lot of competition for people to work. It’s not just about how much salary they are going to make — it’s about the work environment, the ability for stability. We want to make sure our employees have the best environment to work in,” Morrow added. Similarities “One of the reasons I believe why Daldrop chose this area, Phoenix in particular, is because it is a village, a river-based village. Neckartailfingen in Germany where Daldrop is based is also a river-based village, manufacturing community. So, there is a lot of similarities — that smalltown feel,” Morrow said. “We have a lot of connections through multiple employees that lead back to Carrier, also. Everything came together, the timing everything.” “We are thankful for all the economic development support. Everyone has been helping make this happen. So, keep it up, it is working, that is all I got to say, Sullivan said. “If you look at historical industrial manufacturing, this region has skills that have been un-utilized. The northern industrial region has a lot of skills that if we can tap before they go away, we can leverage them. That is what we are trying to do. You’d be surprised at the supply chain left behind from Carrier — that supply chain is still there.” “Operation Oswego County has been fantastic,” Morrow added. “I can’t say enough good things about that group.” What Is Cleanroom Technology Cleanroom technology is a system of specialized engineering, filtration and operational controls used to maintain an extremely low concentration of airborne particles, microbes and chemical vapors. How It Works • Air Filtration: Uses HEPA or ULPA filters to remove 99.97% of tiny particles down to 0.3 microns. • Airflow Control: Directs air in a steady, unidirectional (laminar) or filtered turbulent pattern to push dust away from work areas. • Environmental Regulation: Maintains precise control over temperature, humidity and positive air pressure to block outside air leaks. • Specialized Attire: Requires personnel to wear full-body garments (“bunny suits”), gloves and masks to stop human shedding
Apple Launches 'Apple Home Collection' With Cameras, Lock, Thermostats and More
Apple today debuted the "Apple Home Collection," an accessory lineup it developed with LG Electronics and Schneider Electric. The collection includes cameras, thermostats, temperature sensors, and a door lock. All of the home devices are designed to work with the HomeView, Apple's new home hub. Apple says each one is made from premium materials with a minimal aesthetic.
Scientists supercharge plant immunity to boost its natural defense response
Nanyang Technological University, Singapore (NTU Singapore) scientists have developed a way to "supercharge" a plant's natural immune response.
Official: Man Utd sign ‘excellent’ Liverpool winger
Manchester United have announced the capture of Isaac Konde, a promising teenager who developed at Liverpool’s academy.The 16-year-old is a winger blessed with ‘blistering’ pace and ‘excellent...
Florida State University doctoral student transforms ‘forever chemicals' research into commercial possibilities through NSF's I-Corps program
A Florida State University doctoral student has developed a new approach to destroying “forever chemicals” and is now taking the technology beyond the
Social determinants of health may increase kidney failure risk after critical illness
New research indicates that certain individual- and neighborhood-level social determinants of health may increase the risk of developing post-discharge kidney failure in patients who developed acute kidney injury while in intensive care.
New Wellness Concierge tool supports campus mental health
Wake Forest faculty, staff and students now have a new tool to help increase access to mental health resources through Wayhaven’s Wellness Concierge. Developed by Christine Nicodemus (’15), the Wellness Concierge has been in a pilot phase since the summer and is now available [...]
Business center opening in spring | Nassau County Record, Callahan, Florida
Britney Fletcher West NCR Reporter A new industrial development along U.S. 1 will focus on small business and is expected to open in spring 2027. The Callahan Business Center, being developed by Doors and Spaces Industrial and Jacksonville-based Valentino Properties, will include 15 small-bay industrial spaces designed to accommodate businesses that have outgrown homes, garages, storage units or other smaller workspaces.
Would you trust AI to calculate your true 'biological age'?
Scientists have developed various AI tools to measure people's biological ages. Would you use one?
California Could Become First State to Ban Quartz Countertop Production Amid Health Concerns
California could soon become the first state to ban quartz countertops amid mounting health concerns. California’s Occupational Safety and Health Standards Board is expected to pass a ban as emergency regulation this October, after a rising number of workers have developed silicosis and other lung illnesses.
Fayetteville apartments reopen after renovation
Wilson Park Apartments recently reopened as The Wilson Parkview Condos after a renovation. Fayetteville-based CJC Development redeveloped the two-story, 20-unit property at 15 W. Prospect St., overlooking Wilson Park in...
U.S. Department of Health and Human Services (HHS) Recommends Science-Based Thresholds to Target Dangerous Enhanced Kratom Products
Kratom products credit: CDPH DEA takes action based on updated recommendation from HHS October 11, 2026 - WASHINGTON - On Friday, the U.S. Department of Health and Human Services relesed the following: The U.S. Department of Health and Human Services (HHS) provided a new recommendation to the Drug Enforcement Administration (DEA) that establishes science-based thresholds for 7-hydroxymitragynine (7-OH) and mitragynine pseudoindoxyl (MGPI), potent opioid compounds associated with products marketed as kratom. The Department of Justice today announced that DEA issued new Notices of Intent reflecting HHS’ updated scientific analysis and recommendations, including a new Notice of Intent for 7-OH and MGPI incorporating HHS’ recommended concentration and ratio thresholds. Following a review of available scientific data and comments, HHS Assistant Secretary for Health Admiral Brian Christine, M.D., recommended that DEA use concentration or ratio-based thresholds to determine which products containing 7-OH and MGPI are subject to Schedule I control for purposes of temporary scheduling of these substances under the Controlled Substances Act. The recommendation is designed to target concentrated or chemically altered products while distinguishing them from natural botanical kratom products, which may contain trace amounts of 7-OH and MGPI. “We are drawing a clear line between natural kratom and dangerous, enhanced opioid products,” said HHS Secretary Robert F. Kennedy, Jr. “We listened to the public, followed the science, and developed a clear recommended threshold for temporary scheduling that targets concentrated 7-OH and MGPI without sweeping natural botanical kratom into Schedule I. The Trump Administration will continue taking decisive action against dangerous products that fuel addiction while making sure our policies are grounded in rigorous science.” Under the recommendation, 7-OH and MGPI would be controlled in Schedule I for purposes of temporary scheduling when either substance alone, or their combined amount when both are present: Exceeds 1 milligram per gram in solid powders, encapsulated material, or other solid forms, or exceeds 1 milligram per milliliter in liquid preparations; or When the mass of mitragynine present divided by the mass of 7-OH, or MGPI, or the combined amount of 7-OH and MGPI if both present, is less than 100. The ratio-based approach reflects the alkaloid composition of natural kratom products and provides a way to identify products intentionally enhanced or concentrated with 7-OH or MGPI. Available scientific data indicate that 7-OH occurs naturally in botanical kratom at relatively low or trace levels, while some evidence reviewed by FDA suggests MGPI may also occur at trace levels in some natural or kratom-derived products. FDA's scientific review found that 7-OH is substantially more potent than morphine in preclinical studies, with available data indicating approximately two to nine times greater potency depending on the study. FDA also identified evidence supporting a meaningful risk of opioid-like physical dependence and withdrawal from MGPI. “Our recommendation gives DEA a scientifically supportable framework to distinguish natural botanical kratom from products that have been concentrated or manipulated to deliver dangerous levels of potent opioid compounds,” said Assistant Secretary for Health Admiral Brian Christine, M.D. “This approach allows us to focus on the products that pose the greatest threat to public health.” In July 2025, following an FDA scientific and medical evaluation, HHS recommended that 7-OH above a specified threshold be placed in Schedule I of the Controlled Substances Act. In July 2026, DEA announced its intent to temporarily schedule 7-OH above a specified threshold, and HHS simultaneously sought public comment on the proposed threshold. DEA subsequently temporarily placed MGPI and two synthetic 7-OH derivatives, MGM-15 and MGM-16, in Schedule I. Since then, questions have emerged about how scheduling could affect natural botanical kratom products potentially containing trace amounts of MGPI. The new HHS recommendation responds to those concerns by providing DEA with a more precise threshold based on both the concentration of 7-OH and MGPI and their relationship to mitragynine, the predominant alkaloid in kratom. HHS and FDA will continue working with DEA to protect Americans from dangerous concentrated and synthetic opioid products while ensuring federal policy is grounded in the best available science. Source: HHS
Apple unveils Apple Home Collection smart home accessories developed with LG and Schneider
Apple today confirmed that it is working with at least two third-party companies to develop a new lineup of smart home accessories, including cameras, thermostats, and a smart lock.
Plague is stoppable. The next health threat may not be.
The word plague is scary. Centuries ago, the Black Death killed tens of millions of people and changed the course of history. Plague still kills people around the world, and the word still evokes catastrophe. New fears of plague surfaced on October 2, when a lab worker in Irkutsk, Russia, died of pneumonia. Reports suggested that she may have contracted plague through a laboratory exposure. Understandably, people were alarmed. On October 7, the World Health Organization called for the Russian Federation to be transparent about what it knew. WHO issued an update on October 10. Russian authorities told WHO that testing did not identify plague and that investigations found no laboratory release. WHO said confidence in its risk assessment remained limited and that further clinical, epidemiological, and laboratory information was needed. The cause of the woman’s illness remains unknown, and WHO says a laboratory-associated exposure cannot be excluded. As I explained in a recent interview, this incident is very unlikely to lead to a pandemic. Plague is still active, including in the U.S., which sees a handful of cases each year. But it is a disease we can prevent and treat. Plague doesn’t spread readily, and it responds to antibiotics. The standard response—isolate the patient, trace contacts, and administer antibiotics and monitor for symptoms among contacts for seven days—works. We have even planned for antibiotic-resistant plague. At CDC, we developed a playbook for antibiotic-resistant plague and ran exercises on how to find and stop it. CDC guidance anticipates engineered resistance and recommends two different classes of antibiotics if there’s reason to suspect it. There is no evidence that resistance—or even confirmed plague—is involved in this incident. We have thought through how to address plague, but we’re not ready for the next major health threat that emerges from a lab or from animal spillover to humans. What should concern people is how little stands between the world and the next pathogen to get loose. Since peak COVID, epidemic preparedness has fallen off the political agenda, but the risk is greater than ever. More labs handle dangerous pathogens with more ways to make those pathogens deadlier, and more people live and work in close contact with animals. There are actions we can take now: We need better lab safety in every country. The number of labs that work with dangerous pathogens has increased worldwide over two decades, but there’s no enforceable international standard and no inspection regime; the Biological Weapons Convention, fifty years on, still has no verification mechanism. Labs that study dangerous germs need strong safety systems, training, and oversight. We need to reduce spillover events. Three in four emerging human infections start in animals, and there’s a lot we can do to reduce spillover risk, but the world is doing very little of it. Live-animal markets are one place to act. For instance, closing live-bird markets helped control H7N9 influenza in China. Reducing opportunities for people to encounter infected animals can prevent infections before they become outbreaks. In The Formula for Better Health, which is now out in paperback along with the hardcover, Kindle, and audiobook versions, I argue that labs do too many risky experiments with too many dangerous pathogens in too many institutions, and that every experiment should first answer one basic question: Is the likely benefit greater than the risk? Spillover risk can also be reduced: In the book, I discuss how Brazil cut its deforestation rate by 70% from 2004 to 2012 while increasing agricultural production and reducing risky contact between people and forest animals. We need faster detection and response. Delay costs lives. Strong surveillance, good labs, and trained responders can turn a single case into a small cluster of infections instead of an epidemic. Resolve to Save Lives has worked for nearly a decade to help countries find and stop outbreaks faster. The 7-1-7 target, which Resolve to Save Lives developed with partners in Uganda and elsewhere, provides a clear standard: detect within 7 days, notify within 1 day and complete all essential early response actions within 7 days. In Uganda’s Kasese district, for example, a review of a measles outbreak using 7-1-7 identified shortages of accessible funds, fuel, and vehicles that delayed the response. District leaders established funds they could access quickly. When, a few months later, the Crimean-Congo hemorrhagic fever appeared, the district detected it in three days, notified authorities in one, and mounted an effective response in two. Only one case was confirmed, and the patient survived. Because funds were available before the emergency, authorities were prepared and able to act. This kind of preparation can’t wait until the next crisis begins. Plague is an old disease we that know how to stop. The next threat may be harder to recognize, harder to treat, and easier to spread. Safer labs, less risk of spillover, and faster outbreak detection and response need sustained investment now, while we still have time to prevent the next emergency. Share
Small-town athletes making it big at Nebraska
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Credit: Matt Bradbury October 5, 2026 - By Isabella Backman - Anxiety disorders are the most common mental health challenges in youth. Left untreated, they can disrupt the lives of both children and their families. The good news is that with intervention, most children will overcome these conditions. Across Yale School of Medicine, scientists are working to understand anxiety at every level, from common anxious behaviors to molecular biomarkers in the brain. They are using their findings to develop and disseminate new evidence-based treatments for childhood anxiety. Today, the go-to treatment for childhood anxiety disorders is cognitive behavioral therapy (CBT). This is a form of psychotherapy that teaches children skills for confronting anxious thoughts and helps them practice managing situations that cause anxiety. While it is the gold-standard treatment backed by considerable scientific evidence, up to 50% of children will not see sufficient benefit from CBT alone. Wendy Silverman, PhD, Alfred A. Messer Professor in the Child Study Center, co-directs the Anxiety and Mood Disorders Program alongside Eli Lebowitz, PhD, associate professor in the Child Study Center. One of their main interests is learning how to improve outcomes beyond CBT. “We’re developing cutting-edge, research-based knowledge that can reduce the suffering that anxiety causes children and their families,” says Silverman. Changing parent behavior YSM experts are investigating how to improve CBT outcomes for children by involving the parents. Silverman’s research has uncovered two main components of parent intervention that improve childhood anxiety: not enabling children to completely avoid the things that make them anxious and taking steps to enhance their autonomy. Parents may unintentionally reinforce their child’s anxiety by allowing them to avoid what makes them anxious. They also may unintentionally limit the children’s sense of autonomy by being overly intrusive. “One of the things that we take pride in is that we’ve focused on trying to understand what parents need to do, and to test our ideas and see if changing the parents’ behaviors is enhancing the effects of CBT,” Silverman says. “Our findings thus far suggest that they do." As much as CBT can be helpful, it can also be challenging to get one’s child to do the necessary steps for CBT to work. This is one important reason why Lebowitz created a novel intervention program for parents named Supportive Parenting for Anxious Childhood Emotions (SPACE). Existing intervention programs often teach parents to act as therapists for their child, such as training them on how to practice breathing exercises. “It makes sense, but this doesn’t work very well in practice,” says Lebowitz. “And part of the reason, I think, is that it’s not easy to get your kid to do things, especially if they’re not excited about doing it.” SPACE is unique because it focuses entirely on parent involvement and changing parental behavior—children are not involved in the sessions. For example, parents learn how to use supportive messages that convey confidence that their child can tolerate and manage distress. “It might sound like a parent saying to a child, ‘I get that this is really hard for you, but I know that you can handle it,’” Lebowitz says. The program also works with parents to identify the ways in which they are accommodating anxious behaviors. “We’ll pick one thing that parents are doing that is an accommodation and help them make a detailed plan for how they’re going to change that,” Lebowitz explains. Treating Anxiety in Children and Adolescents Much of the existing research on SPACE has focused on parents of children under age 14. Ongoing studies are now exploring its use with parents of older teens. “Both anxiety and accommodation can interfere with normative developmental shifts during the teen years, including increased autonomy and individuation from parents,” says Rebecca Etkin, PhD, associate research scientist in the Child Study Center. “In this sense, SPACE may be particularly well-suited for anxious teens and their parents. We want to see whether it is effective during this distinct developmental window.” Unfortunately, many families in need of CBT face barriers, including limited availability of services and geographic constraints. One way to improve access is digital interventions. Silverman and her team are developing an evidence-based digitized intervention program for parents that they can access directly from their computer or smart phone. “The work we’re doing will be one of the very few parent interventions that is digitized and importantly tested for effectiveness,” she says. Creating interventions for anxiety-related challenges Silverman and Lebowitz recently received a generous gift to develop and test other interventions that help parents reduce other child anxiety-related behavioral and emotional difficulties, such as restrictive eating and unexplained somatic symptoms. One of these projects in particular focuses on understanding the risks of social media and its potential benefits, including offering a sense of connection. “A lot of research has focused on the idea that social media is harmful and the less of it the better,” says Lebowitz. “But we actually see is that this is not quite right—there are negatives, but there are also positives. So, we’re trying to get a little bit more nuanced of a picture.” The team is working with teens with social anxiety and their parents over an extended period to better understand their social media habits and how their anxiety levels affect engagement with different platforms. The teens will answer questions sent to an app on their phones about mood and social media usage in an effort to capture emotional responses as they unfold. “We hope to develop interventions that can help make the best of social media while protecting against the more problematic effects,” Lebowitz says. The brain’s role in anxiety Researchers are also testing therapies to address anxiety at the neurological and molecular levels. In collaboration with Dylan Gee, PhD, professor of psychology in Yale's Faculty of Arts and Sciences, and Hilary Blumberg, MD, John and Hope Furth Professor of Psychiatric Neuroscience at Yale School of Medicine, Lebowitz and Silverman are using brain imaging to identify changes in a child’s brain before and after parents enroll in SPACE. In one study, children viewed anxiety-inducing images while undergoing magnetic resonance imaging (MRI); the researchers conducted scans with and without the children’s parents nearby. Before SPACE, children’s brains were better able to activate the regulatory circuitry needed to turn off an anxious response when their parents were nearby. But after SPACE, children could activate this circuitry even without the parent around. “As parents work on gradually reducing some of their accommodations, you can see a child get better at regulating their own fear system in the brain,” Lebowitz says. “It’s remarkable.” Research into the molecular underpinnings of anxiety can also inform new childhood anxiety treatments. In a recent study, Lebowitz, Silverman, and Flora Vaccarino, MD, Harris Professor in the Child Study Center, discovered that a protein known as fibroblast growth factor 2 (FGF2) could be protective from the toxic effects of stress. FGF2 levels in children and their parents were linked to the children’s risk of developing anxiety and depression, the study showed. The findings could help explain why some children who are exposed to early life trauma such as poverty or abuse are more prone to developing mental health disorders. And FGF2 could be a target for treatment. “This is very novel because it starts to give a clue to what is the molecular chain that connects those lived experiences to the actual psychological outcomes,” Lebowitz says. New ways to study and treat childhood anxiety Michael Crowley, PhD, associate professor in the Child Study Center, collaborates with Silverman and Lebowitz to study the role that attention plays in development and maintenance of childhood anxiety. There is a large body of research that shows that anxious children, like anxious adults, are prone to focus on threatening stimuli such as angry faces compared with neutral faces. This has led to innovative interventions that involve attention retraining. The idea is that if experts train children to look away from threatening stimuli, it may reduce their anxiety—especially children with social anxiety who are most prone to attend to threats. The researchers have just completed a clinical trial for attention retraining with 10- to 14-year-olds with social anxiety disorders and are currently analyzing the findings. Besides this innovative attention retraining research, as Crowly notes, “I like to design tasks that are engaging to kids,” Crowley says. “My goal is to assess something without the kids knowing what we are assessing.” With this goal in mind, Crowley has created a virtual game, named Boom, to study threat processing in children with anxiety disorders. The game is similar to that of hot potato—the child and three digital players take turns virtually passing a ball to each other’s gloves. At some point, the ball turns into a bomb, and as the bomb lands in each player’s glove, the outline of the glove turns yellow. The goal is to avoid having the bomb go off in your glove. What isn’t obvious is that the game is designed to measure different types of threatening stimuli, both ambiguous and direct. In the game, the direct threat occurs as the bomb is traveling towards your glove. The ambiguous threat is the yellow outlined glove as it is unknown where the bomb will travel next. While children play the game, Crowley’s team measures their brain activity using electroencephalography (EEG). The researchers have discovered that in kids with anxiety, the brain reacts more strongly to ambiguous threats than it does in their peers, but less strongly to direct threats. They believe that the initial abnormally large brain response to not knowing where the bomb is going impairs the brain's ability to properly respond when the threat is actually traveling the child’s way. “The brains of children with anxiety are unable to differentiate between threats you need to do something about and those that are not your problem.” Michael Crowley, PhD, develops innovative games for studying anxiety in children and adolescents.Credit: Matt Bradbury Based on these insights, Crowley hopes to study whether interventions like attention training could restore appropriate threat processing. Crowley’s team is also working on a test called the Balloon Risk Avoidance Task, which evaluates risk-taking and avoidance behaviors. It features a digital balloon that is full of air and about to burst. Kids have six seconds to let air out of the balloon. The more air they let out, the less risk they face that the balloon will pop. But at the same time, the balloon becomes less valuable as it deflates. “The more air you keep in the balloon, the more points you get,” Crowley explains. So far, the researchers have found that when the balloons pop unexpectedly, teens with social anxiety show distinct brain responses. Studying these responses can help psychologists understand the underlying pathways driving the various manifestations of anxiety. The genetics of anxiety When Thomas Fernandez, MD, associate professor in the Child Study Center and of psychiatry, was still in training, there was a lot of excitement about understanding the genetics associated with autism spectrum disorder. Since then, scientists have identified around 250 genes associated with autism. The genetic contribution to anxiety disorders, on the other hand, has historically received less attention. Anxiety is less heritable than autism, but the genetic contribution for anxiety disorders that emerge in childhood may be higher than for anxiety disorders overall. While scientists estimate the heritability of anxiety disorders in general to be around 30% to 50%, some studies suggest higher heritability for certain childhood-onset anxiety presentations. “I saw firsthand how researchers in the field went about finding vulnerability genes for autism,” Fernandez says. “So, we’re using a very similar playbook for childhood anxiety.” “I saw firsthand how researchers in the field went about finding vulnerability genes for autism. So, we’re using a very similar playbook for childhood anxiety.” Thomas Fernandez, MD Associate Professor In the Child Study Center and in Psychiatry Now, Fernandez and Emily Olfson, MD, PhD, assistant professor in the Child Study Center, are studying children and their parents to identify genetic changes that are present in the child but not the parents, known as “de novo mutations.” “All of us have some de novo mutations—maybe about 50 to 100 sprinkled throughout the genome,” Olfson says. “But when they occur within the coding regions of genes, they can be really disruptive.” Previous research shows that people with autism have higher rates of damaging de novo mutations than the general population. In 2022, Olfson, Lebowitz, Silverman, and Fernandez published a study on 68 children and their families that found that children with anxiety had similarly high levels of these mutations. Studying de novo mutations can help point the researchers to where they should be looking for genes associated with anxiety. “The end game is using the genes to steer us toward the right part of biology that we can then target to come up with better treatments,” Fernandez says. Building on those findings, the team is now studying more families to better understand how these de novo mutations, along with other genetic and environmental factors, shape pediatric anxiety disorders. They recently received a National Institutes of Health grant to enroll 750 new families over the next five years. Olfson is the principal investigator, with co-investigators Lebowitz, Fernandez, Silverman, and Shuangge Steven Ma, PhD, department chair and professor of biostatistics at Yale School of Public Health. Neurodevelopment, Risk Genes, and Mental Health Conditions - The Olfson Lab Joel Gelernter, MD, Foundations Fund Professor of Psychiatry, is interested in how different anxiety disorders differ genomically. “We are studying social phobia, panic disorder, and generalized anxiety disorder, working to understand why people differ in their risk to these specific anxiety disorders and evaluating various risk factors,” he says. Gelernter was recently involved in one of the largest studies to date of the genomics underlying anxiety disorder. The study included around 122,000 people with anxiety disorders and around 730,000 without. It found that some genetic differences associated with anxiety were linked to signaling that helps reduce overactivity in the nervous system. Many anxiety medications available today work by targeting this process. “It’s nice when the biology that you get out of a large genome-wide study ratifies things that we already know because that can help increase confidence in further findings from the study,” Gelernter says. Uncovering the neurobiology of psychiatric disorders John Krystal, MD, Robert L. McNeil, Jr. Professor of Translational Research and chair of the Department of Psychiatry, is interested in the neurobiology of psychiatric disorders, including post-traumatic stress disorder (PTSD), of which anxiety is a major symptom. In the late 1980s, Krystal’s team discovered that the drug yohimbine activated symptoms in patients with PTSD. “This was the first time we could link a specific biological mechanism to the symptoms of PTSD,” Krystal says. At the time, he adds, this finding was highly controversial. “A lot of people felt that PTSD was a purely psychological syndrome that didn’t have an underlying biology.” Since then, Krystal has dived deep into understanding the neurobiology of PTSD to learn how to better treat it. His team is evaluating the use of ketamine and psychedelics. These would be among the first treatments to be developed specifically for PTSD. They may also be applicable for other disorders including anxiety disorders, Krystal adds. An important gap in PTSD treatment is the absence of biological tests that inform how to best help patients manage their PTSD symptoms. A doctor doesn’t diagnose cancer based on how they feel. Rather, they use tests of the biology of the cancer to determine the best course of treatment. “And we can’t do that in any psychiatric disorder other than Alzheimer’s disease,” Krystal says. “But now we are building a foundation for this approach to the treatment of anxiety disorders for the first time.” Source: Yale School of Medicine
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