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From immigration to voting to education, the pointed politics of the deep freeze
There is nothing accidental or incidental about the freezing out of immigrant populations. In fact, across policy areas the “freezing” of populations is not only a prong but the point.
Business Briefcase: DSI unveils updated logo design
SHENANDOAH — The “Return to Prominence” revitalization group Downtown Shenandoah Inc. has unveiled a new logo, according to its September-October DSI Herald bulletin. “While our previous logo served us well for many years, it was time for a…
General Duffy's Waterhole goes up for sale in downtown Redmond
Owners of a downtown Redmond community gathering place, taphouse, food truck lot and live music and event space have listed it for sale after eight years in business. General Duffy’s […]
Bend cheesecake business launches vending machine
Little Slice of Hell Cheesecakes launched its vending machine of cheesecakes earlier this month at Midtown Yacht Club, giving Bend a new way to grab local, homemade cheesecakes on the […]
From climate change to the economy to healthcare, NH voters seek solutions with their ballots
Scott Thompson, a retired mechanic from Epsom, usually doesn’t vote in midterm elections, but after a GOP candidate for state representative showed up at his door he decided to make plans to vote on Tuesday.
A new strategy enables precise fabrication of nanoporous carbon structures
Nanoporous carbon materials have attracted significant interest for applications in lightweight structural materials, microdevices, and bio-integrated systems due to their low density, chemical stability, electrical conductivity, and tunable mechanical properties. However, existing fabrication approaches often struggle to simultaneously achieve precise patterning, controllable porosity, and desirable mechanical performance. A research team led by Professor Min Qiu at Westlake University has developed a new fabrication strategy, termed Mix-ice lithography (Mix-IL), that enables direct construction of nanoporous carbon structures with tunable pore architectures and complex geometries. The study has been published in Science Bulletin.
State Board OKs deficit spending for Boise State sports
One board member said it came down to two choices: Approve the $18 million plan or “basically put a bullet in Bronco sports.”
Commentary: Who would want the US to be run like a business?
When pushing for the United States to be run more like a business, please keep in mind that framework naturally conflates the populace with labor and public servants with bosses. […]
VIDEO: Inside an AI-powered lab trying to replace scientists
The Bulletin goes inside the lab to see how it works and ask whether AI can do science without scientists.
The jail is a hospital: 90 percent of inmates need physical, mental healthcare
Alexandria Vega, a behavioral health specialist in the Deschutes County Jail, transitions from cell to cell. In one, an inmate is suicidal. In another she provides formal therapy. For a […]
Commentary: Dancing with the W2 Stars reaches far beyond one evening of entertainment
Let me tell you the “why” behind a cheeky dance competition and your friend’s relentless hints for donations: Valley Residential Services, writes Sheila Hagar.
Bend's newest high school focuses on business and career tech education
Deschutes River High, having just opened its doors last month, is repositioning itself as the magnet high school for Bend-La Pine Schools. The school, on the prior Bend Tech Academy […]
GO-NORTH ‘cautiously optimistic’ ahead of federal rescoring of rural health program
When the federal government announced how much money it was giving New Hampshire as part of its Rural Health Transformation Program, Granite State leaders bragged that the state secured more funding than any other New England state.
The Iron Wall in Rabat: Why Morocco’s Political Shift Won’t Touch the Abraham Accords
As Fatima Ezzahra El Mansouri Takes the Helm as Morocco’s First Female Prime Minister, Israel’s Most Resilient North African Alliance Remains Bulletproof
Rumour: Killzone Project in Early Development, Probably a Remake
Bulletstorm dev People Can Fly linked
August Monthly Review: ChatGPT In Epic
Death, taxes, another frontier lab healthcare launch inspiring truly insane LinkedIn takes. As much as I want to stay away, I repeatedly am the crewman unplugging his ears whenever we pass these sirens. So it’s not the first and probably not the last time we dial up the typewriter rather than tie ourselves to the mast. The full blow-by-blow timeline: Health API Guy is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe The End of the Standalone PHR (Jan 8): ChatGPT Health arrives for consumers, at the time powered by b.well. I was bullish on the approach in that the best way for the PHR to finally solve distribution was to meet consumers were they already are (i.e. When Horizontal Meets Healthcare (Jan 9): OpenAI for Healthcare puts out the shingle for enterprises, with SharePoint ingestion standing in for the EHR integration the product actually needed. Another One: Anthropic’s Healthcare Debut (Jan 16): Claude's version, on HealthEx rails instead of b.well, with Agent Skills for FHIR development as the one true vertical-specific investment. ChatGPT for Clinicians: The Trap Sprung (Apr 24): OpenAI filled in the missing GTM middle with a free product for verified clinicians, effectively peeling the enterprise wrapper off ChatGPT for Healthcare and taking the PLG fight directly to OpenEvidence. OpenAI’s Second Attempt at Health (Jul 31): a relaunch of their patient specific app, now branded Health in ChatGPT, where the privacy partition came out, the connectors thinned, and b.well disappeared in favor of first-party FHIR work against a smaller network Beyond a Shingle So what was announced now? Today, we’re introducing a new electronic health record integration that brings authorized patient context from Epic into ChatGPT for Healthcare, along with the Healthcare Public Data plugin for direct, structured access to official healthcare datasets like PubMed, DailyMed, and CMS Coverage. Together, these capabilities bring ChatGPT closer to the systems and sources healthcare teams trust, while supporting the controls and compliance healthcare work requires. The core portfolio is unchanged from prior announcements we delineated and discussed (aside from the relaunch of patient-facing). Since trade publications still seem to be confusing them by using the wrong names: Enterprise sales motion: ChatGPT for Healthcare Protecting their core product / PLG: ChatGPT for Clinicians Consumer/patient-facing product: Health in ChatGPT So really, this is a feature release (specifically for ChatGPT for Healthcare when it comes to EHR integration). What’s cool about it, though, is that we are moving beyond just putting out a shingle. Everything in the January enterprise launch was horizontalizable: Horizontal tech companies thus generally start verticalization with their “putting out a shingle phase”. Telling the world you’re open for business as a horizontal tech company reliably attracts early inbound interest from buyers who are already trying to force-fit horizontal tools into domain-specific workflows and are eager for any signal that the vendor intends to support their use case more directly. Nothing was really vertical specific, which is exactly what you'd expect from the ultimate hypergrowth horizontal company dipping their toes into specific industries. But eventually you have to stop changing the sign on the door and start changing the product. Can you guess where the horizontal product was going to run out of road? This is the core dilemma writ large: verticalization requires differentiation, while scale economics of consumer and horizontal push toward unification. I’ve buried the lede so deep here it will be painful to some readers, but what should be shocking to no one is that my perspective is that EHR integration is the only path that meaningfully resolves this tension for ChatGPT for Healthcare. Integration with Microsoft Sharepoint is fine, but it is categorically insufficient for any product that hopes to influence clinical decision-making. SMART Money Well here we are, eight months later! Real vertical investment has begun, which surprised a few people. One friend in the industry messaged me: “Absolutely no way Epic gave ChatGPT API access.” Looking forensically at the announcements, the integration is notably read-only across appointment notes, laboratory results, medications, and specialist documentation. So while I’m not a betting man, I'd wager the house this is a SMART on FHIR launch: That sounds a lot like USCDI! The recommended path for the workflow they outline would be SMART on FHIR Their Health AI lead’s post is evocative of both standalone and EHR launch SMART, which another termed “ChartGPT” and “EHR Plugin” The implementation burden for SMART on FHIR is the lowest of the available integrative paths This is the team who literally did patient-facing SMART on FHIR with Epic last month Most importantly, if you’re a horizontal company, you generally still haven’t taken the full plunge and thus (overly) value reusability. SMART on FHIR is the logical compromise: healthcare-specific enough to matter, but standardized enough to reuse. Nobody Asked Judy Another friend asked “I thought they had to go to each health system, or did they go direct to Epic and now health systems opt in?” Given the trust paradigms in healthcare, this functionally cannot be Epic hoovering up all the data for OpenAI and shoving ChatGPT in their customers’ faces (or they would revolt). However, I do believe the aforementioned terrible coverage by TechCrunch and other outlets is probably responsible for that question, given the 325 million reference. When using FHIR as a business associate to an Epic customer, there is no EHR gatekeeping to speak of, as that isn’t how fhir.epic.com works: You register an app You pick your APIs You test against the sandbox APIs You list as “Ready for Production” Hospitals pick your app You test and go live with them Bluntly, nobody had to say yes or no in Verona (nor were they given the chance). Vendor Services (their next developer tier up that I doubt OpenAI is using quite yet in this initial release) certainly has contractual paperwork that some resent, but even there, the twin pressures of mounting antitrust and information blocking make outright gatekeeping increasingly fraught. My friend’s sentiment is, to me, representative of a broader industry neurosis, perhaps a sort of scar tissue of prior eras: people assume the gate is still there and never actually try the door. There are certainly other ways Epic (and any EHR) can put its thumb on the scale, but they are not so dumb as to stand in front of a federally mandated API and play bouncer at this exact moment in time. So I think they can and probably should go deeper, as this release is at best parity and at worst behind vertical-specific competition. OpenEvidence did a basic SMART launch with Sutter Health in February, allowing for more convenient evidence search by providers. They then add patient-context (the equivalent SMART on FHIR flow to what we see here) when Cedars-Sinai went enterprise-wide in May. UpToDate has four distinct applications across deeper workflows like patient engagement listed in Epic Showroom and announced a partnership with Epic to power Art at UGM Abridge and other ambient scribes have invested deeply into the deepest bidirectional clinical copilot workflow with integrations well beyond SMART on FHIR. In that light, the “Who is OpenAI primarily targeting here?” is clear. This release brings them into striking distance of OpenEvidence, but not the others quite yet. They are the only one of the three you can reach without building something truly Epic-specific. When will they go further? Competition is a great motivator to overcome the horizontal demons and start building things that can’t be reused: not across industries, not across EHRs, maybe not past the customer you built them for. That’s the price of actually verticalizing. The question is if and when OpenAI will be willing to pay it. Month in Review Here is the monthly review. As a reminder, this is a regular round-up of the month’s posts and other content to surface things you may have missed across regulation, litigation, interoperability, and beyond. AI assistance is used in these bullet summaries so I can focus on articles. Articles Published: None this month Video Content: The Information Exchange: Standards-based Thruple Edition (Aug 14): Back to school for us too, with Brad reporting in from the CMS Health Tech Ecosystem’s one year anniversary in DC. We get into the January CMS-0057 deadline, the fall rulemaking reading list, and why enrollment still keeps most apps off FHIR. The Information Exchange: Epic Dúnadan Edition (Aug 25): A UGM roundup with Ryan Brickner joining for the first time to check our takes against what the building actually thinks. Rangers, Ergo sitting on top of EHI, and a down-market lineup that needs some cuts. Regulatory: Stacked Deck, Bad Hand (Aug 05): ONC’s website refresh took the entire HIT Policy Committee record with it, so I rebuilt the archive and went looking for the regulatory capture story everyone assumes is buried in there. Stacking the deck and winning the hand turn out to be very different things. The Sixth Generation of Patient Access (Aug 19): A quick catalog of the five generations of patient access we’ve layered on since HIPAA, and the two candidates now competing to be the sixth. One is planned. The other is the market routing around the plan entirely. Court cases: Three Cases Walk Into a Docket (Aug 06): Two surprise settlements cleared the board in a single week, and then Judge Maddox dropped ninety-four pages on Vyne v. Henry Schein. The sleeper is a DMCA holding that makes direct-to-database a considerably riskier business model. Epic v. Health Gorilla: Into the MDL (Aug 10): Nine class actions are headed to Miami, and the Panel signaled it wants to bring the case that spawned them along too. That would leave Epic arguing the requests were obviously fraudulent in one courtroom and unknowable in the other. Amazon v. Perplexity: Agents Are Legalized! (Aug 11): The Ninth Circuit vacated the injunction against Comet, holding that the user is the one accessing the servers rather than the company that built the agent. A real win for agentic access, and a much narrower one than the headline suggests. Veeva v. Epic: Come At Me, Bro (Aug 26): Epic’s response brief wants the dismissal affirmed and, unusually, wants the opinion published as precedent. Buried in it is Epic’s own description of what its non-competes actually prohibit, which current and former employees should read closely. EHRs: The Contract Epic Would Never Sign Today (Aug 04): A 1999 SEC exhibit catches Epic licensing nearly its entire product line, Tapestry included, to the company that became TriZetto. The marketing services menu attached to it is the part that will make you blink. Forecast from Verona (Aug 07): The Epic Almanac makes one argument six different ways: the AI is only as good as the networks behind it. Emmie headlines, Art’s context stack is the most ambitious part, and Penny finally gets an autonomous coding date on the calendar. Works With Epic MyChart (Aug 17): Epic’s first new Showroom category since the death of Workshop certifies hardware instead of software, badge on the box and all. Made for iPhone, but for blood pressure cuffs, and rough news for anyone selling the RPM stack sitting in between. UGM Hot Takes 2026 (Aug 20): Everyone else covered the AI announcements, so I went after Savvy deleting the payment gateway, Rangers as Boost with the timer removed, and a down-market lineup with too many entries. Plus the Health Grid tidbits I cannot help myself on. MyChart Central Grows Up (Aug 24): Device data and Emmie turn Epic’s identity hub into a full consumer platform, which is both a logical answer to ChatGPT and a bit of a mistake. It also happens to be the best scraping target Epic has ever shipped. Industry Analysis: The Wrong Yardstick (Aug 12): Vertical software keeps getting judged against Superhuman and Notion, which is the wrong bar entirely. Your user is comparing your product to a whiteboard and forty phone calls before lunch. Primitives vs. Abstractions (Aug 27): Developers want building blocks, systems of record prefer to hand out business logic, and both sides have a real case. There’s no test from the outside that separates the engineering reason from the competitive one, which is why this keeps ending up in court. Cross-industry Comparisons: The Two Kinds of Platform Power (Aug 18): Attention power and record power are different problems that keep getting handed the same regulatory toolkit. Congress’s latest swing at Big Tech shows both what’s possible and where it falls apart. The Dogs of (Platform) War (Aug 21): A CourtListener alert turned up a property management fight with healthcare’s exact shape and none of the Cures Act. Shell prospects, ghost accounts, a notetaker bot that came back to haunt someone, and a lawyer arguing both sides of the same theory in two states. Fractals All the Way Down (Aug 31): Yardi dominates property management right up until you zoom into one segment, where AppFolio owns it outright and Yardi doesn’t appear at all. Where you draw the line around a B2B software market is about to decide an awful lot of cases. Other News: If Judy Had the Courage (Aug 13): A short eulogy for the era when software was allowed to look insane: WinAMP, bold colors, and everything the grey chatbot era has taken from us. External Media: Portland Monthly Health Tech Meetup: Erin O’Brien channeled my own feelings - maybe it’s just because it’s August and beautiful, but the monthly edition of the PDX Health community meetup was a ripper. Make sure to reach out if interested to join for the next one. STAT’s Coverage of Epic This Month: Brittany Trang of STAT did a fantastic job of breaking the FTC investigation that’s been lurking, as well as UGM related coverage, so I had to give her her wish of a meme. Fall Conferences: I’m pumped to be kicking off my fall conference season in NYC at Nabla Accelerate next month, which Chrissy provided the link to apply for. Here’s the rest of my schedule in case you want to meet up: Commonwell (Redwood Shores, CA): Oct 13-14 Open@Epic (Madison, WI): Oct 21-22 eHealthExchange (Austin, TX): Oct 27 Sequoia Project (Austin, TX): Oct 28-29 HLTH (Vegas): Nov 15-18 RSNA (Chicago): Nov 29-Dec 3 Posts I Liked: HTI-6 Should Unbundle API Certification: Josh Mandel makes the case that HTI-6 should split (g)(10) into separate authorization and data certifications, so a PACS or a genomics platform can certify only the role it actually performs. Imaging is the urgent example, but the structure solves a much bigger problem. On implementing ePrior Auth with Epic: Scott Rossignol’s field notes from a live ePrior Auth build on Epic, including the two app registrations nobody warns you about and the CPT mapping problem waiting at the end. CMS-0057 implementations are going to be such a beast. Healthcare point solutions are starting to look a lot like streaming services: Spencer Dorn runs the cable-to-streaming arc against health IT and lands squarely on the bundling half of the cycle. Bundling can be good! It can also be bad! Life is nuanced. Health API Guy is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Business Bulletin: Are those “Cloud storage is full” messages real?
If you receive an email warning appearing to be from a company you know and trust that states your online storage is full and your family photos, important documents and other files could soon be deleted ... would you click on the "fix" button?
“Big Cat Diaries”: A story about accompaniment and connection
Last week, the Magnuson Theatre hosted their performance of "Big Cat Dairies" inspired by a GU professor's experience in the Amazon rainforest.
Central Oregon farmers, ranchers to learn from visiting business school
Three Central Oregon producers will attend a nationally recognized business management school for farmers and ranchers, which will visit Bend during the last week of October. High Desert Food and […]
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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gamescom wrapped up last weekend, and it was bloody fantastic. It really felt like the industry had a spring in its step again. The show itself was BUZZING, with 368K attendees (+3% over last year), maxed-out exhibit space, and Opening Night Live pulling over 78M online views (+7.5%). Let’s have a look at the games at the event that brought in the most new Steam wishlists between August 23 and 30. One quick thing before we start, and stop me if you’ve heard this one before, but wishlists are NOT a barometer for launch sales (they’re bookmarks, not baskets is what we always say over here at Alinea). With that aside, wishlists are a nice gauge of hype, so let’s dive in. Witche(r)s and Warlocks take the top two spots The biggest game of the event (by new wishlists, anyways) wasn’t a game at all. It was an expansion. The Witcher 3: Wild Hunt’s upcoming expansion, Songs of the Past, nabbed 451K Steam wishlists by the end of the weekend. It’s a big example of something we bang on about constantly: proven IP with built-in fandom is the most powerful force in this market. But said IP can also ripple into other external success stories (more on that later!). Anyway, Songs of the Past debuted at Opening Night Live, and it’s the first Witcher 3 expansion in over a decade, landing next year after a full Witcher 3 remaster (free for existing owners!) arrives next month. The Witcher 3 has sold around 66M copies, and I’ll be one of those owners jumping back in to refresh myself on the core game (like there isn’t enough to play!), then play the expansion next year. This is all part of CDPR’s plan. The studio is clearly whetting everyone’s appetite for The Witcher 4 in 2028 via a classic bridge strategy. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Releasing a free 4K remaster next month – followed by a proper expansion in 2027 – keeps IP top-of-mind across a huge gap between content (games-wise, anyway). It kind of echoes Capcom’s evergreen catalogue strategy. And outsourcing co-development to Fool’s Theory (a studio led by trusted Witcher 3 veterans) keeps CDPR’s internal headcount focused on The Witcher 4. #2 by wishlists between Aug 23 and 30 went to another giant IP: Warlock: Dungeons & Dragons, published by Wizards of the Coast and developed by Invoke Studios (a team of ex-Far Cry, Watch Dogs, and Splinter Cell devs). It’s due to launch in 2027, and it looks brilliant so far. It’s a dark-fantasy open world with third-person spell-slinging. It’s a very Witcher-ish aesthetic. As you might expect, 48% of Warlock’s Steam wishlisters have played Baldur’s Gate 3, and 46% have played The Witcher 3. One to watch. For sure! Mash-ups: Anime GTA (!?) and a city-builder for kids (and adults) Ananta took #3 with 302K new wishlists. It’s an open-world game that looks like GTA and Persona had a baby. It was published by NetEase, developed by Naked Rain, and got a trailer at Opening Night Live. I got hands-on at the show, and it wears its influences openly; there’s literal web-slinging (very Spider-Man) and a LOAD of mini-games (Like a Dragon). It’s free-to-play and out in January. For Ananta, Naked Rain is taking the free-to-play, cosmetics-only route. That’s certainly a choice for a single-player open-world game. Without gacha mechanics driving high ARPU, Ananta is betting purely on top-of-funnel reach and long-term retention. This puts pressure on skin appeal when there’s no multiplayer lobby to flex in (although, co-op is reportedly coming later). Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Then there’s Lego Skylines (273K wishlists between Aug 23 and 30), which does exactly what it says on the tin. It’s a cosy Lego twist on the city-builder genre, as shallow or as deep as you fancy (five min quick sesh or ten-hour no-lifer session; latter for me). There’s some family-friendly stuff in there like couch co-op, which is only really viable on console. Iceflake Studios, which Paradox acquired back in 2020 is developing this one. So Paradox is probably looking for a family-friendly onramp to its rad Cities: Skylines games. The overlap there is plain, with 33% of Lego Skylines wishlisters having played Cities: Skylines and 16% Skylines II. There’s no doubt plenty of parents here (and uncles, ahem) planning to indoctrinate the next gen of city-builders. I’ll definitely be playing with my youngest nephew. This one could be big and educational. I’m very curious to see more. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Mature IP, new and old, rounds out the list As for the rest of the list of gamescom games by new wishlists between Aug 23 and 30: Heroes of Might & Magic III Remake got 189K new wishlists. It remakes the iconic 1999 turn-based-strategy classic in full 3D and 4K. It follows this year’s Heroes of Might & Magic: Olden Era (~1.8M copies sold, as per our estimates), and around a quarter of the III Remake wishlisters have played Olden Era, including 7% of them this month. Wardogs – a $40 PvP shooter – added another 146K to an already massive pile (nearly 1.6M total). It’s published by Team17 and made by Bulkhead. It plays somewhere between the tactical squad stuff of … Squad and the all-out-chaos battlefield of … Battlefield. It’s up to 100 players, and it’s out in about 10 days. It’s already pre-sold over 500K copies on Steam ($16.6M), boosted by a pre-order-only beta. It sold another 70K copies during gamescom, too. Afterworld managed 121K new wishlists. It’s a Paradox-made post-apocalyptic grand-strategy game, and it was announced at the show. It’s a departure from Paradox’s usual historical stuff, and the studio’s first new setting in over a decade. The Paradox purists are into it, with over half its wishlisters having played Hearts of Iron IV (19% this month) and 41% Crusader Kings III (17% this month). Metro 2039 got 110K during the show, tunnelling its total past 1.3M. Nearly 40% of wishlisters have played 2020’s Metro Exodus, the previous mainline title in the series. The Metro novels are Russian, dev 4A Games is Ukrainian, and it’s set in Moscow, so it’s unsurprising that – after the US (17.3% of wishlisters) – the next two countries are Russia (12.7%) and Ukraine (10.0%). The Blood of the Dawnwalker drew in (the blood of) 108K new wishlisters, now totalling an impressive 1.7M (at a $70 price point, though). It’s an open-world dark-fantasy action-RPG set in 14th-century Europe (with vampires!), made by some former Witcher devs at Rebel Wolves. Again, it shows. Over half of Blood of the Dawnwalker’s wishlisters have played The Witcher 3, and its #2 market is Poland, home of Rebel Wolves. That’s that hometown-hero effect we keep banging on about again! And Blood of the Dawnwalker plays very well, by the way. While it looks like a Witcher clone on the surface, it actually brings a lot to the table mechanics-wise. I love the whole time-as-a-currency spin on RPG gameplay. It gives the game a different, refreshing pace. Essentially, you start Blood of the Dawnwalker with a pool of 480 action points spread across 30 days and 30 nights. As for how the game performs, we’ll be posting some numbers next week, so hit subscribe below to get that in your inbox when it’s ready. Subscribe The Witcher’s legacy ripples Make no mistake: on a high level, this was The Witcher‘s gamescom. The #1 game by wishlisters was a Witcher 3 DLC. Warlock is clearly Witcher-inspired – as is Blood of the Dawnwalker, which was made by ex-Witcher devs. There was a lot of other cool stuff on the floor that we’ll no doubt be covering in subsequent newsletters, though! As always, wishlists went through the roof for sequels, remakes, DLC, and licensed IP. As always, though, these wishlists will likely convert to about 5% to 10% of launch-day buyers, with the probable exception of The Witcher DLC – the exception that proves the rule. Either way, we’ve got a nice, diverse list here – one that is very Witcher-y, Paradox-y, and – if you’re a fan of great games on Steam – a bloody good list. We even got a bunch of new IP to get excited for. Great gamescom! Even if we are still processing that unfathomable number of mini Kölsch beers! One more thing: GTA 6 broke the internet (again) Move aside, Spider-Man and The Odyssey (I love you both, really). But the decade’s defining entertainment zeitgeist is round the corner. Unless you’ve been living under a rock, you’ll know that Rockstar dropped an extended look at GTA 6 last week. It was INSANE, the most impressed I’ve ever been by a showcase like this. You can see the budget seeping through every second of the extended look, and this level of game is unobtainable for any other publisher. Everyone’s going nuts, and rightly so. GTA 6 is out in holiday 2026, and it’ll be the biggest entertainment release ever, full stop. For those without a PS5 or Xbox Series console, a $500-$900 console is a big ask in this economy, but GTA will pull a lot of last-generation-console fence sitters over the current-gen fence either way: The autumn timing puts GTA 6 on (digital) shelves for the holidays, meaning a PS5 or Xbox (let’s be honest, mostly the former) will be on many a Christmas and Hanukkah list. Demand will outweigh the struggling supply, though, and PS5 Pros are already sold out and being sold at a markup via scalpers. Every console that isn’t on a shelf is a sale deferred or lost, and worse, it hands scalpers the margin. GTA has cultural clout that reaches everyone. It’s been a mainstream fixture since 2001’s GTA III and its clout has only grown exponentially since then. There’s a touchpoint for every generation alive. The FOMO-word-of-mouth double punch does the rest. Loading... It’ll reactivate the lockdown cohort, the millions who picked up gaming in 2020-21 and churned. GTA 6 will bring them back. Remember when College Football 25 brought a bunch of US gamers to current-gen consoles? GTA will do that globally. Once they’re back (or upgraded), and all GTA’d out, the fresh current-gen-console folks will check out the rest of the current-gen catalogue they missed. GTA Online, if not free to play, will also lead to a boost for PS+ and Xbox Game Pass, another boost for the ecosystem players. Want more free estimates and insights in your inbox twice a week? Subscribe below! Subscribe Even some of the smug PCMR 60FPS crew won’t be able to resist their FOMO and will bite the bullet on a console to play this one early (then double dip). The consoles cost the same as a decent stick of RAM these days anyway lmao… Don’t get me wrong, though. GTA 6 is no silver bullet for the mature console market, but it does prime the current gen for a couple of strong swan-song years. And it’ll also give the consoles more users from which to maximise ARPU. ‘’We are in the latter half of the lifetime cycle of [the PS5],’’ said Sony President and CEO Hiroki Totoki in a Wall Street Journal interview. ‘’That means we do not need to aggressively sell the console today; rather than that, we are focusing on the current revenue from the current user base.’’ The biggest, best premium games always arrive late in a console cycle, so getting more players aboard now, ahead of that content storm (the new current-gen-only Call of Duty included), is a clear win for the platforms. On the Netflix thing, though: let’s all chill out a bit, like. Half my LinkedIn feed was going bonkers treating the reveal debuting on Netflix like it’s the future of entertainment. It wasn’t. It was a six-hour head start, and Netflix left that detail out of the “first-of-its-kind partnership” press release. The extended look hit Netflix at 3pm ET on 27 August, then went up on YouTube and Rockstar’s site for everyone six hours later. And it was all over social immediately, anyways. This reveal was going to reach an untold number of people whether it debuted on Netflix, YouTube, a Times Square screen, or a group chat. The last trailer did nearly half a billion views in a day with no gatekeeper at all. Netflix just stood next to that audience for six hours, borrowing it. It’s was a tidy deal for Netflix, sure. But every outlet on earth was breaking the thing down frame by frame by the evening anyway. Anyway. I’m hype. And we’ll be covering some GTA numbers on the newsletter soon. So hit subscribe below to get that in your inbox when it’s ready! Subscribe The last word Reply to this email – or reach out here – if you have any feedback for the newsletter – or want to request a game for us to cover. [Alinea Analytics boasts the most accurate PC and console estimates in the business. Game makers use our platform to understand their audience, keep an eye on the competition, monitor sales trends, and spot new opportunities. We equip game studios and financial institutions with accurate data and the confidence to make smarter, data-driven decisions. Want to talk about all things games market data? We’d love to chat!]
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