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Women who changed science missing from GCSE and A-level courses
Despite social, economic and institutional barriers limiting women’s formal participation in science, they made numerous key breakthroughs.
Europe’s moderates must stop treating politics as a spectator sport
While centrists have retreated to myriad bubbles, extremists turn up, join up and organise
Wisconsin’s seasonal migrant workers lack access to healthcare — until a mobile clinic pulls up to the farm
Thousands of Wisconsin’s migrant seasonal workers face barriers to getting basic healthcare. A Wautoma-based charity is helping fill that gap by taking its mobile clinic to farm fields, providing low-cost primary care medicine to workers mostly from Mexico.
The big business of personal shopping
From sourcing rare Hermès bags to organising last-minute gifts, independent personal shoppers will go to extraordinary lengths to keep wealthy clients happy
“The Politics of Abuse”: Survivor of Childhood Sexual Abuse Shares How State Court Impacts Those Seeking Justice
Through the statewide tour, Trout and local advocates continued conversations about the barriers survivors face and the role North Carolina's legislature and courts play in addressing them.
Evolution of women’s healthcare focus of URI’s annual Youngken Clinic
KINGSTON, R.I. — Oct. 20, 2026 — Women’s healthcare is evolving rapidly, and while greater emphasis has been placed on comprehensive care, women still face more barriers to healthcare than men, according to the National Institutes of Health. Pharmacists are key players in helping break down those barriers, playing an increasingly important role in improving […]
Peach State Health Plan Releases 2025 Community Impact Report
/PRNewswire/ -- Peach State Health Plan, a care management organization serving Georgians, has released the 2025 Community Impact Report, Removing Barriers to...
Peach State Health Plan Releases 2025 Community Impact Report
Peach State Health Plan, a care management organization serving Georgians, has released the 2025 Community Impact Report, Removing Barriers to Better Health, highlighting continued efforts to...
Fatima El Mansouri: What can Morocco's first female prime minister change for women?
Will Fatima El Mansouri advance women’s rights amid religious and political barriers?
Is smart farming really smart business?
From eerie driverless tractors to precision spraying and sowing, AI is transforming America’s agricultural life
Macron faces political firestorm after riots
Worst street violence in years comes six months ahead of one of Europe’s most closely watched elections
Michigan senior men bare nearly all for charity calendar benefiting aging center
MONROE, Mich. (WXYZ) -- A group of Monroe-area men are proving that age is no barrier to having fun for a good cause.
Supporting quantitative skills in biomedical science with smart worksheets: intentions, impact and barriers to engagement
Every year, hundreds of thousands of students arrive at university with one shared weakness: the maths hiding inside their science. In biomedical science, where pipetting volumes, dilution factors, calibration curves and statistical spread underpin nearly every practical
Apple blames ‘extraordinary’ demand as foldable iPhones sell out
Deliveries of the $2,000 Duo slip to 2027 within hours of going on sale
The many barriers young adults must overcome to vote: A research-based reporting guide
This guide from SciLine offers insights, tips, and story ideas to help journalists report on Generation Z’s voting habits.
New business association coming to Kettering
Leaders sat down for a panel discussion in front of dozens of businesses, where they talked about what the city is working to improve and the barriers they face.
8 Best Science Fantasy Books of the 21st Century
Break genre barriers with spacefaring necromancers and aliens employing goblins
Integrating care for people with serious mental illness
Serious mental illness (SMI) is challenging to address. | People with serious mental illness often face significant barriers to getting the care they need. In this week's episode of "Podnosis," we explore how Amae Health is working to address gaps in the system by bringing psychiatric care, physical healthcare and other support services together under one model.
Americans think it takes $28,000 to start a business. Owners say it's less than half that.
Intuit QuickBooks reports Americans think starting a business costs $28,000, while actual owners spend about $12,000, highlighting perception barriers to entrepreneurship.
Mom-and-Pop Business Owners Grapple with Harsh Times
Report shows small business owners in NYS less optimistic about the economy. Taxes, inflation, labor costs and competition from larger businesses are major concerns right now, they say By Aaron Gifford [caption id=attachment_11067 align=alignright width=300] Ashley Ranslow is director for New York state at The National Federation of Independent Business (NFIB).[/caption] Owners of mom-and-pop businesses in New York state have been less optimistic lately than their peers in other parts of the country, a recent report indicates. The National Federation of Independent Business (NFIB), based on a survey of 11,000 of its members in the Empire State, reported that taxes, inflation, labor costs and competition from larger businesses are major concerns right now. “Indeed, while taxes are a major problem in New York and the United States overall, New York small businesses notably are struggling more with the state’s onerous, multi-level tax burden,” Ashley Ranslow, NFIB’s director for New York state, said in the July report. Compared with surveys of business owners in other states, far fewer New York respondents rated their businesses as in excellent or good health. The report also said labor costs here are about 25% higher than the national average and are the “single most important problem” facing businesses. One respondent to the New York-specific survey complained that too much red tape, taxes and laws that restrict high-yielding companies have stifled their operation’s growth. Others said high disability and workers’ compensation insurance costs, alarming increases in utility rates and excessive building regulations are discouraging. Statewide, New York has a gross domestic product of $2.53 trillion (third in the nation, followed by Texas, $2.90 trillion; and California, $4.25 trillion), a per capita income of $90,500 (sixth) and an unemployment rate of 4.6% (34th). There are 2.4 million small businesses that employ 3.9 million people. [caption id=attachment_11112 align=alignright width=451] Member of the Greater Liverpool Chamber of Commerce gather at one of the several functions the chamber organizes monthly. “Everyone in this business community encourages each other to shop local. Everyone just wants to see each other succeed,” says Megan Wilmot, the chamber director[/caption] “New York state boasts one of the largest, wealthiest and most diverse cities in the world — and that’s still only about half the state’s population,” the report said. “In other words, the state is both its iconic city and so much more — geographically, demographically, economically. But New York is not without its challenges, challenges that include notably high taxes and other weaknesses that impact the small business environment,” it said. The report includes an optimism index that compares responses from New York (NFIB) members with those of their peers in other states across several categories. This ranges from plans to increase employment to expectations for higher sales, to plans to increase inventory or expand. The scores for Empire State business owners were lower in most categories, but they did score higher than the national average in noting that they have current employment openings, and that they are hopeful that the economy will improve. “The metrics so far paint a picture of a state with a series of challenges for small businesses, from a slightly below national average Optimism Index to a more seriously below national business health to very substantially below national Employment Index. What is going on with businesses that are creating these differences?” the report stated. In Central New York, the regional labor force comprises nearly 398,000 workers. The median household income here is $71,463, and the gross domestic product for the region last year totaled $61.3 billion, according to the CenterState CEO economic development and research organization. About half of the region’s labor force works for small and mid-sized businesses, although the number of people employed in that sector has decreased by 7% since 2010, according to CenterState’s 2026 economic forecast report. “While record-high employment in large-scale enterprises provides a strong foundation for Central New York,” the report says, “the long-term health of communities depends on a thriving small business sector to serve as a stabilizer.” Area employers identify several barriers to Central New York’s anticipated growth, including lack of specialized or skilled workers, government regulations, unaffordable housing options and long-term construction disruptions. In the city of Syracuse, the number of jobs in retail trade decreased by 1,500 or 4.7% between July 2025 and this past July. By contrast, the number of jobs in the leisure and hospitality sector increased by 2.5% or 700 jobs, in the same annual period, according to the New York State Department of Labor. Still, there’s plenty of interest for new businesses across Central New York. U.S. Census figures show that the number of applications for new businesses in all four counties increased significantly in the past 20 years. In Cayuga County, there were 324 applications in 2005 compared to 470 last year. In Madison County, the number increased from 385 to 480; Onondaga County, from 2411 to 4132; and Oswego County, from 553 to 836. Downtown Cazenovia is exemplary of Madison County’s trend: In the past year, the village welcomed a bait shop, a thrift store, a vitamin infusion center, a pizzeria, a Pilates studio and an Italian restaurant. A candy store is scheduled to open on the main drag in the months ahead. Oswego’s list of interesting new businesses in the past year includes a bubble tea shop, a hot dog eatery in Fulton, a specialty grocery store that features New York state products in Mexico, a beauty and esthetics studio in Hannibal and a hardware and farm supply store in Sandy Creek. In Onondaga County, the Liverpool area has also enjoyed a steady stream of new shops and eateries in recent years. That suburban community is unique in that, unlike neighboring communities, most of the restaurants are family-owned and not part of a national chain. [caption id=attachment_11116 align=alignright width=300] Megan Wilmot is the executive director of the Greater Liverpool’s Chamber of Commerce.[/caption] Megan Wilmot, executive director of the Greater Liverpool Chamber of Commerce, said independent business owners in her community maintain a strong sense of pride in holding their own against national companies. The chamber helps boost morale with red carpet events, ribbon cuttings, coffee hours and five-year anniversary celebrations for participating businesses. “We have built such a strong community,” Wilmot said. “Everyone in this business community encourages each other to shop local. Everyone just wants to see each other succeed.” In Syracuse, the downtown retail occupancy rate last year was about 82%, a slight improvement from 2024, according to the Downtown Syracuse Committee’s most recent annual report. Buildings with the largest amount of vacant space included The Galleries, One Park Place, and Equitable Towers, though not all of those spaces are designated for retail use. New businesses that opened in downtown Syracuse last year: Better with Time Clothing, Dakshin Curry & Biriyani, Havana Tattoo Society, Milano Bean Café, Miss Daisy, Pausa Coffee, Sweets for Babe, The Society CNY and Yafah Beauty Studio. The Destiny USA mall’s occupancy rate decreased from 80% in 2023 to 72% by the end of 2024, according to Integra Realty Resources. That leaves more than a quarter of the mall’s retail space vacant. “Looking ahead, the retail market is expected to see minimal rent growth, with vacancy rates likely remaining stable in community and neighborhood centers but continuing to rise in enclosed malls,” Integra’s report said. “New construction activity is low and redevelopment plans for former malls like Shoppingtown and Great Northern are still in the planning stages. The proposed Micron chip plant may spur development, but challenges remain in finding co-developers for large-scale projects.” Nationally, the U.S. Chamber of Commerce expects that small businesses will remain resilient and see their sales and revenues eventually improve. That organization, in a recent national survey, found that 25% of small business owners expect the economy to improve in 2027, while 45% indicated that they plan to increase employment in the next 12 months. And 69% said they believe their small business is in good shape and 70% said they are comfortable with their current cash flow. Thirty-one percent of small businesses reported raising their prices in July and 28% are planning to raise their prices within the next three to four months, the report said. Twelve percent indicated that this is a good time to expand their business. “Small business owners voice optimism for future revenues and hiring,” the report said. “High costs continue to be a wet blanket on reinvestment.” The NFIB reported in July that Main Street, despite gas price hikes, “is OK … for now.” Its small business economics trend report said sales across the country have been strong compared to last year, but continued inflation and higher prices from mom-and-pop establishments are causing some “cracks” to show. “If costs stay this high for much longer, reduced investment will have a tangible economic impact,” the report said. “The status quo is OK, but the outlook? The outlook is uncertain.”
The barriers to realizing AI's promise in health care
Without intervention, AI is on track to make health care even more expensive and wasteful.
The Nobel Prize is not an exact science
Winners are only human. The committee could do more to highlight that
Indonesia’s sweeping new halal rules spark business backlash
World’s largest majority-Muslim country to force companies to explain how products from clothes to toilet paper are permissible under Islam
Topeka families face growing health and food gaps
Topeka residents face barriers to health care and fresh food as nonprofits scramble to fill growing service gaps.
Science can't conquer HIV without dismantling barriers
OPINION: New tools can transform HIV prevention and treatment. Their reach depends on confronting the barriers that keep people from care.
Lee Health: Understanding our community's health needs
Lee Health's mission is to be a trusted partner, empowering healthier lives through care and compassion. This mission inspires me and drives our team members and the work they do every day and night. We recognize that to be a trusted partner, we need to know our patients and the communities we serve. We need to understand their changing health needs, the disparities that exist, barriers to care, and the challenges affecting our communities.
How Egyptian femtech is tackling taboos around women's health
Cultural taboos and a lack of understanding can be a barrier for women to access healthcare in Egypt, alongside the cost of treatment. But the country's budding femtech sector is creating new pathways…
School politics class: How the Supreme Court greenlit America’s gerrymandering battle
US Supreme Court
Global private equity fuels Indian healthcare’s push into smaller cities
Hospitals flush with foreign money are expanding rapidly and filling gaps in public infrastructure
Exploring Barriers to Accessing Mental Health Services for Adolescents With Depression in Pokhara Metropolitan City, Nepal: Perspectives of Mental Healthcare Providers
Background In Nepal, depression is one of the most common mental health conditions among adolescents, but mental health services for this population remain limited. Previous studies have iden...
Get used to multi-party politics, it’s here to stay
The prime minister’s promise on electoral reform could entrench the complex fights between five, even six parties
EU leads fight against fossil-fuel nations’ push to delay climate science reports
Dispute looms over next review of the latest science on the warming planet as temperatures continue to rise
Where Are They Now: Fort Smith Northside star Jerry Jennings played two sports at Arkansas
If you know the sports culture of Fort Smith, you know about the great two-sport star who helped break the color barrier there in the late 1960s and for Razorback Nation.
Michael Kearns, actor who made history with HIV reveal, dies at 76
Michael Kearns, an actor who broke barriers by announcing his HIV status in 1991, has reportedly died. He was 76.
Michael Kearns, barrier-breaking gay actor and activist, dies at 76
Gay actor and activist Michael Kearns has died at 76. Kearns was known for his work on stage and screen, including in “And the Band Played On.”
Mental health and ADHD diagnosis can cause harm, says official review
Government-commissioned report calls for more opportunities to work and socialise for young people and rejects claims of ‘snowflake’ generation
The Shelborne by Proper: a Miami landmark is back in business
Following a $100mn restoration, the 1940s Art Deco hotel offers a stylish base for soaking up South Beach
Duke Health-backed survey identifies steep health barriers for Durham residents earning under $75,000
The Durham Community Health Assessment Survey's latest findings will guide Duke's community health planning going forward, Duke Health officials said.
HSBC plans sweeping job cuts across UK wealth business in AI push
Bank is consulting with staff on reductions in roles affecting managers, specialists and financial advisers
Health Data Interoperability Still Faces Persistent Barriers
A CRS report says U.S. health data interoperability still faces persistent barriers. Read about the challenges and implications for connected care today.
Mental health stigma may deter treatment seeking in Japan
A UC Riverside-led study of mental health stigma in Japan has found a striking gap between the need for treatment and people's willingness to seek it, with high levels of social distancing toward people with mental illness serving as a potential barrier.
The politics of losing sleep
There is still a class divide when it comes to work that tramples over your body clock
Spanish PM Pedro Sánchez looks for political lifeline in snap election
Embattled Socialist leader aims to capitalise on housing crisis to remain in power
More than a prescription: Removing barriers so patients can get back to living
See how integrated specialty pharmacy support helped one patient overcome treatment barriers and get back to the moments that matter most.
Some mental health providers hoping to serve Lane County's Oregon Health Plan members say they’re facing barriers
Aspire is one of a few healthcare providers in Lane County that told KLCC they want to – but haven’t been able to – get a contract with Lane County's Medicaid insurer Trillium. That’s left Aspire without access to its target population, and other providers considering scaling back their services.
Yale School of Medicine On the Science of Childhood Anxiety, Say, Anxiety Disorders Are the Most Common Mental Health Challenges In Youth
Credit: Matt Bradbury October 5, 2026 - By Isabella Backman - Anxiety disorders are the most common mental health challenges in youth. Left untreated, they can disrupt the lives of both children and their families. The good news is that with intervention, most children will overcome these conditions. Across Yale School of Medicine, scientists are working to understand anxiety at every level, from common anxious behaviors to molecular biomarkers in the brain. They are using their findings to develop and disseminate new evidence-based treatments for childhood anxiety. Today, the go-to treatment for childhood anxiety disorders is cognitive behavioral therapy (CBT). This is a form of psychotherapy that teaches children skills for confronting anxious thoughts and helps them practice managing situations that cause anxiety. While it is the gold-standard treatment backed by considerable scientific evidence, up to 50% of children will not see sufficient benefit from CBT alone. Wendy Silverman, PhD, Alfred A. Messer Professor in the Child Study Center, co-directs the Anxiety and Mood Disorders Program alongside Eli Lebowitz, PhD, associate professor in the Child Study Center. One of their main interests is learning how to improve outcomes beyond CBT. “We’re developing cutting-edge, research-based knowledge that can reduce the suffering that anxiety causes children and their families,” says Silverman. Changing parent behavior YSM experts are investigating how to improve CBT outcomes for children by involving the parents. Silverman’s research has uncovered two main components of parent intervention that improve childhood anxiety: not enabling children to completely avoid the things that make them anxious and taking steps to enhance their autonomy. Parents may unintentionally reinforce their child’s anxiety by allowing them to avoid what makes them anxious. They also may unintentionally limit the children’s sense of autonomy by being overly intrusive. “One of the things that we take pride in is that we’ve focused on trying to understand what parents need to do, and to test our ideas and see if changing the parents’ behaviors is enhancing the effects of CBT,” Silverman says. “Our findings thus far suggest that they do." As much as CBT can be helpful, it can also be challenging to get one’s child to do the necessary steps for CBT to work. This is one important reason why Lebowitz created a novel intervention program for parents named Supportive Parenting for Anxious Childhood Emotions (SPACE). Existing intervention programs often teach parents to act as therapists for their child, such as training them on how to practice breathing exercises. “It makes sense, but this doesn’t work very well in practice,” says Lebowitz. “And part of the reason, I think, is that it’s not easy to get your kid to do things, especially if they’re not excited about doing it.” SPACE is unique because it focuses entirely on parent involvement and changing parental behavior—children are not involved in the sessions. For example, parents learn how to use supportive messages that convey confidence that their child can tolerate and manage distress. “It might sound like a parent saying to a child, ‘I get that this is really hard for you, but I know that you can handle it,’” Lebowitz says. The program also works with parents to identify the ways in which they are accommodating anxious behaviors. “We’ll pick one thing that parents are doing that is an accommodation and help them make a detailed plan for how they’re going to change that,” Lebowitz explains. Treating Anxiety in Children and Adolescents Much of the existing research on SPACE has focused on parents of children under age 14. Ongoing studies are now exploring its use with parents of older teens. “Both anxiety and accommodation can interfere with normative developmental shifts during the teen years, including increased autonomy and individuation from parents,” says Rebecca Etkin, PhD, associate research scientist in the Child Study Center. “In this sense, SPACE may be particularly well-suited for anxious teens and their parents. We want to see whether it is effective during this distinct developmental window.” Unfortunately, many families in need of CBT face barriers, including limited availability of services and geographic constraints. One way to improve access is digital interventions. Silverman and her team are developing an evidence-based digitized intervention program for parents that they can access directly from their computer or smart phone. “The work we’re doing will be one of the very few parent interventions that is digitized and importantly tested for effectiveness,” she says. Creating interventions for anxiety-related challenges Silverman and Lebowitz recently received a generous gift to develop and test other interventions that help parents reduce other child anxiety-related behavioral and emotional difficulties, such as restrictive eating and unexplained somatic symptoms. One of these projects in particular focuses on understanding the risks of social media and its potential benefits, including offering a sense of connection. “A lot of research has focused on the idea that social media is harmful and the less of it the better,” says Lebowitz. “But we actually see is that this is not quite right—there are negatives, but there are also positives. So, we’re trying to get a little bit more nuanced of a picture.” The team is working with teens with social anxiety and their parents over an extended period to better understand their social media habits and how their anxiety levels affect engagement with different platforms. The teens will answer questions sent to an app on their phones about mood and social media usage in an effort to capture emotional responses as they unfold. “We hope to develop interventions that can help make the best of social media while protecting against the more problematic effects,” Lebowitz says. The brain’s role in anxiety Researchers are also testing therapies to address anxiety at the neurological and molecular levels. In collaboration with Dylan Gee, PhD, professor of psychology in Yale's Faculty of Arts and Sciences, and Hilary Blumberg, MD, John and Hope Furth Professor of Psychiatric Neuroscience at Yale School of Medicine, Lebowitz and Silverman are using brain imaging to identify changes in a child’s brain before and after parents enroll in SPACE. In one study, children viewed anxiety-inducing images while undergoing magnetic resonance imaging (MRI); the researchers conducted scans with and without the children’s parents nearby. Before SPACE, children’s brains were better able to activate the regulatory circuitry needed to turn off an anxious response when their parents were nearby. But after SPACE, children could activate this circuitry even without the parent around. “As parents work on gradually reducing some of their accommodations, you can see a child get better at regulating their own fear system in the brain,” Lebowitz says. “It’s remarkable.” Research into the molecular underpinnings of anxiety can also inform new childhood anxiety treatments. In a recent study, Lebowitz, Silverman, and Flora Vaccarino, MD, Harris Professor in the Child Study Center, discovered that a protein known as fibroblast growth factor 2 (FGF2) could be protective from the toxic effects of stress. FGF2 levels in children and their parents were linked to the children’s risk of developing anxiety and depression, the study showed. The findings could help explain why some children who are exposed to early life trauma such as poverty or abuse are more prone to developing mental health disorders. And FGF2 could be a target for treatment. “This is very novel because it starts to give a clue to what is the molecular chain that connects those lived experiences to the actual psychological outcomes,” Lebowitz says. New ways to study and treat childhood anxiety Michael Crowley, PhD, associate professor in the Child Study Center, collaborates with Silverman and Lebowitz to study the role that attention plays in development and maintenance of childhood anxiety. There is a large body of research that shows that anxious children, like anxious adults, are prone to focus on threatening stimuli such as angry faces compared with neutral faces. This has led to innovative interventions that involve attention retraining. The idea is that if experts train children to look away from threatening stimuli, it may reduce their anxiety—especially children with social anxiety who are most prone to attend to threats. The researchers have just completed a clinical trial for attention retraining with 10- to 14-year-olds with social anxiety disorders and are currently analyzing the findings. Besides this innovative attention retraining research, as Crowly notes, “I like to design tasks that are engaging to kids,” Crowley says. “My goal is to assess something without the kids knowing what we are assessing.” With this goal in mind, Crowley has created a virtual game, named Boom, to study threat processing in children with anxiety disorders. The game is similar to that of hot potato—the child and three digital players take turns virtually passing a ball to each other’s gloves. At some point, the ball turns into a bomb, and as the bomb lands in each player’s glove, the outline of the glove turns yellow. The goal is to avoid having the bomb go off in your glove. What isn’t obvious is that the game is designed to measure different types of threatening stimuli, both ambiguous and direct. In the game, the direct threat occurs as the bomb is traveling towards your glove. The ambiguous threat is the yellow outlined glove as it is unknown where the bomb will travel next. While children play the game, Crowley’s team measures their brain activity using electroencephalography (EEG). The researchers have discovered that in kids with anxiety, the brain reacts more strongly to ambiguous threats than it does in their peers, but less strongly to direct threats. They believe that the initial abnormally large brain response to not knowing where the bomb is going impairs the brain's ability to properly respond when the threat is actually traveling the child’s way. “The brains of children with anxiety are unable to differentiate between threats you need to do something about and those that are not your problem.” Michael Crowley, PhD, develops innovative games for studying anxiety in children and adolescents.Credit: Matt Bradbury Based on these insights, Crowley hopes to study whether interventions like attention training could restore appropriate threat processing. Crowley’s team is also working on a test called the Balloon Risk Avoidance Task, which evaluates risk-taking and avoidance behaviors. It features a digital balloon that is full of air and about to burst. Kids have six seconds to let air out of the balloon. The more air they let out, the less risk they face that the balloon will pop. But at the same time, the balloon becomes less valuable as it deflates. “The more air you keep in the balloon, the more points you get,” Crowley explains. So far, the researchers have found that when the balloons pop unexpectedly, teens with social anxiety show distinct brain responses. Studying these responses can help psychologists understand the underlying pathways driving the various manifestations of anxiety. The genetics of anxiety When Thomas Fernandez, MD, associate professor in the Child Study Center and of psychiatry, was still in training, there was a lot of excitement about understanding the genetics associated with autism spectrum disorder. Since then, scientists have identified around 250 genes associated with autism. The genetic contribution to anxiety disorders, on the other hand, has historically received less attention. Anxiety is less heritable than autism, but the genetic contribution for anxiety disorders that emerge in childhood may be higher than for anxiety disorders overall. While scientists estimate the heritability of anxiety disorders in general to be around 30% to 50%, some studies suggest higher heritability for certain childhood-onset anxiety presentations. “I saw firsthand how researchers in the field went about finding vulnerability genes for autism,” Fernandez says. “So, we’re using a very similar playbook for childhood anxiety.” “I saw firsthand how researchers in the field went about finding vulnerability genes for autism. So, we’re using a very similar playbook for childhood anxiety.” Thomas Fernandez, MD Associate Professor In the Child Study Center and in Psychiatry Now, Fernandez and Emily Olfson, MD, PhD, assistant professor in the Child Study Center, are studying children and their parents to identify genetic changes that are present in the child but not the parents, known as “de novo mutations.” “All of us have some de novo mutations—maybe about 50 to 100 sprinkled throughout the genome,” Olfson says. “But when they occur within the coding regions of genes, they can be really disruptive.” Previous research shows that people with autism have higher rates of damaging de novo mutations than the general population. In 2022, Olfson, Lebowitz, Silverman, and Fernandez published a study on 68 children and their families that found that children with anxiety had similarly high levels of these mutations. Studying de novo mutations can help point the researchers to where they should be looking for genes associated with anxiety. “The end game is using the genes to steer us toward the right part of biology that we can then target to come up with better treatments,” Fernandez says. Building on those findings, the team is now studying more families to better understand how these de novo mutations, along with other genetic and environmental factors, shape pediatric anxiety disorders. They recently received a National Institutes of Health grant to enroll 750 new families over the next five years. Olfson is the principal investigator, with co-investigators Lebowitz, Fernandez, Silverman, and Shuangge Steven Ma, PhD, department chair and professor of biostatistics at Yale School of Public Health. Neurodevelopment, Risk Genes, and Mental Health Conditions - The Olfson Lab Joel Gelernter, MD, Foundations Fund Professor of Psychiatry, is interested in how different anxiety disorders differ genomically. “We are studying social phobia, panic disorder, and generalized anxiety disorder, working to understand why people differ in their risk to these specific anxiety disorders and evaluating various risk factors,” he says. Gelernter was recently involved in one of the largest studies to date of the genomics underlying anxiety disorder. The study included around 122,000 people with anxiety disorders and around 730,000 without. It found that some genetic differences associated with anxiety were linked to signaling that helps reduce overactivity in the nervous system. Many anxiety medications available today work by targeting this process. “It’s nice when the biology that you get out of a large genome-wide study ratifies things that we already know because that can help increase confidence in further findings from the study,” Gelernter says. Uncovering the neurobiology of psychiatric disorders John Krystal, MD, Robert L. McNeil, Jr. Professor of Translational Research and chair of the Department of Psychiatry, is interested in the neurobiology of psychiatric disorders, including post-traumatic stress disorder (PTSD), of which anxiety is a major symptom. In the late 1980s, Krystal’s team discovered that the drug yohimbine activated symptoms in patients with PTSD. “This was the first time we could link a specific biological mechanism to the symptoms of PTSD,” Krystal says. At the time, he adds, this finding was highly controversial. “A lot of people felt that PTSD was a purely psychological syndrome that didn’t have an underlying biology.” Since then, Krystal has dived deep into understanding the neurobiology of PTSD to learn how to better treat it. His team is evaluating the use of ketamine and psychedelics. These would be among the first treatments to be developed specifically for PTSD. They may also be applicable for other disorders including anxiety disorders, Krystal adds. An important gap in PTSD treatment is the absence of biological tests that inform how to best help patients manage their PTSD symptoms. A doctor doesn’t diagnose cancer based on how they feel. Rather, they use tests of the biology of the cancer to determine the best course of treatment. “And we can’t do that in any psychiatric disorder other than Alzheimer’s disease,” Krystal says. “But now we are building a foundation for this approach to the treatment of anxiety disorders for the first time.” Source: Yale School of Medicine
American Cancer Society and Baptist Health Announce Partnership to Expand Cancer Screening Efforts
September 30, 2026 — The American Cancer Society (ACS) is expanding its efforts to improve access to cancer screening and early detection in Southeast Florida through an exclusive partnership with Baptist Health. This effort focuses on breaking down barriers to screening, raising awareness about prevention, and helping more people access recommended cancer screening tests. “This […]
One giant clam contains a month‑by‑month diary of the Great Barrier Reef's climate 200 years ago
When you swim through the azure waters of the Great Barrier Reef, there is one creature on the seafloor that's almost impossible to miss: the giant clam. Its huge, fluted shell frames a soft mantle shimmering ...
LAUP connects Latino families with mental health support in Holland
LAUP in Holland connects Latino families with mental health care through therapy and monthly workshops, addressing stigma, language barriers and cost while helping participants rebuild confidence.
In defence of big business
Despite the lionisation of small companies, prosperity hinges on a handful of large firms
America’s Health Care Workforce Is in Crisis
We must prevent financial barriers from determining who has the opportunity to become a health care leader, writes Michellene Davis.
America’s Health Care Workforce Is in Crisis
We must prevent financial barriers from determining who has the opportunity to become a health care leader, writes Michellene Davis.
Broward Health Offers Low-Cost and Free Mammograms Throughout October for Breast Cancer Awareness Month
MammoThon 2026 and “Beating Cancer Together” initiatives aim to remove cost as a barrier to early breast cancer detection for Broward County women Broward Health is marking Breast Cancer Awareness Month throughout October by hosting two community initiatives designed to make life-saving breast cancer screenings accessible to women regardless of insurance status or income. From October 1-31, the health system […]
CalAIM Offers Housing and Health Support, but Medi-Cal Barriers Leave Some Californians Behind
California’s CalAIM program can connect vulnerable residents with health care and housing, but getting that help isn’t always simple.
Bishop’s computer science chair says AI is eliminating ‘grunt work’ and reshaping digital jobs
Dr. Russell Butler, chair of Bishop’s University’s Department of Computer Science, says artificial intelligence is increasingly taking over routine digital “grunt work,” changing the skills students and workers may need in the years ahead. Photo courtesy of Bishop’s University. Click here to read our platform! Get local news like this every morning. Subscribe free below. Subscribe Pulse Newsroom Artificial intelligence is already taking over some of the routine digital work once performed by entry-level employees, according to Bishop’s University Computer Science chair Dr. Russell Butler — a shift he believes will make expertise, judgement and the ability to evaluate AI-generated work increasingly important. Butler described the change as automation reaching what he calls the “bottom of the cognitive pyramid” during an interview with The Pulse about AI, university education and the future of digital work. His argument is not that humans are disappearing from the workplace. Instead, he sees their role changing as AI becomes capable of handling more of the repetitive tasks involved in computer-based work. “Everything’s converging on just AI basically doing all the grunt work,” Butler said. The bottom of the cognitive pyramid Butler is from Lennoxville, completed his undergraduate studies at Bishop’s and later earned his PhD at the Université de Sherbrooke. He joined Bishop’s in 2019 and now chairs its Department of Computer Science. He uses AI in research, teaching and other creative work, and said the technology is increasingly capable of handling routine digital tasks that once required substantial human time. “You’ve got the grunt work, like moving things around in Excel, doing basic programming tasks,” Butler said. “That’s like the bottom grunt work that the entry-level worker would have done two or three years ago.” Butler went further, saying in his view that much of this type of work has already been absorbed by AI tools. He connected that change to a shift he sees taking place in computer science, where entry-level roles have declined while experienced workers can use AI to increase what they can produce. “A senior developer now has access to essentially an unlimited amount of junior developers on demand,” Butler said. He was describing AI systems metaphorically, not literal employees. His point was that one experienced developer can now ask AI tools to produce code or other technical work that might previously have been assigned to more junior workers. That raises a broader question for universities and employers. If some of the simpler work traditionally given to newcomers can now be done by machines, how do people gain the experience needed to become senior workers themselves? Students doing work that once required years of programming Butler said he is already seeing the change inside his classroom. He created a Bishop’s course called CS208, Coding in Plain English, to show students — including those without traditional programming backgrounds — what they can accomplish using AI. Some come from disciplines such as psychology or neuroscience with no previous programming experience. “What I’m finding is that students who have zero programming experience, they come in from another discipline like psychology or neuroscience or something, they are now able to get up and running with real data sets,” Butler said. Butler’s own doctoral work involved neuroimaging, and he said he has assigned students work he considers comparable to the kinds of analysis he performed during his PhD. He described giving students a real dataset, an expected result and instructions to use AI to complete the analysis. Butler said those students have been able to carry out work at a level he associates with tasks he once performed after years of programming experience. That does not mean a student using AI instantly acquires the same knowledge as an experienced computer scientist. But Butler sees it as evidence that AI can dramatically lower the technical barrier between having a problem to solve and producing a working result. The role of the person using the system then changes. They need to know what to ask for, understand enough about the subject to judge the answer and take responsibility for what is ultimately produced. What about AI hallucinations? One persistent concern surrounding generative AI is hallucination — when a system produces information that sounds convincing but is false or unsupported. Butler said that problem has improved substantially in newer systems and is not as severe as it was with earlier models. He pointed in particular to newer AI systems’ ability to search the web, consult scientific databases and return source links rather than simply generating a citation from their internal model. Butler nevertheless said users should verify what AI produces. “You should verify,” he said while discussing citations generated with AI. His position is that hallucinations have become less common in the systems he uses, not that incorrect AI output is impossible. Human checking remains part of the process. Hours of work compressed Butler offered another example from his administrative work at Bishop’s. The university has been comparing CEGEP courses with first-year Bishop’s courses to determine where students may qualify for advanced standing. Traditionally, Butler said, that means reviewing two sets of course descriptions and manually matching one institution’s courses with another’s. As department chair, that could require hours of reading and comparison. He said AI can now be given both sets of material and asked to generate an initial mapping automatically. “It saves me hours and hours of work,” Butler said. Butler said the AI-generated mapping can also produce a better result than he would produce himself. He sees similar opportunities in businesses. A company may receive specifications, drawings, emails or other digital material from customers and then have employees convert that information into an internal format before anything can be manufactured or delivered. AI can increasingly perform parts of that intermediate processing. In Butler’s view, the employee does not necessarily disappear. Instead, the job becomes more about checking the result. “The human is still there,” he said. Judgement could become more valuable That change is central to Butler’s view of where digital work may be headed. If AI can produce a first draft, write basic code, compare documents or process large amounts of information, he argues that knowledge and judgement become increasingly important. “The real scarce resource going forward is going to be domain knowledge, expertise, and… credentials, authority, the ability to work with other people,” Butler said. He is therefore encouraging students not only to learn AI tools but also to broaden their education. He mentioned acting, fine art and photography as examples of courses that can help develop what he described as taste and intuition — the ability to recognize what is good, what is not and what should be changed. “And that’s the skill that they need now because the grunt work has been automated and now it’s about evaluating what the AI produces and telling it how to improve or expand the output,” Butler said. That does not remove the need for technical knowledge. Butler’s argument is that the emphasis may shift away from manually completing every step of a task and toward directing, checking and improving work produced with AI assistance. He also stressed that humans remain responsible for final decisions. “At the end of the day, the human has to make the final call,” Butler said, pointing to the question of accountability. Physical work may be different Butler draws a distinction between digital work and jobs requiring people to manipulate the physical world. He expects AI to continue advancing quickly in tasks performed almost entirely on computers. He is more cautious about claims that humanoid robots will soon be able to replace workers such as plumbers or electricians. Butler said those trades would not be replaced “anytime soon” in his view and described some current robotics demonstrations as overhyped. He described the situation as counterintuitive. “It’s almost like we solved the highest level first,” he said, contrasting advances in digital AI with the harder problem of building robots capable of operating reliably in the physical world. Butler’s argument is that some digital occupations could face automation sooner than trades requiring complex physical work. The wider AI shift in the Townships Butler’s comments come as local institutions are increasingly grappling with how AI should be used. The federal government recently announced up to $162 million over five years for 10,000 AI-related placements through Mitacs. The Université de Sherbrooke told The Pulse that the number of its collaborative research and innovation projects supported through Mitacs has approximately doubled since 2018-19, while the number of placements has approximately tripled. UdeS also said it already has projects involving both AI adoption and the application of AI to other fields. At Bishop’s, Butler said part of his role involves building the Computer Science department’s local presence, connecting students with regional partners and strengthening relationships with the Sherbrooke technology ecosystem. Those developments put universities in a difficult position. They have to prepare students to use the tools employers increasingly have available while also making sure graduates understand enough to recognize when those tools are wrong, incomplete or being applied to the wrong problem. The risk of losing human skills Butler does not see AI as risk-free. Later in the interview, he raised a separate concern: as AI becomes better at reading, writing, programming and other cognitive tasks, people could lose some of the underlying skills that historically helped produce new ideas. “The other danger is that we’re going to lose the human skills,” Butler said. He specifically mentioned reading and writing and argued that people could lose some of the lower-level understanding that contributes to breakthroughs. Butler said AI systems are based on existing human knowledge and argued that they become much more powerful when paired with a capable person. That tension runs through his view of the technology. AI can remove hours of routine work. It can allow beginners to perform tasks that once required substantial technical training. It can give experienced workers significant leverage. But the more capable the technology becomes, the more important it may be for people to develop the judgement needed to decide what should be done in the first place. For Butler, that is where education may have to change. Students still need to understand their field. They still need to know when something is wrong. And they still need to be able to make the final decision. But if AI increasingly handles the bottom of the cognitive pyramid, the value of a worker may depend less on how quickly they can perform the grunt work and more on whether they understand what the work is supposed to accomplish. Don’t miss the next story that affects your community. Join thousands of readers getting The Pulse every morning—plus breaking news alerts when it matters most. If you value this kind of local journalism, consider supporting it. Subscribe, share and like! Subscribe Share
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I am a voter and resident of Shiprock, and the owner of Shiprock Windows and Glass LLC. I started my business in September 2020.
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The model also includes two new Senior Business Advisors who will provide trusted expertise, stronger community connections, and individualized guidance to entrepreneurs and business owners throughout the region.Kinsman brings a unique perspective to the director’s role as both a local business owner, operating in downtown Southern Pines, and a former Moore County educator. “Her combination of education, business ownership, leadership, and community involvement make her a great fit for the Small Business Center and the work we are continuing to build across Moore and Hoke counties,” said Taylor L. McCaskill, senior director of Workforce Development & Corporate Partnerships in a press release.Kinsman is an active member of the Southern Pines Business Association and has been connected to the Sandhills Small Business Center since the beginning of her entrepreneurial journey. She looks forward to building on that experience by strengthening the Center’s partnerships and expanding its connections throughout the community.She will lead the Center's efforts to support entrepreneurs and business owners throughout Moore and Hoke County and be the connector to the North Carolina Community College System Small Business Center Network operations. The Center offers no-cost, confidential one-on-one counseling, practical workshops, and connections to the resources and partners that help local businesses start, grow, and create jobs.A key part of this new approach, only offered at SCC, is a network of Senior Business Advisors, experienced professionals who will provide individualized guidance in areas such as business planning, finance, marketing, operations, growth strategy, and problem-solving. These advisors will serve as trusted partners to entrepreneurs and business owners, helping them turn ideas into action, overcome barriers, strengthen existing businesses, and pursue new opportunities. This one-on-one counseling is available at no cost, ensuring that high-quality business support is accessible to entrepreneurs at every stage.Senior Business Advisor for Hoke County, Kenna Parks. Photo provided by: SCCKenna Parks has been named the senior business advisor for Hoke County. She is a business professional, entrepreneur, and educator who brings a unique combination of academic training and real-world business experience. She earned her Master of Business Administration (MBA) in 2017 and has built her career around entrepreneurship, marketing, business development, and helping others turn ideas into sustainable opportunities.Senior Business Advisor for Moore County, Katrin Henderson. Photo provided by: SCCAs a military spouse, she has successfully launched and operated businesses across five states, giving her firsthand experience in adapting to diverse markets, building new customer bases and understanding the importance of global reach in today’s business environment. Over the last decade, her areas of focus include business planning, marketing strategy, branding, customer development, financial preparedness, operational planning and connecting entrepreneurs with educational programs and community resources.Parks brings an especially valuable perspective to business advising because she is an entrepreneur herself. She is the owner of Glamo Society Bridal & Formal Wear in Raeford, N.C., giving her firsthand experience with the realities of launching, operating, marketing and growing a small business. She understands that entrepreneurship extends far beyond developing a great idea; it requires strategy, financial awareness, adaptability, strong customer relationships, and consistent execution.Katrin Henderson will serve as the senior business advisor for Moore County. Thriving in hospitality and retail, Henderson has enjoyed positions in Food & Beverage Management and Retail Management in various fine dining and retail establishments in the area, before opening her own children's shop in 2015, in the Village of Pinehurst. She is a native of Moore County.Quickly immersing herself in this new world of small business ownership, Henderson joined various boards and committees, including President Elect of Pinehurst Business Partners and Event Chair for the Holly Arts & Crafts Festival. She also partnered with local organizations such as Moore County Economic Development and Moore County Chamber of Commerce and Sandhills Community College Small Business Center in events and educational opportunities. In 2026, Henderson sold her shop and now offers full-time support to both new and seasoned entrepreneurs through freelance consulting mentorship and the SCC Small Business Center program.The Small Business Center team is passionate about making business resources more accessible, and ensuring entrepreneurs know they do not have to navigate business ownership alone. Through their work with SCC, they are committed to building meaningful relationships with local businesses, community organizations, and industry partners while helping entrepreneurs move from idea to strategy, strategy to action, and action to sustainable growth.“Sandhills Community College believes deeply in the power of small business and entrepreneurship because strong local businesses create jobs, spark innovation, generate investment, and strengthen the communities we serve,” said McCaskill in press release. “Through this new Small Business Center model, Sandhills is building a stronger ecosystem where entrepreneurs can connect, grow, and thrive, while helping drive long-term economic vitality throughout our region.”To learn more about the Center's services or to schedule a consultation, please contact Kinsman directly at kinsmanl@sandhills.edu or 910-695-3938.
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Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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