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Accounting firms grow advisory services for growing clients
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Sundar Pichai: Google’s Frontier Imperative, Compute Scarcity Dilemmas, Future AI Products and Businesses
Alphabet CEO Sundar Pichai has little patience for doubts about Google’s willingness or capacity to compete at the frontier of AI. His company’s latest Gemini 4 Argon model — long-promised and recently delivered — beats OpenAI and Anthropic’s latest public models on coding, math, science, and knowledge-work benchmarks and has placed Google’s AI back among the world’s best. Amid chatter that Google was fine with good-enough lightweight ‘Flash’ models, Pichai pushed back hard against any suggestion that company is limiting its research ambitions. “We won’t do it any other way,” he told me in a Big Technology Podcast interview recorded this week at Google’s Mountain View headquarters. Pursuing cutting-edge research is costly for Google, requiring compute and chips that otherwise could be sold at a high markup by its cloud business. But Pichai said allocating resources to frontier AI development is “ground zero” for Google. “Our cloud business is at any given moment in time forgoing short-term revenues because we are making compute trade-offs to support frontier AI development,” Pichai told me. In our conversation, we discussed Argon (which Pichai says processed three times as many tokens as Gemini 3 in the 72 hours after launch), AI’s role in developing better models, the AI interface of the future, competition with OpenAI, Google’s partnerships with Anthropic and Apple, data centers in space, and the nature of his optimism. You can read the full conversation, lightly edited for length and clarity, below, or listen to it on Apple Podcasts, Spotify, YouTube, or your podcast app of choice. Alex Kantrowitz: Google is back at the frontier with Gemini 4 Argon, which beats OpenAI’s and Anthropic’s public models on benchmarks spanning coding, math, science, and knowledge work. The conventional wisdom was that Google had given up on the frontier to focus on fast, good-enough models for its products. That was wrong? Sundar Pichai: Very wrong. Look, we are so committed to being at the frontier. It’s in our DNA. We won’t do it any other way. We’ve been thinking about the AI frontier for well over a decade now. The frontier is very dynamic. It’s very competitive. It’s very exciting. I couldn’t be more pleased with how Argon has come together. We took our time with it. We made sure we tested it safely and deployed it carefully. We took a bit longer than our other models, given its capabilities. Across the board, be it for agentic work, knowledge work, coding, creative tasks, Argon is one of the really good frontier models. The first 72 hours since we launched, it’s almost up to 25 trillion tokens used, which is about three times what Gemini 3.0 had in the first 72 hours. And we are capacity constrained as we are serving it. Excited, but there are always areas….. You know, the frontier is very dynamic, and you have to keep evolving the models. There are areas which we can see we need to improve as well. We’ll be at work on all of that as well. Which areas? On any given model, Argon would be across the board better at everything if you just look even two months back. But the space is so evolving. Even on coding, for example, there are pockets where we know we need to do better, and there’s clear feedback. We’ll make it better. The argument for standard models is that they’re already good enough to build great products, with the frontier valuable only for certain tasks. Meta built Muse with good models rather than the best, and Google could put standard models into Maps, Gmail, and Search. Why isn’t that sufficient? It’s definitely not how I have thought about it at all. We are deeply committed to driving the state of the art and actually pushing where this technology can go, all the way from transformers. That’s a journey we’ve been on. You will see us continue to do that. When you’re at the frontier, you get an earlier look into the emerging capabilities, earlier than others, which helps you better prepare for the future. We are fortunate to have a wide set of opportunities across consumer and enterprise. Some of our cloud customers, for sure, want the model at the frontier. The frontier models will be better at developing the next set of models in an era of recursive self-improvement. I would argue it matters there. Internally, we have definitely seen a steep point of inflection by deploying Argon to our developers. It definitely tackles problems which our previous models could not do. Being at the frontier puts you at the innovation frontier and helps you drive that as well. There is room for models of all sizes and capabilities. That’s why we did Flash, Flash-Lite, etc. I agree with you that you can develop very good product experiences with not necessarily the most frontier model, because they tend to be slower and more expensive too. But we care about the Pareto frontier, and we’re committed to doing all of that. You said developing frontier models gives you a look at what’s coming. What do you see on the horizon? What makes this moment so exciting is you build something which you think is a culmination of months of work, and you put it out. You already see clear headroom ahead. We’ve all been working on these agentic, long-horizon capabilities, but clearly the frontier is going to have multiple of these agents working together to do things. That’s an example of an exciting paradigm underway. It’s also clear to me that users, both in consumer and enterprise, will have access to some multi-agent framework for them, working all the time doing things. It feels like a moment of infinite possibilities. Sergey Brin said one of Argon’s core innovations was relying more on the model to help develop the model. Yet incidents involving OpenAI’s bots breaking containment and Google’s bots accessing a site they shouldn’t have suggest these systems still aren’t perfectly aligned. Isn’t there reasonable cause for concern about accelerating toward recursive self-improvement? There are three parts to your question. Let’s first talk about RSI itself. You’re right, Sergey mentioned RSI being a critical contributor as we are developing Argon. But to be very clear, today, in a continuum, we are pretty far from the end state of RSI or something like that. The right way to describe it is you have RSI loops along with AI researchers in various aspects of model development. You almost have agents helping AI researchers in some automated way work together to build these models. It’s good to at least understand where we are today, and it’s super exciting. I expect that continuum to keep making progress as we go into next year. The second question is around safety. Security comes from defense in depth. You’re talking about alignment, obviously. We all are doing a lot of work to make sure the models are as aligned as possible. But it’s an active area of research, and there are clear gaps. That’s not the only thing we rely on. You have the work you do on alignment, but beyond that, we put a lot of effort into real-time monitoring as these models are working. Making sure you have good telemetry into what’s happening so that you can intervene in real time if you see unexpected behaviors. How you do that, the architecture with which you do that, how you make sure it’s all sandboxed and isolated in a way that it can continue doing its job during real-time monitoring — these are all areas of investment. Obviously, when we deploy these models, giving customers, enterprises, control, both with real-time monitoring, but their ability to decide where they deploy, what type of data which models ever have access to, etc. All that work is very, very important, and we are doing a lot of that. As an industry, we need to constantly up our game and take the time to do all this stuff, including dedicating the compute required to make sure you can safely deploy these models. The third part is: Is it all enough? This is why there are a lot of conversations in the industry, and I think it’s reasonable to be worried. The right way to approach something you worry about is early on thinking about what more we can do. As an industry, you’re definitely seeing increased levels of work on alignment, testing for safety, etc., as we deploy these models. The next step would be developing better standards so there are cross-industry standards of how we do these things, including the ability to evaluate using independent evaluators. If you look at areas like financial controls, we have accounting standards, we have independent auditors. Those are all the next natural steps for us as an industry to work toward, and regulation will end up playing a role as we go through all of that as well. Google pursues both language models and world models, while some other AI companies like OpenAI have focused more heavily on LLMs as the path to AGI. Why is world-model research important to you? As humans, you obviously perceive the world around you, and you’re taking all those inputs. Making sure these models are able to understand the laws of physics, simulate the world in high fidelity. All that, I think, are key enabling blocks for intelligence. We are working across all possible applications of this. Take an area like robotics. It’s not an accident: If you look at embodied reasoning benchmarks, Argon is state of the art. That all comes from our experience building world models. Inherently, I would expect there will be architectures which will converge all of this in the future. But for us, we view this as, today, this jagged frontier that is intelligence. We want to be at the frontier of all the possible approaches, and that will help us both drive better research, better insights, and develop a much better AGI model, is how we think about it. Some people argue Google should focus on selling its computing resources rather than using them for AI research. Cloud wants to sell compute at a high markup, while researchers need a very big computer to build the best models. How do you balance those demands? Ground zero for us is making sure we are investing in the compute that’s needed to be at the AI frontier. In 2015, I set the company to be AI-first. AI is that key horizontal ingredient across everything we do, all the way from Search to Cloud to Waymo. That is ground zero for us, making sure both for research and developing the models that we have enough compute needed. Beyond that, we have these independent businesses which each have their own long-range plans. They’re using those long-range plans to project forward, and we plan for compute for all of them. The cloud team, they have a business and they have a projection and they have demand signals. They have committed contracts. With that help, we can plan on a long-term compute trajectory for them. We’re fortunate to have this wide set of opportunities. There’s no company in the world which isn’t making trade-offs at any given moment in time. But the first principles we operate on is making sure we have enough compute to invest in the frontier, and that’s non-negotiable, and everything else works on top. Remember, we are building our own compute, our own data centers. There are long lead times. The compute we have today is a function of decisions I made in 2024. Even if you think back to a year from today, last year the agentic coding takeoff hadn’t happened. Today, obviously, when you sit and look at anything, everyone is short—not just us, other companies—and everyone wishes you had two times what you had planned for. That comes with the territory. At any given moment in time, we are planning for what we would need two to three years out in the future. You’re going to find some decisions you make may look suboptimal two years out, depending on where the state of the art is. I don’t spend too much time thinking about it. The way I think about compute allocation is making sure Google DeepMind, both for research and frontier model development, is cutting edge in terms of compute access. After that, we plan for all our businesses. It’s great we can provide our compute to other people too, like we have done. It allows us to scale that up, get real tests for it in the widest application set possible, test it in the real world, and make sure we are at the cutting edge of technology at every layer of our AI stack as well. Ben Horowitz relayed on a podcast that Andy Jassy had said compute was sold out until 2028. Are you seeing the same thing? If today a customer is coming out and asking us for compute in ’27, that is incredibly difficult to do. Even last year we went out and leased some short-term compute to accommodate some customers and help them out. But yes, we are all dealing with similar timelines. Every major technology shift seems to involve overbuilding, from railroads to fiber. Do you think that’s happening here? It depends on the time frames you’re looking at. This level of build, if I take a long enough time frame, it makes complete sense to me. We are at early stages of the most consequential technology ever, and this is not like fiber. It’s not dark. We are using it. We are capacity constrained on a daily basis. The applications, the underlying technology is improving rapidly. But running a company, the way I work through the moment is you look at your demand signals. You look at your committed revenue opportunities that you’re getting in the form of contracts. You balance that with the underlying technical capability, or internally you balance how we are using it internally, the model trajectories. Based on all that, you take a disciplined approach—a confident, aggressive, but disciplined approach—to plan out compute. But when you talk about the broader economy as a whole, you’re having people operate with various levels of risk. I focus on what I can control as a company and plan through it. If your question is, can there be an overbuild? Yes, because you can have some constrained components. Remember, what matters is a set of everything you need to build out that compute. Memory, electricity, electricians…. Land. Like 2,000 components or more. You could get constrained at some point. There could be things which cause bottlenecks, and then you could have overbuilds. There could be external shocks to the economy. There are macro risks. All that is possible at any given time. But am I confident that the compute we are planning for, we will have uses for it given enough time? Absolutely, yes. I was in the room when you said AI would be as profound as fire and electricity. If you believe that, shouldn’t you give researchers the biggest possible computer, even at the expense of today’s cloud profits? We’re all doing some form of that. Our cloud business is at any given moment in time forgoing short-term revenues because we are making compute trade-offs to support frontier AI development. What you’re seeing is true already. But you want to be thoughtful. Even our AI researchers have some constraints, which are also good. That’s what inspires creativity. That’s what helps you come up with a more efficient algorithmic breakthrough, maybe to use less memory. What we are committed to is to invest what’s needed to stay at the frontier. OpenAI President Greg Brockman told me a few months ago that the ideal AI product might have no interface at all—just as natural as conversation. What do you think the interface looks like in the age of AI? Computing historically has been humans adapting to computing. With AI, it’ll be the other way around. The technology will adapt seamlessly to how humans live and go about their day-to-day life. You want to be able to speak to that AI when you want to. It has context. It can be persistently running somewhere, give you continuity. You’re not dealing with a lot of complexity. It’s natural. All that makes sense to me. That doesn’t mean it won’t have any interface, however. Nowadays, even on my phone, Gemini voice models are so good. I can just press the microphone button. I can just ramble. That’s why we call it Rambler. I can ramble. It intelligently corrects with my personal context. Even my friends’ names, weird names, it gets it right, even if it first guesses it wrong. It’s amazing. I’m not going in, backspacing, editing once I finish saying it. It’s remarkable how good it’s gotten. But there are going to be moments you will need an interface. You may want to entertain yourself. You may want to watch a video. You may ask your AI to create something, and you want to watch it, consume it. The way I think about it is, you want it to be as seamless and as natural as possible, and that you are not doing the hard work adapting to whatever the interface is. The technology is adapting to how you’re working at any given moment in time. When I asked Sam Altman about competition from Google, he argued that OpenAI was building AI-native products and implied Google was bolting AI onto existing ones. Do you accept that framing, and can a “bolt-on” compete with an AI-native product? First of all, it’s a very dynamic moment. We are all pushing each other. OpenAI has pushed us as a company too. This is not just we are doing something to them. Far from it. Yes, Google went into its own version of a code red too. In the AI moment, all of us have to respond with varying levels of urgency at any given moment in time. We are constantly building new products as well. Gemini was built from the ground up as a product—the Gemini app I’m talking about. Or tomorrow, as all of us are adapting to agents, are you bolting agents onto ChatGPT, or are they building it natively? How would you think about that? You can always put these questions back. I don’t think of it that way. I think of it as you want to build world-class product experiences that are AI-native and they are winning. Some of it is adapting products, some of it is rethinking new experiences. They will all be part of how you approach this moment. How do you expect to make money from these AI interfaces? If an agent recommends a product and I buy it, should it take a cut of the sale, even if that’s disclosed? I’m going to put enterprise aside. Consumers are going to increasingly value this technology. Take software developers today. Developers are willing to pay for these coding models because it really helps make them more productive. Nobody would want to code the way they were coding three years ago, or even the same time last year. When you’re delivering value, there’s value to be had. I’ve never seen examples where consumer products really scale to billions of users, where people are using it intensely, and haven’t had monetization to go along with it. If you’re providing value to people, there is inherent value to be had. The nature of it may change. You’re asking a scenario in which agents are doing stuff for you. At the end of the day, you will have commercial needs. The agents need to fulfill those commercial needs. The providers on the other side are going to see value in that. There’s going to be some mechanism by which it gets fleshed out. That’s what an efficient system does. But what matters is that you’re building those world-class consumer experiences. I promised myself one product feature request: Can you make Gemini-powered search in Gmail as good as searching Gmail through ChatGPT? What’s going on here? One of the exciting things we announced recently is the unified Gemini agent for enterprise, and we’re bringing that to consumers. These are persistent agents which run 24/7 in the cloud. We’re spinning up a micro VM effectively for every query, and from the runtime, the harness, the model—it’s all a headless service. It’ll work everywhere, and it has your context with you. You can address this agent whether you’re in Workspace, in Search, in Gemini. Agents are going to drive this unification from a customer experience, which people are looking for. When you have a broad product portfolio and you’re moving forward fast, there are always areas where you’re moving forward faster than some other areas. That’s valid feedback. But we are putting a lot of time and effort into making sure, as we build out our agentic experience, that unification and that capability works well across all these services. People have asked where Google’s equivalent of Muse or Dots is. Do you anticipate creating a new product to compete with them? Our goal with Gemini is to be a personal, proactive, and powerful assistant. That’s what we are working toward. You saw us describe the early versions of it at Google I/O this year with Spark. Effectively, already, if you open the Gemini app as a Pro or an Ultra user, you see Chat and Task, and they start giving you that agentic experience. With Argon now, that capability is dramatically accelerated. What we announced recently in our enterprise event, we are bringing that to consumers as well. Soon in Gemini, you will be able to ask something, and it’s a continuum. You don’t need to think about whether you’re asking a chat or an agentic task. It’ll just automatically do the right thing, and it can work persistently in the background securely and get things done for you. Already, empirically, when I look at what’s coming into Gemini in our app, last year you would have tagged them and most of them would have been chats. But a steadily growing percentage is already agentic tasks in Gemini. Yes, we are going to bring personal agents to our consumers. It’ll work in the Gemini app. It’ll work in Google Search. It’ll work in Gmail. You can address it, call it, etc. We want to make sure we’re getting it right. It’ll be powered by Argon, and we are very excited to bring it to our users. Google has invested and committed tens of billions of dollars to Anthropic. What do you see in Dario Amodei that makes you want such a deep investment and partnership? Very early on, when we looked at the founding team of Anthropic, it was very clear to us this was a world-class team which was involved in some of the earliest GPT models. We were quickly able to assess that they would be at the frontier. We’ve always tried to identify and partner with companies which would be at the cutting edge of technology. We’ve done that with SpaceX. We’ve done that with Anthropic. That’s what we saw, and we had a chance to partner. Is your partnership with Apple to license Gemini for Siri expanding, contracting, or standing still? For both us and Apple, that partnership was about translating the capabilities of AI into better experiences for users. I thought Apple has done a phenomenal job of incorporating—they customize these models and build it into Siri—and it’s been great to see the reception. We are committed to doing more. You’re going to do more with them? There’s nothing specific to comment, but it’s a partnership. It’s working well. What have you learned so far about the feasibility of data centers in space? It’s a very exciting project. Projects like this remind me—I still recall that moment in the desert for the DARPA Grand Challenge, watching the Stanley car compete in it, which ended up being the basis for Waymo. With all these technologies, you’re at a moment in time where it looks a bit like sci-fi, but 10 to 20 years down the line, it’s actually working in a meaningful way. I feel the same in space. We’ve always believed in betting big on these technologies. Quantum has been a great example of it. We’re probably 10 years into the journey. Waymo, we are almost 20 years into the journey. Space, we are two to three years into the journey. It’s clear to me that it’s an approach which will make a lot of sense in the future. Being in sub-synchronous orbits with 24/7 access to the most abundant form of energy we have access to will make a lot of sense for this exponential increase in compute that we are going to need. Having said that, this is a challenging project. The team has disciplined milestones. It was a super exciting milestone to send the TPUs up to space. Sometime, as we are speaking, we are expecting a “hello world” moment from them. I look forward to seeing that happen, and we’ll continue investing here too. You previously said 25% of the code written within Google was written by AI. What’s the number today? That number in our world today is meaningless in the sense that every part of what we now touch is influenced by AI deeply. What we are tracking with Argon, for example, it’s been a point of inflection. People are using Argon to really go tackle complex projects, including projects which affect millions of lines of code. In the four weeks since we have launched Argon, we have seen a 30% increase in CLs, and more importantly, almost a similar increase—a one-third decrease in rollbacks. People are writing code more productively and better code with it. We are tracking it with newer metrics now. How are you dealing with opposition to data centers? If you can’t build in the U.S. the way you want to, where else do you go? We’re very committed to building our data centers very responsibly. When I look at our largest data centers in some of the communities where we have been the longest, I visit them, I talk to people. There are people who come and tell us their kids have gone to college because of our investments in these communities, and we’ve grown in those communities. To me, this is about doing it right. Engaging with the communities early, doing it transparently. We are committed to making sure we are bringing incremental power, and we cover 100% of the cost of our power needs for these projects. It’s understanding the impact on neighborhoods and making sure you’re working thoroughly to address them. Done rightly, you can continue making progress. But we are constantly taking feedback into account. I do worry not everyone operates the same way. People have been surprised by data centers showing up in their backyard. Those are all important. As an industry, we should continue to do better. But part of the reason, in a 20-year time frame, we are thinking about things like data centers in space is making sure we are able to put these data centers where maybe the trade-offs will be different. What unproven area of AI is Google working hardest to crack? Is it continual learning—getting models to keep updating after release—or something else? There are multiple parallel paths. You saw with Argon we have a million output tokens. With our Gemini models early on, we had a one-million context window on the input side. These are all examples of breakthroughs we are constantly working on. How do you think about synthetic data? How do you think about continual learning? How do you think about more efficient architectures? We do dedicate a meaningful percentage of our compute to these research bets too. It always goes hand in hand, including our world models. Those are all bets we are placing. Sometimes, as part of these bets, there are ideas that emerge which just make their way into the mainline models. Maybe we don’t fully talk about it, but we have multiple steps in these areas. Working in technology requires optimism that building something will improve the world, but those bets can leave real consequences when they fail. I recently returned to a town in El Salvador where enthusiasm for Bitcoin had given way to unfinished construction and something resembling a ghost town. How do you maintain the optimism you spoke about in your Stanford commencement address while accounting for those risks? I genuinely have a deep conviction that improving technology and improving access to technology makes people’s lives better. It’s been my personal experience in my life, out of which comes that deep conviction, optimism. But with that, I’ve always felt humanity’s journey is always about working hard to harness that technology to make it work well for society. The optimism is not an optimism that you just build whatever you want, whenever. You work hard to make sure you’re building technology in the service of humanity, to make the human condition better. That’s got to be the defining goal as we are approaching it. With that framework, I’m very, very optimistic. We are in very early stages of the kind of progress that we are going to see on many areas. We’re all talking about areas like healthcare. A lot of the progress is ahead. The ability to make things in a fundamentally cheaper way on many things where things have been getting expensive for a long, long time, discovering new materials, etc., which really bend the curve—it’s tough to step today and understand the impact of all that, but they’re going to be very profound. I’m very optimistic, but we have to be rightfully concerned about all the ways this technology can go wrong. Sundar, I know you don’t do many of these. Thank you. Thanks, Alex. Appreciate it.
GTA 6 Digital Preorders Already Topped 6 Million and $594 Million, With PlayStation Accounting for 74%, Sensor Tower Estimates
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Aprio Broadens its AI-Powered Advisory Partnership with Intuit to Further Accelerate Mid-Market Business Growth
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Is the EU research budget actually increasing?
Is a Horizon Europe budget of €158 billion a 10% cut or a significant increase to the EU’s support for research and innovation? What would seem like a question of fact has divided opinion in Brussels since the Irish presidency of the EU Council presented its negotiation box on October 10. The answer depends on factors such as how you adjust for inflation, whether you account for increases in overall EU wealth and if you care about absolute or proportional figures. The €158 billion budget in current prices, proposed by the Irish presidency of the EU Council, was quickly criticised by university lobbies and rejected by the high-level expert group led by former Portuguese science minister Manuel Heitor. It was also decried by the four pro-European political groups in the European Parliament. “How can Europe close its competitiveness gap while cutting the European Competitiveness Fund by 13% and Horizon Europe by nearly 10%?” asked a joint statement by the European People’s Party (EPP), Renew Europe, the Socialists and Democrats and the Greens/European Free Alliance. Together, these parties hold 63% of seats in the Parliament.In stark contrast, Irish foreign affairs minister Helen McEntee said that the proposal “significantly increases investment in competitiveness, research and innovation,” Meanwhile, a presidency press release said that, compared to the current Multiannual Financial Framework (MFF), the proposal would “double the volume of competitiveness related programmes.” So, who is right? That depends on how you make the calculation.Compared to the Commission figure or the previous budget?The first thing to notice is the difference in baselines. When the MEPs say the Irish presidency will cut Horizon Europe by “nearly 10%” they are using the European Commission proposal for the MFF from July 2025, which allocated €175 billion in current prices to Horizon Europe. However, when the Irish foreign affairs minister said the research and competitiveness budget is increasing significantly, she is comparing it to the 2021-27 MFF, which had a Horizon Europe budget of €84.9 billion in 2018 prices.Her point holds when accounting for inflation. Applying a 2% annual inflation rate, the calculation method used by the Commission, the 2021-27 Horizon Europe would have a budget of €97.5 billion in 2025 prices. In comparison, the Irish presidency’s €158 billion figure in current prices translates to €140 billion in 2025 prices. Does the ECF count?But there is more to the dispute. In its statements, the Irish presidency lumped the research budget in with the overall budget for competitiveness. The Parliament statement, however, kept the two separate. This matters because the next MFF includes plans to add a new European Competitiveness Fund (ECF) to fund programmes meant to boost the continent's competitiveness. The Irish negotiating box allocated €245 billion in current prices to this programme.When this is added to the €158 billion for Horizon Europe, as well as programmes such as the EU education programme Erasmus+, the total for “competitiveness, prosperity and security” in the Irish proposal becomes €514 billion in current prices. But it is still uncertain how big a share of this competitiveness budget would go to research. The Commission proposal of July 2025 for the MFF included clear links between the ECF and Horizon Europe, indicating some ECF money will go to research. At the same time, the structure of the ECF is still being negotiated, and a substantial part of its budget is expected to support non-research activities such as defence manufacturing, decarbonisation and digital infrastructure. Related articlesCouncil floats 9.6% budget cut to next Horizon EuropeResearch community to appeal to national governments over planned EU budget cutEU own resources ‘essential’ for future research budget, says leading MEPSo, it is by looking at competitiveness rather than research, or combining the two, that the Irish presidency can claim that its proposed budget will significantly increase investment in competitiveness, research and innovation.According to the Irish presidency proposal, Horizon Europe and other competitiveness-related programmes in the current multiannual budget received €221 billion in current prices. However, since this money is being distributed from 2021 to 2027, it is not directly comparable to the €514 billion in current prices which will be distributed from 2028 to 2034.Research as a proportion of the MFFBut the relative rise in competitiveness-related programmes points to another important distinction: whether you look at the research budget in absolute terms or as a share of the overall MFF. Here, too, the size of the research budget has risen, although only slightly. In the 2021-27 MFF, Horizon Europe accounted for 7% of the total budget. In the Irish presidency’s proposal, it amounts to 8.7%. The share for the total competitiveness envelope went from 17.7% in the current MFF to 28.1% in the Irish presidency proposal.This proportional share may seem irrelevant to universities looking for research funding, but it is becoming significant as budget negotiations between the Parliament, the Commission and the Council begin. On October 2, a group of 17 southern and eastern European countries sent out a statement calling for the EU agriculture and cohesion budgets to be protected. The Parliament’s co-rapporteur on the budget, Siegfried Mureșan of the EPP, has also said that the research envelope is likely to be cut disproportionately as the budget is slimmed down during negotiations.
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Brand Story – With a new Portland-area office, Kernutt Stokes brings its unique and personal touch to the Rose City region.
ON THE JOB: ‘Where Do You See Your Career or Business in 3 to 5 Years?’
“For the next three to five years, I am looking to grow Oswego County Opportunities’ support for the county’s economic development to fight poverty and take advantage of the major investments that are coming to the area.” — Kevin Dean, Executive director, Oswego County Opportunities, Fulton “I love what I’m doing. I’m trying to do this as long as they let me. It’s so exciting to walk the floors at the various factories, talk with community leaders and be part of the solutions to their business problems. As we do this work with manufacturers and community members, we are helping the next generation have these great jobs in skilled manufacturing. I’d like to have the same job title for years to come. I’ve watched the last five years with awe and it makes me proud and excited to be from Upstate New York. I want to keep being part of the conversation that, yes, we can do it in Upstate New York.” — Randy Wolken, President and CEO, Manufacturing Association of Central New York (MACNY) “I oversee the Rochester and Syracuse offices. We’re seeing continual growth as there are more and more job seekers and companies that are looking to fill positions as the economy grows. I’d like to have another Upstate New York office in our region to help promote people under me. I want to see that happen. With an increase in the job market, that is what the end goal is here for sure. We currently have offices in Rochester, Buffalo, Syracuse and Albany, among more than 300 worldwide.” — Briana Calabrese, Marketing director and vice president of finance & accounting and administrative & customer support, Robert Half Recruiters & Employment Agency, Syracuse “Hopefully, we’ll continue to grow by word of mouth. I just took over a couple of years ago. I was an employee for 27 years. Business is great and we’re up on sales from where we were last year and I’m hoping that continues to happen. I get an overwhelming response from people who say they want to support local businesses. It’s my objective when people walk out the door that they want to come back. In a small town like this, it’s crucial. I see myself in five years doing exactly what I’m doing now: sticking with it and trying to grow Fulton Screen Printing.” — Tim Stone, Owner, Fulton Screen Printing, Fulton “I am 85 years old and teach four fitness classes a week and swim four times a week. I hope to live to be 90 — if I can do that, I won’t complain. The older I get, the less afraid I am of dying. What I don’t want to do is get some sickness where I’m lingering and I’m in pain and it just goes on and on. I expect to be exercising as much as I can and I hope I will know when I need to back off to accommodate different problems I may have when I’m older. For a short time, I got up at 6 a.m. to jog for a half hour every morning. But I had to avoid dogs, so I quit jogging. I hope to be able to swim for life. When I swim for half an hour, whatever problems I have wash away. I will still be working in exercise in five years. I also write research articles. It challenges my mind. You have to challenge your mind and body and have some kind of goals and reasons to go on living. My wife died three and a half years ago, so I try to go out and do things, even though she’s no longer here.” — Fred Wilson. Certified personal trainer at Fitness After 50 and leader of senior fitness classes, Syracuse “I expect to continue working as a local financial adviser professional for the next several years. I really enjoy working with my clients and consider it a privilege to come to work every day, helping my clients reach their financial goals.” — Randy L. Zeigler, Certified financial planner practitioner, chartered financial consultant and private wealth adviser, Ameriprise Financial Services, LLC, Oswego “I see myself doing something with young people. I want to open an after-school program as a safe space for high schoolers where they can get tutored, behavioral health, get something to eat. I want to do something with policy. I have thought of doing something with neurodivergent kids where kids can run some kind of business. I want to do anything with community like therapy and psychotherapy. I want to still be able to offer those services to people. At 55, I’m not sure how much I will do. I will see what happens after graduation from Keuka College.” — Della Joyce Smith, Master’s student, Syracuse “I think the core of the gym is in personal training. I don’t see that changing. People will still need a gym and personal training will stay. There may be some loss to AI as there is in just about every industry, but there’s always been the ability to go online and get a workout. I don’t think AI will cut into business any more than the internet has. I think the class structure is shifting. Large group classes might be fading away for a while. I see more people going to specialized classes like Pilates. I wouldn’t be surprised if maybe the traditional classes like boot camps started to fade away. It’s important to adapt. Maybe someday I’ll need to get some new kinds of classes. Everything tends to go in cycles.” — Ryan Vollmer, Certified personal trainer and owner Edge Strength and Conditioning, Syracuse “I have been growing my firm at 24% a year. In five years, we may be purchasing or building a new office building to accommodate the new growth. Right now, our focus is on growth and adding team members, mostly financial advisers and administrative staff.” — Terri Krueger, Chartered financial consultant and senior financial adviser with Orla Wealth Management in Syracuse “Over the next three to five years, I see TDO continuing to experience steady, sustainable growth as new industries establish and expand their presence across Central New York. These investments will create new opportunities throughout the regional manufacturing supply chain, and TDO will continue evolving our capabilities to help both existing manufacturers and emerging industries grow, compete, and succeed.” — Jim D’Agostino, CEO and executive director Central New York TDO (Train, Develop, Optimize), Liverpool
Accounting major turned orthodontist returns to provide care in hometown
This week's Up-and-Comer is Lauren Witte, an orthodontist at Barrow Orthodontics.
How Much Of Qualcomm Stock Rides On One Business?
Phone chip revenue is the central metric to watch at Qualcomm (QCOM). Handset chips generated $5.1 billion in fiscal Q3 2026, accounting for more than half of the company's $9.9 billion in revenue. Total revenue fell 4.0% from a year earlier, and a segment that makes up more than half of sales deserves close attention.
Partners Want AI to Help Them Find New Business, But Most Are Running It on Data They Can’t Use, Introhive Survey Finds
Partners at law and accounting firms say the one thing they most want from business-development technology is help finding new business in relationships their firms already have. But 78% say the relat...
Best Accounts Payable Software for Small Business (2026): Melio Named Top Solution for Flexible Vendor Payments by Software Experts
Software Experts has recognized Melio as the top solution for flexible vendor payments, making it one of the best accounts payable software for small businesses. The review examined how the platform handles invoice capture, payment approvals, vendor transactions, accounting synchronization, and cash flow management.
How the GOP weaponized trans issues and left Democrats searching for a strategy
For the second election cycle in a row, the rights of transgender people have taken center stage politically, despite their accounting for only about 1% of the U.S. population and many voters identifying other issues as far more important.
Zoomlion Expands Mining Machinery Business as International Revenue Grows
Zoomlion Heavy Industry Science & Technology Co., Ltd. ("Zoomlion") is expanding its mining machinery business and strengthening international operations. In the first half of 2026, its mining machinery business grew by more than 57.20% year on year, while company-wide international revenue rose 12.45% to RMB 15.535 billion, accounting for 57.25% of total revenue.
Zoomlion Expands Mining Machinery Business as International Revenue Grows
Zoomlion Heavy Industry Science & Technology Co., Ltd. ("Zoomlion") is expanding its mining machinery business and strengthening international operations. In the first half of 2026, its mining machinery business grew by more than 57.20% year on year, while company-wide international revenue rose 12.45% to RMB 15.535 billion, accounting for 57.25% of total revenue.
Eide Bailly to expand with Washington accounting firm
Accounting and advisory firm Eide Bailly announced that Bellevue, Wash.-based Loveridge Hunt & Co. PLLC will join the firm, effective Oct. 19. Loveridge Hunt provides tax, accounting, audit and consulting services nationwide, specializing in the affordable housing industry. The move will give Loveridge Hunt clients access to Eide Bailly’s expanded tax, advisory and technology services.…
How to do your own bookkeeping as a small business owner
Learn how to keep accurate records, stay organized and prepare for tax season with accounting software like QuickBooks Free.
Barbour Community Health Association appoints new finance chief
Nathan Channell is the new chief financial officer of Barbour Community Health Association. His experience includes banking, accounting and financial reporting.
The Daily Roundup: Montana EMS Agencies Receive First Funds from Federal Health Program
The results are in: this year’s Great Fish Community Challenge was a record-breaking one, with 4,000 donors accounting for a total of $8.6 million going to nonprofits across the Flathead Valley.
Zebulun Egbert Joins PKF O'Connor Davies as Managing Director in Business Development
/PRNewswire/ -- PKF O'Connor Davies, one of the nation's largest accounting, tax and advisory practices, today announced that Zebulun Egbert has joined the...
Financial Integrators, LattaHarris form strategic partnership
Des Moines-based Financial Integrators and Cedar Rapids-based LattaHarris have entered into a strategic partnership to provide more coordinated wealth management, tax, accounting and advisory services to business owners, families and individuals. The firms will remain independent while collaborating to expand access to specialized expertise and resources and enhance client service. Financial Integrators provides wealth management…
Flutter Entertainment PLC Stock (FLUT) Moved Down by 7.20% on Sep 28: Facts Behind the Movement
Flutter halted Brazilian betting operations after a government provisional measure banned online gaming.An extended shutdown will reduce revenue, adjusted EBITDA, and impact non-cash accounting assets.Technical indicators show sell signals, while the company reported annual revenue of $16.38B.
181,160 share rights for AMC Entertainment (AMC)'s accounting chief vest in three January installments
Chris A. Cox's award vests in thirds in January 2027, 2028 and 2029, subject to service. Each vested unit carries a right to one Class A share.
Butler County mental health board eliminates finance department after audits find accounting discrepancies
As the Butler County Mental Health and Addiction Recovery Services Board seeks voter approval of a 1-mill, 10-year renewal levy, the board has voted to eliminate its entire finance department following the discovery of accounting discrepancies dating back more than three years.
Navigating the American Dream: How Integrated Financial Tools, Credit and Rewards Can Help Small Businesses Succeed
(Feature Impact) Owning a small business has been a cornerstone of the “American Dream” for generations. It represents the chance to transform a passion into a livelihood and legacy. However, turning dreams into reality is rarely a smooth or easy process and requires more than ambition alone. Today’s business owners need support and access to tools that enable them to overcome challenges and keep growing.#placement_678081_0_i{width:100%;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid678081 = window.pid678081 || rnd;var plc678081 = window.plc678081 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=678081;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid678081+';place='+(plc678081++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');Recent research conducted by the Capital One Insights Center shows 75% of more than 1,000 surveyed small business owners with more than one employee and annual revenues of up to $20 million are confident about the future, and 69% believe their business is actively primed for growth.While this optimism is promising, 47% of business owners still said their operations either stayed the same or became less efficient over the past year, citing issues like back-office friction and fragmented financial systems that make it difficult to get a clear picture of the health of their businesses.If you’re a small business owner eager to grow but not sure how to get there, start with this advice from real small business owners and experts at Capital One.Identify Sources of FrictionBefore you can pour effort into growth, you must understand what barriers are holding you back. Take time to look under the hood of your business to identify where time and energy is being lost.For example, you may be among the 78% of small business owners who feel stressed and uncertain about expense management – think hours spent hunting for receipts, manually entering numbers into software and reconciling accounts. Operational challenges aren’t just a hassle; they also pull attention away from important priorities like serving your customers and planning for growth. “We were focused on making as many candles as possible, especially during the busy season,” said Katie Roering, co-owner of Fontana Candle Co. “A lot of the back-office tasks like procurement, raw material purchasing, forecasting – all the really important things – were done at 3 a.m., 8 p.m. or on Saturday and Sunday, and there really just was not enough time in the day to get everything done that we needed to. We just knew as we continued to grow, we needed to streamline our processes, build out our team and keep moving forward.”Use Integrated Tools to Manage FinancesInstead of balancing 10 different tracking and analysis tools, you can turn to one-stop solutions to improve efficiency. Time gets lost when you’re forced to manually gather and interpret relevant data before you’re able to act. You need a platform that handles the busywork for you.Integrated, or “all-in-one,” financial tools – like accounting and bookkeeping platforms with automation capabilities or business credit cards featuring built-in analytical tools – allow you to easily stay on top of cash flow and day-to-day operations. For small businesses where every hour and dollar makes a difference, consolidating and automating systems can have an immediate impact. In fact, 51% of survey respondents said integrated tools have already fueled their growth.Leverage Credit Access and Rewards WiselyGrowth requires capital, so access to credit is a game-changer for many business owners, with 77% describing it as a key factor in achieving business resilience. Having funds accessible when you need them makes your business more capable of weathering storms such as equipment failures and seasonal slowdowns. It also puts the power in your hands to act when an exciting opportunity presents itself, like an inventory flash sale or the chance to advertise in a new market.Access to credit comes with another advantage: rewards. By using credit cards for your daily business expenses, you can earn cash back, points or travel rewards. Whether you redeem these to cover everyday expenses, book business trips or reinvest in the business, they can act as a bonus source of income. Learn to maximize rewards like the 84% of small business cardholders surveyed so you aren’t leaving money on the table.To learn more about how small business owners can identify obstacles, employ integrated financial tools and use credit as a tool for growth, read the full report at capitalone.com/about/insights-center.Photos courtesy of Shutterstock
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Science Vs on the 49ers Substation: Anatomy of a Hatchet Job
In August, Pablo Torre Finds Out and Science Vs released an episode about my theory that electromagnetic fields from the electrical substation beside the 49ers facility may be contributing to the team’s run of soft-tissue injuries. As the originator of the theory, I was also a subject of the episode. I sat was interviewed by Wendy Zukerman and Rose Rimler of Sciene Vs. I sent them research, connected them with scientists, and spent hours digging through the City of Santa Clara’s and Silicon Valley Power’s records to help clarify critical details. Both Wendy and Rose came off as affable and professional, showing curiosity during the interviews, with Wendy going out of her way to question the “conspiracy theory” framing itself. Then they titled the episode We Solve the 49ers Viral Conspiracy Theory. I was familiar enough with their catalog that I never expected them to agree with my theory, but I did expect them to give it a fair hearing and to deliver their findings honestly. On both counts they came up short. They were not directly dishonest in anything they said, but rather in what they left out, in how what remained was cut, and in the picture painted by those two things in combination. They asked me to recorded the interview on my phone for better audio quality, and I held on to my copy for reference later. That turned out to be a fortuitous decision. Here is the raw audio of my first interview, unedited*. Only my side was recorded, so their questions aren’t on it, but you can generally infer them from the answers, and every claim I make below about what I said can be checked against my statements in this clip. (Note: Wendy had connection trouble at the beginning of the interview and was cutting in and out, which accounts for the false starts.) 0:00 -1:19:13 Audio playback is not supported on your browser. Please upgrade. Science Vs is a fun show. It is pitched at roughly a high-school understanding of science, for an audience that is skeptical, Snopes-oriented, and worried about misinformation. Take a claim circulating online, interview a supporter of the claim, interview consensus scientists, and then tell people which side of the line it lands on. I have listened to their episodes on raw milk, seed oils, 5G and other contested issues in the wellness space. I have problems with all of them, but each at least made an honest attempt to represent the actual range of scientific opinion by talking to credentialed scientists with differing perspectives. Dissenting researchers were heard from, answered, and often given a chance to respond. This episode did not do that. This article is not a relitigation of the science. I have written extensively about that already. This post is for the record. It is simply an accounting of what was wrong with their episode. Contents Is there a power plant next to the 49ers practice facility? — the clearest single example of getting something objectively wrong For the record — a high-level overview of all of the problems with their investigation Draw your own conclusions — why they had to make this episode at all What they left out about childhood leukemia — the exposure threshold, and playing games with statistics to minimize sick children What they left out about the mechanism — the body of literature they refused to cover, and evidence for the mechanism used against it The scientists Science Vs interviewed and did not air — four credential scientists who support myhe theory, recorded and cut, or not even called How they misrepresented me and my case — an answer severed from its question, and three telling edits How you would actually study the injuries — it doesn’t actually matter which team is the most injured, overall The theory: magnetic fields, oxidative stress, and collagen Since the episode never states my theory, here it is below. Those who are familiar with my work can skip this section. Electrical equipment produces magnetic fields, and those fields induce faint electrical currents in anything that passes through them, including people. My argument goes further than induced current. Mitochondria — the structures that generate a cell’s energy — run on continuous flows of electrons and protons, and those flows carry faint electromagnetic fields of their own. Maxwell’s principle of superposition shows that when two fields share the same space, they add together. An external field does not need to be strong to alter an internal field, it only needs to be present. The electron transport chain inside the mitochondria leaks a small fraction of its electrons by design, and those become reactive oxygen species — free radicals, which healthy cells use as signals. External magnetic fields cause the rate of leakage to change, increasing free radicals. When free radicals accumulate faster than the cell’s antioxidant systems can clear them, the result is oxidative stress. Oxidative stress is a recognized driver of chronic illness, including cardiovascular disease, neurodegeneration, diabetes and cancer, and it is in every medical school curriculum. One of its ordinary effects in connective tissue is that it switches on matrix metalloproteinases — MMPs, the enzymes that break collagen apart — while suppressing new collagen synthesis. Tendons are made of collagen. An athlete loading his soft tissue heavily six days a week is already creating oxidative stress in the tendons, so the addition of magnetic field exposure compounds the damage and inhibits repair, making him more susceptible to injury when enormous force lands on a tendon in a fraction of a second. That is the theory. We know that EMF causes oxidative stress, and we know that oxidative stress degrades collagen. The only thing missing is a study showing that direct connection. I have never claimed certainty that the substation is contributing to the elevated injury rate. I do believe it is likely, and I believe it warrants caution, and that a revenue machine like a major NFL team can easily afford to remove the exposure out of precaution. Is there a power plant next to the 49ers practice facility? Here is the clearest single instance of the problem with this episode. It requires no knowledge of electromagnetic fields at all. This story first came to me through Jon Feliciano, a former 49er, in an interview on Willard & Dibs on 95.7 The Game. Asked about why the 49ers are always injured, he said players used to joke that it was the power plant behind the practice fields. Wendy Zukerman corrects him on air. “It’s important to say that it’s not a power plant near the 49ers site.” Torre then asks her to explain the difference between a substation and a power plant. Her answer: a power plant generates electricity and transmits it to a substation, which converts the voltage into something your house can use and sends it on to your home or your business. There are two problems with that. The first is that there is a power plant on that site. The Gianera Generating Station is a natural-gas-fired peaker plant owned by Silicon Valley Power, and it has been there since 1986. I have published aerial photographs of the location from 1987 in which the gas plant is the only thing standing, before the practice facility was even there. I even mentioned the gas plant in my first interview. (Feliciano has since gone on record about this issue, and it is clear he had the substation in mind rather than the gas plant.) The second is that her definition describes a distribution substation, and the facility beside the 49ers is not that. It is the Northern Receiving Station, which takes in bulk power from outside the city’s grid and delivers it to distribution substations. Silicon Valley Power’s own map distinguishes receiving stations from substations, and Rose Rimler even reads the label out loud in the episode when she walks through that map on air. A few minutes before the map segment, Zukerman tells Torre: “like I said, we fact check everything.” Well, maybe not everything. I made a mistake On the morning of July 6th, at 10:20, I sent Rose and Wendy two studies. During the interview I had been asked which human studies show oxidative stress from electromagnetic fields, and I had not been able to name one on the spot. Rose emailed asking for the studies, I quickly searched for a couple, and I wrote that I thought these were the most relevant from that search. Unfortunately, I was busy and did not read either one closely at first. I picked them because they were topically relevant — one on substation workers, one on power plant workers. Neither were great studies, and their problems go past the ones raised in the episode. That was careless on my part. There is context that did not make the episode, though. Before that email I had been on a Zoom call with Rose talking about EMF and oxidative stress, and I pointed her to Dr. Henry Lai at the University of Washington, who has spent years aggregating the literature on this question. His tallies show that roughly 90% of studies since the late 1990s find oxidative effects from electromagnetic field exposure — hundreds of studies, systematically counted. Rose told me she was already aware of his work. So when she asked for studies, I understood her to have the aggregate view already and that she would report anything within that context. Not reading those two carefully was still a mistake, but the larger mistake was assuming the episode would be based on a thorough review of the actual body of literature, rather than on whatever I happened to send that morning. The second email At 1:49 that same afternoon — three hours and twenty-nine minutes after the first — I sent them a second email that I had been preparing for a while. It was a structured document in six numbered sections, written in response to a request they had made two weeks earlier, laying out my entire argument with citations attached to every link in the chain. The episode aired on August 13th, five weeks later, and not a single item from the second email is in it. Here is how it opens: The full email is included at the bottom of this post in Appendix B. Nearly 1,500 words in total. It contains two named mechanisms with the physics behind them. Occupational studies in humans. The literature on oxidative stress and collagen. A section addressing the strongest counter-evidence against my own theory, which I raised myself. And a closing section stating plainly what the theory cannot yet show. My entire argument, in writing, with detailed citations for every claim, provided to them five weeks before broadcast, and none of it made it into the episode. That is the single largest omission, but it is not an isolated one. The whole episode is riddled with similar problems, and the conclusion they came to is not merely a difference of opinion about the scientific evidence. Through omission and through strategic editing, Science Vs misinformed its audience — about what the evidence shows, about what I argued, and about who they spoke to. That is a notable outcome for a show whose stated purpose is correcting misinformation. For the record I am not going to tell you that Science Vs set out to discredit me, or that they had come to their conclusion before they reported the story, or that they used misleading editing to make me look like a man retreating from his own theory. I cannot know what was in anyone’s head, and I am not going to pretend otherwise, either. What I can tell you is what is on the record. They asked me for evidence and aired the weakest thing I sent. They interviewed three scientists who supported my theory and aired none of them. They discussed childhood leukemia without ever saying the exposure level at which it appears. And they took an answer I gave weeks before Ken Karipidis, the one EMF scientist who was put on air, was interviewed, and placed it directly after his critique, where it comes off as a major concession. A friend of mine who has worked as a journalist for thirty years read that last one and called it sleazy. I agree with her. Those are just the four issues that are impossible to defend as pure editorial decision, but they are not the only issues. The most glaring issues stem from what they left out: The exposure level at which the childhood leukemia association actually appears — three to four milligauss, a number the episode never states despite it being much lower than what I measured. The mechanism itself: The episode gets as far as “oxidative stress could weaken collagen,” which leaves it sounding like speculation, rather than a known pathway. The second email, and all the studies in it. Dr. Paul Héroux at McGill, whose work my proposed mechanism rests on, whose contact details I supplied, and who was never called. Dr. Beatrice Golomb at UC San Diego, who runs a research group on oxidative stress and mitochondrial function and has specific expdertice in collagen, interviewed and not aired. Dr. David Carpenter at Albany, the most prominent academic voice on the harm from magnetic field exposure, interviewed and not aired. Dr. Joel Moskowitz at Berkeley, interviewed and not even credited. The specific, testable condition I put in writing that would make me abandon the theory. My own unprompted statement of the theory’s evidentiary gap. My caveats about my own measurements. My ranking of EMF as one factor among several rather than the only one. The new equipment installed at those facilities between 2010 and 2014, and the sharp rise in system load from 2013 onward. But that is not all. What they kept, they selectively edited to serve a narrative that was not served by the raw transcripts of the interviews. A description of thousands of commercial routers in a workplace, reduced to the Wi-Fi in your house. My own acknowledgment, multiple times, that "I'm not a scientist" clipped in an episode that spends considerable energy pointing out that I am not a scientist. And a qualification I volunteered about my own measurements, cut from my answer and delivered later by their EMF expert as a correction. Together their edit produce a portrait of a wellness guy with Wi-Fi phobia and two bad studies, backing away from his theory the moment a “real” scientist looked at it. A practice facility where nothing changed because no new substation was built. Injuries written off as random because the 49ers were not quite the single most injured team in the league over the period in question. That portrait is false even though almost no individual statement made in the episode is. Draw your own conclusions At the top of the episode, Pablo Torre says his show had been flooded with requests to investigate the substation — that it was the thing they were asked to look into over and over again. Neither show went hunting for this story. It arrived from their own audience, in volume, and it could not be waved off. A thread I posted on X reached twenty-two million people. A guy with a gaussmeter and a brand-new Substack obligated a Pultizer prize winning program to spend an hour on a question about player health, that is considered fringe enough that most media operations won’t touch it. Pablo Torre Finds Out could not ignore it. So Science Vs came in and ran a “debunking” operation instead of an investigation. Everything below is what had to be left on the cutting room floor to deliver the “debunking”. They could not ignore it. So they tried debunked it instead. The demand was strong enough to force an episode, and since the episodes release the 49ers have sustained more injuries, including season ending ones, and interest has only grown. Demand from fans and playets is strong enough to force a better investigation from someone else. An omission is not a lie until you find out what was omitted. What follows is the detailed record so you can see the full picture. Draw your own conclusions. I have drawn mine. I am going to keep publishing. A note about Pablo Torre Finds Out After the episode aired I posted publicly, calling out Pablo Torre Finds Out for concerns I had about the integrity of their investigation, and about an interview directly with Pablo Torre which had been offered but never happened. I have since spoken with a producer at PTFO. The offer had rested on a misunderstanding about where things stood between us, and it fell away as the Science Vs part of the production widened past the science. He apologized for the miscommunication and I accepted. The producer also confirmed to me that they did essentially hand off the entire investigation to Science Vs for narrative purposes — so Pablo would be genuinely curious or potentially surprised by their findings — while still taking responsibility for what went out under their name. I appreciated the candor and the accountability, and I am comfortable with where we left things. So this post is not about PTFO. My disagreement is with Science Vs. What they left out about childhood leukemia Childhood leukemia appears at three milligauss. They gave no number at all. 1. They built an EMF ruler, then discussed childhood cancer without it. The sequence on air went like this: First I measured almost 9 mG, then I measured up to 50 milligauss. Torre reacts with concern — “that sounds high.” Cut to Karipidis: the public limit is 2,000 milligauss. Torre reacts again — “What happens at 2,000?” Karipidis explains that nothing happens at 2,000, that safety factors are built in. Then: at more than 50,000 milligauss you get flickers of light in the retina, and higher still, nerve stimulation. The listener now has a ruler (their ruler) to measure these numbers with. Fifty is nothing by their ruler. Then the episode turns to childhood leukemia and states, accurately, that there is a real association — but tellingly, they never give the exposure level at which that association appears. Childhood leukemia appears at three milligauss. They conveniently left that out. The pooled analyses that produced the World Health Organization’s carcinogen classification found roughly a doubling of childhood leukemia risk above three to four milligauss. That is the number that belongs in that segment, and it is more than ten times below the reading that had just been dismissed as trivial. I gave them that number myself, on tape, in the interview. Describing my own threshold, I said my comfort level for long-term chronic exposure is three to four milligauss, but preferably one. 2. Six children in thirteen million. The episode reports that these fields might explain one to four percent of childhood leukemias, then reframes it as a German estimate of perhaps six cases among thirteen million children. Torre, to his credit, is uncomfortable. What never gets explained is why that number is small. Almost no children lives above three milligauss in Europe. Fewer than two children in a hundred, in the Italian data. So even if the risk to those children doubles, the number of additional cases across an entire country stays small — not because the hazard is small, but because hardly anyone is exposed to it. Count the whole population and the few who are exposed disappear. And the reason hardly anyone is exposed is that siting rules keep housing away from transmission lines. In Europe, at least. The Dutch government has a standing precautionary policy against building new homes in any zone where the annual average magnetic field exceeds 4 milligauss — the same number the episode never mentioned. Denmark and Norway treat 4 milligauss as the level that triggers a look at mitigation. That is five hundred times below the ICNIRP figure quoted on air. The United States has no federal equivalent. That is evidence of infrastructure siting policy working. It is not evidence that there is no hazard. It is evidence that we already act as though there is one. If you listen to the raw audio you will hear that my proposed solution is EMF exposure is to build better infrastructure. What they left out about the mechanism 3. They accused me of cherry-picking, and then cherry-picked themselves. On air, Zukerman tells Torre that people who worry about electromagnetic fields dismiss the studies showing null results and collect the ones showing harm, and that this is why you have to be careful not to cherry-pick. They had two papers I had rattled off in a hurry, and a second email containing a carefully chosen set. They ran the two weakest, graded them on air, and presented the result as the state of the evidence for not only my theory, but the whole question of oxidative stress from magnetic fields. That is cherry-picking from my emails. The bigger picture is what they did with the literature as a whole. Zukerman acknowledges it exists, dismisses it, and disposes of it in a single stroke. You can go online right now, she tells Torre, and find scores of studies showing these fields increase oxidative stress. The issue, she says, is that they are not studies in people. Many of them are in people. The occupational studies in my second email are in people. That email had been in her inbox for five weeks. She waved off the literature on a factual claim that the documents in her possession contradict. (I have written separately about the evidentiary standard at work here). The effect was that they essentially baited me: ask the subject to supply the evidence, take the weakest thing he sends, and let that stand as a proxy for the whole argument. Wendy has been doing this show for ten years and clearly knows how to extract what she needs for her desired narrative. 4. They presented the collagen-improvement research as a gotcha, but I had already addressed it. The episode treats the existence of studies showing that EMF can improve collagen as a surprise that undercuts me, but I had pre-emptively addressed that five weeks earlier in the email they ignored. Those studies use measured, high-intensity pulsed dosing. The mechanism by which they work is oxidative signalling. The cell reads a controlled rise in reactive oxygen species as a warning, upregulates its antioxidant defenses, mounts a repair response, and the therapy stops before the system is overwhelmed. The key point is that it induces an oxidative response, which means those studies are actually evidence for my proposed mechanism, not against it. A field that produces a therapeutic effect cannot be biologically inert (which is the implication when they say “Nothing happens at 2,000 milligauss). Chronic ambient exposure is the same pathway with no off switch, and it is most consequential during the evening and while sleeping, when the body is in repair mode and the exposure does not stop. Section 5 of my email is titled What about the study showing improved collagen synthesis. I raised the counter-evidence myself, explained why I did not think it refuted the theory, and wrote that I was disappointed the question had not come up in the interview. That is worth holding against the cherry-picking charge in the item above: the studies they presented as inconvenient for me were studies I had gone out of my way to put in front of them. 5. Section 1 of my email stated a critical argument that was never put to the expert directly responsible for it. My email says the exposure limits exist to prevent acute effects and do not address chronic exposure at all, and that my dispute is with the entire framework. Zukerman gestures at this once. After Karipidis gives the 2,000 milligauss figure, she tells Torre that I would object because those levels do not capture “more subtle effects.” That is not my argument, and “subtle” is doing a lot of work here. My argument is that the limits are built to prevent acute effects — nerves firing, muscles twitching, etc — and were not designed to address chronic exposure at all. In fact, ICNIRP’s own documents state as much themselves. Mine is a structural objection to what the standard measures, reduced as a concern about subtlety, it becomes a matter of degree, rather than a categorical difference. They interviewed Ken Karipidis, vice chair of ICNIRP — the body that writes those limits. He was asked what the limit is, but he was never asked how it applies to chronic exposure. The scientists Science Vs interviewed and did not air 6. They interviewed four officials of the standards body. The episode credits roughly a dozen researchers. Four of them are associated with ICNIRP. Ken Karipidis is the vice chair. Rodney Croft chaired ICNIRP from 2020 to 2024 and led the development of its current guidelines. Dan Baaken is ICNIRP’s scientific secretary. Frank de Vocht sits on the Main Commission. One of them speaks in the episode. Their institution’s position is more than adequately represented — the 2,000 milligauss figure, the safety factors, the assurance that nothing happens below the line. 7. The four who were left out. Dr. Beatrice Golomb is Professor of Medicine at UC San Diego — a physics undergraduate degree, a PhD in biology, an MD. She directs a research group whose stated focus is the relationship between oxidative stress, mitochondrial function and health. That is the mechanism the episode spent its first half dismissing. Her published work includes the fluoroquinolone case series behind the FDA’s black box warning on an antibiotic class that ruptures tendons, where the accepted mechanism is oxidative stress and mitochondrial toxicity — the back half of my chain, already on a drug label. She is in the credits. She is not in the episode. She has told me she finds my theory biologically plausible, and that she has a recording of her interview. Dr. David Carpenter directed the Institute for Health and the Environment at the University at Albany for decades and is the most prominent academic voice arguing these fields cause harm. Childhood leukemia is the reason these fields carry a WHO classification at all, and Carpenter is the person you call if you want that case made by someone who has spent a career on it. He is in the credits. He is not in the episode. He has told me that when he was interviewed they could not have been less interested in what he had to say. Dr. Joel Moskowitz directs the Center for Family and Community Health at UC Berkeley’s School of Public Health. He told me directly that they interviewed him and that he thought it went well. He does not appear in the episode, and unlike Golomb and Carpenter, he does not even appear in the credits. Dr. Paul Héroux at McGill is the researcher whose work provides the foundation for the oxidative stress mechanism my theory rests on. I gave Rose his email address and phone number. He was never interviewed. They never even called him. 8. “He’s not a scientist.” The episode leans hard on the fact that I am not a credentialed scientist. Zukerman says it. Torre repeats it. “At all.” Having built a segment on that, they then left out the physicist-biologist-physician, the professor of public health, the director of a university environmental health institute, and the McGill researcher whose work the primary mechanism comes from. They spent the episode telling their audience I am not a scientist, and then kept four actual scientists who support the theory off because their argument does not survive otherwise. How they misrepresented me and my case 9. They played my words as a response to an interview I had never heard. Near the end of the hour, Zukerman says she went to me and told me the evidence was lacking. Then she plays me saying I am not wedded to it being an EMF, that I have staked my reputation on it needing more study, and that I am not certain of anything. That segment was placed immediately after Karipidis had finished taking the cherry-picked papers apart. It plays as a man folding under expert scrutiny. Commenters have used it against me since, but it is incorrect. Here is the sequence as it happened. I was interviewed. Karipidis was interviewed weeks later. I was never told what he said, or even who he was. I was never asked to respond to it. I did not know his name until the episode aired. That is not a simple editing decision. That is a quote from one interview, moved to follow a critique from a different interview it was not a response to, so that it would land as a concession. A friend of mine who has spent thirty years as a journalist read that sequence and called it sleazy. She is right. The full passage is reproduced in Appendix A, and it is worth reading. What airs is the preamble. Four paragraphs later I say “to directly answer your question” — and that answer, about what would change my mind if the team relocated, is not in the episode. Neither is the sentence two paragraphs on, where I say the EMF might turn out to be ten percent of the problem. I will say the underlying point again, though, because I meant it and I still do. I am not wedded to my theory that magnetic fields from the substation are contributing to the 49ers injuries. I could be wrong. What I am wedded to is the process of scientific inquiry, and the fact that we should be cautious around these exposures and we need more independently funded studies. 10. Three telling edits. They cut “I’m not a scientist” mid-sentence. What I said: “...and I am not certain of anything. I’m not a scientist. To me, I find the mechanisms compelling. I will go back to the fact that I got into this not because of the 49ers, but because of clients I was working with who suffer from EDS...” What aired: “...and that I am not certain of anything. I’m not.” The clip ends on the first two words of the sentence in which I say I am not a scientist, in an episode that spends considerable energy establishing that I am not a scientist. The full sequence is in Appendix A. They cut my own description of my work. Asked what I do, I said I run a wellness business, that I am focused on writing software to help people navigate environmental stressors, that environmental health is my focus, and that I also do independent journalism and research. What aired is the wellness business and the environmental health, with the software and the journalism removed from my own answer. The software engineering does come up later — narrated by them, as a hacker who grew up to write firmware — but my current work, in my own words, arrives as “wellness guy.” Thousands of commercial routers became home Wi-Fi. What I described: working at a wireless networking company surrounded by thousands of Wi-Fi routers, and a stress-induced health collapse afterward that working in that environment contributed to. What aired: Wi-Fi, the kind you have at home — reinforced by a clip of Christian McCaffrey talking about turning his router off at night. Three cuts, and every one of them makes me seem less credible. That is not a coincidence. 11. I gave them my own caveats and the test that would disprove me. In the first email I wrote that a well-designed chronic, ambient-level exposure study in tendon showing no collagen degradation, run over many months, would undercut my confidence in the theory. That is a specific, testable condition, stated in advance and in writing. There was a second interview, weeks later, which was not used in the episode, but in that I asked again for the falsification criterion to be included. What the episode presents instead is a man saying “we need more study,” which reads as a hedge, an open-ended request for the benefit of the doubt. It is the opposite of a hedge. Section 6 of my second email says, unprompted, that as far as I am aware there is not a single study showing EMF-driven oxidative stress degrading collagen in a human in vivo or in human tendon in a lab. I wrote that because it is true and because it is the first thing anyone should check. Under their standard it becomes the hinge of the entire first half, framed as something they had to surface without my cooperation. I had handed it to them five weeks earlier. And in the interview I said that my 25 to 50 milligauss readings were taken at knee level, and that these fields attenuate quickly, so by the time it reaches your head it is not that high anymore. That did not air either. The qualification arrives later, from Karipidis, as a correction. How you would actually study the injuries 12. They measured the wrong thing. The episode spends its final act on whether the 49ers are the most injured team in the NFL, finds no clean ranking, and lands on “injuries are random”. That is the wrong test. You would define the exposure — measured field levels at the facility — and the outcome narrowly: soft-tissue injuries, not a single MSK injury count that a broken finger and a ruptured Achilles both land in. Then you would compare the 49ers to themselves before and after the exposure changed, and compare that change against every other team over the same window. That controls for league-wide shifts in rules, turf and training load. It is a difference-in-differences design, and it is standard. I sent them that argument on July 28th, in writing, along with the fact that in eleven of the past twelve seasons the 49ers had finished top ten in Adjusted Games Lost. And by the episode’s own reporting, the 49ers are second in games lost to injury over the past decade, with FTN’s Aaron Schatz confirming that once you adjust for starters they come out second worst in the league — after having been one of the healthiest teams for years before that. A finding like that is where an investigation starts, not where it stops. 13. I did a lot of substation research for the episode that was never aired. I had reported that the substation next to the facility was expanded in 2014. That was wrong, and Rose Rimler and I sorted it out together. They gave me credit on air, which I appreciated, but framed it as a concession on my part to something they had found. In fact I had been investigating it myself, was uncertain before they asked, but was waiting for clarification from Silicon Valley Power. The uncertainty centered around a substation named “Esparanca” that was proposed right behind the facilities as part of the stadium construction, but now appears to never have been built. I spent days in Silicon Valley Power’s records, and did eventually reach Silicon Valley Power for confirmation and indentified the mistake myself. I also gave them highly detailed documents on what we do know about those facilities: new equipment installed between 2010 and 2014, and load growth across the system with an inflection around 2013–2014, with the Northern Receiving Station carrying the highest capacity in the system and sitting closest to the data center corridor. None of that is in the episode. I have a separate piece about it coming out soon. *I cut 2 seconds from the raw audio to remove personal information that had no connection to anything in the episode. Appendix A: the passage the clip was taken from This is the sequence from my first interview, in full. The episode uses one fragment of it. It’s tricky because my understanding is that there’s something like a 15-year half-life on collagen remodeling issues. They’re going to get a new crop of players. What I really need, though, is for the injuries to be broken down so we can see the soft tissue injuries. Right now, they’re categorized as MSK injuries, but let’s say we can actually identify them more specifically. Is that right? He was able to do that? Oh, cool. I wasn’t able to find that information. Interesting — I didn’t know that data existed. I tried so hard to get it, and I didn’t know it was available. Maybe you could connect me with that person. That would be amazing. I’m not wedded to it being an EMF, honestly. I’m not. I would say that, to a certain extent, I’ve staked my reputation on the fact that it needs more study. It’s important to look into it, and I am not certain of anything. I’m not a scientist. To me, I find the mechanisms compelling. I will go back to the fact that I got into this not because of the 49ers, but because of clients I was working with who suffer from EDS, Ehlers-Danlos Syndrome, a tendon hypermobility issue. This condition is documented to be partially caused by oxidative stress. I’ve worked with them to mitigate their EMF exposure and have seen people improve. I think it’s a bigger story. In a way, the 49ers represent an occupational cluster with specific exposure risks. If someone would conduct a study on this, I believe we could learn a lot. Perhaps we would discover that it’s like, okay, maybe it’s 10% of the problem. I don’t know the exact number, but I think either way, conducting the study would provide valuable insights. To directly answer your question, it’s challenging for me because it’s part of a bigger story. If the 49ers move and stop having injuries, I might conclude that it was related to the substation. However, if they move and still experience injuries, I would want to analyze the nature of those injuries. Are they primarily soft tissue injuries? I don’t think it’s necessarily a case closed, but the story might lose traction at that point regardless. Three things are worth noting. The aired fragment stops immediately before the sentence in which I say I am not a scientist — the cut described in item 10. It also stops four paragraphs before the words “to directly answer your question.” What the episode plays is the throat-clearing. The actual answer, about what would change my mind, never airs. And two paragraphs in, I say the EMF might turn out to be ten percent of the problem. That is the ranking the episode says I never gave. Appendix B: the full email, July 6th, 1:39 PM Hi Rose, You asked me to send you some studies a couple of weeks ago. I apologize for the delay. I have been incredibly busy. I also wanted to give you a chance to dig in yourself, and get your own perspective before I influenced you too much with mine. That said, I do want to make sure that the actual argument is abundantly clear, so here it is! One note before I begin, there are really two separate questions here: Does the substation cause the soft-tissue injuries? That was my specific claim, and what the podcast is about. Is the theory biologically sound? Can 50/60 Hz fields at these levels do anything biological below the safety limits? Question two is why people have been calling me a conspiracy theorist. The regulatory and advisory bodies (ICNIRP, etc) maintain that anything below their exposure limits is biologically inert, and that position is broadly accepted within the mainstream, but the actual science paints a different picture. To defend my theory I’ve had to defend a much larger claim: that the advisory bodies have the biology wrong. I can’t honestly answer question 1 without first addressing that. Here’s is a simplified outline of my theory, with links to studies: 1. Advisory body thresholds for biological effects The ELF magnetic-field limits (ICNIRP’s ~2,000 mG public / 10,000 mG occupational) exist to prevent acute effects from exposure. If a magnetic field is strong enough, it makes nerves fire and muscles contract. Muscles twitch. You can see faint flashes of light in your vision. People can even feel tingling or even a shock. That happens due to Faraday’s law, which states that a time-varying magnetic field induces an electric field inside the body via the creation of Eddy currents.The standards assume that those currents do nothing below the twitch threshold. They do not consider chronic effects at all. My argument is that they are biologically active and do have chronic effects. 2. There are multipe ELF-EMF mechanisms for inducing oxidative stress. This is basic biophysics. Below are the two primary mechanisms. Simplest first. Dr. Paul Héroux of McGill has the most intuitive explanation, which rests on Maxwell’s principle of superposition: because Maxwell’s equations are linear, two sets of electromagnetic waves sharing the same space simply add together. In the interview I pictured a pebble dropped into a pond, sending out clean ripples. Then a boat motors past at distance, sending larger waves, and where they meet the ripples, the two add together and the original pattern gets distorted. In our cells, the mitochondria run on continuous currents of electrons and protons that carry their own faint electromagnetic fields. An external field from a substation, by the principle of superposition, adds to those internal currents and shifts the pattern. The electron transport chain in the mitochondria leaks a fraction of its electrons by design as reactive oxygen species (ROS), which act as signalling molecules in a healthy cell. Distorting that field increases that electron leakage, creating oxidative stress. A tiny electromagnetic interference results in a large downstream effect. https://www.sciencedirect.com/science/article/pii/S2405844025006474 The more complex pathway is Dimitris Panagopoulos’s Ion Forced-Oscillation / Voltage-Gated Ion Channel (IFO-VGIC) mechanism. Weak, polarized, low-frequency fields force the ions (calcium, potassium, sodium) next to an ion channel’s voltage sensor to oscillate; because that force scales with the inverse cube of the distance involved, fields far below the stimulation threshold can still force the channel open, disrupting the cell’s ion balance and driving ROS overproduction (Nitric oxide and superoxide interact and produce peroxynitrite, a highly unstable cytotoxin that breaks down into free radicals). https://www.researchgate.net/publication/366088934 https://www.spandidos-publications.com/ijo/59/5/92 https://www.mdpi.com/1422-0067/22/18/10041 https://www.frontiersin.org/journals/public-health/articles/10.3389/fpubh.2025.1585441/full https://pmc.ncbi.nlm.nih.gov/articles/PMC3772193/ 3. Evidence of oxidative stress, in vivo, in humans from ELF-EMF There are many studies, and the strongest are occupational, which applies to the 49ers situation. 115 power-plant workers vs. 145 office controls. Serum malondialdehyde (MDA, the standard lipid-peroxidation marker), superoxide dismutase, and catalase were all significantly higher in the exposed group, and the markers rose with increasing field exposure. https://journals.sagepub.com/doi/abs/10.3233/WOR-203244 A follow-up where they reversed the oxidative stress in power plant workers. A double-blind randomized controlled trial: 91 power-plant workers given vitamin E, vitamin C, both, or placebo for 90 days. The antioxidant groups showed reduced lipid peroxidation and raised antioxidant capacity versus controls. https://pubmed.ncbi.nlm.nih.gov/32191586/ A spot-welder study: 46 welders occupationally exposed at 50 Hz, showed significantly altered red-blood-cell antioxidant enzyme activity and concluded ELF-MF “might act as an oxidative stressor… even at the recommended levels of exposure.” https://pubmed.ncbi.nlm.nih.gov/18504600/ A substation-specific study found oxidative stress and DNA damage https://pubmed.ncbi.nlm.nih.gov/24460415/ 4. Oxidative stress degrades collagen This half isn’t controversial at all. Oxidative stress activates the matrix metalloproteinases (MMPs) that break collagen down and suppresses its synthesis. Here are three example studies: Siwik et al. 2001: Oxidative stress raises MMPs and lowers collagen synthesis in cardiac fibroblasts. https://pubmed.ncbi.nlm.nih.gov/11121376/ Fisher et al. 2009: Collagen fragmentation drives oxidative stress and elevates MMP-1 in aged human skin. https://pmc.ncbi.nlm.nih.gov/articles/PMC2631323/ Varani et al. 2006: Decreased collagen production in oxidatively aged skin. https://pubmed.ncbi.nlm.nih.gov/16723701/ 5. What about the study showing improved collagen synthesis I’m glad you asked this question, and I’m bummed we didn’t get to it in the interview because it is a great question, and very important to understand. Superficially it may appear to be a refutation of my theory, but I would argue that it actually supports the underlying argument. That study used a short, high-intensity pulsed dose: therapeutic-PEMF, the same type of field used clinically to stimulate bone and tissue healing. The reason this works is because it triggers the very same biological pathways that can lead to oxidative stress. The exposure still stimulates ROS production, but done at a controlled dosage, for a limited duration it has a different effect. The cell reads the ROS as a warning signal and it upregulates its antioxidant defenses, and mounts a repair/proliferation response. The therapy is then stopped before the cell gets overwhelmed. That is essentially a hormetic response: a small dose of a stressor producing a beneficial adaptation. Two things follow: At the very least, this means the field is biologically active, which by itself undercuts the regulatory claim that these fields are inert below their thresholds. There is a wealth of literature on PEMF (pulsed EMF) bone regeneration and calcium channel signalling (which is the second mechanims in section one). Here is one. https://www.nature.com/articles/srep13856 At best, it leads us straight to my actual concern, which is that under chronic, chaotic and unregulated exposure, the cell’s antioxidant capacity gets overwhelmed, resulting in oxidative stress. There are plentiful examples of things that are beneficial at controlled doses, but harmful at uncontrolled doses. Excecise is one obvious, uncontroversial example. Botox is perhaps a more interesting example. 6. What about a study that shows EMF causing collagen degradation in humans? As far as I am aware there is not a single study showing EMF-driven oxidative stress degrading collagen in a human, in vivo, or in human tendon in a lab. There are studies involving isolated fibroblasts though, which secrete collagen. The most relevant one showed that human fetal scleral fibroblasts exposed to 50 Hz ELF-EMF showed a significant decrease in collagen synthesis and that MMP-2 expression was upregulated, which is the exact mechanism I described in section 2. https://pmc.ncbi.nlm.nih.gov/articles/PMC3626379/ That’s it! Thanks again for the interview. Best, Peter Anthony Cowan Environmental Health · Wellness Tech · Researcher & Journalist Publisher & Editor, Living Energy Bio: petercowan.comSocial: X · Instagram · TikTokApp: sunlightis.lifePhone: [redacted]
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Social Security is Facing a Political Crisis
On Tuesday the Social Security Trustees released their latest report on the system’s finances. The numbers didn’t change much: Unless something is done, the Old Age Survivors and Disability Insurance (OASDI) program, Social Security’s official name, will be unable to pay full benefits starting in either 2032 or 2034, depending on some technical issues. That’s not far away: If the Trustees are right, the prospect of a Social Security crisis will loom over the next presidential administration. It’s important to understand, however, the nature of the looming crisis. It won’t be an economic crisis. It won’t even be a serious fiscal crisis. Whatever you may have heard, Social Security isn’t in danger of going bankrupt. What we’re facing, instead, is potential political crisis. Congress and the White House could easily take action to sustain America’s retirement system. But given the current state of our politics, there’s no guarantee that they will. There is a widespread misunderstanding of how Social Security works. While Social Security was designed to look like a pension fund, it isn’t. A pension fund pays benefits out of a stock of assets it has accumulated over time. In contrast, Social Security operates as a government transfer program, like food stamps or Medicaid. Now, unlike food stamps — but like the highway trust fund — Social Security is on paper supported by a dedicated tax, the payroll tax, that is assigned to that program. But I say “on paper” because from an economic point of view assigning the payroll tax to Social Security is just an accounting convention. What matters for the U.S. economy is the overall balance between government spending and government revenue, not the difference between one type of spending and one source of revenue. So there’s no inherent economic significance to the fact that by 2034 payroll tax receipts will be insufficient to cover promised benefits. There is, however, a legislative issue. As long as the Social Security Administration can pay benefits out of payroll taxes and its cash reserve, there’s no need for Congress to vote each year to authorize benefits — they just keep going out until further notice. However, once those resources become insufficient, benefits will fall —by 17 percent according to the Trustees — unless Congress passes new legislation that “tops up” Social Security’s finances. Yet the current administration and Republican party are such extremists that there is a real risk that Social Security will be held hostage on behalf of their goals. If this should come to pass, the hostage-takers will claim that shoring up Social Security is unaffordable. Right on cue, Mike Johnson, the Trump-sycophant Speaker of the House, declared on Monday that “entitlement programs” like Social Security “have to be adjusted and fixed,” and that Republicans will introduce a plan to that effect next year. But this is a ploy, because while the cost of maintaining Social Security benefits at their promised level isn’t trivial, it is in fact affordable. According to the Trustees’ report, the actuarial balance of OASDI up through 2050 — the amount of additional funds it would need to keep paying full benefits for the next 25 years — is 1.06 percent of GDP. To put that number in perspective, the Trump administration proposes increasing military spending next year by $420 billion, equivalent to about 1.4 percent of GDP – without any discussion of whether that’s affordable Yet how did we get to the point where Social Security will need to be topped up? The main answer is that we have an aging population, with a growing ratio of retirees collecting benefits to workers paying into the system: Trump’s anti-immigration policies are making this problem worse. According to the Trustees’ report, lower immigration will deepen Social Security’s financial hole because many immigrants are working-age adults who will pay into the system for decades before they collect benefits. In fact, this problem may be much bigger than the report acknowledges: The report’s baseline assumption is that we’ll have net immigration of almost 1.2 million people a year, and even the pessimistic case assumes 750,000 a year. Meanwhile actual net immigration has already been cut far below that — and may now be negative. Moreover, Social Security is being financially damaged by growing income inequality in America. Payroll taxes are levied only on wages up to $184,500, and they don’t touch capital income. With the distribution of income increasingly shifting from labor to capital, as well as becoming more unequal among wage-earners, revenue from the Social Security payroll tax has been falling as a share of national income. From 1990 to 2024, it fell from 5.02 percent of gross domestic income to 4.46 percent. Which brings me to the question that, these days, we ask about everything: How might Social Security be affected by the advent of AI? A short answer: If, as many of us fear, AI accelerates rising income inequality, it will further reduce the payroll tax receipts that currently pay for Social Security and further endanger its finances. On the other hand, if AI, as its advocates promise, leads to faster economic growth, it will increase the potential tax base that could and should be used to support Social Security and other social insurance programs. But to take advantage of that larger base, we’ll have to get serious about taxing wealth and capital income. Is Social Security in trouble? Yes, but only because of the way its financing is currently structured — a structure that no longer works well because our society and economy have become so unequal. Moreover, Trump’s immigration policies are further endangering its already deteriorating financial condition. So don’t believe Republicans’ gaslighting that it will be necessary to cut Social Security benefits. All that is necessary to preserve Social Security is political will to raise taxes on the wealthy and a sensible immigration policy. MUSICAL CODA Actually 67 under current law.
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