SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " span " 1,361 found 🔀 AI-powered Shuffle
ACC’s Span Elite Acquires Arctic Harvest Deliveries
The founder of Alaska Harvest Deliveries got a new job helping entrepreneurs, so she sold the business to Alaska Commercial Company.
Virginia Climbs to No. 3 in CNBC's 2026 Top States for Business — Here's What Moved the Needle
Gov. Spanberger credits strategic investments and affordability gains, while a methodology change rewarding infrastructure does some of the heavy lifting.
Virginia climbs to third spot in CNBC ‘Top States for Business’ rankings
Gov. Spanberger touts legislative agenda and workforce development measures, along with years-long infrastructure projects as contributing factors.
There's now one factor that decides more of your lifespan than anything else, scientists say
What do your genes have to do with your lifespan?
OUTDOOR ACCESS FOR DISABLED IN VERMONT
Mountain bike enthusiasts have been working for years on an ambitious 485-mile, multi-use trail called The Velomont that will span the length of the state. They're making sure it's friendly for people people with disabilities, particularly cyclists.
Fort Bend County Fair Announces 2026 Entertainment Lineup Featuring Sawyer Brown, Pat Green
ROSENBERG, Texas (Covering Katy News) — The Fort Bend County Fair has announced its entertainment lineup for its 90th annual celebration, featuring a mix of Texas country stars, Tejano favorites and nationally recognized performers during Championship BBQ Weekend and the fair's 10-day run. The 2026 Fort Bend County Fair begins with Championship BBQ Weekend on Sept. 18-19, followed by the fair Sept. 25 through Oct. 4. The entertainment schedule opens Friday, Sept. 18, with Tejano group Los Morales, followed by Texas country artist Cole Phillips on Saturday, Sept. 19. Phillips has gained attention for his traditional country sound influenced by classic honky-tonk music. The fair officially opens Friday, Sept. 25, with Tyce Delk, a New Mexico native whose touring schedule has expanded across the country. Country music veterans Sawyer Brown will headline Saturday, Sept. 26. The band, whose career spans more than four decades, remains known for hits including "Some Girls Do," "The Race Is On" and "Thank God for You." Go Tejano Day on Sunday, Sept. 27, will feature Prófugos de Nuevo León, along with performances by Los Rinches and Grupo Zenio. The second week of the fair begins Wednesday, Sept. 30, with Bellville singer-songwriter David Lewis, a recent Texas Country Music Association Male Artist of the Year nominee. Oklahoma Red Dirt artist Josh Meloy will perform Thursday, Oct. 1. Texas country star Pat Green returns to the Fort Bend County Fair stage Friday, Oct. 2. Green, whose career includes three Grammy Award nominations, has sold more than 2 million albums and amassed more than 200 million career streams. He is best known for songs including "Wave on Wave" and "Carry On." Country newcomer Vincent Mason will perform Saturday, Oct. 3. Mason has accumulated more than 500 million career streams and was recently nominated for Academy of Country Music New Male Artist of the Year. The fair concludes Sunday, Oct. 4, with Texas music legend Gary P. Nunn, whose "London Homesick Blues" remains one of the state's most recognizable songs. Weekend visitors also can enjoy performances on Music Row by J Paul Jr. & the Zydeco Nubreeds, Southern County Line, Los Rangerz and Horizon. The Fort Bend County Fair Association, a nonprofit organization, supports youth, agriculture and education. According to the association, it has awarded more than $2 million in scholarships during the past decade and generated $1.4 million through its 2025 youth auctions. Tickets go on sale at 10 a.m. Friday, July 10. Guests are encouraged to purchase tickets in advance and select the specific day they plan to attend, as tickets are valid only for the date purchased. Admission includes entry to the fairgrounds, access to the carnival, shopping, exhibits, food vendors and, when scheduled, admission to the rodeo and that day's concert. Season passes and single-day tickets will be available. For tickets and additional information, visit fortbendcountyfair.com or call the Fair Office at 281-342-6171. The address of the Fairgrounds is 4310 Texas 36 S in Rosenberg. 2026 Fort Bend County Fair Entertainment Schedule Championship BBQ Weekend Friday, Sept. 18: Los Morales Saturday, Sept. 19: Cole Phillips Fair Entertainment Friday, Sept. 25: Tyce Delk Saturday, Sept. 26: Sawyer Brown Sunday, Sept. 27 (Go Tejano Day): Prófugos de Nuevo León, Los Rinches and Grupo Zenio Wednesday, Sept. 30: David Lewis Thursday, Oct. 1: Josh Meloy Friday, Oct. 2: Pat Green Saturday, Oct. 3: Vincent Mason Sunday, Oct. 4: Gary P. Nunn × Expand FBCF Fort Bend County Fair 2026 Artist Lineup
World’s largest paper airplane has a 65-foot wingspan
The new Guinness World Record holder flew nearly 200 feet on a single glide.
M+C Saatchi North America Launches Entertainment Marketing Practice
Little Black Book, Former WME executive Jen Bacchus joins to build the agency’s new North American capability spanning talent strategy, entertainment partnerships, brand integrations and branded content
Biological aging clocks in health and disease
Nature Medicine - This review outlines the state of the art of biological clocks and how they could help understand pathobiology, reduce the burden of disease and extend healthspan.
Northern Virginia business optimism rebounds in Q2 as layoff fears hit lowest point in survey's history
18% of respondents are based in Alexandria; tax reduction and right-to-work top policy priorities for Spanberger and General Assembly
VNA Health Group Announces Planned Retirement of Chief Operating Officer and Chief Financial Officer Kevin Rogers, CPA
NEPTUNE, NJ (July 8, 2026) – After more than two decades of service across two tenures with VNA Health Group and a distinguished career spanning more than 35 years in home-based healthcare, Chief Operating Officer and Chief Financial Officer Kevin Rogers, CPA, has announced his plans to retire from his full-time leadership role at the[...]
Edie Stewart new CEO at Forward Arkansas
Forward Arkansas announced Tuesday (July 9) Edie Stewart as its new CEO, effective August 3. Stewart brings more than three decades of experience spanning education, workforce development and the nonprofit...
Gov. Abigail Spanberger signs Virginia budget into law
Spanberger signed a budget on June 29 that includes provisions on funding education, housing, and healthcare.
Meet Naomi Osaka’s Business Partners Behind Her Wimbledon Comeback
Naomi Osaka has returned to IMG while continuing to build Hana Kuma, KINLÒ and an investment portfolio spanning sports and startups.
watchOS 27 adds three new Health upgrades for Apple Watch
watchOS 27 packs a variety of Health-related improvements for Apple Watch users that span three main areas, here’s what’s new.
MannyPay Global Launches U.S. Merchant Processing Division to Help Small Businesses Lower Payment Costs and Accelerate Growth
Backed by global icon Manny Pacquiao, the company introduces a merchant-first payments platform — spanning card processing, integrated commerce te...
This rural Colorado hospital is using AI to go after health insurers that ghosted payments. Here’s how.
The promise of modern AI to help Spanish Peaks Regional Health Center recover lost revenues is built on a system that keeps medical data private.
CBS Sports Names Alabama the Greatest College Football Program of Three Different Decades, and It's Hard to Argue
Spanning the 1930s to the 2010s, the Crimson Tide outpaced every other powerhouse to claim historic dominance across three distinct eras of gridiron excellence and consistency.
Overnight News Digest: Star Spangled Science Saturday, 7/4/26
Welcome to the Overnight News Digest with a crew consisting of founder Magnifico, regular editors side pocket, maggiejean, Chitown Kev, eeff, Magnifico, annetteboardman, Besame, jck, JeremyBloom…
Referee appointment for Spain vs Portugal confirmed
The referee chosen to take charge of the upcoming showdown between Spain and Portugal has on Saturday evening been confirmed.The official primed to oversee proceedings at Dallas Stadium? Anthony Taylo...
NASA's Hubble captures a star-spangled sea of 500,000 stars
Celebrating the United States' 250th anniversary, NASA released a stunning Hubble portrait of Messier 3, an ancient globular cluster with more than 500,000 stars. The remarkable cluster is helping scientists unravel the Milky Way's past thanks to its rare stars and possible origins in a long ago cosmic merger.
Freedom 250 Independence Day Entertainment
Freedom 250 presents events from the National Mall prior to the evening "Salute to America" program.
Dorney Park extends Star-Spangled Nights to three-day celebration with fireworks and entertainment
ALLENTOWN, Pa. -- For the first time, Dorney Park has expanded its annual Star-Spangled Nights celebration into a three-day event, giving guests more opportunities to celebrate the Fourth of July
All 15 MLB broadcasts on July 5 to be televised on NBC's Peacock for 'Star-Spangled Sunday'
Why Brevyn Spann-Ford could have a breakout year
Brevyn Spann-Ford is a name to watch this season.
Trinity Health System School of Medical Laboratory Science celebrates 2026 graduates
STEUBENVILLE — The Trinity Health System School of Medical Laboratory Science graduated its seventh class, comprised of Aliyah Pattie and Audrey Poole. The graduation ceremony was held in the chapel at Trinity Medical Center West, followed by a reception in the Sullivan Room. Trinity’s Medical Laboratory Science program spans 11 months and is designed for […]
‘Education, entertainment and celebration’: American Village hosting 2-day event for Fourth of July, America’s 250th
The two day festival spans from July 3 to July 4, bringing together music, history, food, art and family-friendly experiences in a “dynamic and patriotic setting.”
The Earth Will Not Be Consumed When The Sun Becomes A Red Giant, But Life Will Die Out By 1.8 Billion Years Anyway
Researchers revisited both the Sun's eventual death and the lifespan of Earth's biosphere, and neither result was quite what they were expecting.
Too Big? Jones Explains Poatan’s ‘Perfect Storm’
Jon Jones has a bit of experience with moving up to Heavyweight. “Bones” ruled the 205-pound roost for many, many years before finally making the leap in 2023. He teased a Heavyweight jump for much of that span, but Jones has always been a careful decision-maker in regards to his MMA career and (nearly) undefeated […]
US cooking oil market shrinking due to Ice pressures on Latino households, Mazola owner says
Economic squeeze and anti-immigration raids have hit Hispanic communities, prompting people to shop online and reuse oil
Confirmed: Real Madrid’s fixture list for 2026/27 season announced
The Jose Mourinho era is set to begin once again at the Santiago Bernabéu after La Liga officially unveiled the Real Madrid 2026/27 La Liga fixtures.The Spanish giants will launch their domestic camp...
Microsoft set to cut thousands of jobs next week, spanning Xbox, sales and consulting
Microsoft is preparing another round of layoffs, spanning Xbox, sales and consulting, as it holds down operating costs while pouring more than $100 billion into AI infrastructure.
The Science of NAD+: Why We Must Shift from Lifespan to Healthspan
Discover the science of NAD+ and how it impacts your healthspan. Watch Mona Rosene explain cellular repair and how to fight aging from within.
Green intends to veto just four bills
The measures span issues in education, housing, school facilities and the rainy day fund
The Busy Bar Is a Gadget to Get People to Leave You Alone
Flipper Devices, a company that built a banned hacking device, now wants to hack your attention span.
Kakao Entertainment Announces Genre-Spanning Lineup
Kakao Entertainment enjoyed a highly successful first half of the year, with its Netflix series “The WONDERfools” and “Boyfriend on Demand” hitting global home runs with their distinctive narratives. Also building on the recently released suspense drama “Notes from the Last Row,” Kakao Entertainment’s genre-spanning 2026 slate features the upcoming action-comedy “A Bona Fide Killer” and the thriller “Mousetrap,” cementing - Read our full Pop Culture on The Outerhaven .
How one expert hopes to expand the health span of Southwest Floridians
On “The Florida Roundup,” Shawn Felton talked about his efforts to expand health span among Southwest Florida residents.
America's lifespan has doubled since 1776
U.S. life expectancy has doubled since 1776 thanks to vaccines, antibiotics, sanitation and clean water that reduced infectious disease deaths.
After budget impasse, business as usual for Virginia Democrats, analysts say
This has been a budget battle like none other, with big personalities, personal attacks and what looked like a high-stakes game of chicken with days to go before the Virginia state government couldn’t pay its bills.
NBC Announces Plans For Special 'Star-Spangled Sunday'
NBC is having a special "Star-Spangled Sunday" broadcast next weekend. Next Sunday is July 5, 2026. It's a very special Fourth of July weekend this year. It's America's 250th birthday. NBC and Peacock will be airing all 15 MLB games on Sunday, July 5. Two games - Mets-Braves and Padres-Dodgers - ...
Efzimfotase alfa demonstrated improvements in bone health in treatment-naïve pediatric patients with hypophosphatasia achieving median difference of 1.67 vs placebo in RGI-C Score at week 25 in MULBERRY Phase III trial
Positive results from the MULBERRY Phase III trial showed that efzimfotase alfa (ALXN1850), an investigational enzyme replacement therapy, demonstrated a statistically significant and clinically meaningful improvement in bone health in children (2 to
Pennsylvania measles outbreak tops 70 cases as health leaders pledge to get spread ‘under control’
The most recent measles outbreak started in the area of Lebanon and Lancaster counties in late April. Cases now span six counties.
Cowboys 2026 roster rundown: TE Brevyn Spann-Ford
Cowboys tight end will make his push for more playing time
Yan Diomande chooses PSG as next destination if he leaves RB Leipzig
Diomande registered 12 goals and nine assists for Leipzig, who he only joined last summer from Spanish side Leganes.
MacBook Retail Sales Challenged By Apple Silicon Legacy
The extended lifespan of first-generation M1 MacBooks is impacting retail sales of the newer AI-focused MacBook Air and MacBook Pro laptops.
New York Knicks Champion Mitchell Robinson Makes Heartfelt Post
Mitchell Robinson is coming off his eighth season in the NBA.The 28-year-old has become an extremely valuable player for the New York Knicks in that span.He is coming off a season where he averaged 5.7 points, 8.8 rebounds and 1.2 blocks per contest while shooting 72.3% from the field in 60 games.Knicks Champion Robinson Makes […] The post New York Knicks Champion Mitchell Robinson Makes Heartfelt Post appeared first on HEAVY.
An au pair made my family obsessed with Argentina's World Cup run
What started as childcare turned into a friendship, a World Cup obsession, and a connection that spans two continents.
10 Game-Changing Entertainment Venues Designed by Populous
A look at 10 entertainment venues by Populous, spanning esports, concerts, and more, that are redefining audience experiences worldwide.
Nebraska Hispanic Chamber of Commerce holds networking event for Omaha businesses
Watch: Omaha business leaders met at Mexico's consulate to network with the Nebraska Hispanic Chamber of Commerce
How Outward Intelligence founders bootstrapped to seven-figure revenue
Three friends with résumés spanning Google, Palantir, and Harris Poll skipped venture capital and bootstrapped their startup instead.
TravelTech Show, Business Travel Show Europe name 2026 innovation award winners
Arcube, ImpersonAlly, Acai and Nowadays were recognized in separate competitions for travel technology innovations spanning airline retailing, brand protection, contact center automation and meetings management.
CRAWFORD | Kenny Klein, beloved longtime Louisville sports information director, dies at 66
Klein's career spanned nearly four decades and helped shape the public face of Cardinals athletics through some of its greatest triumphs and most difficult crises.
Behavioral Healthcare Close to Home: SRMC Services Available in Sandoval County
Sandoval County spans more than 3,000 square miles with a population of 160,000 residents. As one of New Mexico’s fastest growing counties, it’s crucial the people who live there have access to high quality healthcare, including behavioral health...
Discovery Education Earns Five 2026 CODiE Award Nominations Spanning Math, Science, Digital Citizenship, and Immersive Learning
Discovery Education Earns Five 2026 CODiE Award Nominations Spanning Math, Science, Digital Citizenship, and Immersive Learning
UT Health San Antonio researcher receives $400,000 Komen grant to study therapeutic yoga for breast cancer survivors
Amelie G. Ramirez, DrPH, MPH, to work with Hispanics in South Texas Contact: Steven Lee, (210) 450-3823, lees22@uthscsa.edu Content provided by Cliff Despres SAN ANTONIO, June 25, 2026 – Amelie G. Ramirez, DrPH, MPH, a cancer researcher at UT Health San Antonio, the academic health center of The University of Texas at San Antonio, is […]
Top Weekly Entertainment Picks
With America’s 250th Anniversary approaching, there are many star-spangled activities taking place in South Jersey, including a fireworks spectacular in
Suspect in $5,000 Academy Sports theft arrested
MEMPHIS, Tenn. — A man accused of stealing over $5000 worth of merchandise from Academy Sports and Outdoor over a span of two days earlier this month is now in jail. Carltrell Taylor, 39, is …
Living with a cat: the mental health impact scientists are only now discovering - Futura-Sciences
A Surprising Connection Between Cats and Schizophrenia? An Australian study has revealed an unexpected link between cat ownership and the risk of developing schizophrenia. Researchers analyzed 17 studies conducted over 44 years, spanning 11 different countries. Their conclusion? Living with a cat could actually double your risk of developing schizophrenia-related...
Politics in the Park: GOP gubernatorial candidates share visions for Wyoming governor
CASPER, Wyo. — Three Republican gubernatorial candidates shared their views on a myriad of topics spanning taxation, energy production, resource rights
Politics in the Park: GOP gubernatorial candidates share visions for Wyoming governor
CASPER, Wyo. — Three Republican gubernatorial candidates shared their views on a myriad of topics spanning taxation, energy production, resource rights
Political earthquake strikes House Democrats and Hispanic caucus with Espaillat's loss
Online violence against women in politics: what shapes political party responses to technology-facilitated gender-based violence?
Political parties have a primary role to play in tackling online violence against women and gender diverse politicians. While the prevalence and impact of TFGBV, such as coordinated disinformation campaigns, deepfake image-based sexual abuse or trolling are well documented, many parties are still building their knowledge on how to respond effectively and have not put in place internal practices and policies that respond to the rapidly evolving, poorly regulated digital ecosystem. About the ReportIn order to promote and protect fair and democratic participation in politics, this ALIGN Report explores what political parties are doing in response to TFGBV and what factors shape their action. The findings, based on existing literature and interviews with gender and politics professionals, indicate there are three sets of factors which donors, civil society and practitioners should consider when designing action to support political parties to respond to TFGBV internally. These are: (1) gender norms; (2) socio-political environment; and (3) internal party factors.Key messagesUnequal gender norms are ubiquitous across politics, shaping expectations of leaders to be strong and assertive, and practices of political parties to uphold masculinist values and sustain cultures of silence. These often lead to weak response to TFGBV against women politicians.The socio-political context can incentivise or disincentivise action, depending on the salience of gender issues, which are increasingly weaponised. Electoral competitiveness, domestic laws (i.e. quota requirements), and even the political system or global normative frameworks influence political will to act.Internal party factors that shape responses will vary across countries and contexts, but include: structures to enforce codes of conduct, policies and reporting mechanisms on (TF)GBV, political ideology, extent of centralisation of leadership, and crucially the meaningful participation of women in decision-making positions, not least through internal women’s wings.Party responses can be seen as a spectrum, with actions falling between active discouragement to address TFGBV to commitment to transform unequal norms and practices within the party.About the ToolkitTogether with the report, this ALIGN toolkit offers gender professionals and others working on democratic strengthening a set of guiding questions and reflection prompts to identify which responses could be most effective and suitable in different contexts. These actions can complement other solutions to TFGBV, such as regulations promoting safety by design. The assessment spans a broad range of factors including: (1) different manifestations of gender norms, (2) the socio-political environment and (3) internal party structures.Key messagesPolitical parties are duty-bound to take action internally to respond to the significant threats posed to women members and candidates, including from their own party colleagues, affiliates and political peers.Existing party approaches to TFGBV can be assessed along a spectrum which ranges from active discouragement and passive acceptance to minimal response and transformative change.To generate effective and context-appropriate solutions to TFGBV, it is important to consider how gender norms shape leadership expectations and internal party practices, while also analysing the impact of the socio-political environment. While actions to support women to stay safe online are very common, codes of conduct and measures to strengthen women’s voice and power in the parties are proposed as most transformative solutions.
Mediterranean-inspired diet with added methionine extends healthy lifespan in mice
A plant- and fish-based, low-protein diet paired with small amounts of an amino acid commonly found in eggs, meat and dairy increased healthy lifespan and decreased frailty and fat mass in mice, according ...
Hodder Tugboat acquires Seaspan's towing business
Hodder Tugboat Co. Ltd., Richmond, British Columbia, has finalized its purchase of the legacy chip and hog fuel barge division of Seaspan Marine, North Vancouver, British Columbia, the companies annou
Amino acid-supplemented ‘longevity diet’ linked to longer healthy lifespan
USC study finds low-protein diet paired with small amounts of amino acid methionine increased healthy lifespan, decreased frailty in mice.
Exclusive | Justice Department Unveils $6.5 Billion Healthcare Fraud Crackdown
Prosecutors are expected to charge around 450 defendants in alleged fraud spanning Medicaid and hospice care.
Accounts in Transit: M+C Saatchi Sport & Entertainment Lands HUGO BOSS
M+C Saatchi Sport & Entertainment is named global PR agency of record for HUGO BOSS’s brands BOSS and HUGO.... Zapwater Communications expands its relationship with Banyan Group, strengthening its role as the brand’s agency of record in North America while adding PR representation for overseas....Diffusion comes on board as PR agency of record for Pehr, a baby and kid brand spanning apparel, nursery and gear.
Indonesian Academy of Sciences launches journal with Taylor & Francis
Publication will be "source of original research spanning science, technology, mathematics and the social sciences"
How Alan Greenspan's "irrational exuberance" underlies today's politics
Can America’s data center backlash stay bipartisan?
Opposition spans party lines as communities resist AI infrastructure's impact on energy costs and resources.
NAIRR Science Program Reshapes Scientific Research, Powered by NVIDIA AI Infrastructure
The U.S. National Science Foundation’s NAIRR pilot program has driven innovative research across the U.S. for over 700 projects — spanning protein prediction and infectious disease outbreak management.
Scientists say most people need more protein than current guidelines suggest
A new review suggests that doing more exercise and eating more protein than current minimum recommendations may help people stay stronger, sharper, and more independent as they age. The goal isn't building a beach body—it's extending healthspan and maintaining the ability to fully enjoy life for decades longer.
ISTA’s Class of 2026: Celebrating 52 Graduates
The Institute of Science and Technology Austria (ISTA) celebrated impressive achievements at this year’s graduation ceremony, with 48 new PhDs and four MSc graduates receiving their degrees. Hailing from 25 countries, the graduates completed their studies in 38 different ISTA research groups spannin
Butterfly that barely ages could help unlock longevity secrets
Scientists discovered that Heliconius butterflies have evolved an extraordinary lifespan, living several times longer than closely related species. Even more surprising, some show little sign of physical decline as they age. Their unusual pollen-feeding lifestyle may play a role, but the research suggests deeper evolutionary changes are also helping them stay healthy for longer.
The Pulse: Women's Health is Having a Reckoning - The Longevity Gap is Where it Starts
Welcome to our new series The Pulse, covering everything you need to know about the age of intelligent health.From ovarian aging and maternal health to cardiovascular and dementia risk, HLTH USA 2026 is programming the women’s health conversations medicine has been too slow to have.While women live longer than men, they spend 25% longer in poor health. The healthspan gap, between how long women live and how long they live in good health, is the defining focus of the next frontier in women’s health. “Diminished healthspan ...
Nearly All EAE Business School Grads Found Jobs In 2025, With Salaries Growing 70%
Spanish school's employment report tracks grads across master's & MBA programs, finding a pronounced tendency to ‘triple jump’.
Beyond the World Cup... 5️⃣ stories shaping Sunday
Spanish football is experiencing a day of high emotion, with the offices and the pitch sharing the spotlight.While the Costa del Sol celebrates a historic return to the top flight after an agonizing j...
Arrakihs, a Spanish mission to illuminate the mystery of dark matter: ‘We have broken molds’
Four-telescope astronomical observatory is at the heart of the first space exploration to be led by the country
From $500 to $1tn: How Elon Musk built his fortune
From a video game sold for $500 (€430) as a teenager to a business empire spanning rockets, electric vehicles, AI and brain implants, Elon Musk has spent decades building companies that have reshaped multiple industries. Here's a look at the businesses behind the world's richest man.
Historical cricket club celebrates bicentenary
The club is the oldest in its county and has a history spanning 200 years.
Unusual creatures are more appealing: What guppies teach us about evolution
Spanish biologist Ignacio Paulin became fascinated by the behavior of these fish, in a project that could now disappear due to budget cuts by the Trump administration
Astros vs Guardians Game Discussion: 6/19/2026
Game Info Game Date/Time: Friday, June 19, 7:10 p.m. CT Location: Daikin Park, Houston, TX TV: Space City Home Network Radio: KBME 790 AM & 94.5 FM HD2; TUDN 102.9 FM HD2 (Spanish)
Some butterflies live 25 times longer than their relatives. Scientists are unlocking their secrets
A tropical butterfly from the Heliconius tribe has evolved to live a maximum lifespan of 348 days, nearly 25 times longer than its relatives.
Asus releases new gaming laptop globally with 1,600 nit Mini LED display and 175 W GPU
Asus has finally released an ultra-premium gaming laptop globally. With up to 320 W of power under full load, the ROG Strix Scar 18 2026 also contains a 4K and 240 Hz Mini LED display that spans 18-inches with 1,600 nits peak brightness at its disposal.
Rays' Drew Rasmussen Accomplishes Impressive Feat Over Three-Game Span
What was Tampa Bay Rays' pitcher Drew Rasmussen able to accomplish of late?
Regulatory investigations reveal systemic failures among Commercial California Health Plans in delivering timely behavioral health care
Commercial California health plans are failing enrollees who need access to behavioral health services for mental health and substance use disorder care, recent investigations have shown. Across three rounds of investigations, the California Department of Managed Health Care found 70 Knox-Keene Act violations and 35 barriers to care across 14 health plans, spanning national, regional, and county-based plans.
Mount Sinai to Lead Aspen Discussions on Youth Mental Health, and Healthspan Science and Practice
Will explore innovative approaches to mental health and new frontiers in healthspan, longevity science, and personalized care during Aspen Ideas: Health and the Aspen Ideas Festival.New York, NY and Aspen, CO, June 18, 2026 (GLOBE NEWSWIRE) -- Mount Sinai Health System experts will lead discussions on innovative community-based approaches to youth mental health and emerging scientific advances that are transforming how we understand healthy aging and healthspan at the 2026 Aspen Ideas: Health an
Gabe Newell, founder of Bellevue’s Valve, buys $70.8M Florida mansion
The 20,000-square-foot house spans from the ocean to the Intracoastal Waterway, with a private dock and a tunnel leading directly from the house to the ocean shore.
Protesting a luxury resort in Albania
Why Albanians are demonstrating against a Trump-family business project. Also: Can a dying Spanish village still be saved?
REV Ocean Launches Maiden Science Voyage to Support Marine Protection, Policy
REV Ocean has set out the details of its Maiden Voyage Science Program: ten partner-led missions spanning the South Atlantic, the…
Six Named to CSC Academic All-District Women's At-Large Teams
SCHENECTADY, N.Y. – Six Union College student-athletes spanning three sports were recognized for their work in competition and in the classroom with spots on the 2026 CSC Academic All-District Women's At-Large Team, selected by College Sports Communicators and announced on Tuesday.
Metro Atlanta Chamber host Spanish officials for international business summit
While Spain’s national team finished with a zero-to-zero draw in its first match of the World Cup, economic leaders are looking to score off the pitch.
How stigma shapes men's mental health
Opening up about mental health isn’t always easy. Learn how stigma affects men and when everyday struggles may be a sign to seek help.
Requiem Creative Wins Multiple Golden Trailer Awards, Earns Clio Entertainment Honors, and Emerges as One of Entertainment Marketing’s Fastest-Rising Agencies
Rapidly growing entertainment marketing agency recognized across theatrical, streaming, television, gaming, music, and digital campaigns less than two years after launchLOS ANGELES, June 15, 2026 (GLOBE NEWSWIRE) -- Requiem Creative, the Los Angeles-based entertainment marketing agency operating within the Ramsey Theory Group portfolio, today announced a series of major industry accolades, including Golden Trailer Awards wins, Clio Entertainment finalist honors, and numerous nominations spanning
This popular brain supplement was linked to shorter lifespans in men
A large-scale study suggests that men with higher levels of the amino acid tyrosine may have shorter lifespans, potentially losing close to a year of life expectancy. The finding is especially intriguing because tyrosine is commonly associated with brain health and is often used in supplements aimed at boosting focus and performance.
👀 Spain wait on Lamine, can he play this afternoon?
The Spanish national team begins its World Cup campaign this afternoon (18:00 CET) against Cape Verde. The big question surrounding the starting eleven is the physical condition of La Roja’s young s...
Aspirus Health Welcomes Jennifer Loesch, North Division Chief Nursing Officer
RHINELANDER, Wis. – Aspirus Health is pleased to announce the appointment of Jennifer Loesch, DNP, MBA, BSN, NE-BC, as Chief Nursing Officer (CNO) for the North Division. In this role, Loesch will oversee nursing strategy and operations across Aspirus Eagle River Hospital, Aspirus Rhinelander Hospital, Aspirus Tomahawk Hospital, and Howard Young Medical Center in Woodruff, promoting excellence in patient care, safety, and nursing leadership. Loesch brings more than 25 years of healthcare experience span...
Americans are living longer, increasing the need of geriatricians. Does Louisiana have enough?
As the baby boomer generation reaches older adulthood and average lifespans continue to increase, the number of geriatricians needed to meet demand is also rising. Here's where the data currently stands in each state.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.