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Misery Index: Lincoln Riley, USC come up short yet again — and it's fair to ask how much more Trojans fans can bear

Sep 27 • 1:30 AM EDT • Sports • sports.yahoo.com

How Steph Curry gave Warriors edge without any contract drama

If you know Steph Curry, you know his priority is finding joy. He doesn’t like drama. He’s not interested in distractions. He’s single-mindedly focused on feeling the thrill of his...

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Wood County Health Department to offer vaccine clinics

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Sep 26 • 2:00 PM EDT • Health • bgindependentmedia.org

Just 4 Minutes a Day: The Surprising Habit Transforming Health After 65 - Futura-Sciences

Why Short Workouts Might Be a Big Deal Starting long or intense workout regimens puts off a lot of people—no surprise there. Yet, muscle strength and balance are crucial for maintaining independence as we age, and unfortunately, these abilities decline faster after age 65. With this in mind, researchers at...

Sep 26 • 1:00 PM EDT • Health • futura-sciences.com

Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL

Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Sep 25 • 5:30 AM EDT • Entertainment • thederrick.com

New Haywood Mall mural aims to spark mental health conversations

A new mural outside of Haywood Mall honors the late son of Walt's Waltz founder Susan Crooks. It will serve as a reminder of hope for the community.

Sep 25 • 5:05 AM EDT • Health • greenvilleonline.com

AI Chatbots Are Quietly Spewing Partisan Talking Points

Partisan websites disguised as independent, local news outlets are infecting chatbots’ responses about key races.

Sep 25 • 4:59 AM EDT • Politics • politico.com

🚨 Europe’s four major leagues call for FIFA reform

Another blow to Gianni Infantino.A major statement was jointly released by Europe’s four biggest leagues this Friday morning!The Premier League, Serie A, La Liga and the Bundesliga have indeed taken...

Sep 25 • 4:45 AM EDT • Sports • sports.yahoo.com

American Idol confirms Lionel Richie’s return for season 25 amid health issues

Sep 25 • 4:26 AM EDT • Health • yahoo.com

AMA grant boosts patient-driven approach to cervical cancer screening

One of the AMA Community Health Impact Lab micro grants will back an innovative effort at Jefferson Health to boost screening.

Sep 25 • 3:00 AM EDT • Health • ama-assn.org

New Pokemon TCG Premium Binders to Release Featuring Numbered...

Starting October 16th, Japan's Pokemon Centers will release a collection of nine Pokemon TCG binders themed after each generation -- with numbered card

Sep 25 • 2:29 AM EDT • Technology • pokebeach.com

Norvell Blinded by QB Loyalty Ahead of Central Arkansas Game

Florida State coach continues to praise his starting quarterback, Ashton Daniels, even after throwing three interceptions in a 50-36 loss to Alabama last Saturday. Norvell praises his confidence and decision-making skills. Daniels has thrown three touchdown passes against ranked teams this season.

Sep 24 • 10:30 PM EDT • Sports • sports.yahoo.com

Hannah Einbinder, Susan Sarandon arrested in protest against Netanyahu

Hannah Einbinder and Susan Sarandon were arrested after protesting the arrival of Israeli Prime Minister Benjamin Netanyahu at the United Nations in New York City. Cynthia Nixon, Elliot Page, Indya Moore, Mary Beth Barone, Caleb Hearon and Sarah Sherman were also at the demonstration.

Sep 24 • 8:38 PM EDT • Entertainment • latimes.com

‘Drop out or DIE’ | TN gubernatorial candidate Hatley’s business vandalized

JOHNSON CITY, Tenn. (WJHL) — Johnson City police are investigating after an alleged vandalism at a business owned by Tennessee independent gubernatorial candidate David Hatley. According to the Joh…

Sep 24 • 5:33 PM EDT • Business • wreg.com

Keweenaw Health Foundation awards $25K to CLK Early Childhood Center

The center offers day care services, coaching and education for children ranging from six weeks to five years old, preparing them for kindergarten.

Sep 24 • 5:12 PM EDT • Health • uppermichiganssource.com

Harvest Festival returns to Littleton Museum

As trees begin to shed their leaves and fall sets in, many are searching for autumnal festivities to celebrate the season. Luckily, Littletonians don’t need to search far from home,

Sep 24 • 4:31 PM EDT • Entertainment • littletonindependent.net

Michigan health officials criticize Trump order pushing changes to childhood vaccines

Trump's executive order calling for a reduction in recommended childhood vaccines came just as students were preparing to return to school.

Sep 24 • 4:21 PM EDT • Health • michiganindependent.com

Stephen A. Smith Says SiriusXM Is Home for Political Independents

The satellite radio giant has channels for progressives and conservatives, even as it turns its POTUS channel into something that caters more to independent thinkers.

Sep 24 • 2:07 PM EDT • Politics • hollywoodreporter.com

Bills defensive lineman T.J. Sanders out indefinitely after having appendectomy

Brady didn’t provide a timetable for Sanders’ return in announcing the player had surgery a day earlier.

Sep 24 • 12:32 PM EDT • Sports • spectrumlocalnews.com

As pharmacies across Vermont close, North Star Health opens 3 new ones

SPRINGFIELD — In the era of independent pharmacy closures and ballooning drug costs, a new pharmacy that charges less for drugs seems counterintuitive, if not impossible. But that’s exactly what North Star Health, a Federally Qualified Health Center that operates medical clinics in Vermont and New Hampshire, did when it officially launched three new pharmacies […]

Sep 24 • 11:50 AM EDT • Health • vnews.com

Genesee Health Plan hosts healthcare tune-up event

Genesee Health Plan is hosting its annual healthcare tune-up event Thursday from 3 p.m. to 6 p.m. at its office on South Linden Road.

Sep 24 • 11:03 AM EDT • Health • wnem.com

Concrete captain recalls hummable `Sail with the Pilot’ commercial

Pilot Financial is celebrating its 25th anniversary as an independent company, with a staff of about 15 that provides back-office, compliance, sales and other support to 120 financial advisors nationwide. Six are based in Greensboro, the others elsewhere in the U.S.

Sep 24 • 10:42 AM EDT • Business • businessnc.com

Cyber Risks Rank as Top Business Concern in 2026 Travelers Risk Index - ProgramBusiness

Cyber risks rank as the No. 1 overall business concern in the 2026 Travelers Risk Index, with artificial intelligence introducing new risks alongside traditional cyber threats.

Sep 24 • 9:00 AM EDT • Business • programbusiness.com

"I assume someone is being greedy somewhere" - Tim Schafer discusses current game industry woes following Double Fine's split with Xbox

Tim Schafer speaks to the BBC about Double Fine going independent, Game Pass, and the games industry in general.

Sep 24 • 8:26 AM EDT • Technology • eurogamer.net

My friend grosses $300,000 a year with her pet-sitting business. She pays herself $50,000. Should I do the same?

“She currently has about 15 sitters, all independent contractors.”

Sep 24 • 8:15 AM EDT • Business • finance.yahoo.com

Things to do. Dwight Yoakam, Oktoberfest, Celtic Thunder, symphony

Autumn means fun things to do in the Canton area, including Oktoberfest downtown and in North Canton, as well as Dwight Yoakam at Palace Theatre.

Sep 24 • 5:58 AM EDT • Entertainment • indeonline.com

Democrats Show Strength in Michigan Senate Race but Trail in Maine, Polls Find

The party’s nominees lead in Michigan and New Hampshire but the Republican incumbent is ahead in Maine, according to New York Times/Siena polls of the three battlegrounds.

Sep 24 • 5:02 AM EDT • Politics • nytimes.com

Measles almost killed me. Now I’m a doctor — and I'm scared of what's happening

Jewel Mullen was in kindergarten in 1961 when she almost died from measles. Now a physician, measles’ return frightens her.

Sep 24 • 4:30 AM EDT • Health • statnews.com

OpenAI agent ‘hacked’ into Australian government health data, Albanese reveals

Sep 24 • 1:37 AM EDT • Health • yahoo.com

Nikon Made a $1,400 Full-Frame Camera for Gen Z and I Might Be Too Old for It

The Z5IIC targets screen-first creators by ditching the viewfinder, but taking this fun-sized full-frame camera into bright sunlight reveals the trade-off.

Sep 24 • 12:01 AM EDT • Technology • pcmag.com

Proprietor stitches together new business

Jake Beechler's leatherworking career started when the nylon sheath for his Leatherman tool wore out.

Sep 23 • 9:00 PM EDT • Business • ouraynews.com

Harry Kane announces he's "fairly close" to extending Bayern contract

Bayern Munich star Harry Kane is closing in on a contract extension that would keep him at the club beyond the summer of 2027.The 33-year-old told The Independent on Wednesday that talks over an exten...

Sep 23 • 3:10 PM EDT • Sports • sports.yahoo.com

Christian Eriksen has Wolfsburg contract terminated after second collapse

Eriksen collapsed during an international friendly while playing for Denmark three months ago

Sep 23 • 10:59 AM EDT • Sports • sports.yahoo.com

Exceptional Earnings and AI Immunity Fuel Hinge Health’s (HNGE) Performance

Osterweis Capital Management, an investment management firm, released its Q2 2026 investor update for its “Osterweis Opportunity Fund”. You can download a copy of the letter here. The fund returned 35.34% in the quarter, significantly outperforming the Russell 2000 Growth Index’s 25.71% gain. Robust corporate profits, AI investment, easing oil-shock concerns, strong labor markets, and […]

Sep 23 • 10:31 AM EDT • Health • finance.yahoo.com

The 2024 Seahawks did indeed have one specific Michigan influence

Sep 23 • 10:08 AM EDT • Sports • sports.yahoo.com

Aberdeen's attacking issues laid bare

The 48 chances created by Stephen Robinson's side is the lowest tally in the division - same for their 37 chances from open play - while they have the fewest shots on target (18) and second-fewest shots (70). It must be noted Aberdeen haven't had the kindest fixtures, with Robinson keen to point out they have faced five of last season's top-six teams in their opening seven games. Eight points have been accrued, leaving the Dons seventh in a congested table and just two points shy of fourth, so there's no reason for panic.

Sep 23 • 9:17 AM EDT • Sports • sports.yahoo.com

UFC champion Sean Strickland gives health update after surviving ATV crash with no helmet

Strickland said he was ‘in a real bad place’ after being involved in the accident

Sep 23 • 8:46 AM EDT • Health • sports.yahoo.com

Penguins’ lineup battle temperature check

A lot can change quickly for the picture of building the NHL roster. Take a look at the last 48 hours, where Blake Lizotte was announced as being out on a week-to-week basis, and Ben Kindel got injured during the preseason game with a day-to-day designation. Add in more injuries to Ville Koivunen and Justin […]

Sep 23 • 8:22 AM EDT • Sports • sports.yahoo.com

Syracuse Basketball Stars Sadiq White Jr. & Olivia Schmitt Join Apex Entertainment's NIL Family

New Men's Head Coach Gerry McNamara to Meet Orange Fans on October 15 at Apex Entertainment's Destiny USA LocationSYRACUSE, NY / ACCESS Newswire / September 23, 2026 / Apex Entertainment®, the …

Sep 23 • 8:02 AM EDT • Entertainment • yourvalley.net

Reform and the UAE – a threat to British politics

By Alex Carlen The United Arab Emirates likes to present itself as part of the solution to the climate crisis. The oil-rich Gulf state has committed to Net Zero by 2050, hosted COP 28, and even declared “championing climate action” as one of three strategic objectives for this week’s session of the United Nations General Assembly. But behind the scenes the UAE has quietly built one of its closest political relationships in Europe with the party most hostile to climate action in Britain: Nigel Farage’s Reform UK. There is no evidence that the UAE is funding Reform. But a new FairSquare report, Petro-populism: the UAE–Reform threat, published today, documents a growing political relationship that should concern anyone interested in the integrity of British democracy. Reform’s leaders have embraced the UAE’s political model and promoted positions that align closely with the Emirati government’s priorities, while the UAE has given Farage and his party unusually warm access and public backing. What is emerging is not simply a relationship between British politicians and a wealthy Gulf state, but a channel through which an authoritarian government can cultivate political influence here, and abroad. Democracy for Sale relies on its readers. If you already support us, thanks so much. If you don’t, sign up to support fearless independent investigative journalism. Subscribe Back in January, Nigel Farage appeared at a GB News event in Dubai. On the 50th floor of a tower overlooking the luxury resorts and upscale residences of Palm Jumeirah, the Reform leader declared: “I want Clacton to look like this.” At the event – which Farage never declared on his official register of interests – senior Emirati officials mixed with British expats. Farage was keen to flatter. “We recognise you are our friends”, he said, assuring them that “a Brexit London, a Reform London, will remember you.” Controversy surrounding Reform’s finances and its susceptibility to foreign influence have centred around high-profile donations from billionaire crypto donors, and the jailing of Nathan Gill, Reform’s former leader in Wales, for accepting bribes to give pro-Russia speeches. Far less attention has been paid to Reform’s blossoming new alliance with the UAE, an oil-rich authoritarian state with a track record of ruinous anti-democratic interventions. Farage wasn’t always so fond of the UAE. Back in 2023 he called it an “absolute monarchy with an abysmal human rights record.” Now Reform’s hierarchy calls the UAE home. Deputy leader Richard Tice splits his time between his constituency and Dubai and has called on the UK to learn from the UAE. The party’s treasurer Nick Candy runs a firm which has been in partnership with a UAE-state linked firm since 2024. Nadhim Zahawi sits on the board of an Abu Dhabi think tank alongside an array of the most senior UAE officials and is reportedly close to three brothers of the country’s despotic ruler Mohammed Bin Zayed. Reform’s leading lights have effusively praised the UAE’s governance model, defended it from criticism, and advanced its political agenda in the UK. GB News, whose two major shareholders – the Legatum Foundation and Paul Marshall – have strong links to the UAE, has been more than happy to broadcast UAE propaganda and was forced to pay damages in 2025 after airing a false claim about a UK charity by the UAE “disinfluencer” Amjad Taha. The UAE has responded in kind. When the UAE Minister for Foreign Affairs conducted an official visit to the UK in May, Farage was the only non-government figure granted an audience. UAE state media publicised the meeting, and said that they discussed “the strategic relations between the two countries and ways to enhance them in a manner that serves mutual interests.” For the UAE these ‘mutual interests’ largely concern its paranoia over political Islam, and in this regard the UAE-Reform alliance is part of a broad and troubling pattern. Following a crackdown on dissent at home in the aftermath of the Arab Spring, the UAE has offered material and political support to a range of violent and authoritarian actors willing to oppose the Muslim Brotherhood with no regard for the consequences. Its meddling in Egypt, Tunisia, Yemen, and most notably Sudan, have been devastating. The UAE’s strategy of seeking out partners on the political fringes who it believes will advance its interests is not unique to Britain – it extends beyond the Middle East to Europe and the US. In France, it has offered clandestine support to Marine Le Pen through secret meetings, as well allegedly funding trips to the region after which Le Pen returned with a renewed focus on the UAE’s perceived enemies – Qatar and the Muslim Brotherhood. Left-wing opposition leader Jean-Luc Mélenchon has accused the UAE of smearing him and of “encouraging discrimination, hatred or violence”. In the US, the UAE actively supported the rise of Donald Trump, establishing itself as a key ally during both his first and second terms. Around these relationships sits a wider ecosystem of figures willing to amplify UAE narratives, that even extends to Andrew Tate and Tommy Robinson. Subscribe In Britain, the UAE has used a combination of aggressive diplomacy and illicit, disruptive tactics to achieve its policy goal of eliminating any perceived threat from political Islam. In 2012, for instance, it threatened to block billion-pound arms deals with the UK and stop inward investment if David Cameron did not act against the Muslim Brotherhood and rein in the BBC’s coverage of the group – going so far as to suggest, with no supporting evidence, that the group had infiltrated the BBC. It has financed smear campaigns against a high-profile UK charity and funded a mercenary to secretly surveil, and possibly assassinate, a British national on British soil. In Reform UK, the UAE has finally found an ally willing to not only ban the Muslim Brotherhood, but to publicly vilify the group and repeat the UAE’s claims that dangerous Muslims are a fifth column in British society, a narrative that aligns with the Islamophobia and anti-immigration sentiments that underpin Reform’s populist politics. The Rycroft review into foreign interference concluded that “hostile states and non-state actors have a clear incentive to attempt to undermine UK democracy.” The UAE’s network and alliance with Reform must be understood within that framework. It is a powerful, disruptive and deeply authoritarian actor with the resources and networks to intervene in our politics, and a track-record of doing so in a multitude of other countries. The evidence of the threat the UAE poses is overwhelming. The question is whether parliamentarians are willing to call the UAE out and demand action using the tools that the government has to respond. Placing the UAE on the “Enhanced Tier” of the Foreign Registration scheme alongside Russia and Iran would send a powerful signal to the UAE that its meddling will no longer be tolerated, and would place Farage’s next trips to the UAE under the scrutiny they deserve. Alex Carlen is research and advocacy manager at London based human rights organisation FairSquare and author of its new report Petro-populism: the UAE–Reform threat. Subscribe

Sep 23 • 6:50 AM EDT • Politics • democracyforsale.substack.com

Donald Trump Wants a Vance-Rubio Ticket in 2028, Says Ari Emanuel

Emanuel also believes David Ellison’s doing right by an independent press.

Sep 23 • 3:47 AM EDT • Politics • hollywoodreporter.com

German business activity grows in September, PMI shows

By Maria Martinez BERLIN, Sept 23 (Reuters) - German business activity expanded solidly in September despite firms facing increased inflationary pressures, a preliminary business survey ​showed on Wednesday. The S&P Global Flash Composite ‌PMI Index fo...

Sep 23 • 3:36 AM EDT • Business • wtaq.com

National Grocers Association CEO warns America could be left with just 'five or six national chains'

The National Grocers Association warns America is facing an "inflection point" where independent grocers could vanish, leaving just five or six national chains.

Sep 23 • 2:48 AM EDT • Business • foxbusiness.com

When should fighters stop fighting?

IN DEPTH: As 49-year-old Yoel Romero prepares to go to war with Darren Till in a bare-knuckle bout, Will Castle delves into the dangers of fighting for too long and why combatants struggle to quit the sport

Sep 23 • 1:00 AM EDT • Sports • sports.yahoo.com

Coleman Health Services: Helping Ohioans thrive through whole-person care

For 48 years, Coleman Health Services has been helping Ohioans find hope, stability, and a path toward a healthier and more independent life. Founded in 1978 as a nonprofit community behavioral health organization in Portage County, Coleman has grown into a nationally recognized provider offering comprehensive behavioral health, residential, employment, crisis, and supportive services throughout […]

Sep 23 • 12:01 AM EDT • Health • signalohio.org

State of Decay Developer Undead Labs Confirms 'Significant' Layoffs Following Independence from Xbox

State of Decay 3 developer Undead Labs has confirmed that it has had to undergo "significant" layoffs following its independence from Xbox.

Sep 22 • 7:19 PM EDT • Technology • ign.com

How Index Switches Will Impact Tencent Music Stock Investors

Tencent Music Entertainment Group was removed from the FTSE All-World Index on its NYSE listing and added on its SEHK listing in September 2026, while fresh research updates highlighted mixed views on its core music operations and broader platform trajectory. The index switch concentrates liquidity closer to Tencent Music Entertainment Group’s onshore business footprint. This may sharpen investor focus on how its streaming, social entertainment, and offline initiatives line up with...

Sep 22 • 5:24 PM EDT • Entertainment • simplywall.st

Report: Kansas fails to meet housing, mental health needs of vulnerable children in foster care

An independent third-party organization offers the 2025 annual assessment of Kansas' foster care system in light of a court-ordered settlement of a lawsuit.

Sep 22 • 3:59 PM EDT • Health • kansasreflector.com

Rachel Zoe designs innovative Aflac jacket to promote cancer screenings

Leave it to Rachel Zoe to turn a cancer screening reminder into a fashion statement with luxe tech twists.

Sep 22 • 1:53 PM EDT • Entertainment • centraloregondaily.com

Real Salt Lake's Diego Luna out following knee surgery

By MLSsoccer staffReal Salt Lake midfielder Diego Luna is expected to miss the remainder of the 2026 MLS season after undergoing a successful meniscus repair in his knee last week, the club announced ...

Sep 22 • 1:37 PM EDT • Sports • sports.yahoo.com

Political Pulse: Samuel Hare Sr. runs as Independent in District 32 House race

Independent candidate Samuel Hare Sr. shares his vision for Rapid City's District 32, including a business plan for using his construction background to tackle housing and recidivism rates.

Sep 22 • 1:00 PM EDT • Politics • kotatv.com

Dearborn mall heads to auction with one bidder

Court documents say the mall’s value is “substantially less than the outstanding indebtedness owed."

Sep 22 • 12:46 PM EDT • Business • crainsdetroit.com

Hot Spring County Fair Reminder (September 2026)

Click here to view this image from malvern-online.com.

Sep 22 • 12:24 PM EDT • Entertainment • malvern-online.com

With "a dozen" music levels, Rayman Legends Retold doubles down on the best bit of the original game, and having played it I couldn't be happier

By adding in more music tracks to Rayman Legends Retold, Ubisoft proves the indefatigable spirit of the 2013 game is still alive.

Sep 22 • 12:00 PM EDT • Technology • eurogamer.net

Penguins Injury Updates on Kindel, Brazeau; Koivunen Hurt, Too

Pittsburgh Penguins center Ben Kindel did not return to the bench for the second period of the team’s first preseason […]

Sep 22 • 10:44 AM EDT • Sports • sports.yahoo.com

What CDC's new teen health survey shows, and what it skips

Teen suicide risk hit a 10-year low in 2025. Guns, sexual violence, and self-harm. Where are the 2025 data on transgender teens? Missing data changes public health policy. Teen suicide risk hit a 10-year low in 2025. CDC asked more than 10,000 high school students over 100 questions in spring 2025. Yesterday, it published a report covering a fraction of them. The report focsed on five areas: diet, physical activity, sleep, digital behaviors, and mental health, reflecting the priorities of the Make America Healthy Again movement. There was good news. Fewer teens seriously considered suicide in 2025 than in any survey year since 2015: 14%, down from 20% in 2023. Sadness fell. Underlying Conditions is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe Sports participation, which dipped to 49% in 2021, is back to its 2015 level of 58%. Daily PE fell from 27% to 20% in two years, while fewer students eat breakfast daily than a decade ago. Guns, sexual violence, and self-harm. The questionnaire is public, and it goes well beyond those five areas. Students answered questions about sexual violence, self-harm, and whether they got help when they felt sad or anxious. They said how quickly they could get a loaded gun. They reported whether food ran out at home and whether they felt close to people at school. There were questions about sexual identity, including whether they were transgender. The report did not publish any of the answers students gave to those questions. CDC posts the raw survey data online, so anyone can see what the report left out. The report doesn’t cover the health of sexual minority students. Among students who identified as gay, lesbian, bisexual, questioning, or another non-straight identity, persistent sadness fell from 66% to 57% between 2023 and 2025. Serious thoughts of suicide fell from 41% to 30%. Those drops were bigger than the ones among straight students, although the gap remains wide: 28% of straight students reported persistent sadness, about half the rate of LGBQ+ students. About 1 in 7 girls reported sexual violence in the past year. One in 6 students hurt themselves on purpose. Among students who needed help for sadness or anxiety, half rarely or never got it. And among students who had seriously considered suicide, 43% said they could get a loaded gun without an adult’s permission. One protective factor rose sharply. In 2023, 55% of students said they felt close to people at their school; in 2025, 63% did. CDC’s earlier research ties that kind of connection to better mental health. Where are the 2025 data on transgender teens? In 2023, CDC's national survey asked high school students, for the first time, whether they were transgender. Their answers are the only nationally representative data on transgender teens, and their mental health is by far the worst of any demographic. That year, 71% of transgender students reported persistent sadness, 54% seriously considered suicide, and 26% attempted it, compared with 38%, 18%, and 8% of cisgender students. But we don’t have 2025 data. The timing matters because students took the survey in spring 2025, as federal policy toward transgender youth shifted. On January 28th, an executive order directed agencies to end federal support for gender-affirming care for people under 19, and several hospitals paused that care within days. In February, the CDC said it would no longer process transgender identity data. Later in 2025, the Supreme Court upheld Tennessee’s ban on gender-affirming care for minors, and HHS ended the 988 Lifeline’s dedicated line for LGBTQ+ youth. Researchers disagree about how much state policy shapes trans teens’ mental health. A 2024 Trevor Project study estimated that anti-trans laws increased suicide attempts among trans and nonbinary youth. Critics dispute its methods and its estimates. The 2025 survey could have added national evidence to that fight. CDC collected the data but hasn’t publicly released it. Missing data changes public health policy. Surveillance works as a feedback loop. It can show officials whether their policies help or hurt. The CDC didn’t provide data on the students most exposed to transgender policy shifts. The report kept measures that frame health as personal choice, like fruit, breakfast, and sports. It left out measures that track policy, like gun access, mental healthcare, food at home, and school climate, all of which respond to what legislators and agencies decide. HHS did not respond to questions that I sent on September 21st.

Sep 22 • 10:31 AM EDT • Health • celinegounder.com

RSM US Middle Market Business Index Holds Near Recent Highs as Rising Profits and Business Investment Sustain Optimism

/PRNewswire/ -- The RSM US Middle Market Business Index (MMBI) remained near recent highs, registering at 111.8 for the third quarter, which is a statistically...

Sep 22 • 9:08 AM EDT • Business • prnewswire.com

Can AI Be Slowed Down? Stanford HAI Experts Weigh the Risks, Rules and Race Ahead

In a new series called 'Prompt Response,' Stanford’s Surya Ganguli, Diyi Yang and Rob Reich examined emergent agent behavior, recursive self-improvement, independent evaluation and whether a 'kill switch' can make advanced AI safer.

Sep 22 • 8:00 AM EDT • Science • hai.stanford.edu

Wall St futures pause after AI rally, focus on Mideast tensions

Wall Street's main indexes were steady on Tuesday, ​following strong AI-driven gains in the previous session, while investors awaited potential talks between the United ‌States and Iran that could end their six-month-old conflict.

Sep 22 • 6:19 AM EDT • Business • reuters.com

Springboks announce new captain as team to face Australia revealed

Andre Esterhuizen will lead the world champions in the clash in Perth

Sep 22 • 6:12 AM EDT • Sports • sports.yahoo.com

Premier League’s Most Successful Club Floundering Again

Manchester United are back here again. The Premier League’s most successful club are floundering, again.Sunday’s draw with winless Fulham compounded an alreadymiserable week for Michael Carrick. I...

Sep 22 • 5:10 AM EDT • Sports • sports.yahoo.com

Watch: Greg Ballard on why he's returning to politics and ditching the GOP

The former Republican Indianapolis mayor has been retired from politics for a decade. He's back as an independent for secretary of state, with a mission.

Sep 22 • 5:03 AM EDT • Politics • indystar.com

One of country music’s best bands loses beloved member indefinitely: ‘My heart is full’

He issued a statement through the band announcing that he was stepping away.

Sep 22 • 5:00 AM EDT • Entertainment • pennlive.com

Sunda Energy, Meridian Mining, Quantum Helium, Light Science Technologies, Foresight Solar, hVIVO

Sunda Energy PLC (AIM:SNDA, FRA:GHA0) has raised £5.25 million to fund completion of its New Zealand acquisition. It's also launching a retail offer for a further £525,000. Meridian Mining Plc (LSE:MNO, TSX:MNO, OTCQX:MRRDF) has delivered a net present value of $2.09 billion for its Cabaçal project in Brazil. The CEO says the economics could make it the next major near-term gold-copper mine. Quantum Helium Ltd (AIM:QHE) is targeting Q4 2026 for a larger fracture stimulation programme at Sagebrush-1 in Colorado. It's also taking a 9% stake in Herencia Resources. Light Science Technologies Holdings PLC (AIM:LST, FRA:9FD) has secured a repeat order from a healthcare devices customer, pushing that contract past £500,000. It's building out higher-margin work in defence and medical sectors. Foresight Solar Fund Ltd (LSE:FSFL, FRA:1F5) says it's considering all strategic options to lift a share price stuck below the value of its assets. The board says it needs to "act decisively" to close that gap. hVIVO PLC (AIM:HVO) has appointed Caroline Shaw as an independent non-executive director. She brings more than 30 years of senior healthcare leadership to the board. Follow us and subscribe on YouTube, our social channels, and on proactiveinvestors.co.uk.

Sep 22 • 4:49 AM EDT • Science • finance.yahoo.com

The lifelong habit that could slow ageing

Study probes usefulness of health parameter called ‘vitality capacity’ to understand ageing

Sep 22 • 1:03 AM EDT • Health • health.yahoo.com

Surging diesel prices threaten North Country trucking businesses

With diesel prices inching closer to $7 a gallon, independent truckers say soaring fuel costs are threatening to put them out of business.

Sep 21 • 6:28 PM EDT • Business • wcax.com

6 Insights We're Learning from Sleep Research That Could Change How You Age

Sleep isn’t just a time for rest. Growing evidence suggests it may be one of the most powerful factors influencing how well we age, affecting everything from brain health and memory to hospital recovery and long-term independence. For more than two decades, Dr. Katie Stone, a sleep researcher Sutter Health Research Institute, has helped advance […]

Sep 21 • 4:36 PM EDT • Health • vitals.sutterhealth.org

Littleton Craft Fair returns Oct. 3

While the weather is getting cooler and farmers market season is slowly coming to a close, that doesn’t mean outdoor shopping is quite over. Littleton’s annual Craft Fair is set

Sep 21 • 3:44 PM EDT • Entertainment • littletonindependent.net

Van Orden hosts Right to Repair roundtable in Holmen

Rep. Derrick Van Orden met with independent repair shop owners in Holmen on Monday for a roundtable focused on Right to Repair legislation.

Sep 21 • 3:07 PM EDT • Politics • wxow.com

Tove Lo talks new album 'Estrus,' motherhood and giving advice

Before making her newest album, "Estrus," Swedish singer-songwriter Tove Lo felt pressure to make it profound. But after returning to a small village in Sweden, she was instead reminded of who she is at her core: "the same f— messy girl."

Sep 21 • 1:06 PM EDT • Entertainment • latimes.com