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It's Your Business | Couple brings gym to Fisher with Jacked Rabbit Fitness
Travis Enghausen and Ashley Warlow hope to have a grand opening on the weekend of Nov. 14 for their business, which they’ve decided to call Jacked Rabbit Fitness — perfectly
Four-Run Second Inning Helps Keep Rangers Playoff Hopes Alive
The Texas Rangers kept postseason pressure on the Houston Astros by capitalizing on a massive early inning against the Minnesota Twins.
Thunderbirds visit Monterey mental health facility to inspire youth
A U.S. Air Force Thunderbirds pilot and team members visited Ohana, a mental health facility in California, to share messages of teamwork, perseverance, and hope with young patients.
Robert Stone: Patients Should Never Have to Choose Between the Best Science and the Most Human Care
Robert Stone: Patients Should Never Have to Choose Between the Best Science and the Most Human Care / cancer, City of Hope, Dan Peres, Mary Ellen Podmolik,
Nebraska vs Michigan State
Big Ten play! I am probably wearing a suit and tie by now. I wonder if I’ll get to watch the game in any way. I bought a Starlink mobile just to get internet at this place we’re going to. I hope it works. HOW TO WATCH Time: 4:00pm CST Location: Memorial Stadium, Lincoln, NE Surface: Hellas Turf […]
Giving Props: Vikings Player Bets Vs the Buccaneers
Hopefully better than last week’s picks
The Camilla Foundation to host 3rd annual "Cultivating Hope: An Evening for Children's Health" on October 6
The Camilla Foundation will host its third annual "Cultivating Hope: An Evening for Children's Health" on Tuesday, October 6, 2026, at The Botanic Garden at Georgia Southern University in Statesboro. The public event will raise funds and awareness for children's mental health services in Bulloch County.
Colby Parkinson considered questionable
Rams hopeful that Colby Parkinson can play Sunday
Rangers Thumped 10-2 by Twins to Open Massive Series
With their playoff hopes on the line, the Texas Rangers started their massive series against the Minnesota Twins with a 10-2 defeat.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Is metascience being co-opted?
In July, the White House released a report that argued academia is deeply dysfunctional and in need of radical reform.Science: A New Golden Age sets out a litany of problems many academics will recognise: interminable waits for grants; short-term funding rather than support for longer, more ambitious projects; ballooning administrative requirements; pressure to publish, and many more. “The scientific machine is getting bogged down,” it says. At least on the face of it, Science: A New Golden Age is a triumph for the metascience movement, a loose-knit, global group of academics, philanthropists and think tankers that want far more testing and experimentation in how we fund public research and innovation. The report tells US research funders to set up internal metascience units to do just this. But it has also set alarm bells ringing that metascience is being conveniently deployed to help justify the defunding of US universities, which US vice president JD Vance has openly labelled “the enemy.” “Just because you have an issue with your plumbing in your house doesn't mean you light the entire house on fire and burn it to the ground,” said Colette Delawalla, chief executive of Stand Up for Science, a group campaigning against what it says are attacks on scientists by the Trump administration. No one is arguing that academia doesn’t need reform, but there’s debate over how far and how fast the system should be shaken up. Does public R&D need slow and steady evidence-based adjustment, or radical new experiments?One of the key arguments in Science: A New Golden Age is that there’s not enough funding for what it calls “mid-level” science: engineering-heavy projects that require tens of millions of dollars, involve ten to a hundred people, and last around five years. Such a project might develop a brain-computer interface for people with Alzheimer's disease, for example. As such, the US National Science Foundation (NSF) has already announced $1.5 billion to set up so-called X-Labs, effectively new research organisations to pursue breakthroughs in areas such as quantum sensing and new scientific instruments. Funding divertedBut there’s a catch: this money has squeezed NSF budgets for more traditional, fundamental research grants, Science reported in June, likely meaning less cash for university-based scientists. Science: A New Golden Age also makes various swipes at universities, accusing them of extracting overheads from scientists to fund administrative bloat. “We have become dependent on a narrow set of legacy institutions,” it says. The report doesn’t mention it, but the US government is simultaneously seeking greater powers over federal funding, which would allow political appointees at funding agencies to screen or cancel research grants mid-project. The White House is also seeking to slash the NSF’s budget by more than half in 2027, although similar cuts proposed for 2026 were blocked by Congress. Convenient hookThis has worried some that the metascience agenda could be misused as a kind of smokescreen to further weaken universities. James Wilsdon, executive director of the Research on Research Institute at University College London, said that the report contains lots of “interesting ideas” and agrees that in places, academia is a “pretty broken system.” But the risk is that metascience is being deployed as a “convenient hook” to support cuts and a “political land grab” to transfer grant power from scientists to political appointees in US funding agencies.So far, the metascience agenda hasn’t been seized on by radical right parties in Europe. But Wilsdon worries it will cross the Atlantic, politicising research reform efforts and making them more difficult to carry out. The report is already making some in Europe sceptical of the entire idea. “The system is not without flaws, but the metascience discussion is not likely to improve the system but rather to generate munition to undermine it,” said Claes de Vreese, a professor of AI and society at the University of Amsterdam. Peter Thiel protégéOfficially, Science: A New Golden Age has just one named author: Michael Kratsios, the director of the Office of Science and Technology Policy and a former chief of staff to Silicon Valley mogul Peter Thiel. He also served as chief financial officer of Thiel’s Clarium Capital Management. Since the 1990s, Thiel has criticised US universities for moving away from teaching what he views as the classic works of western civilisation, and drifting towards “anti-Western zealotry.” And since 2011, he has offered two-year fellowships of $250,000 to young people to skip or drop out of university, and instead start companies or pursue scientific research. “College can be good for learning about what’s been done before, but it can also discourage you from doing something new,” according to the Thiel Fellowships website. In other areas, the Trump administration has promoted academics with a longstanding interest in metascience. For example, the head of the National Institutes of Health, Jay Bhattacharya, in 2020 co-authored a study arguing the funder backs overly conservative proposals, although he achieved wider prominence as a critic of pandemic lockdowns. Careless talk costs fundingEven before the Trump administration embraced the metascience agenda, some metascientists privately wondered whether they should be careful not to overstate dysfunctions in academia, in case this gets used as ammunition against universities. But others think being cautious with criticism is pointless. After all, last year, the Trump administration sought to cut funding from US universities on an entirely different premise: supposed antisemitism on campus. “I don't think these governments need a technical metascientific excuse to attack the universities, they will want to do so anyway,” said Will Stone, a researcher at Science Works, a new think tank advocating for a “metascience revolution” in the UK. “I think researchers should report what they find, even when the findings may be used to advance policies they disagree with,” echoed Russell Funk, a researcher at the University of Minnesota, who in 2023 co-authored a highly influential paper that argued scientific papers were becoming less disruptive over time. No justificationThat said, Funk thinks that metascientific research certainly doesn’t justify a weakening of universities. Instead, scientists need “time, resources and stability to pursue unfamiliar ideas,” he said. “Taking away those conditions works against the very goal the reforms are supposed to achieve.”The Institute for Progress, a Washington DC-based innovation policy think tank that has championed X-Labs and metascience units, also says that reforms should complement, not supplant, universities. “Unpredictable, unreliable, and reduced federal funding to researchers is destabilising to the very foundations of research and development and is bad,” said Jenn Gustetic, the institute’s director of metascience and R&D policy.Evolution or revolution?This points to a much bigger divide in the metascience community: how far and how fast should public R&D be shaken up? Does it need evolution or revolution? For example, Science: A New Golden Age says the science system relies too heavily on traditional “workhorse” project grants, the type that pay out around $250,000 a year to fund “hypothesis-driven science by small teams on tractable questions.” However, in criticising project grants, the report “decisively picks one side of a debate that is far from settled,” David Hilmer Rex, a metascientist based in Denmark, has written. In June, Pierre Azoulay, a metascientist at the Massachusetts Institute of Technology, defended project grants, saying that the alternative of X-Labs “merits scepticism.”A-B testingOne challenge in metascience is that it’s easier to generate evidence for some types of change than others. Most straightforwardly, research funders can run A-B tests on different ways of awarding money. For example, Germany’s Volkswagen Foundation recently trialled distributed peer review, where applicants rate each other’s proposals, and measured its results against traditional review panels. Distributed peer review made quicker decisions, although awarded money to largely different ideas. However, much of the focus of the metascience movement has been on founding fast-moving and free-acting new research organisations and funders, in contrast to the alleged stodginess of mainstream academia or public innovation grants. A culture of speed and freedom are the animating principles behind Germany’s Sprind or the UK’s Advanced Research and Invention Agency (Aria).Related articlesViewpoint: it's time to experiment with how Europe funds science European researchers sound the alarm that Trump rule changes will hit cooperationHowever, while it’s possible to closely study previously successful bodies, such as the US Defense Advanced Research Projects Agency (Darpa), for historical clues to their secret sauce, it’s impossible to guarantee in advance that the likes of Sprind or Aria will actually work as hoped. But advocates of new organisations say this inherent uncertainly shouldn’t stop us trying. “If we wait for definitive proof that something will work before we try it, I don't know where your proof is coming from,” said Stone. Trade-offsUp until now, experiments in metascience haven’t generally come with hard trade-offs over money. In the US, new ideas such as focused research organisations have often been funded by billionaire philanthropists. In Europe, new innovation agencies such as Sprind and Aria, or the Netherland’s new National Agency for Disruptive Innovation, haven’t needed explicit cuts elsewhere in the research system. But with the $1.5 billion establishment of X-Labs by the NSF, the trade-offs are becoming clearer. Some metascientists privately wonder whether a smaller pilot would have been more appropriate, given that the idea is untested. The Institute for Progress counters that the $1.5 billion X-Labs budget is spread out over a decade, so will account for less than 2% of the NSF’s annual budget. “It’s important to remember that [Darpa] was once an institutional experiment as well. Now it’s one of the most cited innovative funding models in the world,” said Gustetic.As for Europe?The US isn’t the only country placing metascience at the heart of its research strategy. Science: A New Golden Age looks admiringly at the UK, which in 2024 set up a Metascience Unit to scrutinise how it funds research. In Brussels, it’s more of a mixed picture. In 2018, the EU set up the European Innovation Council to funnel grants and equity to start-ups, although it’s sometimes criticised for awarding money too slowly. Recently, the council has started experimenting with challenges, where teams of inventors compete to overcome a technological challenge. The European Commission also wants to experiment with partially randomising grant winners, to cut down on bureaucracy. However, the Commission’s own advisers have said the EU’s own research schemes are too conventional. They want the Commission to establish a new dedicated unit to scrutinise and experiment with funding. But there’s no sign of a such unit emerging in Brussels’ plans for the next Horizon Europe programme, which from 2028 is set to distribute more than €160 billion over seven years. Sam Bogerd, director of breakthrough innovation at the Brussels-based Arq Foundation, an AI-focused think tank that also looks at metascience, says that Europe might have the opposite problem to the US: universities and basic research funding are still reasonably well supported, but there’s not enough experimentation. “We're not taking a close enough look at where this money can achieve the most, and I am worried that the good ideas around metascience will be tainted politically by their association with the Trump administration,” he said. He’s still lobbying for the Commission to set up an experimental unit. But in the meantime, the Arq Foundation plans to do its own research, and is currently hiring two metascience researchers to run the rule over how Brussels spends research funding.
EU science policy wonks debate prospect of stronger ties with Canada
Europe’s research and innovation sector has started asking questions on how European Commission President Ursula von der Leyen’s offer to make Canada “the first associate member of the EU” would actually work in practice, and who will get to shape priorities in a transatlantic relationship that is getting stronger. The Commission says it wants “a new model of association” under which the EU and Canada will aim to develop “a shared space” to face ongoing challenges. “Working in close coordination with our member states and the European Parliament, we will aim to create a new form of partnership that has not existed until now, building the closest imaginable form of association with a partner outside Europe,” a spokesperson told Science|Business.Locked in an escalating trade war with US President Donald Trump, who has repeatedly talked of annexing Canada, Prime Minister Mark Carney has been looking east, but full EU membership was never in play. Taking the floor a day after von der Leyen’s proposal, he agreed to strengthen ties under “an alliance of the future” but reined in enthusiasm on the new label. He also suggested expanding Canada’s involvement in the Erasmus+ student mobility scheme, to which it currently has limited access, and the next iteration of Horizon Europe. Canada joined the present Horizon Europe in 2024, but only contributes to collaborative projects.Neither side has detailed the next practical steps in developing this new relationship. “I think nobody at the moment truly knows how this will work,” said Michael Browne, chief executive and founder of Crowdhelix, a global collaborative network that connects players in research and innovation. “It’s more of a statement of intent for closer collaboration, which requires legislative frameworks and approval processes, which have not started.”Kurt Deketelaere, secretary general of the League of European Research Universities, said von der Leyen’s pitch to Canada is “politically significant, but the legal content still has to be negotiated and constructed.”Mattias Björnmalm, secretary general of the Cesaer university group, agreed that she had only opened “a political door” to Canada, as “associate membership does not come with a predefined set of rights in the EU institutions.”Not only does this status not currently exist as a legal category in the two treaties that set up how the EU functions, but the Commission president cannot unilaterally create a new category of EU membership.According to Deketelaere, Article 217 of the Treaty on the Functioning of the EU, which allows the bloc to make association deals with non-EU countries involving reciprocal rights and duties, is “the most obvious existing legal basis for building a much deeper EU-Canada relationship.”Getting universities involvedNo matter how this new cooperation takes shape, Liviu Matei, who heads the School of Education, Communication and Society at King’s College London, hopes to see universities involved in discussions from an early stage.“Its primary motivations, entirely justifiably, are political and geopolitical,” he said. “In the area of higher education, however, restricting the initiative to political and geopolitical considerations would limit the scope of cooperation and lead to distorted frameworks and counterproductive implementation.”It is all the more important since academic interests on the two sides of the Atlantic are “neither identical nor fully aligned,” Matei added. “This is not insurmountable; it simply requires work to articulate the details of this privileged cooperation, including its governance and funding frameworks, as well as its substantive content in education and research.”Related articlesCanada looks to deepen research and education links with the EUZaharieva hopes for a Horizon Europe deal in 2026Canada might participate in European Research Council schemes, for example, which was not on offer in the present Horizon Europe association agreement. But “there would have to be something in it for the EU,” Browne said. “They don’t want to be funding projects outside of the EU where intellectual property is going to sit outside of the EU. There has to be some kind of transfer of knowledge.”But access to funding will not by itself resolve all the practical difficulties of working together, said Björnmalm. “For researchers and students, these include visas and residence arrangements, recognition of qualifications and study periods, and the conditions for pursuing a research career across borders,” he said. “For universities, there is scope for more predictable access to shared laboratories, computing and research data, and stronger support for joint doctoral training and long-term institutional partnerships.”Linda Doyle, provost and president of Trinity College Dublin, said Europe should strive for the “closest possible expression” of this new political alliance. “If Europe is serious about recovering its voice and its place in the world, it needs to be strongly allied with countries who share its values and its vision for a stable, rules-based, peaceful world.”
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Health Care Partnership outlines workforce progress
More local nursing graduates are staying in the region, according to officials offering an update on the progress of the New Hanover Healthcare Career Partnership at a public forum last night. According to Jack Watson, dean of UNCW’s College of Health & Human Services, the number of UNCW nursing graduates choosing to remain in the area after graduation has climbed from 27% to the mid-40% range. The New Hanover Healthcare Career Partnership aims to address the region’s healthcare worker shortage, with a key focus on nursing through strategic partnerships between UNCW, Cape Fear Community College (CFCC), New Hanover County Schools and the Wilmington Chamber of Commerce Foundation. "Each of the partners had pathway programs,” said Watson, “but they were almost at times done in a silo." One of the New Hanover Community Endowment's largest commitments to date, the collaborative received a $22.3 million grant in 2023, to be disbursed over three years, beginning in 2024. At the public forum, leadership addressed the nursing bottleneck created by the pandemic, and Laurie Whalin, president of the Novant Health Coastal Region, acknowledged that Novant Health had relied heavily on travel nurses during that period, with travel nurses making up about 47% of staff and nursing turnover at 35% at the height of the pandemic. "I can say we are in a tremendously different place today,” Whalin said at the forum. The number of travel nurses employed by the Novant Health Coastal Region has dropped to around 100 today, which Whalin says accounts for less than 4% of the workforce. Roughly two years into the grant term, major stakeholders in the collaboration pointed to various accomplishments tied to the initiative. According to Stephen Hill, vice president of talent development with the Greater Wilmington Chamber of Commerce, 250 more nurses live in New Hanover County in 2026 than in 2023. Whalin added that between 2021 and 2025, the Novant Health Coastal Region has hired close to 1,200 registered nurses. Additionally, according to Whalin, over the past two years, hiring and retention of nursing graduates from UNCW increased by 103%, while hiring and retention of nursing graduates from CFCC increased by 70%. Mandy Mills, director of career & technical education at New Hanover County Schools, pointed to the launch of its first Health Sciences Academy program, established across the county's four traditional high schools (Hoggard High School, Laney High School, Ashley High School and New Hanover High School), which started with 38 students last year. Mills also pointed to growth in the district’s Nursing Fundamentals course, which grew from 10 seats in 2023 to 50 in 2025-2026 and is now offered at all four traditional high schools. Watson emphasized the growing nursing class sizes and offered an update on the school’s accelerated nursing degree, which launched last year. Eleven students graduated in the first class, and all passed their boards on the first try, Watson said. This year’s class has 24 students. When the endowment announced its $22.3 million grant for the collaborative in 2023, UNCW and CFCC were each slated to receive the bulk of the funds, at about $10 million each. UNCW’s plans for the grant money included expanding its simulation lab, Watson said. He added that construction is expected to begin on the simulation lab this year and will likely extend through next year. According to Mary Ellen Naylor, dean of Health & Human Services at CFCC, the college has experienced growth in its associate degree nursing retention, rising from 59% in 2023 to 76% for the May 2026 class. CFCC used part of its endowment funding to support wraparound services, including a housing stipend, tuition assistance, exam assistance, emergency assistance, drop-in daycare and clinical and educational supplies. "We have very strong … students, but once they get into the program, there are competing priorities,” Naylor said. “They are working multiple jobs. They have children. They're single parents." According to Naylor, in 2026, 94% of students who used support services are still enrolled or have graduated. Addressing a question from an audience member about an approaching “enrollment cliff,” driven largely by dropping birth rates, Watson and Naylor said demand remains strong at both schools. “Right now … we do have more applicants than we have spots in our nursing program, and it is still a competitive process to get into,” Watson said. “I do not foresee that changing.” "(We've) doubled enrollment in our nursing programs over the last few years, but just as Dean Watson said, we still have very robust applicant pools, so it is still very competitive to get in,” Naylor said. "We have the applicant pool to support that, but again, it's not as easy as just saying, 'Okay … we're going to take another 90 students.' It's making sure all the resources and infrastructure that we need to educate the students outside the classroom is there as well." In response to a question about applying the collaborative model to other healthcare positions besides nursing, Sophie Dagenais, CEO and president of the endowment, said she sees the potential for the model to expand to other healthcare jobs and even other industries, but that the endowment hopes to learn from this model first. “This is a grant that is in year two of three years, and first we wanted to learn what is this going to demonstrate, what will we learn and then how may we scale it possibly,” she said. According to endowment spokesperson Amber Rogerson, funds for the program are set to expire after June 2027. “It's too early to discuss what happens after that,” wrote Rogerson in an email, “though we know the partners are considering the future, and some of the work supported by the grants is now built into their regular operations.”
Health Care Partnership outlines workforce progress
More local nursing graduates are staying in the region, according to officials offering an update on the progress of the New Hanover Healthcare Career Partnership at a public forum last night. According to Jack Watson, dean of UNCW’s College of Health & Human Services, the number of UNCW nursing graduates choosing to remain in the area after graduation has climbed from 27% to the mid-40% range. The New Hanover Healthcare Career Partnership aims to address the region’s healthcare worker shortage, with a key focus on nursing through strategic partnerships between UNCW, Cape Fear Community College (CFCC), New Hanover County Schools and the Wilmington Chamber of Commerce Foundation. "Each of the partners had pathway programs,” said Watson, “but they were almost at times done in a silo." One of the New Hanover Community Endowment's largest commitments to date, the collaborative received a $22.3 million grant in 2023, to be disbursed over three years, beginning in 2024. At the public forum, leadership addressed the nursing bottleneck created by the pandemic, and Laurie Whalin, president of the Novant Health Coastal Region, acknowledged that Novant Health had relied heavily on travel nurses during that period, with travel nurses making up about 47% of staff and nursing turnover at 35% at the height of the pandemic. "I can say we are in a tremendously different place today,” Whalin said at the forum. The number of travel nurses employed by the Novant Health Coastal Region has dropped to around 100 today, which Whalin says accounts for less than 4% of the workforce. Roughly two years into the grant term, major stakeholders in the collaboration pointed to various accomplishments tied to the initiative. According to Stephen Hill, vice president of talent development with the Greater Wilmington Chamber of Commerce, 250 more nurses live in New Hanover County in 2026 than in 2023. Whalin added that between 2021 and 2025, the Novant Health Coastal Region has hired close to 1,200 registered nurses. Additionally, according to Whalin, over the past two years, hiring and retention of nursing graduates from UNCW increased by 103%, while hiring and retention of nursing graduates from CFCC increased by 70%. Mandy Mills, director of career & technical education at New Hanover County Schools, pointed to the launch of its first Health Sciences Academy program, established across the county's four traditional high schools (Hoggard High School, Laney High School, Ashley High School and New Hanover High School), which started with 38 students last year. Mills also pointed to growth in the district’s Nursing Fundamentals course, which grew from 10 seats in 2023 to 50 in 2025-2026 and is now offered at all four traditional high schools. Watson emphasized the growing nursing class sizes and offered an update on the school’s accelerated nursing degree, which launched last year. Eleven students graduated in the first class, and all passed their boards on the first try, Watson said. This year’s class has 24 students. When the endowment announced its $22.3 million grant for the collaborative in 2023, UNCW and CFCC were each slated to receive the bulk of the funds, at about $10 million each. UNCW’s plans for the grant money included expanding its simulation lab, Watson said. He added that construction is expected to begin on the simulation lab this year and will likely extend through next year. According to Mary Ellen Naylor, dean of Health & Human Services at CFCC, the college has experienced growth in its associate degree nursing retention, rising from 59% in 2023 to 76% for the May 2026 class. CFCC used part of its endowment funding to support wraparound services, including a housing stipend, tuition assistance, exam assistance, emergency assistance, drop-in daycare and clinical and educational supplies. "We have very strong … students, but once they get into the program, there are competing priorities,” Naylor said. “They are working multiple jobs. They have children. They're single parents." According to Naylor, in 2026, 94% of students who used support services are still enrolled or have graduated. Addressing a question from an audience member about an approaching “enrollment cliff,” driven largely by dropping birth rates, Watson and Naylor said demand remains strong at both schools. “Right now … we do have more applicants than we have spots in our nursing program, and it is still a competitive process to get into,” Watson said. “I do not foresee that changing.” "(We've) doubled enrollment in our nursing programs over the last few years, but just as Dean Watson said, we still have very robust applicant pools, so it is still very competitive to get in,” Naylor said. "We have the applicant pool to support that, but again, it's not as easy as just saying, 'Okay … we're going to take another 90 students.' It's making sure all the resources and infrastructure that we need to educate the students outside the classroom is there as well." In response to a question about applying the collaborative model to other healthcare positions besides nursing, Sophie Dagenais, CEO and president of the endowment, said she sees the potential for the model to expand to other healthcare jobs and even other industries, but that the endowment hopes to learn from this model first. “This is a grant that is in year two of three years, and first we wanted to learn what is this going to demonstrate, what will we learn and then how may we scale it possibly,” she said. According to endowment spokesperson Amber Rogerson, funds for the program are set to expire after June 2027. “It's too early to discuss what happens after that,” wrote Rogerson in an email, “though we know the partners are considering the future, and some of the work supported by the grants is now built into their regular operations.”
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In their heyday, the Dallas Cowboys would often win on Sundays simply due to the star on the side of their helmets. Twenty straight playoff appearances will do that kind of thing, intimidating the opposing sideline before the ball was even kicked off. The Houston Astros have experienced their own championship pedigree. What started with […]
Morocco’s youth between hope and resignation
On September 23, Moroccans will elect a new parliament. Despite a growing economy, many young people feel left behind. While some are prepared to fight for political change, others see emigration as their only option.
'We deserve to win something - this could be the year'
Joe: This may read as a bizarre statement as a lifelong fan - I do not want Brighton to win any silverware this year. Having said that, I'd hope Tony Bloom would be better than that if a trophy arrives, which I'm sure he is. Nicholas: Brighton have set the bar for other clubs.
‘Real World: San Diego’ Alum Robin Hibbard Shares Health Update After Substance Abuse Struggles
Real World: San Diego alum and former The Challenge star Robin Hibbard is sharing a hopeful health update after a years-long battle with substance abuse. Hibbard, 46, shared the update in the comments...
Player Preview: Adam Oumiddoch
The four-star freshman hopes to be a regular contributor from day one.
$7,000 grant to expand access to mental health services in Saginaw County
Child and Family Service of Saginaw County has received $7,000 grant from MyMichigan Health to support the organization’s Hope Counseling Scholarship Fund.
The Cardinals Season is Over, But the Future is Bright
The 2026 schedule hasn’t yet concluded, but the Cardinals’ playoff hopes are officially extinguished. From JJ’s debut and Burley’s monstrous blast that set the tone for the season on opening day, to a group of SFA baseball players taking their shirts off and swinging them over their heads. Jordan Walker reintroducing himself to the baseball […]
Cardiff pain must lead to progress for Charlton
Charlton Athletic fan Paul Sullivan hopes the club can use the extended international break wisely
New Hope for Diagnosing C.T.E. in Brain Injured Patients
Scientists are developing imaging techniques and blood tests that one day may enable doctors to identify the disease definitively in living patients.
Medicine goes global: How international students break into pre-health fields
With changing immigration policies and growing uncertainty over work authorization for foreign nationals, one student organization on campus hopes to help pre-health international students gain a competitive edge.
Air district report links Richmond Chevron refinery emissions to elevated health risks
Residents in Richmond hope to learn more about the state of their air quality during a public meeting focused on the Chevron Richmond Refinery.
Air district to detail Chevron Richmond Refinery health risk assessment
Residents in Richmond hope to learn more about the state of their air quality during a public meeting focused on the Chevron Richmond Refinery.
Morocco’s youth take Gen Z protest demands to the polls
Young candidates hope the election can turn youth frustration into political participation.
Analyst Believes UNC Will Miss Second Straight Bowl Game
With Bill Belichick in the hot seat, analysts clash over whether he can salvage North Carolina's postseason hopes.
RenewTowns initiative hopes to bring new downtown business in Jefferson; Community meeting scheduled for Thursday
JEFFERSON — The RenewTowns initiative is hoping to bring a new business to downtown Jefferson, starting with a community meeting on Sept. 24. The RenewTowns project is a "community-driven program
Marathon Didn't Reach As Many Players As Bungie 'Hoped' And 'Needs To Evolve'
The excellent extraction shooter is in a bad place
Bungie is freeing vaulted Destiny 2 campaigns after Marathon "did not reach as many players as we had hoped"
Bungie promises to unvault Destiny 2 campaigns and raids that were locked away, all while rebuilding the shooter's future, after a tepid response to Marathon.
Republicans Enter Final Midterm Stretch With a Significant Financial Edge
The party and its allies are currently set to spend hundreds of millions of dollars more on advertising than Democrats are, giving Republicans some hope in a tough midterm environment.
Fuseini brings Rams hope of a revival
Derby County fan writer Amelia Warren analyses what makes Mohammed Fuseini an important summer signing for Derby County this season.
Kolo Muani says Juventus showed the right mentality against Atalanta
Randal Kolo Muani is proud of the mindset Juventus showed as they beat Atalanta 2-0 in Serie A this weekend, and he hopes that mentality continues.Juventus performed well in their midweek match agains...
Northern Light Health Walk for Hope honors loved ones impacted by cancer
Participants of the fundraiser paid tribute to their loved ones through holding signs and sharing stories.
Pokemon account posts Pokemon Ruby & Sapphire played on unknown emulator fuelling Switch re-release hopes
The official Pokemon X account has recently posted footage of the much-loved Pokemon Ruby & Sapphire being played on unknown emulator. This has naturally sparked hopes of a re-release of the games on…
North Carolina State Basketball 2026-27 Preview
The North Carolina State Wolfpack were hopeful that Will Wade would steady the ship after several so-so seasons under Kevin Keatts. However, not long after the Wolfpack was upset by Texas in the First Four game of the NCAA Tournament, Wade decided to return to LSU. NC State Basketball 2026-27 Preview While it was a …
They planned their lives in America. Now, they're looking elsewhere.
Former H-1B hopefuls and international graduates are building new lives abroad, as a stable future in the US increasingly becomes a pipe dream.
Alabama Democrats facing tough political gravity
Even a little uncertainty in some of the Alabama races should give Democrats some hope.
Business Buzz
The Business Buzz features news about the economic scene, promotions, acquisitions and expansions. Contact Pat Hill at pat.hill@pikespeaknewspapers.com or (719) 636-0358. Tony Perry/Park State Bank & Trust provided the sound system for the Sept. 11 ceremony in Lions Park. SSR Mining Cripple Creek Victor is the presenting sponsor of the Light of Hope Teller, a […]