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Online fraud looks like business as usual
Establishing a clear set of employee guidelines doesn’t have to be complicated.
Sporting scandals that shook the world: Lance Armstrong, Hansie Cronje, 'Crashgate'
Manchester City are far from the first. The lure of glory and riches on the biggest stages have tempted plenty of other sports stars to break the rules.
Escape to Key West for the water, nature, serenity
Key West, the continental United States’ southernmost city, blends a colorful 19th-century heritage with a laid-back contemporary vibe. Visitors will find palm-shaded streets, picturesque historic homes, a lively multicultural culinary
‘Survivor 51’ recap: A historic moment leads to an epic blunder
A historic moment on ‘Survivor 51’ leads to an epic blunder as one player attempts for showy valor, but ends up with unintentional comedy instead. Read EW’s recap.
Africa’s science diplomacy push turns to universities
Africa’s attempt to shape its own science diplomacy agenda is raising a harder question for the continent’s universities: are they equipped to tur...
Chicago police issue alert about sting of overnight business burglaries on North, West Sides
In each incident, four unknown suspects arrived at a business, targeting cash registers, cash in gaming machines and store merchandise for theft, police said.
Upworthy Launching Entertainment Studio Led By Sarah Yourgrau
One of the dominant digital platforms of the early social media era has hired Sarah Yourgrau to help it develop positive, uplifting stories to new platforms.
Disney Comms Executive Naomi Bulochnikov-Paul Departing
She has been with the company since 2017.
Study connects food insecurity to mental health in young mothers
A new review of research from across sub-Saharan Africa found that inadequate access to food is linked to depression, suicide attempts, HIV vulnerabilities, and poorer sexual and reproductive health outcomes among adolescent mothers.
A storied NASA observatory could be weeks away from falling to Earth after failed rescue attempt
A daring mission failed to rescue NASA’s Swift telescope, and the nearly 22-year-old observatory will soon burn up in Earth’s atmosphere.
UConn Football Learns Game Time For Week 6
The Huskies have to get through Syracuse first, but they'll take on Temple on Oct. 10.
Attacks on Science, Who's Behind Them, and Their Harm: My Congressional Testimony
Dr. Gretchen Goldman testified before the Senate Environmental and Public Works committee on the effects of attacks on science.
Florida woman indicted for 'attempting to kill' Rihanna in shooting
A Florida woman has been formally indicted for "attempting to kill" Rihanna, the Los Angeles District Attorney's Office announced.
The Color Purple
Temple Civic Theatre will present "The Color Purple" starting Thursday. For information and tickets visit templecivictheatre.com.
The Legal and Policy Landscape of Crisis Pregnancy Centers
This brief examines the legal status of Crisis Pregnancy Centers, attempts to regulate them, and future efforts to expand their footprints as they gain more recognition and funding from local, state, and federal programs.
Port Townsend kinetic sculpture race emphasizes art, absurdity
In The Great Port Townsend Bay Kinetic Sculpture Race, human-powered handmade sculptures attempt to cross pavement, water, sand and mud on an 8-mile course.
Revealed: Roma were also interested in Da Cunha
One of the biggest surprises in this year’s Serie A is Como’s Lucas Da Cunha.Roma reportedly made an attempt this summer for Da Cunha. They weren’t the only Italian team to make an attempt: Napo...
Milan Testing the Waters for Bayern Munich Defender
Milan ended up standing pat in the back late in the summer despite a few attempts and the persistent buzz because they couldn’t find the right man, but they’ll likely address the role in January, ...
Scientists Found a Lifeform That Endures Hell—and It May Not Be Alone
There’s never been a eukaryotic organism that got out of these temperatures alive—until now.
Can doctors temporarily “pause” the human body? Scientists are trying to buy the body more time
Suspended animation sounds like science fiction: slow the body almost to a standstill, pause the damage caused by injury or blood loss, then restart normal function later. Scientists cannot place heal...
Conference League 'very winnable'
Brighton owner Tony Bloom says he is looking forward to seeing what the Seagulls can achieve after results he described as the "best in the history of the football club". In a rare interview, Bloom told BBC South East victory over Manchester United in the Carabao Cup, a 3-0 win over Premier League champions Arsenal and beating Coventry City 5-0 had boosted confidence at the club. Bloom helped transform Brighton's fortunes after he became majority shareholder in 2009, when the team were struggling in the third tier of English football and playing at a temporary ground.
Boxed into a corner?
The Premier League has opened a Pandora's box of problems which cannot be closed. This looks like a gigantic mess, but could also become a bit of a joke, especially if they attempt to rewrite history, and change the winners' names on the Premier League and cup trophies over these past 15 years.
Health inspectors find fruit flies, roaches, trapped mouse in Dearborn
Wayne County health inspectors found pests and temperature violations at several Dearborn restaurants recently.
Some Baptist Health systems temporarily offline
Baptist Health Central Alabama is managing an unexpected IT disruption after a server outage at a third-party vendor knocked systems offline Monday afternoon.
Hayden Panettiere's ex Wladimir Klitschko petitions to protect their daughter's inheritance
LOS ANGELES — Actor Hayden Panettiere’s ex-fiancé, Wladimir Klitschko, has filed an urgent petition asking that he be allowed to act as their 11-year-old daughter’s temporary representative in California court
Mike Johnson, Bernie Sanders to campaign in Central Valley for 22nd District race
The dueling visits come as Rep. David Valadao and challenger Randy Villegas face off in one of the country’s most competitive congressional races.
Eastview Mall owner, town of Victor accused of attempting to avoid debts
Mortgage lenders U.S. Bank and Wells Fargo have filed for foreclosure.
Mamdani releases plan to combat antisemitism in New York amid concerns over his criticism of Israel
The plan is the mayor's most forceful attempt to address concerns from the Jewish community over antisemitism.
What the HealthPartners-Essentia merger means for consumers and Minnesota health care
Three merger attempts in one year, including the newly proposed HealthPartners-Essentia deal, reflect the “dynamic, almost chaotic environment” situation in U.S. health care right now.
Hayden Panettiere's ex petitions to protect daughter's inheritance
Hayden Panettiere's ex-fiancé Wladimir Klitschko has filed an urgent petition to act as their 11-year-old daughter's temporary representative in California court.
'Jimmy Kimmel Live!' ratings surge after wild year and Trump feud
Late night comedian and host Jimmy Kimmel is constantly be saying and doing things that make national headlines, from feuding with President Donald Trump, getting temporarily suspended from the
Mike Lee blocks effort to prevent Trump from tearing down memorials
Sen. Mike Lee (R-UT) on Monday night blocked a bipartisan effort to prevent the Trump administration from demolishing the John F. Kennedy Center for the Performing Arts without congressional approval. Sen. Jeff Merkley (D-OR) attempted to pass the Protecting Presidential Memorials Act, a bill he co-led with Sen. Lisa Murkowski (R-AK), by unanimous consent. The […]
Entertainment headlines with Brenda Alexander
Nick Cannon has a new reality show coming, and Hayden Panettiere's ex, files for temporary guardianship of their daughter.
Temple Health posted a $22.7 million operating profit in fiscal 2026
The North Philadelphia nonprofit's revenue climbed to $3.6 billion from $3.3 billion.
Healthcare author, leader in contemplative science to deliver URI College of Nursing’s Fall Distinguished Lecture
KINGSTON, R.I. — Sept. 29, 2026 — Susan Bauer-Wu, an internationally respected author and leader in healthcare and contemplative science will discuss mindful leadership in healthcare in the latest installment of the University of Rhode Island College of Nursing’s Distinguished Lecture series on Wednesday, Oct. 21, 6 p.m. at the Rhode Island Nursing Education Center […]
Healthcare author, leader in contemplative science to deliver URI College of Nursing’s Fall Distinguished Lecture
KINGSTON, R.I. — Sept. 29, 2026 — Susan Bauer-Wu, an internationally respected author and leader in healthcare and contemplative science will discuss mindful leadership in healthcare in the latest installment of the University of Rhode Island College of Nursing’s Distinguished Lecture series on Wednesday, Oct. 21, 6 p.m. at the Rhode Island Nursing Education Center […]
October Prime Day 2026: The Amazon deals we're shopping from Hanes, Carhartt, Apple and more ahead of Prime Big Deal Days
We have the scoop on top pre-Prime Day discounts ahead of the October savings event, including tech must-haves, vacuums, fall style upgrades and more.
Jacob Elordi confronts paparazzi during night out with Kendall Jenner
Jacob Elordi attempted to set some boundaries with paparazzi, as he and Kendall Jenner were hounded by photographers in Paris during fashion week.
Ukraine’s Academy of Sciences warns against Russian cooperation after attack
The National Academy of Sciences of Ukraine has urged the international scientific community not to “restore or legitimise institutional cooperation with Russian state scientific and educational structures,” after a Russian drone hit its Presidium building in central Kyiv, killing at least two people and injuring several others. The drone strike took place in the early afternoon on September 28 while staff were working.The academy called the strike, one of several Russian attacks on Ukraine’s capital using jet-powered drones in recent days, an act of terrorism. “It is a strike [. . .] on the very idea that knowledge, research, and the search for truth should serve life, not its destruction,” it said in a statement.The academy thanked the global scientific community for its solidarity following the attack and warned against any temptation to normalise scientific relations with Russia.“Science cannot exist outside of moral responsibility. There can be no ‘ordinary scientific cooperation’ with a state that kills people and destroys scientific institutions of another country,” it said.“We urge not to create opportunities for Russian state institutions to return to the international scientific community as if nothing happened. There can be no ‘science beyond politics’ when science is attacked with weapons.”After the full-scale invasion of Ukraine in 2022, Europe almost entirely cut institutional ties and joint programmes with Russian science, although personal academic contacts are still ongoing.Related articlesRussia widens targeting of European research centresHow geopolitical rifts cut scientific collaborationThe European Federation of Academies of Sciences and Humanities (ALLEA), for instance, continues to exclude the Russian Academy of Sciences from its network.ALLEA condemned the latest attack as a “barbaric act” and part of a broader “systematic targeting of Ukraine’s scientific and cultural infrastructure.” This is a “deliberate attempt to erase the conditions under which free inquiry, knowledge, and democratic life are possible,” it said in a statement.Since Russia’s full-scale invasion, more than 4,650 educational institutions across Ukraine have been damaged, and a further 423 have been destroyed, according to ALLEA.National academies across Europe joined ALLEA in condemning the attack. “Science is about the pursuit of knowledge for the benefit of humanity, so this is an attack on civilisation itself,” said Paul Nurse, president of the UK’s Royal Society.Attacks on scientific, university and cultural institutions “are attacks on the foundations of society and constitute a clear violation of international law,” wrote the German National Academy of Sciences Leopoldina.The presidents of the US National Academies of Sciences, Engineering and Medicine also released a joint statement condemning the attack and pledging to continue to support the Ukrainian research community.The targeting of the Ukrainian academy prompted outcry from European leaders. “Today, science became a target for Russia,” European Commission President Ursula von der Leyen wrote on social media.“These strikes are the latest illustration of the Russian regime’s hostile contempt for science and truth,” said French President Emmanuel Macron.
"Contempt for Science and Truth": Macron Condemns Russian Strike on Ukraine’s Science Academy
The attack on the National Academy of Sciences follows drone hits on a Kyiv university where 160 sheltered, and damage to a UNESCO World Heritage site.
Newly discovered iron minerals might hold primordial water from when Earth formed
Researchers may have found a missing link in how Earth's mantle gets wet: newly discovered iron minerals that can store water at the extremely high temperatures and pressures present near our planet's core.
German firm Metro loses control of Russian business after Putin decree
Russian President Vladimir Putin has ordered that the assets of German retailer Metro AG be placed under temporary administration. The move comes amid escalating tensions between Germany and Russia over the Ukraine war.
The Senate passes the Protect College Sports Act
The U.S. Senate passed the Protect College Sports Act Monday night, marking the most significant milestone to date in the attempt to legislate reform in college athletics.
How an obscure government code unlocks opportunity for businesses
What rhymes with "snakes" and helps the government classify economic activity? NAICS — or the North American Industry Classification System. These codes categorize every industry from artificial turf installation to zucchini farming. But they’re not exactly easy to get. Today we look at one business’ quest for a NAICS code and what makes them so valuable. Fact checking by Leyla Doss. Your Next Listen — How to take the temperature of the US consumer Connect with The Indicator — Sign up for The Indicator’s weekly newsletter! — Buy the Planet Money book — Find our socials, YouTube and more! — For sponsor-free episodes, subscribe to NPR+ Support public media with NPR+ and enjoy perks for over 25 podcasts like this one. This show’s perks include sponsor-free listening. Learn more at plus.npr.org.
Hayden Panettiere's ex Wladimir Klitschko petitions to protect their daughter's inheritance
LOS ANGELES (AP) — Actor Hayden Panettiere's ex-fiancé Wladimir Klitschko has filed an urgent petition asking that he be allowed to act as their 11-year-old daughter's temporary representative in California
Senate passes college sports bill that would rein in athlete payments and transfers
The Senate passed a sweeping bipartisan bill on Monday that would regulate college sports, an attempt to end “chaos” in an industry that has been upended by skyrocketing athlete payments and near-unrestricted transfers between schools.
Jackson business, political leaders call on feds to reject baseball park inside Grand Teton
Even a temporary field on already-disturbed land would do damage, letter says.
Jackson business, political leaders call on feds to reject baseball park inside Grand Teton
Even a temporary field on already-disturbed land would do damage, letter says.
CDC vaccine policy recommendations grind to a halt under Health Secretary Kennedy
Federal vaccine recommendations have stalled following Health Secretary Robert F. Kennedy Jr.'s dismissal of the advisory committee and subsequent legal challenges to his attempts to overhaul immunization policy.
Late Night Fun with Evolution and Oppenheimer
Bats by the millions would be falling from the roofs of caves if that ankle-locking design, an all-or-nothing proposition, had not come about all at once
Health Department shuts down Mililani eatery for food violations
The Hawaii Department of Health on Friday issued a red placard and immediately shut down Blazin Steaks at Mililani Shopping Center after inspectors found repeated failures to keep food at safe temperatures.
NYC business leaders renew push to ease short-term rental restrictions
(The Center Square) — New York City business leaders are urging the City Council to ease restrictions on short-term rentals they say have created a shortage of temporary housing.
Start times announced for Arizona State, Arizona's Week 6 games
Arizona State will have a late-night kickoff in Tempe, while Arizona goes on the road for an early kickoff in Week 6.
Kremlin transfers control of German retailer Metro's Russia business
FRANKFURT, Germany (AP) — President Vladimir Putin has ordered the Russian assets of German retailer Metro AG placed under temporary administration. The step comes against a background of tension between Germany and Russia over the war in Ukraine.
Senate Nears Vote on College Sports Bill That Would Rein in Athlete Payments and Transfers
WASHINGTON (AP) — The Senate is poised to pass a sweeping bipartisan bill on Monday that would regulate college sports, an attempt to end “chaos” in an industry that has been upended by skyrocketing athlete payments and near-unrestricted transfers between schools. Passage of the legislation would be ...
Kremlin transfers control of German retailer Metro's Russia business
President Vladimir Putin has ordered the Russian assets of German retailer Metro AG placed under the temporary administration.
The United States Will Be Worse off for Losing International Scientists
The U.S. has long benefited from the scholarship of international scientists. The Trump administration's policies are forcing many to reconsider their careers here.
‘Starship is in orbit’: cheers go up as huge SpaceX rocket circles Earth for first time
Mission goes ahead despite some fears an initial engine failure after the Texas launch would scupper the attempt
Mayor Sarno joins Health Commissioner Caulton Harris to bring greetings at Department of Elder Affairs Hispanic Heritage Month Luncheon at the Ray Jordan Senior Center
Mayor Domenic J. Sarno was honored to join Health & Human Services Commissioner Helen Caulton Harris and the Springfield Department of Elder Affairs team on Friday to bring greetings at a special Hispanic Heritage Month Luncheon celebration with our seniors at the Raymond A. Jordan Senior Center. This special luncheon is a collaboration between the Raymond A. Jordan Senior Center and the North End Senior Center and celebrated Hispanic heritage and the valued contributions of our senior community. Members of the senior centers were invited for a vibrant day of music, dance, food, and culture. El Morro bakery provided lunch to members by our kind and dedicated Elder Affairs staff. Grupo Erupxion performed live music. Special thanks to host/emcee Joanna, the Springfield Department of Elder Affairs and the Council on Aging team for bringing us together to celebrate the beautiful mosaic of our Springfield. Mayor Sarno states, “We are always proud to celebrate the vibrancy and beautiful mosaic that is our Springfield community. On behalf of the City of Springfield, we celebrate and welcome the continued contributions of Hispanic Americans toward our community, including their cultural heritage, public service, and entrepreneurial spirit. I commend and appreciate this collaboration between the North End Senior Center and the Ray Jordan Senior Center to host this special luncheon in celebration of Hispanic Heritage Month for all our seniors to enjoy. ‘Que tenga buena salud y Dios te bendiga’ – Good health and God Bless.”
SpaceX launches Starship on 10-hour test flight, aiming to orbit Earth 6 times
SpaceX's massive Starship rocket lifted off from Texas Sunday morning on its most ambitious mission yet, marking its first attempt at orbit.
General contractor more than doubles Valley office space
Alston Construction doubles its Phoenix office space to 10,000 square feet in Tempe as major Arizona general contractors expand operations.
In brief: '9 to 5' headed back to theaters and more
Pour yourself a cup of ambition and head out to your local movie theater. 9 to 5 is headed back to movie theaters for a special, weeklong run starting on Oct. 9. This will be a newly restored version of the classic satirical workplace comedy starring the late Dolly Parton. Additionally, Disney is set to donate net proceeds from each ticket purchased for the rerelease in the U.S. to the Dollywood Foundation in support of its flagship program, Dolly Parton’s Imagination Library. Disney is the parent company of ABC News ...Off Campus star Ella Bright has found her next gig. The actress confirmed she will star opposite Mason Thames in the movie Narcs in a post shared to her Instagram Story. This marks Bright's first major studio feature role. The upcoming coming-of-age comedy will be made for Sony Pictures. While the movie's plot is being kept under wraps, it will serve as the directorial debut of John Phillips, the writer of No Hard Feelings, Good Boys and Dirty Grandpa ... TNCMS.AdManager.render({region: 'fixed-big-ad-top-asset', slot: 1, fold: "above"}); Did you miss Evil Dead Burn in theaters? Not to worry. The film is set to make its global streaming debut on HBO Max on Oct. 2. Souheila Yacoub, Tandi Wright, Hunter Doohan, Luciane Buchanan, Erroll Shand and Maude Davey star in the film that was directed by Sébastien Vaniček ...Copyright © 2026, ABC Audio. All rights reserved. Thank you for reading kmaland.comAt KMA, we attempt to be accurate in our reporting. If you see a typo or mistake in a story, please contact us by emailing kmaradio@kmaland.com.
A trailblazer in science and teaching - College of Arts and Sciences
Chemistry Professor Emerita Linda Spremulli will be honored for her lasting impact on generations of scientists ahead of the Linda L. Spremulli Trailblazer Chemistry Symposium on Oct. 2.
Starship Attempts Its First Launch To Orbit Today Carrying Big Dreams You Can Watch Take Flight
If the launch is successful, plans for humanity’s return to the Moon may look a touch less improbable.
Why Cleaning Isn’t the Mental Health Miracle Everyone Believes It To Be - Futura-Sciences
Where the “therapeutic cleaning” idea comes from The belief in cleaning as a kind of moving meditation is tempting: repetitive gestures, a structured task, instant visible results—it all seems reminiscent of mindfulness. This narrative sounds great in theory, but available studies reveal a far more complex picture, one where context...
Mexico’s journalists have long faced bullets. Now lawsuits against them are rising
Politicians and judges are increasingly attempting to shut down press freedoms in Mexico, raising concerns among journalism watchdog groups
In defense of the mid-cute: Why forgettable rom-coms are perfect for our exhausted brains
Room temperature romantic comedies are dominating the genre. Is that such a bad thing?
Pitching, prose, politics: The many sides to Larry Jackson
As a newspaper sports columnist, Larry Jackson had an edge over contemporaries such as Red Smith, Jim Murray and Shirley Povich. He not only wrote about Jackie Robinson, he pitched against him. Thi…
‘Powerful and beautiful’: Here’s why we all need body fat
From releasing hormones to regulating our temperature, fat has myriad roles in the body. Here’s how much you need and why chasing extreme fat-loss goals is unhealthy.
‘Powerful and beautiful’: Here’s why we all need body fat
From releasing hormones to regulating our temperature, fat has myriad roles in the body. Here’s how much you need and why chasing extreme fat-loss goals is unhealthy.
Health Tech Keeps Choosing Violence
Last week was an absolute dump of health tech litigation mayhem, with enough new filings to make my wife seriously question my bedtime reading. Here’s what’s inside: OpenEvidence v. Doximity: Doximity didn’t wait for the deadline. It wants OpenEvidence’s case thrown out entirely, and its motion adds some awkward details about vanished Slack data and borrowed NPIs. Plus, Epic v. Apple offers a look at what a normal discovery fight looks like. Texas v. Epic: Epic took another shot at the State’s antitrust pleadings, asking the court to make Texas spell out how its employment restrictions harm competition and why Texas law reaches a Wisconsin company’s noncompetes. Veeva v. Epic: The two Wisconsin law professors finally weighed in on whether a would-be employer can challenge someone else’s noncompete. Audacious Inquiry v. CRISP: Our sleepy patent case just evolved into a much more interesting form, with CRISP firing back with attempted monopolization and information blocking counterclaims. Cognizant v. Infosys: After weeks of emails and phone calls, I finally have Judge Starr’s sealed ruling on Infosys’s antitrust counterclaims. Some survived, offering clues about where the Epic (and other system of record) antitrust cases stand their best chance OpenEvidence v. Doximity
Fall Into Good Health
As temperatures drop and routines begin to change, fall is a great time to take stock of your horse’s health and wellness needs. From nutrition and recovery to grooming, hoof care and forage, these products can help keep horses feeling their best through the changing season and into winter.
New formulation helps RNA vaccines withstand high temperatures
MIT researchers used artificial intelligence to create more stable, heat-resistant RNA vaccines.
Carrot Top released from hospital following reported suicide attempt
The comedian is with family and reportedly “doing well” following the Sept. 18 incident in Las Vegas.
Man accused of holding business owner at knife point in attempted robbery in South City
A 51-year-old man is being charged and accused of holding a business owner at knife point in an attempted robbery.
Presidents Cup Sunday results: U.S. clinches victory with huge rally
On the final day of the Presidents Cup, the United States attempts to rally to victory over the underdog International team.
Nightly drone shows, four days of live entertainment to be showcased at 99th Maui County Fair
The 99th Maui County Fair will bring four days of live entertainment to the main stage, featuring a mix of Hawaiian music, hula, local favorites and island contemporary performers. The much-anticipated fair is set for Oct. 1–4 at the County’s War Memorial Complex. This year, every night of the fair at 8:30 p.m., fairgoers can […]
Presidents Cup Sunday results: U.S. cuts into Internationals' lead as singles play begins
On the final day of the Presidents Cup, the United States attempts to rally to victory over the underdog International team.
Main sponsor? Firm 🔞 offers millions to Corinthians and Flamengo
Amid the controversy over the end of betting companies, the +18 platform Fatal Model offered MILLIONS in an attempt to become the main sponsor of Corinthians and Flamengo.The adult content company off...
[Science Bulletin] KERI develops direct carbon coating technology for substrates
Korea Electric Research Institute grows graphene and graphite thin films at room temperature while MSIT launches safety inspections for semiconductor labs
October Prime Day 2026: The Amazon early deals we're tracking from Hanes, DeWalt, Apple and more ahead of Prime Big Deal Days
We have the scoop on top pre-Prime Day discounts ahead of the October savings event, including tech must-haves, vacuums, fall style upgrades and more.
How Harry Kane corrected Bayern Munich’s ‘serious mistake’ template
FC Bayern learned a hard lesson with the departure of Robert Lewandowski.
Politics chat: Trump vs the media; rolling back health and education spending
We look at President Trump's fight with some of the White House press corps, as well as his attempt to claw back $810 million in Congressionally-approved funds for health and education spending.
Politics chat: Trump vs the media; rolling back health and education spending
We look at President Trump's fight with some of the White House press corps, as well as his attempt to claw back $810 million in Congressionally-approved funds for health and education spending.
Rogers Tries to Make El-Sayed’s Health Care Plan Scary
_Taylor, Michigan_HERE’S HOW YOU CAN TELL Mike Rogers is anxious to make up ground in the Michigan Senate race: He held a press conference on health care last weekend. Health care is usually a rough issue for Republicans, because voters associate the GOP with attacking cherished programs like Medicare and Medicaid that Democrats have historically supported. It’s a particularly difficult issue in this campaign, because a few months ago Donald Trump and the Republicans refused to extend temporary financial assistance in the Affordable Care Act. As a result of that decision, more than 20 million Americans faced higher insurance prices this year. That’s not a policy choice you want to be defending at a time when voters frequently cite the cost of health care as a top concern. Throw in the fact that Democratic nominee Abdul El-Sayed can draw on his credibility as a doctor and former public health director in Detroit, and it might seem like Rogers’s best bet would be to avoid health care altogether. But Rogers had his reasons to spotlight health care last Saturday. And they became apparent a few minutes before he spoke, when members of his campaign staff There’s a lot happening. Too much, some days. We can’t promise to have all the answers. But we can promise to keep asking the questions, following the facts, and figuring things out alongside people who care about where this country is headed. Read with us. Learn with us. And when it matters, stand with us. Join the side you’re already on. Join Bulwark+
See ‘The Science of Autumn Foliage’
GROTON — As summer fades and cooler temperatures arrive, New England prepares for one of its most spectacular annual displays: the changing of the leaves.
“Resident Evil” (2026) Review and Film Franchise Retrospective
After years of poorly made adaptations, “Resident Evil” (2026), directed by Zach Cregger, attempts a new approach to a story that fans have witnessed many times. From 2002 to 2017, Sony released six action-horror movies based on the game series. Mostly directed by Paul W. S. Anderson, the films would create new characters and seemed...
YouTube and Meta Reverse Course, Will Accept 'Musk' Trailer Ad
The Google unit says the ad was "temporarily restricted" while Meta calls it "an error." TikTok and X remain silent.
Carrot Top released from hospital after suicide attempt
Carrot Top has been released from the Las Vegas hospital where he was treated after a reported suicide attempt.
Carrot Top leaves hospital after suicide attempt: How he's doing now
Carrot Top has been released from the Las Vegas hospital where he was treated after a reported suicide attempt.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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